M28LV16 [STMICROELECTRONICS]
16K (2K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION; 16K （ 2K ×8 ）低压并行EEPROM与软件数据保护
| 型号： | M28LV16 |
| 厂家： | 
ST |
| 描述： | 16K (2K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION |
| 文件： | 总17页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28LV16
16K (2K x 8) LOW VOLTAGE PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
FAST ACCESS TIME: 200ns
SINGLE LOW VOLTAGE OPERATION
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page WriteOperation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Data Polling
24
1
PDIP24 (P)
PLCC32 (K)
– ToggleBit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITYSINGLE POLYSILICON,
CMOS TECHNOLOGY:
24
– Endurance >100,000 Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
1
SO24 (MS)
300 mils
TSOP28 (N)
8 x 13.4mm
M28LV16 is replaced by the products
described on the document M28C16A
Figure 1. Logic Diagram
DESCRIPTION
The M28LV16 is a 2K x 8 low power Parallel
EEPROMfabricatedwithSGS-THOMSONproprie-
tary single polysilicon CMOS technology. The de-
vice offers fast access time with low power
dissipation and requires a 2.7V to 3.6V power
supply. The circuit has been designed to offer a
flexible microcontroller interface featuring both
hardware and software handshaking with Data
Polling and Toggle Bit. The M28LV16 supports 64
byte page write operation. ASoftware DataProtec-
tion (SDP) is also possible using the standard
JEDEC algorithm.
V
CC
11
8
A0-A10
DQ0-DQ7
W
E
M28LV16
Table 1. Signal Names
RB *
A0 - A10
Address Input
G
DQ0 - DQ7 Data Input / Output
W
Write Enable
Chip Enable
Output Enable
Ready / Busy
Supply Voltage
Ground
E
V
SS
G
AI01567B
RB
VCC
VSS
Note: * RB function is offered only with TSOP28 package.
November 1997
1/17
This is information on a product still in production but not recommended for new design.
M28LV16
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
A7
A6
1
2
3
4
5
6
7
8
9
24
V
CC
1 32
23 A8
A6
A8
A5
22 A9
A5
A4
A3
A9
A4
21
20
W
G
NC
NC
G
A3
A2
19 A10
M28LV16
A2
A1
9
M28LV16
25
A1
18
E
A10
E
A0
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
A0
DQ0
NC
DQ7
DQ6
DQ1 10
DQ2 11
DQ0
17
V
12
SS
AI01568
AI01569B
Warning: NC = Not Connected, DU = Don’t Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
G
NC
A9
A8
NC
W
22
21
A10
E
A7
A6
1
24
23
V
CC
A8
2
DQ7
DQ6
DQ5
DQ4
DQ3
A5
3
22
A9
A4
4
21
W
A3
5
20
G
A2
6
19
A10
E
V
28
1
15
14
CC
RB
M28LV16
M28LV16
A1
7
18
V
SS
A0
8
17
DQ7
DQ6
DQ5
DQ4
DQ3
NC
A7
A6
A5
A4
A3
DQ2
DQ1
DQ0
A0
DQ0
DQ1
DQ2
9
16
10
11
12
15
16
V
15
A1
SS
AI01570
7
8
A2
AI01124C
Warning: NC = Not Connected.
2/17
M28LV16
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
– 40 to 85
Unit
°C
°C
V
Ambient Operating Temperature
Storage Temperature Range
Supply Voltage
TSTG
VCC
VIO
– 65 to 150
– 0.3 to 6.5
– 0.3 to VCC +0.6
– 0.3 to 6.5
4000
Input/Output Voltage
V
VI
Input Voltage
V
VESD
Electrostatic Discharge Voltage (Human Body model) (2)
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure toAbsolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. 100pF through 1500Ω; MIL-STD-883C, 3015.7
(1)
Table 3. Operating Modes
Mode
E
1
X
X
0
0
G
X
1
W
X
X
1
DQ0 - DQ7
Hi-Z
Standby
Output Disable
Write Disable
Read
Hi-Z
X
0
Hi-Z
1
Data Out
Data In
Write
1
0
Note: 1. 0 = V ; 1 = VIH; X = VIL or VIH.
IL
PIN DESCRIPTION
OPERATION
In order to prevent data corruption and inadvertent
write operations during power-up, a Power On
Reset(POR) circuitresetsall internalprogramming
cicuitry. Access to the memory in write mode is
allowed after a power-up as specifiedin Table 7.
Addresses (A0-A10). The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
low to enable all read/write operations. When Chip
Enable is high, power consumption is reduced.
Read
The M28LV16is accessedlike astatic RAM. When
E and G are low with W high, the data addressed
is presentedon the I/O pins. The I/O pins are high
impedance when either G or E is high.
Output Enable (G). The Output Enable input con-
trols the data output buffers and is used to initiate
read operations.
DataIn/ Out (DQ0 - DQ7). Datais written to orread
from the M28LV16 through the I/O pins.
Write
Write operations are initiated when both W and E
are low and G is high.TheM28LV16 supports both
E and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurs last and the Data on the rising edge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion.
Write Enable (W). TheWrite Enable input controls
the writing of data to the M28LV16.
Ready/Busy (RB). Ready/Busy is an open drain
output that can be used to detect the end of the
internal write cycle.
It is offered only with the TSOP28 package. The
reader should refer to the M28LV17 datasheet
for more information about the Ready/Busy
function.
3/17
M28LV16
Figure 3. Block Diagram
E
G
W
V
GEN
RESET
CONTROL LOGIC
PP
ADDRESS
LATCH
A6-A10
(Page Address)
64K ARRAY
ADDRESS
LATCH
A0-A5
Y
DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI01520
Page Write
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
read cycle.
Page write allows up to 64 bytes to be consecu-
tively latched into the memory prior to initiating a
programming cycle. All bytes must be located in a
single page address, that is A6-A10 must be the
same for all bytes. The page write can be initiated
during any byte write operation.
Following the first byte write instruction the host
may send another address and data with a mini-
mum data transfer rateof 1/tWHWH (see Figure13).
If atransitionofEor Wis not detectedwithin tWHWH
the internal programming cycle will start.
Microcontroller Control Interface
The M28LV16 provides two write operation status
bitsandonestatuspin that can beusedtominimize
the system write cycle. These signals are available
on the I/O port bits DQ7 or DQ6 of the memory
during programming cycle only.
Toggle bit (DQ6). The M28LV16 offers another
way for determining when the internal write cycle
iscompleted. During the internalErase/Writecycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read the memory. When the internal cycle is com-
pleted the toggling will stop and the device will be
accessible for a new Read or Write operation.
,
Page Load Timer Status bit (DQ5). In the Page
Write mode data may be latched by E or W. Up to
32 bytes may be input. The Data output (DQ5)
indicates the status of the internal Page Load
Timer. DQ5 may be read by asserting Output En-
able Low (tPLTS). DQ5 Low indicates the timer is
running, High indicates time-out after which the
write cycle will start andno new data may be input.
Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP
TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
4/17
M28LV16
Figure 5. Software Data Protection Enable Algorithm and Memory Write
WRITE AAh in
Address 555h
WRITE AAh in
Address 555h
Page
Write
Instruction
(Note 1)
Page
Write
Instruction
(Note 1)
WRITE 55h in
Address 2AAh
WRITE 55h in
Address 2AAh
WRITE A0h in
Address 555h
WRITE A0h in
Address 555h
WRITE
is enabled
SDP is set
Write Page
(1 up to 64 bytes)
SDP ENABLE ALGORITHM
WRITE IN MEMORY
WHEN SDP IS SET
AI01509B
Note: 1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.
Software Data Protection
Figure 6. Software Data Protection Disable
Algorithm
The M28LV16 offers a software controlled write
protection facility that allows the user to inhibit all
write modes to the device including the Chip Erase
instruction. This can be useful in protecting the
memory from inadvertent write cycles that may
occur due to uncontrolledbus conditions.
WRITE AAh in
Address 555h
The M28LV16is shippedasstandardin the”unpro-
tected” state meaning that the memory contents
can be changed as required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operation where no further write commands have
any effect on the memory contents. The device
remains in this mode until a valid Software Data
Protection (SDP) disable sequence is received
whereby the device reverts to its ”unprotected”
state. The Software Data Protection is fully non-
volatile and is not changed by power on/off se-
quences.
WRITE 55h in
Address 2AAh
WRITE 80h in
Address 555h
Page
Write
Instruction
WRITE AAh in
Address 555h
WRITE 55h in
Address 2AAh
To enable the Software Data Protection (SDP) the
devicerequirestheusertowrite (with aPage Write)
three specific data bytes to three specific memory
locations as per Figure 5. Similarly to disable the
Software Data Protection the user has to write
specificdata bytesinto six differentlocationsasper
Figure 6 (with a Page Write). This complexseries
ensures that the user will never enable or disable
the Software Data Protectionaccidentally.
WRITE 20h in
Address 555h
Unprotected State
AI01510
5/17
M28LV16
Table 4. AC Measurement Conditions
Figure 8. AC Testing Equivalent Load Circuit
Input Rise and Fall Times
Input Pulse Voltages
≤ 20ns
V
CC
0V to VCC -0.3V
1.5V
Input and Output Timing Ref.
Voltages
1.8kΩ
Note that Output Hi-Z is defined as the point where data is no
longer driven.
DEVICE
UNDER
TEST
OUT
Figure 7. AC Testing Input Output Waveforms
1.3kΩ
C
= 100pF
L
V
–0.3V
0V
CC
0.5 V
CC
C
includes JIG capacitance
L
AI01274
AI01396
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
ILI
Parameter
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
10
10
8
Unit
Input Leakage Current
Output Leakage Current
µA
µA
ILO
0V ≤ VIN ≤ VCC
E = VIL, G = VIL, f = 5 MHz, VCC = 3.3V
E = VIL, G = VIL, f = 5 MHz, VCC = 3.6V
mA
mA
Supply Current
(CMOS inputs)
(1)
ICC
10
(1)
Supply Current (Standby)
CMOS
ICC2
E > VCC –0.3V
50
µA
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
– 0.3
2
0.6
V
V
V
V
VCC +0.5
0.2 VCC
VOL
VOH
IOL = 1 mA
IOH = 1 mA
0.8 VCC
Note: 1. All I/O’s open circuit.
Table 7. Power Up Timing (1) (TA = 0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
tPUR
Parameter
Time Delay to Read Operation
Min
1
Max
Unit
µs
ms
V
tPUW
Time Delay to Write Operation
Write Inhibit Threshold
10
1.5
VWI
2.5
Note: 1. Sampled only, not 100% tested.
6/17
M28LV16
Table 8. Read Mode AC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
M28LV16
-250
Symbol
Alt
Parameter
Test Condition
Unit
-200
-300
Min Max Min Max Min Max
Address Valid to Output
Valid
tAVQV
tELQV
tGLQV
tACC
tCE
tOE
tDF
E = VIL, G = VIL
G = VIL
200
200
100
55
250
250
150
60
300
300
150
60
ns
ns
ns
ns
ns
ns
Chip Enable Low to Output
Valid
Output Enable Low to
Output Valid
E = VIL
Chip Enable High to Output
Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
0
0
0
0
0
0
Output Enable High to
Output Hi-Z
(1)
tGHQZ
tDF
E = VIL
55
60
60
Address Transition to
Output Transition
tAXQX
tOH
E = VIL, G = VIL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 9. Read Mode AC Waveforms
A0-A10
E
VALID
tAVQV
tAXQX
tGLQV
tEHQZ
tGHQZ
G
tELQV
Hi-Z
DQ0-DQ7
DATA OUT
AI01511B
Note: Write Enable (W) = High
7/17
M28LV16
Table 9. Write Mode AC Characteristics
(TA = 0 to70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
tAVWL
Alt
tAS
Parameter
Test Condition
E = VIL, G = VIH
G = VIH, W = VIL
G = VIH
Min
0
Max
Unit
ns
Address Validto Write Enable Low
Address Validto Chip Enable Low
Chip Enable Low to Write Enable Low
tAVEL
tAS
0
ns
tELWL
tCES
0
ns
Output Enable High to Write Enable
Low
tGHWL
tOES
E = VIL
0
ns
tGHEL
tWLEL
tWLAX
tELAX
tWLDV
tELDV
tELEH
tWHEH
tOES
tWES
tAH
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
W = VIL
G = VIH
0
ns
ns
ns
ns
µs
µs
ns
ns
0
100
100
tAH
tDV
E = VIL, G = VIH
G = VIH, W = VIL
1
1
tDV
Chip Enable Low to Input Valid
tWP
tCEH
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
100
0
1000
Write Enable High to Output Enable
Low
tWHGL
tOEH
0
ns
tEHGL
tEHWH
tWHDX
tEHDX
tWHWL
tWLWH
tWHWH
tWHRH
tDVWH
tDVEH
tOEH
tWEH
tDH
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Byte Load Repeat Cycle Time
0
0
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
0
tDH
0
tWPH
tWP
tBLC
tWC
tDS
50
100
0.2
100
3
Write Cycle Time
Data Valid before Write Enable High
Data Valid before Chip Enable High
50
50
tDS
8/17
M28LV16
Figure 10. Write Mode AC Waveforms - Write Enable Controlled
A0-A10
E
VALID
tAVWL
tELWL
tGHWL
tWLAX
tWHEH
tWHGL
G
tWLWH
W
tWLDV
tWHWL
DATA IN
tDVWH
DQ0-DQ7
tWHDX
AI01521
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
A0-A10
E
VALID
tAVEL
tGHEL
tWLEL
tELAX
tELEH
G
tEHGL
W
tELDV
tEHWH
DATA IN
tDVEH
DQ0-DQ7
tEHDX
AI01522
9/17
M28LV16
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A10
Addr 0
Addr 1
Addr 2
Addr n
E
tPLTS
G
tWHWL
tWHRH
W
tWLWH
tWHWH
Byte 2
tWHWH
DQ0-DQ7
DQ5
Byte 0
Byte 1
Byte n
Byte n
AI01523
Figure 13. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
tWHWH
W
tAVEL
tWLAX
2AAh
A0-A5
Byte Address
Page Address
Byte 0
tWHDX
555h
A6-A10
DQ0-DQ7
555h
tDVWH
AAh
55h
A0h
Byte 62
Byte 63
AI01515
Note: A6 through A10 must specify the same page address during each high to lowtransition of W (or E) after the software code has been
entered. G must be high only when W and E are both low.
10/17
M28LV16
Figure 14. Data Polling Waveform Sequence
A0-A10
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI01516
Figure 15. Toggle Bit Waveform Sequence
A0-A10
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE
READY
INTERNAL WRITE SEQUENCE
AI01517
Note: 1. First Toggle bit is forced to ’0’
11/17
M28LV16
ORDERING INFORMATION SCHEME
Example:
M28LV16
-200 K
1
T
Speed
Package
P (2) PDIP24
PLCC32
Temperature Range
Option
-200
-250
-300
200ns
250ns
300ns
1
6
0 to 70 °C
T
Tape & Reel
Packing
K
–40 to 85 °C
MS (2) SO24 300mils
N (1) TSOP28
8 x 13.4mm
Notes: 1. The M28LV16 in TSOP28 package has a Ready/Busy output on pin 1.
2. Packages available on request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFh).
For a list ofavailableoptions (Package, etc...) or for further information on any aspect of this device, please
contact the SGS-THOMSON Sales Office nearest to you.
12/17
M28LV16
PDIP24 - 24 pin Plastic DIP, 600 mils width
mm
Min
inches
Symb
Typ
Max
5.08
1.78
4.06
0.56
1.78
0.30
32.26
16.26
13.97
–
Typ
Min
Max
0.200
0.070
0.160
0.021
0.070
0.012
1.270
0.640
0.550
–
A
A1
A2
B
3.94
0.38
3.56
0.38
1.14
0.20
0.155
0.015
0.140
0.015
0.045
0.008
B1
C
D
E
14.80
12.50
–
0.583
0.492
–
E1
e1
eA
L
2.54
0.100
15.20
3.05
1.02
0°
17.78
3.82
2.29
15°
0.598
0.120
0.040
0°
0.700
0.150
0.090
15°
S
α
N
24
24
PDIP24
A2
A
A1
e1
L
B1
B
D
α
C
eA
S
N
1
E1
E
PDIP
Drawing is not to scale.
13/17
M28LV16
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
inches
Min
Symb
Typ
Max
3.56
2.41
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
B
0.100
0.060
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
j
–
–
–
–
N
32
32
Nd
Ne
7
7
9
9
CP
0.10
0.004
PLCC32
D
A1
D1
j
1 N
B1
e
Ne
E1 E
D2/E2
B
Nd
A
CP
PLCC
Drawing is not to scale.
14/17
M28LV16
SO24 - 24 lead Plastic Small Outline, 300 mils body width
mm
Min
2.46
0.13
2.29
0.35
0.23
15.20
7.42
–
inches
Min
Symb
Typ
Max
2.64
0.29
2.39
0.48
0.32
15.60
7.59
–
Typ
Max
0.104
0.011
0.094
0.019
0.013
0.614
0.299
–
A
A1
A2
B
0.097
0.005
0.090
0.014
0.009
0.598
0.292
–
C
D
E
e
1.27
0.050
H
10.16
0.61
0°
10.41
1.02
8°
0.400
0.024
0°
0.410
0.040
8°
L
α
N
24
24
CP
0.10
0.004
SO24
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
15/17
M28LV16
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
mm
Min
inches
Min
Symb
Typ
Max
1.25
0.20
1.15
0.27
0.21
13.60
11.90
8.10
–
Typ
Max
0.049
0.008
0.045
0.011
0.008
0.535
0.469
0.319
–
A
A1
A2
B
0.95
0.17
0.10
13.20
11.70
7.90
–
0.037
0.007
0.004
0.520
0.461
0.311
–
C
D
D1
E
e
0.55
0.022
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
28
28
CP
0.10
0.004
TSOP28
A2
22
21
e
28
1
E
B
7
8
D1
A
CP
D
DIE
C
TSOP-c
A1
α
L
Drawing is not to scale.
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M28LV16
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consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
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