M28R400CT120ZB6_技术文档

M28R400CT

M28R400CB

4 Mbit (256Kb x16, Boot Block)

1.8V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Package

–

V_DD= 1.65V to 2.2V Core Power Supply

V_DDQ= 1.65V to 2.2V for Input/Output

V_PP= 12V for fast Program (optional)

■

ACCESS TIMES: 90ns, 120ns

PROGRAMMING TIME

FBGA

–

10µs typical

Double Word Programming Option

■

COMMON FLASH INTERFACE

64 bit Security Code

MEMORY BLOCKS

–

TFBGA46 (ZB)

6.39 x 6.37mm

–

Parameter Blocks (Top or Bottom

location)

–

Main Blocks

■

BLOCK LOCKING

–

All blocks locked at Power Up

Any combination of blocks can be locked

WP for Block Lock-Down

SECURITY

–

64 bit user Programmable OTP cells

64 bit unique device identifier

One Parameter Block Permanently

Lockable

■

AUTOMATIC STAND-BY MODE

PROGRAM and ERASE SUSPEND

100,000 PROGRAM/ERASE CYCLES per

BLOCK

■

ELECTRONIC SIGNATURE

–

Manufacturer Code: 20h

Top Device Code, M28R400CT: 882Ah

Bottom Device Code, M28R400CB:

882Bh

June 2004

1/48

M28R400CT, M28R400CB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Security Block Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V_DDSupply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

_DDQSupply Voltage (1.65V to 2.2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V_PPProgram Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/48

M28R400CT, M28R400CB

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 14

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

V

_PPStatus (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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M28R400CT, M28R400CB

Figure 11.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75 mm pitch, Bottom View Package Outline28

Table 19. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data. . . 28

Figure 13.TFBGA46 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 29

Figure 14.TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 29

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 22. Top Boot Block Addresses, M28R400CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. Bottom Boot Block Addresses, M28R400CB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 27. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 28. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 29. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 17.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 39

Figure 18.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 19.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 20.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 21.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 44

Table 30. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 31. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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M28R400CT, M28R400CB

SUMMARY DESCRIPTION

The M28R400C is a 4 Mbit (256Kbit x 16) non-vol-

atile Flash memory that can be erased electrically

at the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (1.65 to

2.2V) supply. V_DDQallows to drive the I/O pin

down to 1.65V. An optional 12V V_PPpower supply

is provided to speed up customer programming.

The memory is offered in a TFBGA46 (0.75mm

pitch) package and is supplied with all the bits

erased (set to ’1’).

Figure 2. Logic Diagram

V

DD DDQ PP

The device features an asymmetrical blocked ar-

chitecture. The M28R400C has an array of 15

blocks: 8 Parameter Blocks of 4 KWord and 7

Main Blocks of 32 KWord. M28R400CT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28R400CB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 4., Block Ad-

dresses.

18

16

A0-A17

DQ0-DQ15

W

E

M28R400CT

M28R400CB

G

The M28R400C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and block

erase. When V_PP≤ V_PPLKall blocks are protected

against program or block erase. All blocks are

locked at power-up.

RP

WP

V

SS

AI04392

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

Table 1. Signal Names

A0-A17

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

E

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system design. The Protection Register is divid-

ed into two 64 bit segments, the first one contains

a unique device number written by ST, while the

second one is one-time-programmable by the us-

er. The user programmable segment can be per-

manently protected. The Security Block,

parameter block 0, can be permanently protected

by the user. Figure 5., shows the Security Block

Memory Map.

G

Output Enable

Write Enable

Reset

W

RP

WP

Write Protect

Core Power Supply

V

DD

Power Supply for

Input/Output

V

DDQ

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

Optional Supply Voltage for

Fast Program & Erase

V

PP

SS

Ground

NC

Not Connected Internally

5/48

M28R400CT, M28R400CB

Figure 3. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

WP

NC

A17

A

B

C

D

E

F

A13

A14

A15

A16

A11

A10

A8

W

V

A7

A5

A4

A2

A1

A0

PP

RP

A12

A9

A6

A3

DQ11

DQ12

DQ4

DQ2

DQ3

DQ14

DQ15

DQ7

DQ5

DQ6

DQ13

DQ8

DQ9

DQ10

E

V

DQ0

DQ1

V

DDQ

SS

V

SS

DD

G

AI04142

6/48

M28R400CT, M28R400CB

Figure 4. Block Addresses

M28R400CT

Top Boot Block Addresses

M28R400CB

Bottom Boot Block Addresses

3FFFF

3F000

3FFFF

4 KWords

32 KWords

38000

37FFF

Total of 8

4 KWord Blocks

30000

Total of 7

32 KWord Blocks

38FFF

4 KWords

38000

37FFF

32 KWords

30000

0FFFF

32 KWords

4 KWords

08000

07FFF

Total of 7

07000

32 KWord Blocks

Total of 8

0FFFF

4 KWord Blocks

32 KWords

08000

07FFF

00FFF

00000

4 KWords

00000

AI04393

Note: Also see APPENDIX A., Tables 22 and 23 for a full listing of the Block Addresses.

Figure 5. Security Block Memory Map

88h

User Programmable OTP

Unique device number

85h

84h

Parameter Block # 0

81h

80h

Protection Register Lock

2

1

0

AI03523

7/48

M28R400CT, M28R400CB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A17). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Write Bus

operation.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at V_ILand Reset is at V_IHthe device is in active

mode. When Chip Enable is at V_IHthe memory is

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable, E, or Write En-

able, W, whichever occurs first.

state. When Reset is at V_IH, the device is in normal

operation. Exiting reset mode the device enters

read array mode, but a negative transition of Chip

Enable or a change of the address is required to

ensure valid data outputs.

V

_DDSupply Voltage (1.65V to 2.2V). V_DD

provides the power supply to the internal core of

the memory device. It is the main power supply for

all operations (Read, Program and Erase).

V_DDQSupply Voltage (1.65V to 2.2V). V_DDQ

provides the power supply to the I/O pins and en-

ables all Outputs to be powered independently

from V_DD. V_DDQcan be tied to V_DDor can use a

separate supply.

V_PPProgram Supply Voltage. V_PPis both a

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage V_DDand the

Program Supply Voltage V_PPcan be applied in

any order.

If V_PPis kept in a low voltage range (0V to 3.6V)

V_PPis seen as a control input. In this case a volt-

age lower than V_PPLKgives protection against pro-

gram or block erase, while V_PP> V_PP1enables

these functions (see Table 14., DC Characteris-

tics, for the relevant values). V_PPis only sampled

at the beginning of a program or block erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

each block. When Write Protect is at V_IL, the Lock-

Down is enabled and the protection status of the

block cannot be changed. When Write Protect is at

V_IH, the Lock-Down is disabled and the block can

be locked or unlocked. (refer to Table 6., Read

Protection Register and Lock Register).

Reset (RP). The Reset input provides a hard-

ware reset of the memory. When Reset is at V_IL,

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

mized. After Reset all blocks are in the Locked

If V_PPis in the range 11.4V to 12.6V it acts as a

power supply pin. In this condition V_PPmust be

stable until the Program/Erase algorithm is com-

pleted (see Table 16 and 17).

V_SSGround. V_SSis the reference for all voltage

measurements.

Note: Each device in a system should have

V_DD, V_DDQand V_PPdecoupled with a 0.1µF ca-

pacitor close to the pin. See Figure 7., AC Mea-

surement Load Circuit. The PCB track widths

should be sufficient to carry the required V_PP

program and erase currents.

8/48

M28R400CT, M28R400CB

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2., Bus Operations, for a summary.

See Figures 9 and 10, Write AC Waveforms, and

Tables 16 and 17, Write AC Characteristics, for

details of the timing requirements.

Output Disable. The data outputs are high im-

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

pedance when the Output Enable is at V_IH.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at V_IHand the device is in

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

V_IHduring a program or erase operation, the de-

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity even if Chip Enable is Low, V_IL, and the supply

current is reduced to I_DD1. The data Inputs/Out-

puts will still output data if a bus Read operation is

in progress.

Reset. During Reset mode when Output Enable

is Low, V_IL, the memory is deselected and the out-

puts are high impedance. The memory is in Reset

mode when Reset is at V_IL. The power consump-

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

able inputs. If Reset is pulled to V_SSduring a Pro-

gram or Erase, this operation is aborted and the

memory content is no longer valid.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

able must be at V_ILin order to perform a read op-

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see COMMAND INTERFACE section).

See Figure 8., Read AC Waveforms, , and Table

15., Read AC Characteristics, for details of when

the output becomes valid.

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

and Write Enable are at V_ILwith Output Enable at

V_IH. Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

Table 2. Bus Operations

V

Operation

Bus Read

E

G

W

RP

WP

X

DQ0-DQ15

Data Output

Data Input

Hi-Z

PP

V

IH

V

Don't Care

V or V

DD

IL

IH

V

Bus Write

Output Disable

Standby

X

IL

IH

PPH

V

X

Don't Care

IH

V

X

Hi-Z

IH

V

IL

Reset

X

Hi-Z

Note: X = V or V , V = 12V ± 5%.

PPH

IL

IH

9/48

M28R400CT, M28R400CB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time during, to

monitor the progress of the operation, or the Pro-

gram/Erase states. See APPENDIX D., Table 30.,

Write State Machine Current/Next, sheet 1 of 2.,

for a summary of the Command Interface.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V_DDis lower than V_LKO. Com-

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 3., Commands,

in conjunction with the text descriptions below.

cations to automatically match their interface to

the characteristics of the device. One Bus Write

cycle is required to issue the Read Query Com-

mand. Once the command is issued subsequent

Bus Read operations read from the Common

Flash Interface Memory Area. See APPENDIX B.,

COMMON FLASH INTERFACE (CFI), Tables 24,

25, 26, 27, 28 and 29 for details on the information

contained in the Common Flash Interface memory

area.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

Read Memory Array Command

■

The first bus cycle sets up the Erase

command.

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

■

The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Erase aborts if Reset turns to V_IL. As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 7., Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See APPENDIX C., Figure 18., Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

for using the Block Erase command.

Read Status Register Command

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register at any address, until another

command is issued. See Table 10., Status Regis-

ter Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Chip Erase Command

Read Electronic Signature Command

The Chip Erase command can be used to erase

the entire chip. It sets all of the bits in unprotected

blocks of the memory to ’1’. All previous data is

lost. Two Bus Write operations are required to is-

sue the Chip Erase Command.

The Read Electronic Signature command reads

the Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code, the

Block Lock and Lock-Down Status, or the Protec-

tion and Lock Register. See Tables 4, 5 and 6 for

the valid address.

■

The first bus cycle sets up the Chip Erase

command.

■

The second confirms the Chip Erase

command and starts the Program/Erase

Controller.

Read CFI Query Command

The command can be issued to any address. If

any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area, allowing programming equipment or appli-

10/48

M28R400CT, M28R400CB

pears to start but will terminate, leaving the data

unchanged. No error condition is given when pro-

tected blocks are ignored.

During the erase operation the memory will only

accept the Read Status Register command. All

other commands will be ignored, including the

Erase Suspend command. It is not possible to is-

sue any command to abort the operation.

ming aborts if Reset goes to V_IL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See APPENDIX C., Figure 16., Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Chip Erase commands should be limited to a max-

imum of 100 Program/Erase cycles. After 100 Pro-

gram/Erase cycles the internal algorithm will still

operate properly but some degradation in perfor-

mance may occur.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

Typical chip erase times are given in Table 7.

Program Command

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program Command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

Program/Erase Suspend Command

■

The first bus cycle sets up the Program

command.

The second latches the Address and the Data

to be written and starts the Program/Erase

Controller.

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

■

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 7., Program, Erase

Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to V_IL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Block Lock, Block Lock-Down or

Protection Program commands will also be ac-

cepted. The block being erased may be protected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programmed correctly.

See APPENDIX C., Figure 15., Program Flow-

chart and Pseudo Code, for the flowchart for using

the Program command.

Double Word Program Command

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Chip Enable to V_IH. Program/Erase is aborted if

Reset turns to V_IL.

See APPENDIX C., Figure 17., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 19., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Suspend command.

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when V_PPis not at V_PPH. The command can be

executed if V_PPis below V_PPHbut the result is not

guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

Program/Erase Resume Command

■

The first bus cycle sets up the Double Word

Program Command.

The second bus cycle latches the Address and

the Data of the first word to be written.

The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See APPENDIX C., Figure 17., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

Read operations output the Status Register con-

tent after the programming has started. Program-

11/48

M28R400CT, M28R400CB

ure 19., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Resume command.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 9. shows the protection status after issuing

a Block Lock command.

Protection Register Program Command

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, BLOCK LOCK-

ING, for a detailed explanation.

The Protection Register Program command is

used to Program the 64 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Block Unlock Command

Two write cycles are required to issue the Protec-

tion Register Program command.

The Blocks Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock command.

■

The first bus cycle sets up the Protection

Register Program command.

■

The first bus cycle sets up the Block Unlock

command.

■

The second latches the Address and the Data

to be written to the Protection Register and

starts the Program/Erase Controller.

■

The second Bus Write cycle latches the block

address.

Read operations output the Status Register con-

tent after the programming has started.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 9. shows the protection status after issuing

a Block Unlock command. Refer to the section,

BLOCK LOCKING, for a detailed explanation.

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register protects bit 2 of the Protec-

tion Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of the Security Block (see Figure 5., Se-

curity Block Memory Map). Attempting to program

a previously protected Protection Register will re-

sult in a Status Register error. The protection of

the Protection Register and/or the Security Block

is not reversible.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,

or have its protection status changed when WP is

low, V_IL. When WP is high, V_IH,the Lock-Down

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

The Protection Register Program cannot be sus-

pended. See APPENDIX C., Figure 21., Protec-

tion Register Program Flowchart and Pseudo

Code, for the flowchart for using the Protection

Register Program command.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

■

The first bus cycle sets up the Block Lock

command.

■

The second Bus Write cycle latches the block

address.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table 9. shows the protection status

after issuing a Block Lock-Down command. Refer

to the section, BLOCK LOCKING, for a detailed

explanation.

■

The first bus cycle sets up the Block Lock

command.

■

The second Bus Write cycle latches the block

address.

12/48

M28R400CT, M28R400CB

Table 3. Commands

Commands

Bus Write Operations

No. of

Cycles

1st Cycle

2nd Cycle

Addr

3nd Cycle

Addr

Bus

Op.

Bus

Op.

Bus

Op.

Addr Data

Data

Read

Addr

Read Memory Array

Read Status Register

1+

Write

X

FFh

70h

Data

Read

Status

Register

X

Signature

Read Electronic Signature

Read CFI Query

Block Erase

1+

2

Write

X

55h

X

90h

98h

20h

80h

Read

Write

Signature

Query

D0h

(2)

Addr

CFI Addr

Block

Addr

Chip Erase

2

X

D0h

40h or

10h

Data

Input

Program

2

X

Addr

Data

Input

Data

Input

(3)

3

Write

X

30h

Write

Addr 1

Write

Addr 2

Double Word Program

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

1

Write

X

50h

B0h

D0h

Block

Address

Block Lock

2

Write

X

60h

C0h

Write

01h

D0h

2Fh

Block

Address

Block Unlock

Block Lock-Down

Block

Address

Protection Register

Program

Data

Input

Address

Note: 1. X = Don't Care.

2. The signature addresses are listed in Tables 4, 5 and 6.

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 4. Read Electronic Signature

Code

Device

E

G

W

A0

A1

A2-A7

A8-A17

DQ0-DQ7

DQ8-DQ15

Manufacture.

Code

V

IL

V

IL

0

Don't Care

20h

00h

IL

IH

IL

V

M28R400CT

M28R400CB

0

Don't Care

2Ah

2Bh

88h

IL

IH

IL

Device Code

V

IL

IH

Note:

RP = V .

IH

13/48

M28R400CT, M28R400CB

Table 5. Read Block Lock Signature

Block Status

Locked Block

E

G

W

A0

A1 A2-A7

A8-A11

A12-A17

DQ0 DQ1 DQ2-DQ15

V

IL

V

IH

V

0

Don't Care Block Address

1

0

00h

IL

IH

V

Unlocked Block

IL

IH

IL

Locked-Down

Block

(1)

V

0

Don't Care Block Address

1

00h

IL

IH

IL

IH

X

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see BLOCK LOCKING section.

Table 6. Read Protection Register and Lock Register

Word

E

G

W

A0-A7

A8-A17

DQ0

DQ1

DQ2

DQ3-DQ7 DQ8-DQ15

OTP Prot.

data

Security

prot. data

V

Lock

80h Don't Care

0

00h

IL

IH

V

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h Don't Care

82h Don't Care

83h Don't Care

84h Don't Care

ID data

IL

IH

ID data

85h Don't Care OTP data

86h Don't Care OTP data

87h Don't Care OTP data

88h Don't Care OTP data

OTP data

OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

Table 7. Program, Erase Times and Program/Erase Endurance Cycles

M28R400C

Parameter

Test Conditions

Unit

Min

Typ

10

Max

200

5

V

= V

DD

Word Program

µs

PP

V

= 12V ±5%

= V

Double Word Program

Main Block Program

10

µs

PP

0.16

0.32

0.02

0.04

1

s

PP

V

5

s

PP

DD

V

= 12V ±5%

= V

4

s

PP

Parameter Block Program

Main Block Erase

V

4

s

PP

DD

= 12V ±5%

= V

10

s

PP

V

1

s

PP

DD

= 12V ±5%

= V

2

s

PP

Chip Erase (preprogrammed)

Chip Program

V

2

s

PP

DD

= 12V ±5%

= V

1.25

25

s

PP

V

s

PP

DD

= 12V ±5%

= V

0.8

10

s

PP

Parameter Block Erase

V

PP

DD

Program/Erase Cycles (per Block)

100,000

cycles

14/48

M28R400CT, M28R400CB

BLOCK LOCKING

The M28R400C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their lock status cannot be

changed using software commands alone. A

Locked or Unlocked block can be Locked-Down by

issuing the Lock-Down command. Locked-Down

blocks revert to the Locked state when the device

is reset or powered-down.

The Lock-Down function is dependent on the WP

input pin. When WP=0 (V_IL), the blocks in the

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

WP=1 (V_IH) the Lock-Down function is disabled

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be relocked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is low , blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

resets all blocks , including those in Lock-Down, to

the Locked state.

■

Lock/Unlock - this first level allows software-

only control of block locking.

■

Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■

V_PP≤ V_PPLK- the third level offers a hardware

protection against program and block erase on

all blocks.

The lock status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 9., de-

fines all of the possible protection states (WP,

DQ1, DQ0), and APPENDIX C., Figure 20., shows

a flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 5.,

will output the lock status of that block. The lock

status is represented by DQ0 and DQ1. DQ0 indi-

cates the Block Lock/Unlock status and is set by

the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the protection status will be changed. After

completing any desired lock, read, or program op-

erations, resume the erase operation with the

Erase Resume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend. Refer to APPENDIX D., COM-

MAND INTERFACE AND PROGRAM/ERASE

CONTROLLER STATE, for detailed information

on which commands are valid during erase sus-

pend.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

15/48

M28R400CT, M28R400CB

Table 8. Block Lock Status

Item

Address

Data

Block Lock Configuration

LOCK

DQ0=0

DQ0=1

DQ1=1

Block is Unlocked

Block is Locked

xx002

Block is Locked-Down

Table 9. Protection Status

Current

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

Protection Status

(WP, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Allowed

After

WP transition

Current State

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The protection status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block)

as read in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

16/48

M28R400CT, M28R400CB

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

or Output Enable returns to V_IH. Either Chip En-

able or Output Enable must be toggled to update

the latched data.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 10., Status Register Bits. Refer to Table 10.

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

V_PPStatus (Bit 3). The V_PPStatus bit can be

used to identify an invalid voltage on the V_PPpin

during Program and Erase operations. The V_PP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V_PPbecomes invalid during an operation.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V_PP

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

When the V_PPStatus bit is Low (set to ‘0’), the volt-

age on the V_PPpin was sampled at a valid voltage;

when the V_PPStatus bit is High (set to ‘1’), the V_PP

pin has a voltage that is below the V_PPLockout

Voltage, V_PPLK, program and block erase opera-

tions cannot be performed.

Once set High, the V_PPStatus bit can only be reset

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

17/48

M28R400CT, M28R400CB

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to APPENDIX C., FLOWCHARTS

AND PSEUDO CODES, for using the Status

Register.

Table 10. Status Register Bits

Bit

Name

Logic Level

Definition

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

Status

PP

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level '1' is High, '0' is Low.

18/48

M28R400CT, M28R400CB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 11. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–40

–55

–0.5

Max

85

(1)

T

°C

V

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

T

125

155

BIAS

T

STG

V

IO

V

+ 0.5

DDQ

V

, V

DDQ

2.7

13

V

DD

V

PP

Program Voltage

V

t

Time for V at V

PPH

100

hours

VPPH

PP

Note: 1. Depends on range.

19/48

M28R400CT, M28R400CB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 12.,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 12. Operating and AC Measurement Conditions

M28R400CT, M28R400CB

Parameter

90

120

Units

Min

Max

Min

Max

V

Supply Voltage

1.7

2.0

1.65

2.2

V

DD

1.7

2.0

85

1.65

– 40

2.2

85

Supply Voltage (V

≤ V

)

DD

DDQ

Ambient Operating Temperature

– 40

°C

pF

ns

V

Load Capacitance (C )

30

L

Input Rise and Fall Times

Input Pulse Voltages

10

0 to V

DDQ

V

/2

DDQ

V

/2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 6. AC Measurement I/O Waveform

Figure 7. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DDQ

V

0V

DD

25kΩ

AI00610

DEVICE

UNDER

TEST

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI00609C

L

Table 13. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

IN

= 0V

IN

C

V

OUT

12

pF

OUT

Note: Sampled only, not 100% tested.

20/48

M28R400CT, M28R400CB

Table 14. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V≤ V ≤ V

LI

IN

DDQ

I

0V≤ V

≤V

±10

20

µA

LO

OUT DDQ

I

E = V , G = V , f = 5MHz

10

15

mA

DD

SS

IH

E = V

± 0.2V,

Supply Current (Stand-by or

Automatic Stand-by)

DDQ

I

50

20

50

400

µA

DD1

RP = V

± 0.2V

DDQ

Supply Current

(Reset)

I

RP = V ± 0.2V

15

10

5

DD2

SS

Program in progress

mA

µA

V

= 12V ± 5%

PP

I

Supply Current (Program)

Supply Current (Erase)

DD3

Program in progress

= V

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

DD4

Erase in progress

= V

5

V

PP

DD

E = V

± 0.2V,

Supply Current

(Program/Erase Suspend)

DDQ

I

DD5

Erase suspended

Program Current

(Read or Stand-by)

I

PP

V

> V

µA

PP

DD

Program Current

(Read or Stand-by)

I

V

≤ V

5

µA

mA

PP1

DD

I

RP = V ± 0.2V

Program Current (Reset)

PP2

SS

Program in progress

10

V

= 12V ± 5%

PP

I

Program Current (Program)

PP3

Program in progress

= V

5

µA

mA

µA

V

PP

DD

Erase in progress

= 12V ± 5%

10

V

PP

I

Program Current (Erase)

PP4

Erase in progress

= V

5

V

PP

DD

V

Input Low Voltage

Input High Voltage

–0.5

0.4

V

IL

V

–0.4

V

+0.4

DDQ

IH

DDQ

I

= 100µA, V = V min,

DD DD

OL

V

OL

Output Low Voltage

Output High Voltage

0.1

V

= V

min

DDQ

I

= –100µA, V = V min,

DD DD

OH

V

OH

–0.1

DDQ

V

= V

min

DDQ

Program Voltage (Program or

Erase operations)

V

PP1

1.65

2.2

Program Voltage

(Program or Erase

operations)

V

PPH

11.4

12.6

V

Program Voltage

(Program and Erase lock-out)

V

1

2

V

PPLK

V

DD

Supply Voltage (Program

V

LKO

and Erase lock-out)

21/48

M28R400CT, M28R400CB

Figure 8. Read AC Waveforms

tAVAV

VALID

A0-A17

E

tAVQV

tAXQX

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQV

tGHQX

tGHQZ

tGLQX

VALID

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

OUTPUTS

ENABLED

DATA VALID

STANDBY

AI04144b

Table 15. Read AC Characteristics

M28R400C

Symbol

Alt

Parameter

Unit

90

120

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

Max

Min

90

0

ns

AVAV

RC

t

ACC

AVQV

(1)

t

Address Transition to Output Transition

0

t

OH

AXQX

EHQX

EHQZ

(1)

(2)

(1)

(2)

(1)

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

Min

Max

Min

0

25

90

0

ns

t

OH

t

HZ

30

120

0

t

Chip Enable Low to Output Valid

t

CE

ELQV

ELQX

t

LZ

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

t

Min

0

t

OH

GHQX

t

DF

Max

Min

25

30

0

30

35

0

GHQZ

t

OE

GLQV

GLQX

t

OLZ

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV GLQV

ELQV

22/48

M28R400CT, M28R400CB

Figure 9. Write AC Waveforms, Write Enable Controlled

23/48

M28R400CT, M28R400CB

Table 16. Write AC Characteristics, Write Enable Controlled

M28R400C

Symbol

Alt

Parameter

Unit

90

120

50

t

WC

Write Cycle Time

Min

90

50

0

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

AVWH

AS

DS

CS

t

50

DVWH

t

0

ELWL

t

90

0

120

ELQV

(1,2)

Output Valid to V Low

0

t

PP

QVVPL

t

Output Valid to Write Protect Low

0

QVWPL

(1)

t

V

High to Write Enable High

Min

200

0

200

0

ns

t

VPS

PP

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

WHAX

WHDX

WHEH

AH

DH

CH

t

0

t

30

50

30

50

WHEL

WHGL

WHWL

t

WPH

t

WLWH

WP

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 2.2V).

PP

24/48

M28R400CT, M28R400CB

Figure 10. Write AC Waveforms, Chip Enable Controlled

25/48

M28R400CT, M28R400CB

Table 17. Write AC Characteristics, Chip Enable Controlled

M28R400C

Symbol

Alt

Parameter

Unit

90

120

50

0

t

WC

Write Cycle Time

Min

90

50

0

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

AVEH

AS

DS

AH

DH

t

DVEH

t

Chip Enable High to Address Transition

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

EHAX

t

0

EHDX

t

CPH

30

0

30

0

EHEL

t

EHGL

t

WH

EHWH

t

CP

50

90

50

120

ELEH

t

ELQV

(1,2)

Output Valid to V Low

Min

0

ns

t

PP

QVVPL

t

Data Valid to Write Protect Low

QVWPL

(1)

t

V

High to Chip Enable High

PP

200

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

Write Protect High to Chip Enable High

Min

0

ns

WLEL

t

50

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 2.2V).

PP

26/48

M28R400CT, M28R400CB

Figure 11. Power-Up and Reset AC Waveforms

W, E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI03537b

Table 18. Power-Up and Reset AC Characteristics

M28R400C

Symbol

Parameter

Test Condition

Unit

90

120

During

Program and

Erase

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip Enable Low,

Output Enable Low

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

27/48

M28R400CT, M28R400CB

PACKAGE MECHANICAL

Figure 12. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

SD

FE

E1

SE

E

e

ddd

BALL "A1"

e

b

A

A2

A1

BGA-Z13

Note: Drawing is not to scale.

Table 19. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.200

0.0079

1.000

0.0394

0.400

6.390

5.250

0.350

6.290

–

0.450

0.0157

0.2516

0.2067

0.0138

0.2476

–

0.0177

D

6.490

0.2555

D1

ddd

E

–

0.100

0.0039

6.370

0.750

3.750

0.570

1.310

0.375

6.270

6.470

0.2508

0.0295

0.1476

0.0224

0.0516

0.0148

0.2469

0.2547

e

–

E1

FD

FE

SD

SE

28/48

M28R400CT, M28R400CB

Figure 13. TFBGA46 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

AI03860

Figure 14. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package)

1

2

3

4

5

6

7

8

START

POINT

A

B

C

D

E

F

END

POINT

AI03861

29/48

M28R400CT, M28R400CB

PART NUMBERING

Table 20. Ordering Information Scheme

Example:

M28R400CT

120 ZB

6

T

Device Type

M28

Operating Voltage

R = V = 1.65V to 2.2V; V

= 1.65V or 2.2V

DDQ

DD

Device Function

400C = 4 Mbit (256Kb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

90 = 90ns

120 = 120ns

Package

ZB = TFBGA46: 0.75mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

U = Lead-free Package, Tape & Reel Packing, 16mm

Table 21. Daisy Chain Ordering Scheme

Example:

M28R400C

-ZB T

Device Type

M28R400C

Daisy Chain

-ZB = TFBGA46: 0.75 mm pitch

Option

T = Tape & Reel Packing

U = Lead-free Package, Tape & Reel Packing, 16mm

Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc.) or for further information on any aspect of this device, please contact

the ST Sales Office nearest to you.

30/48

M28R400CT, M28R400CB

APPENDIX A. BLOCK ADDRESS TABLES

Table 22. Top Boot Block Addresses,

M28R400CT

Table 23. Bottom Boot Block Addresses,

M28R400CB

Size

(KWord)

Size

(KWord)

#

Address Range

#

Address Range

0

1

4

3F000-3FFFF

3E000-3EFFF

3D000-3DFFF

3C000-3CFFF

3B000-3BFFF

3A000-3AFFF

39000-39FFF

38000-38FFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

14

13

12

11

10

9

32

4

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

2

4

3

4

5

4

6

4

8

7

4

7

8

32

6

4

9

5

4

10

11

12

13

14

4

3

4

2

4

1

4

0

4

31/48

M28R400CT, M28R400CB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 24, 25,

26, 27, 28 and 29 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 29., Security Code Area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 24. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 25. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

Device Code

ST

882Ah

882Bh

Top

Bottom

01h

02h-0Fh

10h

reserved Reserved

0051h

"Q"

"R"

"Y"

11h

0052h

0059h

0003h

0000h

0035h

0000h

Query Unique ASCII String "QRY"

12h

13h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

Intel

compatible

14h

15h

Address for Primary Algorithm extended Query table (see Table 28.)

P = 35h

NA

16h

17h

Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists)

18h

19h

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

1Ah

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

32/48

M28R400CT, M28R400CB

Table 26. CFI Query System Interface Information

Offset

Data

Description

Value

V

Logic Supply Minimum Program/Erase or Write voltage

DD

1Bh

0017h

1.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

DD

1Ch

1Dh

1Eh

0022h

00B4h

00C6h

2.2V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

PP

11.4V

12.6V

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

000Ch

0005h

0003h

16µs

1s

Typical time-out per single word program = 2 µs

n

Typical time-out for Double Word Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

4s

Typical time-out for full chip erase = 2 ms

n

512µs

8s

Maximum time-out for word program = 2 times typical

n

Maximum time-out for Double Word Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

32s

Maximum time-out for chip erase = 2 times typical

33/48

M28R400CT, M28R400CB

Table 27. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0013h

512 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0002h

0000h

n

4

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

2Ch

0002h

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Dh

2Eh

0006h

0000h

Region 1 Information

Number of identical-size erase block = 0006h+1

7

64 KByte

8

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

7

31h

32h

0006h

0000h

Region 2 Information

Number of identical-size erase block = 0006h+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

34/48

M28R400CT, M28R400CB

Table 28. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0067h

0000h

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

"R"

"I"

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Chip Erase supported

(1 = Yes, 0 = No)

Yes

No

Suspend Erase supported

Suspend Program supported

Legacy Lock/Unlock supported

Queued Erase supported

No

Instant individual block locking supported (1 = Yes, 0 = No)

Yes

No

Protection bits supported

Page mode read supported

Synchronous read supported

(1 = Yes, 0 = No)

No

bit 31 to 9 Reserved; undefined bits are ‘0’

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

(P+B)h = 40h

0003h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

(P+C)h = 41h

(P+D)h = 42h

(P+E)h = 43h

0022h

00C0h

0001h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

2.2V

12V

01

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

(P+10)h = 45h

(P+11)h = 46h

(P+12)h = 47h

0080h

0000h

0003h

Protection Field 1: Protection Description

80h

00h

This field describes user-available. One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

8 Byte

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7

Lock/bytes JEDEC-plane physical low address

bit 8 to 15 Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2 = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2 = user programmable bytes

(P+13)h = 48h

Reserved

Note: 1. See Table 25., offset 15 for P pointer definition.

35/48

M28R400CT, M28R400CB

Table 29. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

Data

00XX

XXXX

Description

Protection Register Lock

64 bits: unique device number

64 bits: User Programmable OTP

36/48

M28R400CT, M28R400CB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 15. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

Write 40h or 10h

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

37/48

M28R400CT, M28R400CB

Figure 16. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03539b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

38/48

M28R400CT, M28R400CB

Figure 17. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI03540b

39/48

M28R400CT, M28R400CB

Figure 18. Block Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

40/48

M28R400CT, M28R400CB

Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI03542b

41/48

M28R400CT, M28R400CB

Figure 20. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

Write 60h

writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Write 90h

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI04364

42/48

M28R400CT, M28R400CB

Figure 21. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0xC0) ;

Write C0h

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

43/48

M28R400CT, M28R400CB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER

STATE

Table 30. Write State Machine Current/Next, sheet 1 of 2.

Command Input (and Next State)

Data

When

Read

Block

Erase

Setup

(20h)

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array “1”

Array

Read Array Prog.Setup Ers. Setup

Read Array

Read Sts. Read Array

Read

“1”

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Read

“1”

Electronic

Signature

Program

Setup

Erase

Setup

Read

Read Array

Status

Elect.Sg.

Read CFI

“1”

Program

Setup

Erase

Setup

Read

CFI

Read Array

Status

Query

Lock

(complete)

Lock Cmd

Error

Lock

(complete)

Lock Setup “1”

Status

Lock Command Error

Lock Cmd

“1”

Program

Setup

Erase

Setup

Read

Read Array

Status

Error

Lock

“1”

Program

Setup

Erase

Setup

Read

Read Array

Status

(complete)

Prot. Prog.

“1”

Protection Register Program

Protection Register Program continue

Setup

Prot. Prog.

“0”

(continue)

Prot. Prog.

“1”

Program

Setup

Erase

Setup

Read

Status

Read Array

Program

Read Array

Status

(complete)

Prog. Setup “1”

Program

“0”

Prog. Sus

Read Sts

Program (continue)

(continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

Status

Array

Status

(continue) Read Array (continue)

Program Prog. Sus Program

(continue) Read Array (continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Prog. Sus Prog. Sus

Read Sts Read Array

Read Array

Prog. Sus

Read

Elect.Sg.

Electronic Prog. Sus

Signature Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

(continue) Read Array (continue)

Prog. Sus

Read CFI

Prog. Sus

CFI

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

“0”

Read Array

(continue) Read Array (continue)

Program

(complete)

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

BlockErase

Setup

Erase

Erase Command Error

(continue) CmdError (continue)

BlockErase

Cmd.Error

Program

Setup

Erase

Setup

Read

Read Array

Status

BlockErase

(continue)

Erase Sus

Read Sts

Block Erase (continue)

BlockErase

Sus Read

Sts

Erase Sus

Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Status

Array

Read Array (continue) Read Array (continue)

BlockErase

Sus Read

Array

Erase Sus

Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

Read Array (continue) Read Array (continue)

BlockErase

Sus Read

Elect.Sg.

Electronic Erase Sus

Signature Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

Read Array (continue) Read Array (continue)

44/48

M28R400CT, M28R400CB

Command Input (and Next State)

Data

When

Read

Block

Erase

Setup

(20h)

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

BlockErase

Sus Read

CFI

Erase Sus

Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

CFI

Read Array (continue) Read Array (continue)

BlockErase

(complete)

Program

Setup

Erase

Read

“1”

“0”

“1”

Status

Read Array

Setup

Read Array

Status

Chip Erase

Setup

Chip Erase

(continue)

Chip Erase Command Error

Chip Erase

Cmd.Error

Program

Setup

Erase

Setup

Read

Status

Read Array

Erase (continue)

Read Array

Chip Erase

(continue)

Chip Erase

(complete)

Program

Setup

Erase

Setup

Read

Status

Read Array

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

Table 31. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Read

Elect.Sg.

(90h)

Read CFI

Query

(98h)

Lock

Confirm

(01h)

Lock Down

Confirm

(2Fh)

Unlock

Confirm

(D0h)

Chip Erase

Set Up

Current State

Lock Setup

(60h)

Prot. Prog.

Setup (C0h)

(80h)

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Read Array

Read Status

Lock Setup

Read Array

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Read Elect.Sg.

Read CFI Query

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Lock

Command

Error

Lock Setup

Lock Command Error

Lock (complete)

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Lock Cmd Error

Lock (complete)

Lock Setup

Read Array

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Prot. Prog.

Setup

Protection Register Program

Prot. Prog.

(continue)

Protection Register Program (continue)

Prot. Prog.

(complete)

Read

Elect.Sg.

Read CFI

Query

Chip Erase

Set Up

Lock Setup

Read Array

Setup

Prog. Setup

Program

(continue)

Program (continue)

Prog.

Suspend

Read

Prog.

Suspend

Read CFI

Query

Program

Suspend

Read Array

Prog. Suspend

Read Status

Program

(continue)

Program Suspend Read Array

Elect.Sg.

Prog.

Suspend

Read

Prog.

Suspend

Read CFI

Query

Program

Suspend

Read Array

Prog. Suspend

Read Array

Program

(continue)

Program Suspend Read Array

Elect.Sg.

45/48

M28R400CT, M28R400CB

Command Input (and Next State)

Lock

Read

Elect.Sg.

(90h)

Read CFI

Query

(98h)

Lock Down

Confirm

(2Fh)

Unlock

Confirm

(D0h)

Chip Erase

Set Up

Current State

Lock Setup

Prot. Prog.

Setup (C0h)

Confirm

(01h)

(60h)

(80h)

Prog.

Suspend

Read

Prog.

Suspend

Read CFI

Query

Program

Suspend

Read Array

Prog. Suspend

Read Elect.Sg.

Program

(continue)

Program Suspend Read Array

Elect.Sg.

Prog.

Suspend

Read

Prog.

Suspend

Read CFI

Query

Program

Suspend

Read Array

Prog. Suspend

Read CFI

Program

(continue)

Elect.Sg.

Program

(complete)

Read

Elect.Sg.

Read

CFIQuery

Prot. Prog.

Setup

Chip Erase

Set Up

Lock Setup

Read Array

Block Erase

Command

Error

Block Erase

Setup

Erase

(continue)

Block Erase Command Error

Block Erase

Cmd.Error

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Lock Setup

Chip Erase

Set Up

Setup

Block Erase

(continue)

Block Erase (continue)

Erase

Suspend

Read

Erase

Suspend

Read CFI

Query

Block Erase

Suspend

Read Status

Erase

Suspend

Read Array

Erase

(continue)

Lock Setup

Erase Suspend Read Array

Elect.Sg.

Erase

Suspend

Read

Erase

Suspend

Read CFI

Query

Block Erase

Suspend Read

Array

Erase

Suspend

Read Array

Erase

(continue)

Erase Suspend Read Array

Elect.Sg.

Erase

Suspend

Read

Erase

Suspend

Read CFI

Query

Block Erase

Suspend Read

Elect.Sg.

Erase

Suspend

Read Array

Erase

(continue)

Elect.Sg.

Erase

Suspend

Read

Erase

Suspend

Read CFI

Query

Block Erase

Suspend Read

CFI Query

Erase

Suspend

Read Array

Erase

(continue)

Lock Setup

Elect.Sg.

Block Erase

(complete)

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Read Array

Chip Erase

Command

Error

Chip Erase

Setup

Erase

(continue)

Chip Erase Command Error

Chip Erase

Cmd.Error

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Lock Setup

Chip Erase

Set Up

Read Array

Setup

Chip Erase

(continue)

Chip Erase (continue)

Chip Erase

(complete)

Read

Elect.Sg.

Read CFI

Query

Prot. Prog.

Setup

Chip Erase

Set Up

Lock Setup

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

46/48

M28R400CT, M28R400CB

REVISION HISTORY

Table 32. Document Revision History

Date

Version

-01

Revision Details

January 2001

20-Feb-2001

First Issue

-02

Chip Erase Command added

TFBGA package connections modified

TFBGA package mechanical data and outline drawing modified

TFBGA package daisy chain drawings modified

27-Jul-2001

-03

Completely rewritten and restructured, document status changed to Preliminary

Data.

05-Mar-2002

03-Mar-2003

-04

4.1

Document status changed to Data Sheet

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 04 equals 4.0). Revision History moved to end of document.

90ns Speed Class added. Chip Erase cycles limited to 100,000. t

parameter

VPPH

added to Table 11, Absolute Maximum Ratings.

15-Jun-2004

5.0

Package specifications updated. U option added to Table 20., Ordering Information

Scheme and Table 21., Daisy Chain Ordering Scheme.

47/48

M28R400CT, M28R400CB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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48/48


型号：	M28R400CT120ZB6
厂家：	ST
描述：	4 Mbit (256Kb x16, Boot Block) 1.8V Supply Flash Memory 4兆位（ 256Kb的X16 ，引导块） 1.8V供应快闪记忆体闪存存储内存集成电路
文件：	总48页 (文件大小：864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M28R400CT120ZB6 [STMICROELECTRONICS]

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