M28V420-180M1TR [STMICROELECTRONICS]
512KX8 FLASH 12V PROM, 180ns, PDSO44, 0.525 INCH, PLASTIC, SO-44;
| 型号： | M28V420-180M1TR |
| 厂家： | 
ST |
| 描述： | 512KX8 FLASH 12V PROM, 180ns, PDSO44, 0.525 INCH, PLASTIC, SO-44 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总27页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28V410
M28V420
LOW VOLTAGE
4 Megabit (x8 or x16, Block Erase) FLASH MEMORY
PRODUCT PREVIEW
DUAL x8 and x16 ORGANIZATION
SMALL SIZE PLASTIC PACKAGESTSOP56
and SO44
MEMORY ERASE in BLOCKS
44
– One 16K Byte or 8K Word Boot Block (top or
bottom location) with hardware write and
erase protection
1
– Two 8K Byte or 4K Word Key Parameter
Blocks
– One 96K Byte or 48K Word Main Block
– Three 128K Byte or 64K Word Main Blocks
3.3V ± 0.3V SUPPLY VOLTAGE
SO44 (M)
TSOP56 (N)
14 x 20mm
12V ± 10% or 5% PROGRAMMING VOLTAGE
10,000 PROGRAM/ERASE CYCLES
PROGRAM/ERASE CONTROLLER
AUTOMATIC STATIC MODE
Figure 1. Logic Diagram
LOW POWER CONSUMPTION
– 2mA Typical in Static Operation
– 55µA Typical in Standby
– 0.2µA Typical in Deep Power Down
– 15/20mATypical Operating Consumption
(Byte/Word)
HIGH SPEED ACCESS TIME: 120ns
EXTENDED TEMPERATURE RANGES
V
CC
V
PP
18
DQ15A-1
A0-A17
15
RP
W
E
DQ0-DQ14
BYTE
M28V410
M28V420
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7
Data Input / Outputs
DQ8-
DQ14
Data Input / Outputs
G
DQ15A-1
E
Data Input/Output or Address Input
Chip Enable
V
SS
G
Output Enable
AI01408
W
Write Enable
BYTE
RP
Byte/Word Organization
Reset/Power Down/Boot Block Unlock
Program & Erase Supply Voltage
Supply Voltage
VPP
VCC
December 1994
1/27
This is preliminary informationon a new product now in development.Detailsare subjectto change without notice.
M28V410, M28V420
Figure 2A. TSOP Pin Connections
Figure 2B. SO Pin Connections
NC
NC
A15
A14
A13
A12
A11
A10
A9
1
56
NC
A16
BYTE
V
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
PP
V
SS
DU
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
2
W
DQ15A-1
3
A8
DQ7
4
A9
DQ14
DQ6
5
A10
A11
A12
A13
A14
A15
A16
BYTE
6
DQ13
DQ5
7
A8
8
NC
NC
W
DQ12
DQ4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
V
CC
CC
M28V410
M28V420
(Normal)
M28V410
M28V420
RP
NC
NC
14
15
43
42
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
V
SS
DQ15A-1
SS
G
V
PP
DU
DQ0
DQ8
DQ7
DQ14
DQ6
NC
A17
A7
DQ1
DQ9
DQ13
DQ5
DQ2
A6
DQ10
DQ3
DQ12
DQ4
A5
A4
V
E
SS
DQ11
V
CC
A3
AI01410
A2
A0
A1
NC
NC
NC
28
29
AI01409
Warning: NC = Not Connected, DU = Don’t Use
Warning: DU = Don’t Use
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
grade 1
grade 3
grade 6
0 to 70
–40 to 125
–40 to 85
°C
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
–50 to 125
–65 to 150
–0.6 to 7
°C
°C
V
(2, 3)
VIO
VCC
–0.6 to 7
V
(2)
VA9
A9 Voltage
–0.6 to 13.5
V
Program Supply Voltage, during Erase
or Programming
(2)
VPP
–0.6 to 14
V
(2)
VRP
RP Voltage
–0.6 to 13.5
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Maximum DC voltage on I/O is VCC + 0.5V, overshoot to 7V allowed for less than 20ns.
2/27
M28V410, M28V420
Table 3. Operations
Operation
Read Word
Read Byte
E
G
VIL
VIL
VIH
VIH
VIH
X
W
VIH
VIH
VIL
VIL
VIH
X
RP
VIH
VIH
VIH
VIH
VIH
VIH
VIL
BYTE
VIH
VIL
VIH
VIL
X
DQ0 - DQ7
Data Output
Data Output
Data Input
Data Input
Hi-Z
DQ8 - DQ14
DQ15A-1
Data Output
Address Input
Data Input
Address Input
Hi-Z
VIL
VIL
VIL
VIL
VIL
VIH
X
Data Output
Hi-Z
Write Word
Write Byte
Data Input
Hi-Z
Output Disable
Standby
Hi-Z
X
Hi-Z
Hi-Z
Hi-Z
Power Down
X
X
X
Hi-Z
Hi-Z
Hi-Z
Note: X = VIL or VIH, VPP = VPPL or VPPH
Table 4. Electronic Signature
Organis
ation
A1-A8 &
A10-A17
DQ0 -
DQ7
DQ8 - DQ15
Code
Device
E
G
W
BYTE A0 A9
DQ14
A-1
Manufact.
Code
Don’t
Care
VIL VIL VIH
VIL VIH
VIH
VIH
VIH
VIL
VIL VID
VIH VID
20h
0F3h
0FBh
20h
00h
0
Word-
wide
Don’t
Care
M28V410 VIL
00h
00h
Hi-Z
Hi-Z
Hi-Z
0
0
Device
Code
VIL VIH
VIH VID
Don’t
Care
M28V420 VIL
Manufact.
Code
Don’t
Care
Don’t
Care
VIL VIL VIH
VIL VIH
VIL VID
VIH VID
Byte-
wide
Don’t
Care
Don’t
Care
M28V410 VIL
VIL
VIL
0F3h
0FBh
Device
Code
VIL VIH
VIH VID
Don’t
Care
Don’t
Care
M28V420 VIL
Note: RP = VIH
DESCRIPTION
BYTE is Low and the x8 organizationis selected,
the Data Input/Outputsignal DQ15 actsasAddress
line A-1 and selects the lower or upper byte of the
memory word for output on DQ0-DQ7, DQ8-DQ14
remain high impedance. When BYTE is High the
memory uses the Address inputs A0-A17 and the
Data Input/OutputsDQ0-DQ15. Memory control is
provided by Chip Enable, Output Enableand Write
Enable inputs. A Reset/Power Down/Boot block
unlock, tri-level input, places the memory in deep
power down, normal operation or enables pro-
gramming and erasure of the Boot block.
The M28V410 and M28V420FLASH MEMORIES
are non-volatile memories that may be erased
electrically at the block level and programmed by
byte or word. The interface is directly compatible
with most microprocessors. SO44 and TSOP56
packages are used.
Organization
The organization, as 512K x 8 or 256K x 16, is
selectable by an external BYTE signal. When
3/27
M28V410, M28V420
Table 5. Instructions
1st Cycle
2nd Cycle
Address
Mnemo
Instruction
nic
Cycles
Operation Address (1)
Data (4)
Operation
Data
Read
Memory
Array
Read
RD
1+
1+
3
Write
Write
Write
X
X
X
0FFh
Read (2)
Data
Address
Read
Status
Register
Status
Register
RSR
RSIG
70h
90h
Read (2)
Read (2)
X
Read
Electronic
Signature
Signature
Adress (3)
Signature
Block
Address
EE
PG
Erase
2
2
Write
Write
X
X
20h
Write
Write
0D0h
Program
40h or 10h
Address
Data Input
Clear
Status
Register
CLRS
1
Write
X
50h
Erase
Suspend
ES
ER
1
1
Write
Write
X
X
0B0h
0D0h
Erase
Resume
Notes: 1. X = Don’t Care.
2. The first cycle of the RD, RSR or RSIG instruction is followed by read operations toread memory array, Status Register
or Electronic Signature codes. Any number of Read cycle can occur after one command cycle.
3. Signature address bit A0=VIL will output Manufacturer code. Address bit A0=VIH will output Device code. Other address bits are
ignored.
4. When word organization is used, upper byte is don’t care for command input.
Block’of 96K Bytes or 48K Words, and three ’Main
Blocks’of 128KBytesor64KWords. TheM28V410
memory has the Boot Block at thetop of the mem-
ory address space (3FFFFh) and the M28V420
locates the Boot Block starting at the bottom
(00000h). Erasure of each block takes typically 1
second and each block can be programmed and
erased over 10,000 cycles.
Table 6. Commands
Hex Code
Command
00h
10h
Invalid/Reserved
Alternative Program Set-up
Erase Set-up
20h
40h
Program Set-up
The Boot Block is hardware protected from acci-
dental programming or erasure depending on the
RP signal. Program/Erase commands in the Boot
Block are executed only when RP is at 12V. Block
erasure may be suspendedwhile data is read from
other blocks of the memory, then resumed.
50h
Clear Status Register
Read Status Register
Read Electronic Signature
Erase Suspend
70h
90h
Bus Operations
0B0h
0D0h
0FFh
Sixoperationscan beperformedbytheappropriate
bus cycles, Read Byte or Word from the Array,
Read Electronic Signature, Output Disable,
Standby,Power Down and Write the Command of
an Instruction.
Erase Resume/Erase Confirm
Read Array
Blocks
Command Interface
Erasure of the memories is in blocks. There are 7
blocks in the memory address space, one Boot
Blockof 16K Bytesor 8K Words, two ’Key Parame-
ter Blocks’ of 8K Bytes or 4K Words, one ’Main
Commands can be written toa CommandInterface
(C.I.) latch to perform read, programming, erasure
and to monitor the memory’s status. When power
4/27
M28V410, M28V420
Table 7. Status Register
Mnemon
Logic
Level
Bit
Name
Definition
Ready
Note
ic
’1’
’0’
’1’
Indicates the P/E.C. status, check during Program
or Erase, and on completion before checking bits
b4 or b5 for Program or Erase Success
P/ECS
7
P/E.C. Status
Busy
Suspended
Erase
Suspend
Status
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until an
Erase Resume instruction is given.
ESS
ES
6
5
4
3
In progress or
Completed
’0’
’1’
’0’
’1’
Erase Error
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
Erase Status
Erase Success
Program Error
Program
Status
PS bit set to ’1’ if the P/E.C. has failed to program
a byte or word.
PS
Program
Success
’0’
’1’
’0’
V
PP Low, Abort
VPPS bit is set if the VPP voltage is below
PPH(min) when a Program or Erase instruction
VPPS
VPP Status
V
has been executed.
VPP OK
2
1
0
Reserved
Reserved
Reserved
Notes: Logic level ’1’ is High, ’0’ is Low.
is first applied, on exit from power down or if VCC
falls below VLKO, the command interface is reset to
Read Memory Array.
word programmingtakes typically9µs, blockerase
typically 1 second. Erasureof a memory block may
be suspended in order to read data from another
block and then resumed. AStatusRegister may be
read atany time, including duringthe programming
or erase cycles, to monitor the progress of the
operation.
Instructions and Commands
Eight Instructions are defined to perform Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, Erase, Program, Clear Status
Register, Erase Suspend and Erase Resume. An
internalProgram/EraseController(P/E.C.) handles
all timing and verificationof the Programand Erase
instructions and provides status bits to indicate its
operation and exit status. Instructions are com-
posed of a first command write operation followed
by either second command write, to confirm the
commands for programming or erase, or a read
operationtoread datafromthe array,theElectronic
Signatureor the Status Register.
Power Saving
The M28V410 and M28V420 have a number of
power saving features. Following a Read access
the memory enters a static mode in which the
supply current is typically 2mA. A CMOS standby
mode is entered when the Chip Enable E and the
Reset/PowerDown (RP) signals are at VCC, when
the supply current drops to typically 60µA. Adeep
power down mode is enabled when the Re-
set/Power Down (RP) signal is at VSS, when the
supply current drops to typically 0.2µA. The time
requiredto awakefromthedeeppowerdownmode
is 700ns maximum, with instructions to the C.I.
recognised after only 580ns.
For added data protection, the instructions for byte
or word program and block erase consist of two
commands that are written to the memory and
which start the automaticP/E.C. operation.Byte or
5/27
M28V410, M28V420
Table 8. AC Measurement Conditions
SRAM Interface Levels
EPROM Interface Levels
≤ 10ns
Input Rise and Fall Times
≤ 10ns
0 to 3V
1.5V
Input Pulse Voltages
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
EPROM Interface
C
2.4V
L
2.0V
0.8V
0.45V
C
C
C
= 30pF for SRAM Interface
L
L
L
AI01275
= 100pF for EPROM Interface
includes JIG capacitance
AI01276
Table 9. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
Unit
pF
6
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
Signal Descriptions
DQ0-DQ7 Data Input/Outputs. The data inputs, a
byte or the lower byte of a word to be programmed
or a command to the C.I., are latched when both
ChipEnable E and Write EnableW are active. The
data output from the memory Array, the Electronic
Signature or Status Register is valid when Chip
Enable E and Output Enable G are active. The
output is high impedance when the chip is dese-
lected or the outputs are disabled.
A0-A17 Address Inputs. The address signals,
inputs for the memory array, are latched during a
write operation.
A9 Address Input is also used for the Electronic
SignatureOperation. When A9 is raised to 12V the
Electronic Signature may be read.The A0signal is
used to read two words or bytes, when A0 is Low
the Manufacturercode is read and when A0 isHigh
the Device code. When BYTE is Low DQ0-DQ7
output the codes and DQ8-DQ15 are don’t care,
when BYTE is High DQ0-DQ7 output the codes
and DQ8-DQ15 output 00h.
DQ8-DQ14 and DQ15A-1 Data Input/Outputs.
These input/outputs are used in the word-wide
organization. When BYTE is High for the most
significant byte of the input or output, functioning
as described for DQ0-DQ7 above. When BYTE is
Low, DQ8-DQ14 are high impedance, DQ15A-1 is
the Address A-1 input.
6/27
M28V410, M28V420
Table 10. DC Characteristics
(TA = 0 to70°C; VCC = 3.3V ± 0.3V;VPP = 12V±5% or 12V±10%)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±1
Unit
µA
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±10
40
45
35
40
3
µA
(1, 3)
ICC
Supply Current (Read Byte-wide) TTL
Supply Current (Read Word-wide) TTL
Supply Current (Read Byte-wide) CMOS
Supply Current (Read Word-wide) CMOS
Supply Current (Standby) TTL
E = VIL, G = VIL, f = 5MHz
E = VIL, G = VIL, f = 5MHz
E = VSS, G = VSS, f = 5MHz
E = VSS, G = VSS, f = 5MHz
E = VIH, RP = VIH
mA
mA
mA
mA
mA
(1, 3)
ICC
(1, 3)
ICC
(3)
ICC1
E = VCC ± 0.2V,
RP = VCC ± 0.2V,
Supply Current (Standby) CMOS
150
µA
BYTE = VCC ± 0.2V or VSS
(3)
ICC2
Supply Current (Power Down)
Supply Current (Program Byte-wide)
Supply Current (Program Word-wide)
Supply Current (Erase)
RP = VSS ± 0.2V
Byte program in progress
Word program in progress
Erase in progress
5
50
60
30
10
200
µA
mA
mA
mA
mA
µA
ICC3
ICC4
(2)
ICC5
Supply Current (Erase Suspend)
Program Current (Read or Standby)
E = VIH, Erasesuspended
VPP > VCC
IPP
Program Leakage Current (Read or
Standby)
IPP1
V
PP ≤ VCC
±15
µA
IPP2
IPP3
IPP3
IPP4
IPP5
VIL
Program Current (Power Down)
Program Current (Program Byte-wide)
Program Current (Program Word-wide)
Program Current (Erase)
RP = VSS ± 0.2V
Byte program in progress
Word program in progress
Erase in progress
5
30
µA
mA
mA
mA
µA
V
40
30
Program Current (Erase Suspend)
Input Low Voltage
Erase suspended
200
0.6
–0.5
2
VIH
Input High Voltage
VCC + 0.5
0.4
V
VOL
VOH
VPPL
Output Low Voltage
IOL = 2mA
V
Output High Voltage
IOH = –2mA
2.4
0
V
Program Voltage (Normal operation)
4.1
V
Program Voltage (Program or Erase
operations) 5% range
11.4
12.6
V
V
VPPH
Program Voltage (Program or Erase
operations) 10% range
10.8
11.4
13.2
VID
IID
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
13
V
A9 = VID
500
µA
Supply Voltage (Erase and Program lock-
out)
VLKO
VHH
2
V
V
Input Voltage (RP, Boot unlock)
Boot block Program or Erase
11.4
13
Notes: 1. Automatic Power Saving reduces ICC to ≤ 2mA typical in static operation.
2. Current increases to ICC + ICC5 during a read operation.
3. CMOS levels VCC ± 0.2V and VSS ± 0.2V. TTL levels VIH and VIL.
7/27
M28V410, M28V420
Table 11. Read AC Characteristics
(TA = 0 to70°C; VCC = 3.3V ± 0.3V;VPP = 12V±5% or 12V±10%)
M28V410 / 420
-150
-120
-180
Symbol
Alt
Parameter
Test Condition
Unit
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
Address Valid to
Next Address Valid
tAVAV
tAVQV
tPHQV
tRC
tACC
tPWH
tLZ
E = VIL, G = VIL
E = VIL, G = VIL
E = VIL, G = VIL
G = VIL
120
150
180
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to
Output Valid
120
700
150
700
180
700
Power Down High
to Output Valid
(1)
Chip Enable Low to
Output Transition
tELQX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chip Enable Low to
Output Valid
(2)
tELQV
tCE
G = VIL
120
60
150
65
180
70
Output Enable Low
to Output Transition
(1)
tGLQX
tOLZ
tOE
tOH
tHZ
E = VIL
Output Enable Low
to Output Valid
(2)
tGLQV
E = VIL
Output Enable High
to Output Transition
tEHQX
G = VIL
Chip Enable High
to Output Hi-Z
(1)
tEHQZ
G = VIL
50
55
60
Output Enable High
to Output Transition
tGHQX
tOH
tDF
E = VIL
Output Enable High
to Output Hi-Z
(1)
tGHQZ
E = VIL
45
50
55
Address Transition
to Output Transition
tAXQX
tOH
E = VIL, G = VIL
Notes: 1. Sampled only, not 100% tested.
2. G may bedelayed by up to tELQV - tGLQV after the fallingedge of E without increasing tELQV
.
8/27
M28V410, M28V420
Figure 5. Read Mode AC Waveforms
9/27
M28V410, M28V420
Table 12. Write AC Characteristics,Write Enable Controlled
(TA = 0 to70°C; VCC = 3.3V ± 0.3V;VPP = 12V±5% or 12V±10%)
M28V410 / 420
-150
-120
-180
Symbol
Alt
Parameter
Unit
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
tAVAV
tWC Write Cycle Time
120
1
150
180
1
ns
Power Down High to Write Enable
Low
tPHWL
tPS
tCS
tWP
1
0
µs
Chip Enable Low to Write Enable
Low
tELWL
0
0
ns
Write Enable Low to Write Enable
High
tWLWH
tDVWH
tWHDX
100
100
0
100
100
0
100
100
0
ns
ns
ns
tDS Input Valid to Write Enable High
Write Enable High to Input
Transition
tDH
Write Enable High to Chip Enable
High
tWHEH
tCH
10
10
10
ns
Write Enable High to Write Enable
tWHWL
tAVWH
tWPH
Low
50
95
50
95
50
95
ns
ns
ns
ns
ns
tAS Address Validto Write Enable High
Power Down VHH (Boot Block
tPHS
tPHHWH
tVPHWH
tWHAX
200
200
10
200
200
10
200
200
10
Unlock) to Write Enable High
tVPS VPP High to Write Enable High
Write Enable High to Address
Transition
tAH
Write Enable High to Output Valid
(Word/Byte Program)
(1, 2)
tWHQV1
6
6
6
µs
(1, 2)
(1)
Write Enable High to Output Valid
(Boot Block Erase)
tWHQV2
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
sec
sec
sec
Write Enable High to Output Valid
(Parameter Block Erase)
tWHQV3
tWHQV4
tQVPH
Write Enable High to Output Valid
(Main Block Erase)
(1)
Output Validto Reset/Power Down
High
tPHH
0
0
0
0
0
0
ns
ns
ns
tQVVPL
Output Validto VPP Low
Reset/Power Down High to Boot
Block Relock
(3)
tPHBR
200
200
200
Notes: 1. Time is measured to Status Register Read giving bit b7 =’1’.
2. For Program or Erase of the Boot Block RP must be at VHH
.
3. Time required for Relocking the Boot Block.
10/27
M28V410, M28V420
Figure 6. Program & Erase AC Waveforms, W Controlled
11/27
M28V410, M28V420
Table 13. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to70°C; VCC = 3.3V ± 0.3V;VPP = 12V±5% or 12V±10%)
M28V410 / 420
-150
-120
-180
Symbol
Alt
Parameter
Unit
SRAM
Interface
EPROM
Interface
EPROM
Interface
Min
Max
Min
Max
Min
Max
tAVAV
tPHEL
tWC
tPS
Write Cycle Time
120
1
150
180
1
ns
Power Down High to Chip
Enable Low
1
0
µs
Write Enable Low to Chip
Enable Low
tWLEL
tCS
0
0
ns
Chip Enable Low to Chip Enable
High
tELEH
tDVEH
tEHDX
tWP
tDS
tDH
100
100
0
100
100
0
100
100
0
ns
ns
ns
Input Valid to Chip Enable High
Chip Enable High to Input
Transition
Chip Enable High to Write
Enable High
tEHWH
tEHEL
tAVEH
tCH
tWPH
tAS
10
50
95
10
50
95
10
50
95
ns
ns
ns
Chip Enable High to Chip
Enable Low
Address Valid to Chip Enable
High
Power Down VHH (Boot Block
Unlock) to Chip Enable High
tPHHEH
tVPHEH
tEHAX
tPHS
tVPS
tAH
200
200
10
200
200
10
200
200
10
ns
ns
ns
VPP High to Chip Enable High
Chip Enable High to Address
Transition
Chip Enable High to Output
Valid (Word/Byte Program)
(1, 2)
tEHQV1
6
6
6
µs
Chip Enable High to Output
Valid (Boot Block Erase)
(1, 2)
tEHQV2
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
sec
sec
sec
Chip Enable High to Output
Valid (Parameter Block Erase)
(1)
tEHQV3
Chip Enable High to Output
Valid (Main Block Erase)
(1)
tEHQV4
Output Valid to Reset/Power
Down High
tQVPH
tPHH
0
0
0
0
0
0
ns
ns
ns
tQVVPL
Output Valid to VPP Low
Reset/Power Down High to Boot
Block Relock
(3)
tPHBR
200
200
200
Note: 1. Time is measured to Status Register Read giving bit b7 =’1’.
2. For Program or Erase of the Boot Block RP must be at VHH
.
3. Time required for Relocking the Boot Block.
12/27
M28V410, M28V420
Figure 7. Program & Erase AC Waveforms, E Controlled
13/27
M28V410, M28V420
Table 14. Word/Byte Program, Erase Times
(TA = 0 to70°C; VCC = 3.3V ± 0.3V)
M28V410 / 420
Parameter
Test Conditions
Unit
Min
Typ
1.2
0.6
1
Max
4.2
2.1
7
Main Block Program (Byte)
Main Block Program (Word)
Boot or Parameter Block Erase
Main Block Erase
V
PP = 12V ±5%
sec
sec
sec
sec
sec
sec
sec
sec
VPP = 12V ±5%
V
V
PP = 12V ±5%
PP = 12V ±5%
2.4
6
14
20
10
40
60
Main Block Program (Byte)
Main Block Program (Word)
Boot or Parameter Block Erase
Main Block Erase
VPP = 12V ±10%
VPP = 12V ±10%
VPP = 12V ±10%
VPP = 12V ±10%
3
5.8
14
DEVICE OPERATION (cont’d)
DQ8-DQ14 are high impedance. When BYTE is
High the memory is organized x16 and data in-
put/output uses DQ0-DQ15 with the memory ad-
dressed by A0-A17.
E Chip Enable. The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High de-selects the memory
and reducesthe powerconsumptiontothe standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Both addressesand data
inputs are then latched on the rising edge of E.
VPP ProgramSupply Voltage. Thissupply voltage
is used for memory Programming and Erase.
V
PP ±10% tolerance option is provided for applica-
tion requiringmaximum 100writeanderase cycles.
VCC Supply Voltage. It is the main circuit supply.
RP Reset/Power Down. This is a tri-level input
which locks the Boot Block from programmingand
erasure, and allows the memory to be put in deep
power down.
VSS Ground. It is the reference for all voltage
measurements.
Memory Blocks
When RP is High (up to 6.5V maximum) the Boot
Block is locked and cannot be programmed or
erased. When RP is above 11.4V the Boot Block is
unlockedforprogrammingorerasure.WithRPLow
the memory is in deep power down, and if RP is
within VSS+0.2V the lowest supply current is ab-
sorbed.
The memoryblocks ofthe M28V410and M28V420
are shown in Figure 8. The difference between the
two productsissimply aninversionoftheblockmap
to position the Boot Block at the top or bottom of
the memory. The selectionof the Boot Block at the
top or bottom of the memory depends on the
microprocessor needs.
G Output Enable. The Output Enable gates the
outputs through the data buffers during a read
operation.
Each block of the memory can be erased sepa-
rately, but only by one block at a time. The erase
operation is managed by the P/E.C. but can be
suspended in orderto read from another block and
then resumed.
W Write Enable. It controls writing to the Com-
mand Register and Input Address and Data
latches. Both Addresses and Data Inputs are
latched on the rising edge of W.
Programming and erasure of the memory is dis-
abled when the program supply is at VPPL. For
successful programming and erasure the program
BYTE Byte/Word Organization Select. Thisinput
selects either byte-wide or word-wide organization
of the memory. When BYTEis Low the memory is
organized x8 or byte-wide and data input/output
uses DQ0-DQ7 while A-1 acts as the additional,
LSB, of the memory address that multiplexes the
upper or lower byte. In the byte-wide organization
supply must be at VPPH
.
The BootBlockprovides additionalhardwaresecu-
rity by use of the RP signal which must be at VHH
before any program or erase operation will be
executed by the P/E.C. on the Boot Block.
14/27
M28V410, M28V420
Figure 8. Memory Map, Word-wide Addresses
M28V410 TOP BOOT BLOCK
M28V420 BOTTOM BOOT BLOCK
A0-A17
3FFFFh
Word Wide
A0-A17
3FFFFh
Word Wide
8K BOOT BLOCK
64K MAIN BLOCK
3E000h
3DFFFh
30000h
2FFFFh
4K PARAMETER BLOCK
4K PARAMETER BLOCK
48K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
3D000h
3CFFFh
20000h
1FFFFh
3C000h
3BFFFh
10000h
0FFFFh
48K MAIN BLOCK
30000h
2FFFFh
04000h
03FFFh
64K MAIN BLOCK
4K PARAMETER BLOCK
4K PARAMETER BLOCK
8K BOOT BLOCK
20000h
1FFFFh
03000h
02FFFh
64K MAIN BLOCK
10000h
0FFFFh
02000h
01FFFh
64K MAIN BLOCK
00000h
00000h
AI01411
Operations
Write. Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. Awrite operation is initiated when
Chip Enable E is Low and Write Enable W is Low
withOutput EnableG High. Commands, InputData
and Addressesare latchedon the rising edge of W
or E. As for the Read operation,when BYTE is Low
a byte is input, DQ8-DQ14 are ’don’t care’ and A-1
is an additional address. When BYTE is High a
word is input.
Operations are defined as specific bus cycles and
signals which allow memory Read, Command
Write, Output Disable, Standby,Power Down, and
Electronic Signature Read. They are shown in Ta-
ble 3.
Read. Read operations are used to output the
contents of the Memory Array, the Status Register
or the Electronic Signature. Both Chip Enable E
and Output Enable G must be low in order to read
the output of the memory. The Chip Enable input
alsoprovides powercontrol andshouldbe usedfor
device selection. Output Enable should be used to
gatedataontotheoutputindependentofthe device
selection. Aread operation will outputeither a byte
or a word depending on the BYTE signal level.
WhenBYTEis Low theoutputbyte ison DQ0-DQ7,
DQ8-DQ14 are Hi-Z and A-1 is an additional ad-
dress input. When BYTEis High the output word is
on DQ0-DQ15.
Output Disable. Thedata outputsare high imped-
ance when the Output Enable G is High with Write
EnableW High.
Standby. Thememory is in standbywhen the Chip
Enable E is High. The power consumption is re-
duced to the standby level and theoutputsare high
impedance, independent of the Output Enable G
or Write Enable W inputs.
PowerDown. Thememoryis in PowerDownwhen
RP is low. The power consumption is reduced to
the Power Down level, and Outputs are in high
impedance, independant of the Chip Enable E,
Output Enable G or Write Enable W inputs.
The data read depends on the previous command
written to the memory (see instructions RD, RSR
and RSIG).
15/27
M28V410, M28V420
Electronic Signature. Two codes identifying the
manufacturerand the device can be read from
the memories, the manufacturer code for SGS-
THOMSON is 20h, and the device codes are 0F3h
for the M28V410(Top BootBlock) and0FBhfor the
M28V420(Bottom Boot Block). These codes allow
programming equipment or applications to auto-
maticallymatchtheirinterfacetothe characteristics
of the particular manufacturer’sproduct.
giving the command 70h.SubsequentReadopera-
tions output the contents of the Status Register.
The contents of the status register are latched on
the falling edge of E or G signals, and can be read
until E or G returns to its initial high level. Either E
or G must be toggled to V to update the latch.
IH
Additionally, any read attempt during program or
erase operation will automatically output the con-
tents of the Status Register.
Read Electronic Signature (RSIG) instruction.
Thisinstructionuses3 operations.Itconsists ofone
write operation giving the command 90h followed
by two read operations to output the manufacturer
and device codes. The manufacturer code, 20h, is
output when the address line A0 is Low, and the
device code, 0F3h for the M28V410or 0FBh forthe
M28V420, when A0 is High.
The Electronic Signatureis output by a Read Array
operation when the voltage applied to A9 is at VID,
the manufacturercode is output when the Address
input A0is Low and the devicecodewhen this input
is High. Other Address inputs are ignored. The
codes are output on DQ0-DQ7. When the BYTE
signal is High the outputs DQ8-DQ15 output 00h,
when Low these outputs are high impedance and
Address input A-1 is ignored.
Erase (EE) instruction. This instruction uses two
write operations.The first command written is the
Erase Set-up command 20h. The second com-
mand isthe Erase Confirm command0D0h.During
the inputofthe second command anaddressof the
block to be erased is given and this is latched into
the memory. If the second command given is not
the EraseConfirm command then the status regis-
ter bitsb4 and b5 areset andthe instruction aborts.
Read operations output the status register after
erasure has started.
The Electronic Signature can also be read,without
raising A9 to VID, after giving the memory the
instruction RSIG (see below).
Instructions and Commands
The memories include a Command Interface(C.I.)
which latches commands written to the memory.
Instructions are made up from one or more com-
mands to perform memory Read, Read Status
Register, Read Electronic Signature, Erase, Pro-
gram, Clear Status Register, Erase Suspend and
Erase Resume. These instructions require from 1
to 3 operations,the first of which is always a write
operation and is followed by either a further write
operation to confirm the first command or a read
operation(s) to output data.
Duringthe executionof the erasebythe P/E.C., the
memory accepts only the RSR (Read Status Reg-
ister) and ES (Erase Suspend) instructions. Status
Register bit b7 returns ’0’ while the erasure is in
progress and ’1’ when it has completed. After com-
pletion the Status Register bit b5 returns ’1’ if there
has been an Erase Failure because erasure has
not been verified even after the maximum number
of erase cycles have been executed. Status Reg-
ister bitb3 returns’1’ ifVPP doesnotremain atVPPH
level when the erasureis attemptedand/orproced-
ing.
A Status Register indicates the P/E.C. status
Ready or Busy, the suspend/in-progressstatus of
erase operations, the failure/successof erase and
program operations and the low/correct value of
the Program Supply voltage VPP.
The P/E.C. automatically sets bits b3 to b7 and
clears bit b6 & b7. It cannot clear bits b3 to b5. The
register can be read by the Read Status Register
(RSR) instruction and cleared by the Clear Status
Register (CLRS) instruction. The meaning of the
bits b3 to b7 is shown in Table 7. Bits b0 to b2 are
reserved for future use (and should be masked out
during status checks).
VPP must be at VPPH when erasing, erase should
not be attempted when VPP < VPPH as the results
will beuncertain.IfVPP fallsbelow VPPH orRP goes
Low the erase aborts and must be repeated, after
having cleared the Status Register (CLRS).
The BootBlock can only be erasedwhen RP is also
at VHH
.
Read (RD) instruction. TheRead instruction con-
sists of one write operation giving the command
0FFh. Subsequent read operations will read the
addressedmemory array contentandoutputabyte
or word depending on the level of the BYTEinput.
Program (PG) instruction. This instruction uses
two write operations. The first command written is
the Program Set-up command 40h (or 10h). A
secondwriteoperationlatchestheAddressand the
Data to be written and starts the P/E.C. Read
operationsoutput the status register after the pro-
gramming has started.
Read Status Register (RSR) instruction. The
Read Status Register instruction may be given at
any time, including while the Program/Erase Con-
troller is active. It consists of one write operation
Memory programming is only made by writing ’0’in
place of ’1’ in a byte or word.
16/27
M28V410, M28V420
DEVICE OPERATION (cont’d)
sumefeaturesofthememoriesare showninFigure
9 to Figure 11.
During the execution of the programming by the
P/E.C., the memory accepts only the RSR (Read
StatusRegister)instruction.The StatusRegisterbit
b7 returns’0’ while the programming is in progress
and ’1’ when it hascompleted. After completionthe
Status register bit b4 returns ’1’ if there has been a
Program Failure. Status Register bit b3 returns a
’1’ if VPP does not remain at VPPH when program-
ming is attempted and/or during programming.
Programming. The memory can be programmed
byte-by-byte(or word-by-wordinx16organization).
The Program Supply voltage VPP must be applied
before program instructions are given, and if the
programming is in the BootBlock, RPmust also be
raised to VHH to unlock the Boot Block. The Pro-
gram Supply voltage may be applied continuously
during programming.
The program sequenceis started by writing a Pro-
gram Set-up command (40h) to the Command
Interface,this isfollowedbywritingthe addressand
data byte or word to the memory. The Pro-
gram/EraseControllerautomaticallystartsandper-
forms the programming after the second write
operation, providing that the VPP voltage (and RP
voltage if programming the Boot Block) are correct.
During the programming the memory status is
checked by reading the statusregister bit b7 which
shows the status of the P/E.C. Bit b7 = ’1’ indicates
that programming is completed.
VPP mustbe at VPPH whenprogramming, program-
ming should not be attempted when VPP < VPPH
as the results will be uncertain. Programming
aborts if VPP drops below VPPH or RP goes Low. If
aborted the data may be incorrect. Then after
having cleared the Status Register (CLRS), the
memory must be erased and re-programmed.
The Boot Block can onlybe programmed when RP
is at VHH
.
Clear Status Register (CLRS) instruction. The
Clear Status Register uses a single write operation
which clears bits b3, b4 and b5, if latched to ’1’ by
the P/E.C., to ’0’. Its use is necessary before any
new operation when an error has been detected.
A full status check can be made after each
byte/word or after a sequence of data has been
programmed. The status check is made on bit b3
for any possible VPP error and on bit b4 for any
possibleprogramming error.
Erase Suspend (ES) instruction. The Erase op-
erationmay be suspended bythis instructionwhich
consists of writing the command 0B0h. The Status
Register bit b6 indicates whether the erase has
actually been suspended,b6 = ’1’, or whether the
P/E.C. cycle was the last and the erase is com-
pleted, b6 = ’0’.
Erase. The memory can be erased by blocks. The
Program Supply voltage VPP must be applied be-
fore the Erase instruction is given, and if the Erase
is of the Boot Block RP must also be raised to VHH
to unlock the Boot Block. The Erase sequence is
started by writing an Erase Set-upcommand (20h)
to the Command Interface, this is followed by an
address in the block to be erased and the Erase
Confirm command (0D0h).
During the suspension the memory will respond
only to Read (RD), Read Status Register (RSR) or
Erase Resume (ER) instructions. Read operations
initially output the status register while erase is
suspendedbut, following a Read instruction, data
from other blocks of the memory can be read. VPP
must be maintained at VPPH while erase is sus-
pended. If VPP does not remain at VPPH or the RP
signal goes Low while erase is suspended then
erase is aborted while bits b5 and b3 of the status
register are set. Erase operationmust be repeated
after having cleared the status register, to be cer-
tain to erase the block.
The Program/Erase Controller automatically starts
and performs the block erase, providing the VPP
voltage (and the RP voltage if the erase is of the
BootBlock) iscorrect.During theerasethememory
status is checked by reading the status register bit
b7 which shows the status of the P/E.C. Bit b7 =
’1’ indicates that erase is completed.
A full status check can be made after the block
erase by checkingbit b3 for anypossibleVPP error,
bits b5 and b6 for any command sequence errors
(erase suspended) and bit b5 alone for an erase
error.
Erase Resume (ER) instruction. If an Erase Sus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 0D0h. The status register bit b6 is
cleared when erasure resumes. Read operations
output the status register after the erase is re-
sumed.
Reset. Note that after any program or erase in-
struction has completed with an error indication or
after any VPP transitions down to VPPL the Com-
mand Interface must be reset by a Clear Status
Register Instruction before data can be accessed.
The suggested flow charts for programs that use
the programming, erasure and erase suspend/re-
17/27
M28V410, M28V420
Automatic Power Saving
Power Up
The Supply voltage VCC and the Program Supply
voltage VPP can be applied in any order. Themem-
ory Command Interface is reset on power up to
Read Memory Array, but a negative transition of
Chip Enable E or a change of the addresses is
required to ensure valid data outputs. Care must
be taken to avoid writes to the memory when VCC
is above VLKO and VPP powers up first. Writes can
be inhibited by driving either E or W to VIH. The
memory is disabled until RP is up to VIH.
The M28V410 and M28V420 memories place
themselves in a lower power state when not being
accessed. Following a Read operation, after a
delay equalto the memory access time, the Supply
Current is reduced from a typical read current of
20mA (CMOS inputs, word-wide organization) to
less than 2mA.
Power Down
The memories provide a power down control input
RP. When this signal is taken to below VSS + 0.2V
all internal circuits are switchedoff and the supply
current drops to typically 0.2µA and the program
current to typically 0.1µA. If RP is taken low during
a memory read operation then the memory is de-
selectedand theoutputs become highimpedance.
If RP is taken low during a program or erase
sequence then it is aborted and the memory con-
tent is no longer valid.
Supply Rails
Normal precautionsmust be taken for supply volt-
age decoupling, each device in a system should
have the VCC andVPP rails decoupledwitha 0.1µF
capacitor close to the VCC and VSS pins. The PCB
trace widths should be sufficient to carry the VPP
program and erase currents required.
Recovery from deep power down requires 700ns
to a memory read operation, or 580ns to a com-
mand write. On return from power down the status
register is cleared to 00h.
18/27
M28V410, M28V420
Figure 9. Program Flow-chart and Pseudo Code
Start
Write 40h
Command
PG instruction:
– write 40h command
– write Address & Data
(memory enters read status
state after the PG instruction)
Write Address
& Data
Read Status
Register
do:
– read status register
(E or G must be toggled)
NO
b7 = 1
while b7 = 1
YES
NO
NO
V
Low
If b3 = 0, V
low error:
– error handler
PP
PP
b3 = 0
YES
Error (1, 2)
Program
Error (1, 2)
If b4 = 0, Program error:
– error handler
b4 = 0
YES
End
AI01278
Notes: 1. Status check of b3 (VPP Low) and b4 (Program Error) can be made after each byte/word programming or after a sequence.
2. If a VPP Low or Program Erase is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
19/27
M28V410, M28V420
Figure 10. Erase Flow-chart and Pseudo Code
Start
Write 20h
Command
EE instruction:
– write 20h command
– write Block Address
(A12-A17) & command 0D0h
(memory enters read status
state after the EE instruction)
Write Block Address
& 0D0h Command
Suspend
Loop
NO
do:
Read Status
– read status register
(E or G must be toggled)
if EE instruction given execute
suspend erase loop
Register
Suspend
YES
NO
NO
NO
NO
b7 = 1
YES
while b7 = 1
V
Low
If b3 = 0, V
low error:
PP
PP
– error handler
b3 = 0
YES
Error (1)
Command
Sequence Error
If b4, b5 = 0, Command Sequence error:
– error handler
b4, b5 = 1
YES
Erase
If b5 = 0, Erase error:
– error handler
b5 = 0
Error (1)
YES
End
AI01279
Note: 1. If VPP Low or Erase Error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
20/27
M28V410, M28V420
Figure 11. Erase Suspend & Resume Flow-chart and Pseudo Code
Start
Write 0B0h
Command
ES instruction:
– write 0B0h command
(memory enters read register
state after the ES instruction)
do:
Read Status
Register
– read status register
(E or G must be toggled)
NO
NO
b7 = 1
YES
while b7 = 1
If b6 = 0, Erase completed
(at this point the memory wich
accept only the RD or ER instruction)
Erase
Complete
b6 = 1
YES
Write 0FFh
Command
RD instruction:
– write 0FFh command
– one o more data reads
from another block
Read data from
another block
Write 0D0h
Command
ER instruction:
– write 0D0h command
to resume erasure
Erase Continues
AI01280
21/27
M28V410, M28V420
Figure 12. Command Interface and Program Erase Controller Flow-diagram (a)
WAIT FOR
COMMAND
WRITE (1)
NO
90h
YES
BYTE
IDENTIFIER
NO
70h
YES
READ
ARRAY
READ
STATUS
NO
50h
YES
CLEAR
STATUS
NO
40h or
10h
YES
PROGRAM
SET-UP
NO
20h
YES
READ
STATUS
PROGRAM
ERASE
SET-UP
NO
0FFh
YES
YES
READY
(2)
NO
OD0h
NO
YES
ERASE
COMMAND
ERROR
READ
STATUS
A
B
AI01286C
Notes: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or
if VCC falls below VLKO, the Command Interface defaults to Read Array mode.
2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
22/27
M28V410, M28V420
Figure 13. Command Interface and Program Erase Controller Flow-diagram (b)
A
B
ERASE
(READ STATUS)
YES
READY
(2)
NO
NO
0B0h
YES
READ
STATUS
ERASE
SUSPEND
YES
READY
(2)
NO
ERASE
SUSPENDED
?
NO
READ
STATUS
YES
YES
NO
70h
NO
READ
STATUS
YES
0D0h
READ
ARRAY
READ
STATUS
(ERASE RESUME)
AI01287B
Note: 2. P/E.C. status(Ready or Busy) is read on Status Register bit 7.
23/27
M28V410, M28V420
ORDERING INFORMATION SCHEME
Example:
M28V410
-80
N
1
TR
VCC Range
Array Org.
Top Boot
Temp. Range
Option
V
3.3V
1
2
1
0 to 70 °C
TR Tape & Reel
Packing
Bottom Boot
3
6
–40 to 125 °C
–40 to 85 °C
Speed
Package
-120 120ns
-150 150ns
-180 180ns
M
N
SO44
TSOP56
14 x 20mm
For a list of available options(VCC Range, Array Organisation, Speed, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest
to you.
24/27
M28V410, M28V420
TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20mm
mm
Min
inches
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
14.10
-
Typ
Min
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.555
-
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
13.90
-
0.002
0.037
0.007
0.004
0.780
0.720
0.547
-
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
56
56
CP
0.10
0.004
TSOP56
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale
25/27
M28V410, M28V420
SO44 - 44 lead Plastic Small Outline, 525 mils body width
mm
Min
2.42
0.22
2.25
inches
Min
Symb
Typ
Max
2.62
0.23
2.35
0.50
0.25
28.30
13.40
Typ
Max
0.103
0.010
0.093
0.020
0.010
1.114
0.528
A
A1
A2
B
0.095
0.009
0.089
C
0.10
28.10
13.20
0.004
1.106
0.520
D
E
e
1.27
0.050
H
15.90
44
16.10
0.626
44
0.634
L
0.80
0.031
α
3°
3°
N
CP
0.10
0.004
SO44
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale
26/27
M28V410, M28V420
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany -Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.
27/27
相关型号：
©2020 ICPDF网 联系我们和版权申明