M28W160BTB100GB1T_技术文档

M28W160BT

M28W160BB

16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory

■ SUPPLY VOLTAGE

– V = 2.7V to 3.6V: for Program, Erase and

DD

Read

– V

= 1.65V or 2.7V: Input/Output option

DDQ

– V

= 12V: optional Supply Voltage for fast

PP

µBGA

Program

■ ACCESS TIME

– 2.7V to 3.6V: 90ns

– 2.7V to 3.6V: 100ns

TSOP48 (N)

12 x 20mm

µBGA46 (GB)

8 x 6 solder balls

■ PROGRAMMING TIME:

– 10µs typical

– Double Word Programming Option

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

■ COMMON FLASH INTERFACE

– 64 bit Security Code

Figure 1. Logic Diagram

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

V

DD DDQ PP

■ BLOCK PROTECTION on TWO PARAMETER

BLOCKS

20

16

– WP for Block Protection

A0-A19

DQ0-DQ15

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

W

E

■ 100,000 PROGRAM/ERASE CYCLES per

M28W160BT

M28W160BB

BLOCK

G

■ 20 YEARS of DATA RETENTION

– Defectivity below 1ppm/year

RP

WP

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W160BT: 90h

– Bottom Device Code, M28W160BB: 91h

V

SS

AI02628

May 2000

1/39

M28W160BT, M28W160BB

Figure 2. µBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

WP

A18

A19

A17

A

B

C

D

E

F

A13

A14

A15

A16

A11

A10

A8

W

V

A7

A5

A4

A2

A1

A0

PP

RP

A12

A9

A6

A3

DQ11

DQ12

DQ4

DQ2

DQ3

DQ14

DQ15

DQ7

DQ5

DQ6

DQ13

DQ8

DQ9

DQ10

E

V

DQ0

DQ1

V

DDQ

SS

V

SS

DD

G

AI02629

Figure 3. TSOP Connections

Table 1. Signal Names

A0-A19

Address Inputs

A15

A14

A13

A12

A11

A10

A9

1

48

A16

DQ0-DQ7

Data Input/Output, Command Inputs

Data Input/Output

Chip Enable

V

DDQ

SS

DQ8-DQ15

DQ15

DQ7

E

DQ14

DQ6

G

Output Enable

A8

DQ13

DQ5

W

Write Enable

NC

W

DQ12

DQ4

RP

WP

Reset

Write Protect

RP

12

13

37

36

V

M28W160BT

M28W160BB

DD

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

PP

WP

V

Supply Voltage

DD

Power Supply for

Input/Output Buffers

A19

A18

A17

A7

V

DDQ

Optional Supply Voltage for

Fast Program & Erase

V

PP

SS

A6

A5

Ground

A4

NC

Not Connected Internally

A3

V

E

SS

A2

A1

24

25

A0

AI02630

2/39

M28W160BT, M28W160BB

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(2)

T

A

–40 to 85

–40 to 125

–55 to 155

Ambient Operating Temperature

T

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

BIAS

T

STG

V

–0.6 to V

+0.6

IO

DDQ

–0.6 to 4.1

–0.6 to 13

V

, V

DD DDQ

V

Program Voltage

V

PP

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Depends on range.

DESCRIPTION

Organisation

The M28W160B is a 16 Mbit non-volatile Flash

memory that can be erased electrically at the block

level and programmed in-system on a Word-by-

Word basis. The device is offered in the TSOP48

(10 x 20mm) and the µBGA46, 0.75mm ball pitch

packages. When shipped, all bits of the

M28W160B are in the ‘1’ state.

The array matrix organisation allows each block to

be erased and reprogrammed without affecting

other blocks. Each block can be programmed and

The M28W160B is organised as 1 Mbit by 16 bits.

A0-A19 are the address lines; DQ0-DQ15 are the

Data Input/Output. Memory control is provided by

Chip Enable E, Output Enable G and Write Enable

W inputs. The Program and Erase operations are

managed automatically by the P/E.C. Block pro-

tection against Program or Erase provides addi-

tional data security.

The upper two (or lower two) parameter blocks

can be protected to secure the code content of the

memory. WP controls protection and unprotection

operations.

erased over 100,000 cycles. V

allows to drive

DDQ

the I/O pin down to 1.65V. An optional 12V V

PP

power supply is provided to speed up the program

phase at customer production line environment.

An internal Command Interface (C.I.) decodes the

instructions to access/modify the memory content.

The Program/Erase Controller (P/E.C.) automati-

cally executes the algorithms taking care of the

timings necessary for program and erase opera-

tions. Verification is performed too, unburdening

the microcontroller, while the Status Register

tracks the status of the operation.

Memory Blocks

The device features an asymmetrical blocked ar-

chitecture. The M28W160B has an array of 39

blocks: 8 Parameter Blocks of 4 KWord and 31

Main Blocks of 32 KWord. M28W160BT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W160BB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Tables 3 and 4.

The two upper parameter block can be protected

from accidental programming or erasure using

WP. Each block can be erased separately. Erase

can be suspended in order to perform either read

or program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed.

The following instructions are executed by the

M28W160B: Read Array, Read Electronic Signa-

ture, Read Status Register, Clear Status Register,

Program, Double Word Program, Block Erase,

Program/Erase Suspend, Program/Erase Re-

sume and CFI Query.

3/39

M28W160BT, M28W160BB

Table 3. Top Boot Block Addresses,

M28W160BT

Table 4. Bottom Boot Block Addresses,

M28W160BB

Size

(KWord)

Size

#

Address Range

#

Address Range

(KWord)

32

4

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

4

FF000-FFFFF

FE000-FEFFF

FD000-FDFFF

FC000-FCFFF

FB000-FBFFF

FA000-FAFFF

F9000-F9FFF

F8000-F8FFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

F8000-FFFFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

4

32

8

7

6

4

5

4

3

4

2

4

1

4

0

4

4/39

M28W160BT, M28W160BB

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A19). The address signals

are inputs driven with CMOS voltage levels. They

are latched during a write operation.

Reset Input (RP). The RP input provides hard-

ware reset of the memory. When RP is at V , the

IL

memory is in reset mode: the outputs are put to

High-Z and the current consumption is minimised.

When RP is at V , the device is in normal opera-

IH

tion. Exiting reset mode the device enters read ar-

ray mode.

Data Input/Output (DQ0-DQ15). The data in-

puts, a word to be programmed or a command to

the C.I., are latched on the Chip Enable E or Write

Enable W rising edge, whichever occurs first. The

data output from the memory Array, the Electronic

Signature or Status Register is valid when Chip

Enable E and Output Enable G are active. The

output is high impedance when the chip is dese-

lected, the outputs are disabled or RP is tied to V .

Commands are issued on DQ0-DQ7.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

V

Supply Voltage (2.7V to 3.6V). V

pro-

DD

vides the power supply to the internal core of the

memory device. It is the main power supply for all

operations (Read, Program and Erase). It ranges

from 2.7V to 3.6V.

V

Supply Voltage (1.65V to V ). V

DD DDQ

DDQ

provides the power supply to the I/O pins and en-

ables all Outputs to be powered independently

IL

from V . V

can be tied to V or it can use a

DD

DDQ

DD

separate supply. It can be powered either from

1.65V to 2.2V or from 2.7V to 3.6V.

coders and sense amplifiers. E at V deselects

IH

V

Program Supply Voltage (12V). V

is

PP

the memory and reduces the power consumption

to the stand-by level. E can also be used to control

writing to the command register and to the memo-

both a control input and a power supply pin. The

two functions are selected by the voltage range

applied to the pin.

ry array, while W remains at V .

IL

If V is kept in a low voltage range (0V to 3.6V)

PP

Output Enable (G). The Output Enable controls

the data Input/Output buffers.

Write Enable (W). This input controls writing to

the Command Register, Input Address and Data

latches.

V

is seen as a control input. In this case a volt-

PP

age lower than V

gives an absolute protection

PPLK

against program or erase, while V

> V

en-

PP

PP1

ables these functions. V value is only sampled

PP

at the beginning of a program or erase; a change

in its value after the operation has been started

does not have any effect and program or erase are

carried on regularly.

Write Protect (WP). Write Protect is an input to

protect or unprotect the two lockable parameter

blocks. When WP is at V , the lockable blocks are

IL

protected. Program or erase operations are not

If V is used in the range 11.4V to 12.6V acts as

PP

achievable. When WP is at V , the lockable

IH

a power supply pin. In this condition V

value

PP

blocks are unprotected and they can be pro-

grammed or erased (refer to Table 9).

must be stable until P/E algorithm is completed

(see Table 22 and 23).

V

Ground. V is the reference for all the volt-

SS

age measurements.

5/39

M28W160BT, M28W160BB

DEVICE OPERATIONS

Four control pins rule the hardware access to the

Flash memory: E, G, W, RP. The following opera-

tions can be performed using the appropriate bus

cycles: Read, Write the Command of an Instruc-

tion, Output Disable, Stand-by, Reset (see Table

5).

and Addresses are latched on the rising edge of W

or E, whichever occur first.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is at V .

IH

Stand-by. Stand-by disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register and the CFI. Both Chip

when Chip Enable E is at V and the device is in

IH

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

Enable (E) and Output Enable (G) must be at V

IL

in order to perform the read operation. The Chip

Enable input should be used to enable the device.

Output Enable should be used to gate data onto

the output independently of the device selection.

The data read depend on the previous command

written to the memory (see instructions RD, RSIG,

RSR, RCFI). Read Array is the default state of the

device when exiting Reset or after power-up.

G or Write Enable W inputs. If E switches to V

during program or erase operation, the device en-

ters in stand-by when finished.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high impedance. The memory is

IH

in Reset mode when RP is at V . The power con-

IL

sumption is reduced to the Stand-by level, inde-

Write. Write operations are used to give Com-

mands to the memory or to latch Input Data to be

programmed. A write operation is initiated when

pendently from the Chip Enable E, Output Enable

G or Write Enable W inputs. If RP is pulled to V

SS

during a Program or Erase, this operation is abort-

ed and the memory content is no longer valid as it

has been compromised by the aborted operation.

Chip Enable E and Write Enable W are at V with

IL

Output Enable G at V . Commands, Input Data

IH

(1)

Table 5. User Bus Operations

V

Operation

Read

E

G

W

RP

WP

X

DQ0-DQ15

Data Output

Data Input

Hi-Z

PP

V

IH

V

Don’t Care

V or V

DD

IL

IH

V

Write

X

IL

IH

PPH

V

Output Disable

Stand-by

Reset

X

Don’t Care

IH

V

X

Hi-Z

IH

V

IL

X

Hi-Z

Note: 1. X = V or V , V = 12V ± 5%.

PPH

IL

IH

Table 6. Read Electronic Signature (RSIG Instruction)

Code

Device

E

G

W

A0

A1-A7

A8-A19

DQ0-DQ7 DQ8-DQ15

V

Manufact. Code

Don’t Care

20h

90h

91h

00h

IL

IH

IL

V

IL

M28W160BT

M28W160BB

IH

Device Code

V

IL

IH

Note: 1. RP = V

.

IH

6/39

M28W160BT, M28W160BB

INSTRUCTIONS AND COMMANDS

section) giving the command 90h. A subsequent

read will output the Manufacturer or the Device

Code (Electronic Signature) depending on the lev-

els of A0 (see Tables 6). The Electronic Signature

can be read from the memory allowing program-

ming equipment or applications to automatically

match their interface to the characteristics of

M28W160B. The Manufacturer Code is output

Eleven instructions are available (see Tables 7

and 8) to perform Read Memory Array, Read Sta-

tus Register, Read Electronic Signature, CFI Que-

ry, Erase, Program, Double Word Program, Clear

Status Register, Program/Erase Suspend and

Program/Erase Resume. Status Register output

may be read at any time, during programming or

erase, to monitor the progress of the operation.

An internal Command Interface (C.I.) decodes the

instructions while an internal Program/Erase Con-

troller (P/E.C.) handles all timing and verifies the

correct execution of the Program and Erase in-

structions. P/E.C. provides a Status Register

whose bits indicate operation and exit status of the

internal algorithms.

when the address lines A0 is at V , the Device

IL

Code is output when A0 is at V . Address A1-A7

IH

must be kept to V , other addresses are ignored.

IL

The codes are output on DQ0-DQ7 with DQ8-

DQ15 at 00h.

CFI Query (RCFI)

The Common Flash Interface Query mode is en-

tered by writing 98h. Next read operations will read

the CFI data. The CFI data structure contains also

a security area; in this section, a 64 bit unique se-

curity number is written, starting at address 80h.

This area can be accessed only in read mode by

the final use and there are no ways of changing

the code after it has been written by ST. Write a

read instruction to return to Read mode (refer to

the Common Flash Interface section).

The Command Interface is reset to Read Array

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

. Com-

DD

LKO

mand sequence must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read Array.

Read (RD)

The Read instruction consists of one write cycle

(refer to Device Operations section) giving the

command FFh. Next read operations will read the

addressed location and output the data. When a

device reset occurs, the memory is in Read Array

as default.

Table 7. Commands

Hex Code

Command

00h, 01h, 60h,

2Fh, C0h

Invalid/Reserved

Read Status Register (RSR)

10h

20h

30h

40h

50h

70h

Alternative Program Set-up

Erase Set-up

The Status Register indicates when a program or

erase operation is complete and the success or

failure of operation itself. Issue a Read Status

Register Instruction (70h) to read the Status Reg-

ister content.

The Read Status Register instruction may be is-

sued at any time, also when a Program/Erase op-

eration is ongoing. The following Read operations

output the content of the Status Register. The Sta-

tus Register is latched on the falling edge of E or

G signals, and can be read until E or G returns to

Double Word Program Set-up

Program Set-up

Clear Status Register

Read Status Register

Read Electronic Signature, or

CFI Query

90h or 98h

B0h

V . Either E or G must be toggled to update the

IH

latched data. Additionally, any read attempt during

program or erase operation will automatically out-

put the content of the Status Register.

Program/Erase Suspend

Program/Erase Resume, or

Erase Confirm

D0h

Read Electronic Signature (RSIG)

The Read Electronic Signature instruction con-

sists of one write cycle (refer to Device Operations

FFh

Read Array

7/39

M28W160BT, M28W160BB

Table 8. Instructions

1st Cycle

2nd Cycle

Addr.

3nd Cycle

Addr.

Mne-

Instruction Cycles

monic

(1)

Operat.

Data Operat.

Data

Operat.

Data

Addr.

Read Memory

Array

Read

Address

(2)

RD

1+

Write

X

FFh

70h

Data

Read

Read Status

Register

Status

Register

(2)

RSR

X

Read

RSIG Electronic

Signature

90h or

98h

1+

Write

X

Signature

Read

(3)

Address

98h or

90h

CFI

Address

RCFI CFI Query

1+

2

Write

55h

X

Query

D0h

Block

Address

EE

PG

Erase

20h

Write

40h or

10h

Data

Input

Program

2

X

Write

Address

Double Word

Program

Data

Input

Data

Input

(4)

3

X

30h

50h

Address 1

Write

Address 2

DPG

Clear Status

Register

CLRS

PES

1

X

Program/

Erase

Suspend

1

Write

X

B0h

D0h

Program/

Erase

PER

Resume

Note: 1. X = Don’t Care.

2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations to read memory array, Status Register or

Electronic Signature codes. Any number of Read cycle can occur after one command cycle.

3. Signature address bit A0=V will output Manufacturer code. Address bit A0=V will output Device code. Address A7-A1 must be

IL

IH

kept to V . Other address bits are ignored.

IL

4. Address 1 and Address 2 must be consecutive Addresses differing only for address bit A0.

Erase (EE)

Status Register bit b7 returns ’0’ while the erasure

is in progress and ’1’ when it has completed. After

completion the Status Register bit b5 returns ’1’ if

there has been an Erase Failure. Status register

bit b1 returns ’1’ if the user is attempting to pro-

gram a protected block. Status Register bit b3 re-

Block erasure sets all the bits within the selected

block to ’1’. One block at a time can be erased. It

is not necessary to program the block with 00h as

the P/E.C. will do it automatically before erasing.

This instruction uses two write cycles. The first

command written is the Erase Set up command

20h. The second command is the Erase Confirm

command D0h. An address within the block to be

erased is given and latched into the memory dur-

ing the input of the second command. If the sec-

ond command given is not an erase confirm, the

status register bits b4 and b5 are set and the in-

struction aborts.

turns a ’1’ if V is below V

.

PP

PPLK

Erase aborts if RP turns to V . As data integrity

IL

cannot be guaranteed when the erase operation is

aborted, the erase must be repeated. A Clear Sta-

tus Register instruction must be issued to reset b1,

b3, b4 and b5 of the Status Register. During the

execution of the erase by the P/E.C., the memory

accepts only the RSR (Read Status Register) and

PES (Program/Erase Suspend) instructions.

Read operations output the status register after

erasure has started.

8/39

M28W160BT, M28W160BB

Table 9. Memory Blocks Protection Truth Table

(1,3)

(2,4)

(1,4)

Lockable Blocks

Protected

Other Blocks

Protected

V

RP

WP

PP

V

X

IL

IH

V

X

Protected

IL

(5)

V

Protected

Unprotected

V

or V

IL

DD

PPH

V

Unprotected

IH

DD

PPH

Note: 1. Notes:1.X’ = Don’t Care

2. RP is the Reset/Power Down.

3. V is the program or erase supply voltage.

PP

4. V /V are logic high and low levels.

IH IL

5. V must be also greater than the Program Voltage Lock-Out V

.

PP

PPLK

Table 10. Status Register Bits

Logic

Mnemonic

Bit

Name

Definition

Ready

Note

Level

’1’

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits b4 or b5 for Program or Erase

Success

P/ECS

7

P/E.C. Status

’0’

Busy

’1’

’0’

Suspended

Erase

Suspend

Status

On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’ until an

Erase Resume instruction is given.

ESS

6

In progress or

Completed

’1’

’0’

Erase Error

ES bit is set to ’1’ if P/E.C. has applied the

maximum number of erase pulses to the block

without achieving an erase verify.

ES

PS

5

4

Erase Status

Erase Success

’1’

’0’

’1’

Program Error

Program

Status

PS bit set to ’1’ if the P/E.C. has failed to program

a word.

Program Success

V

PP

Invalid, Abort VPPS bit is set if the V voltage is below V

PP PPLK

when a Program or Erase instruction is executed.

is sampled only at the beginning of the

Erase/Program operation.

V

Status

VPPS

PSS

3

2

PP

V

PP

V

OK

’0’

PP

’1’

’0’

Suspended

Program

Suspend

Status

On a Program Suspend instruction P/ECS and

PSS bits are set to ’1’. PSS remains ’1’ until a

Program Resume Instruction is given

In Progress or

Completed

Program/Eraseon

protected Block,

Abort

’1’

’0’

Block

Protection

Status

BPS bit is set to ’1’ if a Program or Erase

operation has been attempted on a protected

block

BPS

1

0

No operation to

protected blocks

Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

9/39

M28W160BT, M28W160BB

Program (PG)

The memory array can be programmed word-by-

word. This instruction uses two write cycles. The

first command written is the Program Set-up com-

mand 40h (or 10h). A second write operation latch-

es the Address and the Data to be written and

starts the P/E.C.

reprogrammed. A Clear Status Register instruc-

tion must be issued to reset b4, b3 and b1 of the

Status Register.

During the execution of the program by the P/E.C.,

the memory accepts only the RSR (Read Status

Register) and PES (Program/Erase Suspend) in-

structions.

Read operations output the Status Register con-

tent after the programming has started. The Status

Register bit b7 returns ’0’ while the programming

is in progress and ’1’ when it has completed. After

completion the Status register bit b4 returns ’1’ if

there has been a Program Failure. Status register

bit b1 returns ’1’ if the user is attempting to pro-

gram a protected block. Status Register bit b3 re-

Clear Status Register (CLRS)

The Clear Status Register uses a single write op-

eration which clears bits b1, b3, b4 and b5 to ‘0’.

Its use is necessary before any new operation

when an error has been detected.

The Clear Status Register is executed writing the

command 50h.

Program/Erase Suspend (PES)

turns a ’1’ if V

is below V . Programming

PPLK

PP

aborts if RP goes to V . As data integrity cannot

Program/Erase suspend is accepted only during

the Program Erase instruction execution. When a

Program/Erase Suspend command is written to

the C.I., the P/E.C. freezes the Program/Erase op-

eration. Program/Erase Resume (PER) continues

the Program/Erase operation. Program/Erase

Suspend consists of writing the command B0h

without any specific address.

The Status Register bit b2 is set to ‘1’ (within 5µs)

when the program has been suspended. b2 is set

to ‘0’ in case the program is completed or in

progress. The Status Register bit b6 is set to ‘1’

(within 30µs) when the erase has been suspend-

ed. b6 is set to ‘0’ in case the erase is completed

or in progress. The valid commands while erase is

suspended are Program/Erase Resume, Pro-

gram, Read Array, Read Status Register, Read

Identifier, CFI Query. While program is suspended

the same command set is valid except for program

instruction. During program/erase suspend mode,

the chip can be placed in a pseudo-stand-by mode

IL

be guaranteed when the program operation is

aborted, the memory location must be erased and

reprogrammed. A Clear Status Register instruc-

tion must be issued to reset b4, b3 and b1 of the

Status Register.

During the execution of the program by the P/E.C.,

the memory accepts only the RSR (Read Status

Register) and PES (Program/Erase Suspend) in-

structions.

Double Word Program (DPG)

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when V

also be executed if V is below V

is not at V

. The operation can

PP

PPH

but result

PPH

PP

could be uncertain. This instruction uses three

write cycles. The first command written is the Dou-

ble Word Program Set-Up command 30h. A sec-

ond write operation latches the Address and the

Data of the first word to be written, the third write

operation latches the Address and the Data of the

second word to be written and starts the P/E.C.

Read operations output the Status Register con-

tent after the programming has started. The Status

Register bit b7 returns ’0’ while the programming

is in progress and ’1’ when it has completed. After

completion the Status register bit b4 returns ’1’ if

there has been a Program Failure. Status register

bit b1 returns ’1’ if the user is attempting to pro-

gram a protected block. Status Register bit b3 re-

by taking E to V . This reduces active current con-

IH

sumption. Program/Erase is aborted if RP turns to

V .

IL

Program/Erase Resume (PER)

If a Program/Erase Suspend instruction was previ-

ously executed, the program/erase operation may

be resumed by issuing the command D0h. The

status register bit b2/b6 is cleared when program/

erase resumes. Read operations output the status

register after the program/erase is resumed.

The suggested flow charts for programs that use

the programming, erasure and program/erase

suspend/resume features of the memories are

shown from Figures 10, 11, 12, 13 and 14.

turns a ’1’ if V

is below V . Programming

PPLK

PP

aborts if RP goes to V . As data integrity cannot

IL

be guaranteed when the program operation is

aborted, the memory location must be erased and

10/39

M28W160BT, M28W160BB

Table 11. Program, Erase Times and Program/Erase Endurance Cycles

(T = 0 to 70°C or –40 to 85°C; V = 2.7V to 3.6V)

A

DD

M28W160B

Parameter

Test Conditions

Unit

(1)

Min

Max

200

5

Typ

V

PP

= V

DD

Word Program

10

µs

V

= 12V ±5%

= V

Double Word Program

PP

0.16

0.32

0.02

0.04

1

sec

cycles

PP

Main Block Program

Parameter Block Program

Main Block Erase

V

5

PP

DD

V

= 12V ±5%

= V

4

PP

V

4

PP

DD

= 12V ±5%

= V

10

PP

V

1

PP

DD

= 12V ±5%

= V

0.8

PP

Parameter Block Erase

V

PP

DD

Program/Erase Cycles (per Block)

100,000

Note: T = 25 °C.

A

11/39

M28W160BT, M28W160BB

BLOCK PROTECTION

Automatic Stand-by

Two parameter blocks (#0 and #1) can be protect-

ed against Program or Erase to ensure extra data

security. Unprotected blocks can be programmed

or erased.

Automatic Stand-by provides a low power con-

sumption state during read mode. Following a

read operation, after a delay close to the memory

access time, the device enters Automatic Stand-

by: the Supply Current is reduced to I

values.

CC1

WP tied to V protects the two lockable blocks.

IL

The device keeps the last output data stable, till a

new location is accessed.

V

below V

protects all the blocks. Any pro-

PP

PPLK

gram or erase operation on protected blocks is

aborted. The Status Register tracks when the

event occurs.

Stand-by or Reset

Refer to the Device Operations section.

Power Up

Table 9 defines the protection methods.

The Supply voltage V

and the Program Supply

DD

POWER CONSUMPTION

voltage V

can be applied in any order. The

PP

The M28W160B puts itself in one of four different

modes depending on the status of the control sig-

nals: Active Power, Automatic Stand-by, Stand-by

and Reset define decreasing levels of current con-

sumption. These allow the memory power to be

minimised, in turn decreasing the overall system

power consumption. As different recovery time are

linked to the different modes, please refer to the

AC timing table to design your system.

memory Command Interface is reset on power up

to Read Memory Array, but a negative transition of

Chip Enable E or a change of the addresses is re-

quired to ensure valid data outputs. Care must be

taken to avoid writes to the memory when V

is

DD

above V

. Writes can be inhibited by driving ei-

LKO

ther E or W to V . The memory is disabled if RP

IH

is at V .

IL

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling, each device in a system should

Active Power

When E is at V and RP is at V , the device is in

IL

IH

active mode. Refer to DC Characteristics to get

the values of the current supply consumption.

have the V

0.1µF capacitor close to the V

and V

rails decoupled with a

DD

PP

and V

pins.

DD

PP

The PCB trace widths should be sufficient to carry

the required V program and erase currents.

PP

12/39

M28W160BT, M28W160BB

COMMON FLASH INTERFACE (CFI)

The CFI data structure gives information on the

device, such as the sectorization, the command

set and some electrical specifications. Tables 12,

13, 14 and 15 show the addresses used to retrieve

each data. The CFI data structure contains also a

security area; in this section, a 64 bit unique secu-

rity number is written, starting at address 80h. This

area can be accessed only in read mode by the fi-

nal user and there are no ways of changing the

code after it has been written by ST. Write a read

instruction to return to Read mode. Refer to the

CFI Query instruction to understand how the

M28W160B enters the CFI Query mode.

The Common Flash Interface (CFI) specification is

a JEDEC approved, standardised data structure

that can be read from the Flash memory device.

CFI allows a system software to query the flash

device to determine various electrical and timing

parameters, density information and functions

supported by the device. CFI allows the system to

easily interface to the Flash memory, to learn

about its features and parameters, enabling the

software to configure itself when necessary.

Tables 12, 13, 14, 15, 16 and 17 show the address

used to retrieve each data.

Table 12. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 13, 14, 15, 16 and 17. Query data are always presented on the lowest order data outputs.

Table 13. CFI Query Identification String

Offset

Data

Description

00h

0020h

Manufacturer Code

Device Code

Reserved

0090h - top

0091h - bottom

01h

02h-0Fh

10h

reserved

0051h

Query Unique ASCII String "QRY"

11h

0052h

12h

0059h

13h

0003h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

14h

0000h

15h

offset = P = 0035h

0000h

Address for Primary Algorithm extended Query table

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

18h

0000h

19h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

note: 0000h means none exists

1Ah

Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

13/39

M28W160BT, M28W160BB

Table 14. CFI Query System Interface Information

Offset

Data

Description

V

DD

V

DD

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0027h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

0036h

00B4h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Note: This value must be 0000h if no V pin is present

PP

V

[Programming] Supply Maximum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

1Eh

00C6h

Note: This value must be 0000h if no V pin is present

PP

n

Typical timeout per single byte/word program (multi-byte program count = 1), 2 µs

(if supported; 0000h = not supported)

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

n

Typical timeout for maximum-size multi-byte program or page write, 2 µs

(if supported; 0000h = not supported)

n

Typical timeout per individual block erase, 2 ms

(if supported; 0000h = not supported)

n

Typical timeout for full chip erase, 2 ms

(if supported; 0000h = not supported)

n

Maximum timeout for byte/word program, 2 times typical (offset 1Fh)

(0000h = not supported)

n

Maximum timeout for multi-byte program or page write, 2 times typical (offset 20h)

(0000h = not supported)

n

Maximum timeout per individual block erase, 2 times typical (offset 21h)

(0000h = not supported)

n

Maximum timeout for chip erase, 2 times typical (offset 22h)

(0000h = not supported)

14/39

M28W160BT, M28W160BB

Table 15. Device Geometry Definition

Offset Word

Data

Description

Mode

n

27h

28h

29h

2Ah

2Bh

2Ch

0015h

0001h

0000h

0002h

Device Size = 2 in number of bytes

Flash Device Interface Code description: Asynchronous x16

n

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within device

bit 7 to 0 = x = number of Erase Block Regions

Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."

2. x specifies the number of regions within the device containing one or more con-

tiguous Erase Blocks of the same size. For example, a 128KB device (1Mb)

having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is consid-

ered to have 5 Erase Block Regions. Even though two regions both contain

16KB blocks, the fact that they are not contiguous means they are separate

Erase Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

M28W160BT M28W160BT Erase Block Region Information

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

001Eh

0000h

0001h

0007h

0000h

0020h

0000h

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in

size. The value z = 0 is used for 128 byte block size.

e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase

Block Region:

e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = "1 block")

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

M28W160BB M28W160BB

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

0007h

0000h

0020h

0000h

001Eh

0000h

0001h

15/39

M28W160BT, M28W160BB

Table 16. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

(P)h = 35h

0050h

0052h

0049h

0031h

0030h

0006h

0000h

Primary Algorithm extended Query table unique ASCII string “PRI”

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

Major version number, ASCII

Minor version number, ASCII

Extended Query table contents for Primary Algorithm

bit 0

bit 1

bit 2

bit 3

bit 4

Chip Erase supported

Erase Suspend supported

Program Suspend

Lock/Unlock supported

Quequed Erase supported

(1 = Yes, 0 = No)

(P+7)h

(P+8)h

bit 31 to 5 Reserved; undefined bits are ‘0’

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported during Erase or

Program operation

bit 0

Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’

(P+A)h = 3Fh

(P+B)h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are implemented.

bit 0

bit 1

Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No)

Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+C)h = 41h

(P+D)h = 42h

(P+E)h

0027h

00C0h

0000h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

DD

PP

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Supply Optimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Reserved

Table 17. Security Code Area

Offset

81h

Data

XXXX

Description

82h

64 bits unique device number.

83h

84h

16/39

M28W160BT, M28W160BB

Table 18. DC Characteristics

(T = 0 to 70°C or –40 to 85°C; V = V

A

= 2.7V to 3.6V)

Test Condition

0V≤ V ≤ V

DD

DDQ

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Min

Typ

Max

±1

Unit

µA

I

LI

IN

DDQ

I

0V≤ V

≤V

±10

20

µA

LO

OUT DDQ

I

E = V , G = V , f = 5MHz

10

15

mA

CC

SS

IH

E = V

RP = V

± 0.2V,

Supply Current (Stand-by or

Automatic Stand-by)

DDQ

I

50

20

50

400

µA

CC1

± 0.2V

DDQ

Supply Current

(Reset)

I

RP = V ± 0.2V

15

10

5

CC2

SS

Program in progress

mA

µA

V

= 12V ± 5%

PP

I

Supply Current (Program)

Supply Current (Erase)

CC3

Program in progress

= V

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

CC4

Erase in progress

= V

5

V

PP

DD

E = V

Erase suspended

± 0.2V,

Supply Current

(Program/Erase Suspend)

DDQ

I

CC5

Program Current

(Read or Stand-by)

I

V

> V

µA

PP

DD

Program Current

(Read or Stand-by)

I

V

≤ V

5

µA

PP1

DD

I

RP = V ± 0.2V

Program Current (Reset)

PP2

SS

Program in progress

10

mA

V

PP

= 12V ± 5%

I

Program Current (Program)

PP3

Program in progress

= V

5

10

5

µA

mA

µA

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

Program Current (Erase)

PP4

Erase in progress

= V

V

PP

DD

–0.5

0.4

0.8

V

Input Low Voltage

Input High Voltage

IL

V

≥ 2.7V

DDQ

V

–0.4

V

+0.4

DDQ

V

IH

0.7 V

+0.4

DDQ

I

= 100µA, V = V min,

DD DD

OL

V

Output Low Voltage

Output High Voltage

0.1

V

OL

V

= V

min

DDQ

I

= –100µA, V = V min,

DD DD

OH

V

OH

V

–0.1

DDQ

V

DDQ

= V

min

DDQ

Program Voltage (Program or

Erase operations)

V

1.65

3.6

PP1

Program Voltage

(Program or Erase

operations)

V

PPH

11.4

12.6

V

Program Voltage

(Program and Erase lock-out)

V

1

2

V

PPLK

V

DD

Supply Voltage (Program

V

LKO

and Erase lock-out)

17/39

M28W160BT, M28W160BB

Table 19. AC Measurement Conditions

Figure 5. AC Testing Load Circuit

Input Rise and Fall Times

≤ 10ns

V

/2

DDQ

0 to V

Input Pulse Voltages

DDQ

V

/2

DDQ

Input and Output Timing Ref. Voltages

1N914

3.3kΩ

Figure 4. AC Testing Input Output Waveform

DEVICE

UNDER

TEST

OUT

V

DDQ

C

= 50pF

L

V

/2

DDQ

0V

C

includes JIG capacitance

L

AI00610

AI00609B

(1)

Table 20. Capacitance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

IN

V

IN

= 0V

C

V

OUT

12

pF

OUT

Note: 1. Sampled only, not 100% tested.

18/39

M28W160BT, M28W160BB

(1)

Table 21. Read AC Characteristics

(T = 0 to 70°C or –40 to 85°C)

A

M28W160B

90

= 2.7V to 3.6V

100

Unit

Symbol

Alt

Parameter

V

DD

V

= 2.7V to 3.6V

DD

V

= 2.7V min

V

= 1.65V min

DDQ

Min

100

Min

Max

t

Address Valid to Next Address Valid

Address Valid to Output Valid

90

ns

AVAV

RC

t

ACC

90

100

AVQV

(2)

t

Address Transition to Output Transition

0

t

OH

AXQX

(2)

(3)

(2)

(3)

(2)

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

ns

t

OH

EHQX

t

25

90

30

t

HZ

EHQZ

t

Chip Enable Low to Output Valid

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

Reset High to Output Valid

100

ns

t

CE

ELQV

ELQX

t

0

LZ

t

OH

GHQX

t

25

30

35

t

DF

GHQZ

t

OE

GLQV

t

0

OLZ

GLQX

t

PWH

150

PHQV

(2,4)

t

Reset Pulse Width

100

t

RP

PLPH

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

4. The device Reset is possible but not guaranteed if t

< 100ns.

PLPH

19/39

M28W160BT, M28W160BB

Figure 6. Read AC Waveforms

20/39

M28W160BT, M28W160BB

(1)

Table 22. Write AC Characteristics, Write Enable Controlled

(T = 0 to 70°C or –40 to 85°C)

A

M28W160B

90

= 2.7V to 3.6V

100

Symbol

Alt

Parameter

Unit

V

DD

V

= 2.7V to 3.6V

DD

V

= 2.7V min

V

= 1.65V min

DDQ

Min

100

Min

90

50

0

Max

t

WC

Write Cycle Time

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Reset High to Write Enable Low

Reset Pulse Width

50

AVWH

AS

DS

CS

PS

t

DVWH

t

0

ELWL

t

90

100

PHWL

(2, 3)

100

t

RP

PLPH

(2, 4)

Reset Low to Program/Erase Abort

30

µs

PLRH

(2, 5)

Output Valid to V Low

0

ns

t

PP

QVVPL

t

Data Valid to Write Protect Low

QVWPL

(2)

t

V

PP

High to Write Enable High

200

0

200

0

t

VPS

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

WHAX

WHDX

WHEH

AH

DH

CH

t

0

Write Enable High to Output Enable

Low

t

30

ns

WHGL

t

WPH

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

30

50

30

50

ns

WHWL

t

WLWH

WP

t

WPHWH

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. The device Reset is possible but not guaranteed if t

< 100ns.

PLPH

4. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.

5. Applicable if V is seen as a logic input (V < 3.6V).

PP

21/39

M28W160BT, M28W160BB

Figure 7. Write AC Waveforms, W Controlled

22/39

M28W160BT, M28W160BB

(1)

Table 23. Write AC Characteristics, Chip Enable Controlled

(T = 0 to 70°C or –40 to 85°C)

A

M28W160B

90

= 2.7V to 3.6V

100

Symbol

Alt

Parameter

Unit

V

= 2.7V to 3.6V

DD

V

= 2.7V min

= 1.65V min

DDQ

VDDQ

Min

90

50

0

Max

Min

Max

t

WC

Write Cycle Time

100

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

50

0

AVEH

AS

DS

AH

t

DVEH

t

Chip Enable High to Address Transition

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Reset High to Chip Enable Low

EHAX

t

0

EHDX

DH

t

CPH

30

0

30

0

EHEL

t

EHGL

t

WH

EHWH

t

CP

50

90

50

100

ELEH

t

PS

PHEL

(2, 3)

t

Reset Pulse Width

100

t

RP

PLPH

(2, 4)

Reset Low to Program/Erase Abort

30

µs

ns

t

PLRH

(2, 5)

Output Valid to V Low

0

t

PP

QVVPL

t

Data Valid to Write Protect Low

0

200

0

200

0

ns

QVWPL

(2)

t

V

PP

High to Chip Enable High

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

Write Protect High to Chip Enable High

WLEL

t

50

WPHEH

Note: 1. See AC Testing Measurement conditions for timing measurements.

2. Sampled only, not 100% tested.

3. The device Reset is possible but not guaranteed if t

< 100ns.

PLPH

4. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.

5. Applicable if V is seen as a logic input (V < 3.6V).

PP

23/39

M28W160BT, M28W160BB

Figure 8. Write AC Waveforms, E Controlled

24/39

M28W160BT, M28W160BB

Figure 9. Reset AC Waveform

Reset during Read Mode

tPLPH

RP

tPHQV

Reset during Program with t_PLPH≤ t_PLRH

Abort

Complete

tPHWL

tPHEL

tPLRH

tPLPH

RP

Reset during Program/Erase with t_PLPH> t_PLRH

Abort

Complete

Reset

tPHWL

tPHEL

tPLRH

tPLPH

RP

AI03537

25/39

M28W160BT, M28W160BB

Figure 10. Program Flowchart and Pseudo Code

Start

Write 40h or 10h

Command

Program instruction:

– write 40h or 10h command

– write Address & Data

(memory enters read status state after

the Program instruction)

Write Address

& Data

do:

NO

Read Status

– read status register (E or G must be

toggled) if PES instruction given execute

suspend program loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

– error handler

b3 = 0

YES

Error (1, 2)

Program

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI03538

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operationor after a

PP

sequence.

2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

26/39

M28W160BT, M28W160BB

Figure 11. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

Command

DPG instruction:

– write 30h command

– write Address 1 & Data 1 (3)

– write Address 2 & Data 2 (3)

(memory enters read status state after

the Program instruction)

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

NO

do:

Read Status

Register

– read status register (E or G must be

toggled) if PES instruction given execute

DPG suspend loop

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

V

Invalid

Error (1, 2)

If b3 = 1, V

invalid error:

PP

– error handler

b3 = 0

YES

Program

Error (1, 2)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI03539

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

27/39

M28W160BT, M28W160BB

Figure 12. Program or DPG Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Command

PES instruction:

Write 70h

– write B0h command

Command

do:

– read status register

(E or G must be toggled)

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

NO

b2 = 1

YES

Program Complete

If b2 = 0 Program completed

Write a read

Command

Read data from

another address

PER instruction:

– write D0h command to resume

the program

Write D0h

Command

Write FFh

Command

– if the program operation completed

then this is not necessary.

The device returns to Read Array as

normal (as if the Program/Erase

suspend was not issued).

Read Data

Program Continues

AI03540

28/39

M28W160BT, M28W160BB

Figure 13. Erase Flowchart and Pseudo Code

Start

Write 20h

Command

EE instruction:

– write 20h command

– write Block Address (A12-A20) &

command D0h

(memory enters read status state after

the EE instruction)

Write Block Address

& D0h Command

do:

– read status register (E or G must be

toggled) if PES instruction given execute

suspend erase loop

NO

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

– error handler

PP

Error (1)

PP

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase Error (1)

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error:

– error handler

b1 = 0

YES

End

AI03541

Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

29/39

M28W160BT, M28W160BB

Figure 14. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Command

PES instruction:

– write B0h command

do:

Write 70h

Command

– read status register

(E or G must be toggled)

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

Erase Complete

If b6 = 0, Erase completed

Read data from

another block

or

Program

PER instruction:

– write D0h command to resume

erasure

Write D0h

Command

Write FFh

Command

– if the erase operation completed

then this is not necessary.

The device returns to Read Array as

normal (as if the Program/Erase

suspend was not issued).

Read Data

Erase Continues

AI03549

30/39

M28W160BT, M28W160BB

Figure 15. Command Interface and Program Erase Controller Flowchart (a)

WAIT FOR

COMMAND

WRITE (1)

NO

90h

YES

READ

SIGNATURE

NO

98h

YES

CFI

QUERY

NO

70h

YES

READ

STATUS

NO

50h

YES

READ

ARRAY

CLEAR

STATUS

NO

40h or

10h

YES

PROGRAM

SET-UP

NO

30h

YES

C

READ

DPG

SET-UP

NO

STATUS

20h

YES

C

ERASE

SET-UP

NO

FFh

YES

NO

B

D0h

YES

ERASE

COMMAND

ERROR

A

AI03547

Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or

if V falls below V , the Command Interface defaults to Read Array mode.

DD

LKO

2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

31/39

M28W160BT, M28W160BB

Figure 16. Command Interface and Program Erase Controller Flowchart (b)

A

B

ERASE

(READ STATUS)

YES

READY

(2)

NO

B0h

ERASE

SUSPENDED

NO

YES

READ

STATUS

YES

ERASE

SUSPEND

YES

NO

READ

STATUS

70h

NO

YES

READY

(2)

READ

SIGNATURE

NO

90h

NO

READ

STATUS

CFI

QUERY

98h

NO

PROGRAM

SET-UP

40h or

10h

c

NO

DPG

SET-UP

30h

NO

YES

(READ STATUS)

READ

ARRAY

ERASE

RESUME

D0h

AI03548

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

32/39

M28W160BT, M28W160BB

Figure 17. Command Interface and Program Erase Controller Flowchart (c)

C

B

PROGRAM

(READ STATUS)

YES

READY

(2)

NO

B0h

YES

READ

STATUS

PROGRAM

SUSPEND

NO

PROGRAM

SUSPENDED

YES

READY

(2)

YES

NO

YES

READ

STATUS

READ

STATUS

70h

NO

YES

NO

READ

SIGNATURE

90h

NO

CFI

QUERY

98h

NO

(READ STATUS)

YES

READ

ARRAY

PROGRAM

RESUME

D0h

AI03545

Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

33/39

M28W160BT, M28W160BB

Table 24. Ordering Information Scheme

Example:

M28W160BT

90

N

6

T

Device Type

M28

Operating Voltage

W = V = 2.7V to 3.6V; V

= 1.65V or 2.7V

DDQ

DD

Device Function

160B = 16 Mbit (1Mb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Random Speed

90 = 90 ns

100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

GB = µBGA46: 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 25. Daisy Chain Ordering Scheme

Example:

M28W160B

-GB T

Device Type

M28W160B

Daisy Chain

-GB = µBGA46: 0.75 mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

34/39

M28W160BT, M28W160BB

Table 26. Revision History

Date

Revision Details

July 1999

09/21/99

First Issue

Parameter Block Erase Typ. specification change (Table 11)

Added t and t (Tables 22, 23 and Figures 7, 8)

WHGL

EHGL

µBGA Package Mechanical Data change (Table 27)

Daisy Chain diagrams, Package and PCB Connections, added (Figures 20, 21)

10/20/99

Access Time conditions change

Reset mode function change to remove Power Down mode

Instructions description clarification

Change of Parameter Block Erase value (Table 11)

Block Protections description clarification

Security Code Area definition change (Table 17)

02/09/00

I

and I

value change (Table 18)

CC2

CC3

t

value change (Tables 22, 23)

PLRH

Program, Erase, Command Interface flowcharts clarification (Figures 10, 11, 12, 13, 14, 15, 16, 17)

µBGA Package Mechanical Data change (Table 28)

µBGA Package Outline diagram change (Figure 19)

Document type: from Preliminary Data to Data Sheet

04/19/00

05/17/00

Daisy Chain part numbering defined

µBGA Daisy Chain diagrams, Package and PCB Connections re-designed (Figure 20, 21)

µBGA Package Outline diagram change (Figure 19)

35/39

M28W160BT, M28W160BB

Table 27. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.4764

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.4685

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0276

5°

α

N

48

CP

0.10

0.0039

Figure 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Drawing is not to scale.

36/39

M28W160BT, M28W160BB

Table 28. µBGA46 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data

mm

Min

inch

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.000

0.0394

0.180

–

0.0071

–

0.700

0.350

6.390

5.250

–

0.0276

0.0138

0.2516

0.2067

–

0.300

6.340

–

0.400

0.0118

0.2496

–

0.0157

D

6.440

0.2535

D1

ddd

e

–

0.008

0.0003

0.750

6.370

3.750

0.570

1.310

0.375

–

0.0295

0.2508

0.1476

0.0224

0.0516

0.0148

–

E

6.320

6.420

0.2488

0.2528

E1

FD

FE

SD

SE

–

Figure 19. µBGA46 - 8 x 6 balls, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

SE

SD

FE

E1

E

e

ddd

BALL "A1"

e

b

A

A2

A1

BGA-G05

Drawing is not to scale.

37/39

M28W160BT, M28W160BB

Figure 20. µBGA46 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

AI03298

Figure 21. µBGA46 Daisy Chain - PCB Connections (Top view through package)

1

2

3

4

5

6

7

8

START

POINT

A

B

C

D

E

F

END

POINT

AI3299

38/39

M28W160BT, M28W160BB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

39/39


型号：	M28W160BTB100GB1T
厂家：	ST
描述：	16 Mbit 1Mb x16, Boot Block Low Voltage Flash Memory 16兆位1Mb的X16 ，引导块低电压闪存闪存
文件：	总39页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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