M28W320CB85GB6T [STMICROELECTRONICS]
32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory; 32兆位(2MB X16 ,引导块) 3V供应闪存型号: | M28W320CB85GB6T |
厂家: | ST |
描述: | 32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory |
文件: | 总42页 (文件大小:276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M28W320CT
M28W320CB
32 Mbit (2Mb x16, Boot Block) Low Voltage Flash Memory
PRELIMINARY DATA
■ SUPPLY VOLTAGE
– V = 2.7V to 3.6V: for Program, Erase and
DD
Read
– V
= 1.65V or 2.7V: Input/Output option
DDQ
– V = 12V: optional Supply Voltage for fast
PP
µBGA
Program
■ ACCESS TIME
– 2.7V to 3.6V: 90ns
– 2.7V to 3.6V: 100ns
TSOP48 (N)
12 x 20mm
µBGA47 (GB)
8 x 6 solder balls
■ PROGRAMMING TIME:
– 10µs typical
– Double Word Programming Option
■ PROGRAM/ERASE CONTROLLER (P/E.C.)
■ COMMON FLASH INTERFACE
■ MEMORY BLOCKS
Figure 1. Logic Diagram
– Parameter Blocks (Top or Bottom location)
– Main Blocks
■ BLOCK PROTECTION UNPROTECTION
– All Blocks protected at Power Up
– Any combination of blocks can be protected
– WP for block locking
V
V
V
DD DDQ PP
21
16
A0-A20
DQ0-DQ15
■ SECURITY
W
E
– 64-bit user Programmable OTP cells
– 64-bit unique device identifier
– One Parameter Block Permanently Lockable
■ AUTOMATIC STAND-BY MODE
■ PROGRAM and ERASE SUSPEND
M28W320CT
M28W320CB
G
RP
WP
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS of DATA RETENTION
– Defectivity below 1ppm/year
V
SS
■ ELECTRONIC SIGNATURE
AI03521
– Manufacturer Code: 20h
– Top Device Code, M28W320CT: 88BAh
– Bottom Device Code, M28W320CB: 88BBh
May 2000
1/42
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M28W320CT, M28W320CB
Figure 2. µBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
WP
A18
A20
DQ2
DQ3
A19
A17
A
B
C
D
E
F
A13
A14
A15
A16
A11
A10
A8
W
V
A7
A5
A4
A2
A1
A0
PP
RP
A12
A9
A6
A3
DQ11
DQ12
DQ4
DQ14
DQ15
DQ7
DQ5
DQ6
DQ13
DQ8
DQ9
DQ10
E
V
DQ0
DQ1
V
DDQ
SS
V
V
SS
DD
G
AI02686
Figure 3. TSOP Connections
Table 1. Signal Names
A0-A20
Address Inputs
Data Input/Output, Command Inputs
Data Input/Output
Chip Enable
A15
A14
A13
A12
A11
A10
A9
1
48
A16
DQ0-DQ7
V
DDQ
V
SS
DQ8-DQ15
DQ15
DQ7
E
DQ14
DQ6
G
Output Enable
A8
DQ13
DQ5
W
Write Enable
NC
A20
W
DQ12
DQ4
RP
WP
Reset
Write Protect
RP
12
13
37
36
V
DD
M28W320CT
M28W320CB
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
PP
WP
V
Supply Voltage
DD
Power Supply for
Input/Output Buffers
A19
A18
A17
A7
V
DDQ
Optional Supply Voltage for
Fast Program & Erase
V
V
PP
SS
A6
Ground
A5
A4
NC
Not Connected Internally
A3
V
SS
A2
E
A1
24
25
A0
AI03522
2/42
M28W320CT, M28W320CB
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
(2)
T
A
–40 to 85
–40 to 125
–55 to 155
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
BIAS
T
STG
V
–0.6 to V
+0.6
IO
DDQ
–0.6 to 4.1
–0.6 to 13
V
, V
DD DDQ
V
V
Program Voltage
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Depends on range.
DESCRIPTION
Data Input/Output. Memory control is provided by
Chip Enable E, Output Enable G and Write Enable
W inputs. The Program and Erase operations are
managed automatically by the P/E.C. Block pro-
tection against Program or Erase provides addi-
tional data security.
The M28W320C is a 32 Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a Word-by-
Word basis. The device is offered in the TSOP48
(10 x 20mm) and the µBGA47, 0.75mm ball pitch
packages. When shipped, all bits of the
M28W320C are in the 1 state.
Memory Blocks
The device features an asymmetrical blocked ar-
chitecture. The M28W320C has an array of 71
blocks: 8 Parameter Blocks of 4 KWord and 63
Main Blocks of 32 KWord. M28W320CT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W320CB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Tables 3 and 4.
All Blocks are protected at power up. Instruction
are provided to protect, unprotect any block in the
application. A second register locks the protection
status while WP is low (see Block Protection De-
scription). Each block can be erased separately.
Erase can be suspended in order to perform either
read or program in any other block and then re-
sumed. Program can be suspended to read data in
any other block and then resumed.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power UP. Blocks can be
unprotected to make changes in the application
and then reprotected. A parameter block ”Security
Block” can be permanently protected against pro-
gramming and erase in order to increase the data
security. Each block can be programmed and
erased over 100,000 cycles. V
the I/O pin down to 1.65V. An optional 12V V
allows to drive
DDQ
PP
power supply is provided to speed up the program
phase at customer production line environment.
An internal Command Interface (C.I.) decodes the
instructions to access/modify the memory content.
The Program/Erase Controller (P/E.C.) automati-
cally executes the algorithms taking care of the
timings necessary for program and erase opera-
tions. Verification is performed too, unburdening
the microcontroller, while the Status Register
tracks the status of the operation.
The architecture includes a 128 bits Protection
register that are divided into Two 64-bits segment.
In the first one, starting from address 81h to 84h,
is written a unique device number, while the sec-
ond one, starting from 85h to 88h, is programma-
ble by the user. The user programmable segment
can be permanently protected programming the
bit.1 of the Protection Lock Register (see protec-
tion register and Security Block). The parameter
block (# 0) is a security block. It can be permanent-
ly protected by the user programming the bit.2 of
the Protection Lock Register (see protection regis-
ter and Security Block).
The following instructions are executed by the
M28W320C: Read Array, Read Electronic Signa-
ture, Read Status Register, Clear Status Register,
Program, Double Word Program, Block Erase,
Program/Erase Suspend, Program/Erase Re-
sume, CFI Query, Block Protect, Block Lock, Block
Unprotect, Protection Program.
Organisation
The M28W320C is organised as 2 Mbit by 16 bits.
A0-A20 are the address lines; DQ0-DQ15 are the
3/42
M28W320CT, M28W320CB
Table 3. Top Boot Block Addresses,
M28W320CT
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F00000-F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
Size
(KWord)
#
Address Range
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
4
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
8
7
6
5
4
3
2
1
0
4/42
M28W320CT, M28W320CB
Table 4. Bottom Boot Block Addresses,
M28W320CB
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
Size
#
Address Range
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
5/42
M28W320CT, M28W320CB
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
memory is in reset mode: the outputs are put to
High-Z and the current consumption is minimised.
When RP is at V , the device is in normal opera-
IH
Address Inputs (A0-A20). The address signals
are inputs driven with CMOS voltage levels. They
are latched during a write operation.
tion. Exiting reset mode the device enters read ar-
ray mode.
V
Supply Voltage (2.7V to 3.6V). V
pro-
DD
DD
Data Input/Output (DQ0-DQ15). The data in-
puts, a word to be programmed or a command to
the C.I., are latched on the Chip Enable E or Write
Enable W rising edge, whichever occurs first. The
data output from the memory Array, the Electronic
Signature, the block protection status or Status
Register is valid when Chip Enable E and Output
Enable G are active. The output is high impedance
when the chip is deselected, the outputs are dis-
vides the power supply to the internal core of the
memory device. It is the main power supply for all
operations (Read, Program and Erase). It ranges
from 2.7V to 3.6V.
V
Supply Voltage (1.65V to V ). V
DD DDQ
DDQ
provides the power supply to the I/O pins and en-
ables all Outputs to be powered independently
from V . V
can be tied to V or it can use a
DD
DD
DDQ
separate supply. It can be powered either from
1.65V to V
abled or RP is tied to V . Commands are issued
IL
.
DD
on DQ0-DQ7.
V
Program Supply Voltage (12V). V is both
PP
PP
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
a control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
coders and sense amplifiers. E at V deselects
IH
the memory and reduces the power consumption
to the stand-by level. E can also be used to control
writing to the command register and to the memo-
If V is kept in a low voltage range (0V to 3.6V)
PP
V
PP
is seen as a control input. In this case a volt-
ry array, while W remains at V .
Output Enable (G). The Output Enable controls
the data Input/Output buffers.
age lower than V
gives an absolute protection
IL
PPLK
against program or erase, while V > V
en-
PP1
PP
ables these functions. V value is only sampled
PP
at the beginning of a program or erase; a change
in its value after the operation has been started
does not have any effect and program or erase are
carried on regularly.
Write Enable (W). This input controls writing to
the Command Register, Input Address and Data
latches.
Write Protect (WP). This input gives an addition-
al hardware protection level against program or
If V is used in the range 11.4V to 12.6V acts as
PP
a power supply pin. In this condition V
value
PP
erase when pulled at V , asdescribed in the Block
IL
must be stable until P/E algorithm is completed
Protection description.
(see Table 24 and 25).
Reset Input (RP). The RP input provides hard-
ware reset of the memory. When RP is at V , the
V
SS
Ground. V is the reference for all the volt-
SS
IL
age measurements.
6/42
M28W320CT, M28W320CB
DEVICE OPERATIONS
and Addresses are latched on the rising edge of W
or E, whichever occur first.
Four control pins rule the hardware access to the
Flash memory: E, G, W, RP. The following opera-
tions can be performed using the appropriate bus
cycles: Read, Write the Command of an Instruc-
tion, Output Disable, Stand-by, Reset (see Table
5).
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register and the CFI. Both Chip
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at V .
IH
Stand-by. Stand-by disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable E is at V and the device is in
IH
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
Enable (E) and Output Enable (G) must be at V
IL
in order to perform the read operation. The Chip
Enable input should be used to enable the device.
Output Enable should be used to gate data onto
the output independently of the device selection.
The data read depend on the previous command
written to the memory (see instructions RD, RSIG,
G or Write Enable W inputs. If E switches to V
IH
during program or erase operation, the device en-
ters in stand-by when finished.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high impedance. The memory is
RSR, RCFI). Read Array is the default state of the
device when exiting reset or after power-up.
Write. Write operations are used to give Com-
mands to the memory or to latch Input Data to be
programmed. A write operation is initiated when
in Reset mode when RP is at V . The power con-
IL
sumption is reduced to the stand-by level, inde-
pendently from the Chip Enable E, Out-put Enable
G or Write Enable W inputs. If RP is pulled to V
SS
during a Program or Erase, this operation is abort-
ed and the memory content is no longer valid as it
has been compromised by the aborted operation.
Chip Enable E and Write Enable W are at V with
IL
Output Enable G at V . Commands, Input Data
IH
(1)
Table 5. User Bus Operations
V
Operation
Read
E
G
W
RP
WP
X
DQ0-DQ15
Data Output
Data Input
Hi-Z
PP
V
V
V
V
Don’t Care
V or V
DD
IL
IL
IL
IL
IH
IH
IH
IH
V
V
V
V
V
V
V
Write
X
IL
IH
PPH
Output Disable
Stand-by
Reset
V
V
V
X
Don’t Care
Don’t Care
Don’t Care
IH
IH
IH
X
X
X
Hi-Z
IH
V
X
X
X
X
Hi-Z
IL
Note: 1. X = V or V , V = 12V ± 5%.
PPH
IL
IH
Table 6. Read Electronic Signature (RSIG Instruction)
Code
Device
E
G
W
A0 A1 A2-A7
A8-A11
A12-A20
DQ0-DQ7 DQ8-DQ15
Manufact.
Code
V
V
V
V
V
V
0
Don’t Care Don’t Care
20h
00h
IL
IL
IH
IL
IL
V
V
V
V
V
V
V
V
M28W320CT
M28W320CB
0
0
Don’t Care Don’t Care
Don’t Care Don’t Care
BAh
BBh
88h
88h
IL
IL
IL
IL
IH
IH
IH
IH
IL
IL
Device
Code
V
7/42
M28W320CT, M28W320CB
Table 7. Read Block Signature (RSIG Instruction)
Block Status
Protected Block
Unprotected Block
E
G
W
A0
A1 A2-A7
A8-A11
A12-A20
DQ0 DQ1 DQ2-DQ15
V
V
V
V
V
V
V
0
0
Don’t Care Block Address
Don’t Care Block Address
1
0
0
0
00h
00h
IL
IL
IL
IL
IL
IL
IH
IH
IH
IL
IH
IH
IH
V
V
V
V
V
V
V
V
IL
IL
(1)
Locked Block
0
Don’t Care Block Address
00h
X
1
Note: 1. A Locked Block can be protected ”DQ0 = 1” or unprotected ”DQ0 = 0”; see Block protection section.
Table 8. Read Protection Register and Protection Register Lock (RSIG Instruction)
Word
E
G
W
A0-A7
A8-A20
DQ0
DQ1
DQ2
DQ3-DQ7 DQ8-DQ15
OTP Prot.
data
Security
prot. data
V
V
V
Lock
80h Don’t Care
0
00h
00h
IL
IL
IH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Unique Id 0
Unique Id 1
Unique Id 2
Unique Id 3
OTP 0
81h Don’t Care
82h Don’t Care
83h Don’t Care
84h Don’t Care
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
IH
IH
ID data
ID data
85h Don’t Care OTP data
86h Don’t Care OTP data
87h Don’t Care OTP data
88h Don’t Care OTP data
OTP data
OTP data
OTP data
OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP 1
OTP 2
OTP 3
8/42
M28W320CT, M28W320CB
INSTRUCTIONS AND COMMANDS
read will output the Manufacturer Code, the De-
vice Code, the Block protection Status, or the Pro-
tection Register. See Tables 6, 7 and 8 for the
valid address. The Electronic Signature can be
read from the memory allowing programming
equipment or applications to automatically match
their interface to the characteristics of
M28W320C.
Sixteen instructions are available (see Tables 9
and 10)to perform Read Memory Array, Read Sta-
tus Register, Read Electronic Signature, CFI Que-
ry, Erase, Program, Double Word Program, Clear
Status Register, Program/Erase Suspend, Pro-
gram/Erase Resume, Block Protect, Block Unpro-
tect, Block Lock and Protection Register Program.
Status Register output may be read at any time,
during programming or erase, to monitor the
progress of the operation.
An internal Command Interface (C.I.) decodes the
instructions while an internal Program/Erase Con-
troller (P/E.C.) handles all timing and verifies the
correct execution of the Program and Erase in-
structions. P/E.C. provides a Status Register
whose bits indicate operation and exit status of the
internal algorithms.
CFI Query (RCFI)
The Common Flash Interface Query mode is en-
tered by writing 98h. Next readoperations will read
the CFI data. The CFI data structure contains also
a security area; in this section, a 64 bit unique se-
curity number is written, starting at this address
81h. This area can be accessed only in read mode
and there are no ways of changing the code after
it has been written by ST. Write a read instruction
to return to Read mode (refer to the Common
Flash Interface section).
The Command Interface is reset to Read Array
when power is first applied, when exiting from Re-
Table 9. Commands
set or whenever V
is lower than V
. Com-
DD
LKO
mand sequence must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read Array.
Hex Code
00h
Command
Invalid/Reserved
Read (RD)
10h
Alternative Program Set-up
Erase Set-up
The Read instruction consists of one write cycle
(refer to Device Operations section) giving the
command FFh. Next read operations will read the
addressed location and output the data. When a
device reset occurs, the memory is in Read Array
as default.
20h
30h
Double Word Program Set-up
Program Set-up
40h
50h
Clear Status Register
Read Status Register
Read Status Register (RSR)
The Status Register indicates when a program or
erase operation is complete and the success or
failure of operation itself. Issue a Read Status
Register Instruction (70h) to read the Status Reg-
ister content. The Read Status Register instruction
may be issued at any time, also when a Program/
Erase operation is ongoing. The following Read
operations output the content of the Status Regis-
ter. The Status Register is latched on the falling
edge of E or G signals, and can be read until E or
70h
Read Electronic Signature, or
CFI Query
90h or 98h
B0h
Program/Erase Suspend
Program/Erase Resume, Erase
Confirm or Unprotect Confirm
D0h
FFh
01h
2Fh
C0h
60h
Read Array
G returns to V . Either E or G must be toggled to
IH
update the latched data. Additionally, any read at-
tempt during program or eraseoperation will auto-
matically output the content of the Status Register.
Protect Confirm
Lock Confirm
Read Electronic Signature (RSIG)
Protection Program
Protection Set-up
The Read Electronic Signature instruction con-
sists of one write cycle (refer to Device Operations
section) giving the command 90h. A subsequent
9/42
M28W320CT, M28W320CB
Table 10. Instructions
1st Cycle
2nd Cycle
Addr.
3nd Cycle
Addr.
Mne-
monic
Instruction Cycles
(1)
Operat.
Data Operat.
Data
Operat.
Data
Addr.
Read Memory
Array
Read
Address
(2)
RD
1+
1+
Write
X
X
FFh
70h
Data
Read
Read
Read Status
Register
Status
Register
(2)
(2)
(2)
RSR
Write
Write
X
Read
Electronic
Signature
Signature
90h or
98h
RSIG
1+
X
Data
Read
Read
(3)
Address
98h or
90h
CFI
Address
RCFI
EE
Read CFI
Erase
1+
2
Write
Write
Write
Write
Write
55h
X
Query
D0h
Block
Address
20h
Write
40h or
10h
Data
Input
PG
Program
2
X
Write
Write
Address
Double Word
Program
Data
Input
Data
Input
(4)
3
X
30h
50h
Address 1
Write
Address 2
DPG
Clear Status
Register
(5)
1
X
CLRS
Program/
Erase
Suspend
PES
1
1
Write
Write
X
X
B0h
D0h
Program/
Erase
PER
Resume
Block
Address
BP
BU
BL
Block Protect
2
2
2
Write
Write
Write
X
X
X
60h
60h
60h
Write
Write
Write
01h
D0h
2Fh
Block
Unprotect
Block
Address
Block
Address
Block Lock
Protection
Register
Program
Data
Input
PRP
2
Write
X
C0h
Write
Address
Note: 1. X = Don’t Care.
2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the memory array or special register. Any
number of read cycle can occur after one command cycle.
3. The signature address recognized are listed in the Tables 6, 7 and 8.
4. Address 1 and Address 2 must be consecutive address differing only for address bit A0.
5. A read cycle after a CLSR instruction will output the memory array.
Erase (EE)
Status Register bit b7 returns ’0’ while the erasure
is in progress and ’1’ when it has completed. After
completion the Status Register bit b5 returns ’1’ if
there has been an Erase Failure. Status register
bit b1 returns ’1’ if the user is attempting to pro-
gram a protected block. Status Register bit b3 re-
Block erasure sets all the bits within the selected
block to ’1’. One block at a time can be erased. It
is not necessary to program the block with 00h as
the P/E.C. will do it automatically before erasing.
This instruction uses two write cycles. The first
command written is the Erase Set up command
20h. The second command is the Erase Confirm
command D0h. An address within the block to be
erased is given and latched into the memory dur-
ing the input of the second command. If the sec-
ond command given is not an erase confirm, the
status register bits b4 and b5 are set and the in-
struction aborts.
turns a ’1’ if V is below V
.
PP
PPLK
Erase aborts if RP turns to V . As data integrity
IL
cannot be guaranteed when the erase operation is
aborted, the erase must be repeated. A Clear Sta-
tus Register instruction must be issued to reset b1,
b3, b4 and b5 of the Status Register. During the
execution of the erase by the P/E.C., the memory
accepts only the RSR (Read Status Register) and
PES (Program/Erase Suspend) instructions.
Read operations output the status register after
erasure has started.
10/42
M28W320CT, M28W320CB
(1)
Table 11. Protection States
(2)
(3)
Current State
Next State After Event
Program/Erase
Allowed
(WP, DQ1, DQ0)
Protect
Unprotect
Lock
WP transition
100
101
110
111
000
001
yes
no
101
101
111
111
001
001
100
100
110
110
000
000
111
111
111
111
011
011
000
001
011
011
100
101
yes
no
yes
no
(4)
011
no
011
011
011
111 or 110
Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.
2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = V
IH
and A0 = V .
IL
3. Next state is the protection statusof a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
its logic value.
4. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.
IH
Table 12. Status Register Bits
Logic
Mnemonic
Bit
Name
Definition
Ready
Note
Level
’1’
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits b4 or b5 for Program or Erase
Success.
P/ECS
7
P/E.C. Status
’0’
Busy
’1’
’0’
Suspended
Erase
Suspend
Status
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until an
Erase Resume instruction is given.
ESS
6
In progress or
Completed
’1’
’0’
Erase Error
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
ES
PS
5
4
Erase Status
Erase Success
’1’
’0’
’1’
Program Error
Program
Status
PS bit set to ’1’ if the P/E.C. has failed to program
a word.
Program Success
V
V
Invalid, Abort
OK
V
bit is set if the V voltage is below V
PPS PP PPLK
PP
when a Program or Erase instruction is executed.
is sampled only at the beginning of the
V
Status
VPPS
PSS
3
2
PP
V
PP
’0’
PP
erase/program operation.
’1’
’0’
Suspended
Program
Suspend
Status
On a Program Suspend instruction P/ECS and
PSS bits are set to ’1’. PSS remains ’1’ until a
Program Resume Instruction is given.
In Progress or
Completed
Program/Erase on
protected Block,
Abort
’1’
’0’
Block
Protection
Status
BPS bit is set to ’1’ if a Program or Erase
operation has been attempted on a protected
block.
BPS
1
0
No operation to
protected blocks
Reserved
Note: Logic level ’1’ is High, ’0’ is Low.
11/42
M28W320CT, M28W320CB
Program (PG)
The memory array can be programmed word-by-
word. This instruction uses two write cycles. The
first command written is the Program Set-up com-
mand 40h (or 10h). A second write operation latch-
es the Address and the Data to be written and
starts the P/E.C.
tion must be issued to reset b4, b3 and b1 of the
Status Register.
During the execution of the program by the P/E.C.,
the memory accepts only the RSR (Read Status
Register) and PES (Program/Erase Suspend) in-
structions.
Clear Status Register (CLRS)
Read operations output the Status Register con-
tent after the programming has started. The Status
Register bit b7 returns ’0’ while the programming
is in progress and ’1’ when it has completed. After
completion the Status register bit b4 returns ’1’ if
there has been a Program Failure. Status register
bit b1 returns ’1’ if the user is attempting to pro-
gram a protected block. Status Register bit b3 re-
The Clear Status Register uses a single write op-
eration which clears bits b1, b3, b4 and b5 to 0. Its
use is necessary before any new operation when
an error has been detected.
The Clear Status Register is executed writing the
command 50h.
Program/Erase Suspend (PES)
turns a ’1’ if V
is below V
. Programming
Program/Erase suspend is accepted only during
the Program Erase instruction execution. When a
Program/Erase Suspend command is written to
the C.I., the P/E.C. freezes the Program/Erase op-
eration. Program/Erase Resume (PER) continues
the Program/Erase operation. Program/Erase
Suspend consists of writing the command B0h
without any specific address.
The Status Register bit b2 is set to ’1’ (within 5µs)
when the program has been suspended. b2 is set
to ’0’ in case the program is completed or in
progress. The Status Register bit b6 is set to ’1’
(within 30µs) when the erase has been suspend-
ed. b6 is set to ’0’ in case the erase is completed
or in progress. The valid commands while erase is
suspended are: Program/Erase Resume, Pro-
gram, Read Array, Read Status Register, Read
Identifier, CFI Query, Block Protect, Block Unpro-
tect, Block Lock and Protection Program. The user
can protect the Block being erased issuing the
Block Protect, Block Lock or Protection Program
commands. In this case the protection status bit
will change immediately, but when the erase is re-
sumed, the operation will complete The valid com-
mands while program is suspended are: Program/
Erase Resume, Read Array, Read Status Regis-
ter, Read Identifier, CFI Query.
PP
PPLK
aborts if RP goes to V . As data integrity cannot
IL
be guaranteed when the program operation is
aborted, the memory location must be erased and
reprogrammed. A Clear Status Register instruc-
tion must be issued to reset b4, b3 and b1 of the
Status Register.
During the execution of the program by the P/E.C.,
the memory accepts only the RSR (Read Status
Register) and PES (Program/Erase Suspend) in-
structions.
Double Word Program (DPG)
This featureis offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0. Programming should not be attempt-
ed when V is not at V
. The operation can
PP
PPH
also be executed if V is below V
but result
PP
PPH
could be uncertain. This instruction uses three
write cycles. The first command written is the Dou-
ble Word Program Set-Up command 30h. A sec-
ond write operation latches the Address and the
Data of the first word to be written, the third write
operation latches the Address and the Data of the
second word to be written and starts the P/E.C.
Read operations output the Status Register con-
tent after the programming has started. The Status
Register bit b7 returns ’0’ while the programming
is in progress and ’1’ when it has completed. After
completion the Status register bit b4 returns ’1’ if
there has been a Program Failure. Status register
bit b1 returns ’1’ if the user is attempting to pro-
gram a protected block. Status Register bit b3 re-
During program/erase suspend mode, the chip
can be placed in a pseudo-stand-by mode by tak-
ing E to V This reduces active current consump-
IH
tion. Program/Erase is aborted if RP turns to V .
IL
Program/Erase Resume (PER)
If a Program/Erase Suspend instruction was previ-
ously executed, the program/erase operation may
be resumed by issuing the command D0h. The
status register bit b2/b6 is cleared when program/
erase resumes. Read operations output the status
register after the program/erase is resumed.
turns a ’1’ if V
is below V
. Programming
PP
PPLK
aborts if RP goes to V . As data integrity cannot
IL
be guaranteed when the program operation is
aborted, the memory location must be erased and
reprogrammed. A Clear Status Register instruc-
12/42
M28W320CT, M28W320CB
The suggested flow charts for programs that use
the programming, erasure and program/erase
suspend/resume features of the memories are
shown from Figures 11, 12, 13, 14 and 15.
second command is block Protect command 01h.
The address within the block being protected must
be given in order to write theprotection state. If the
second command is not recognized by the C.I the
bit 4 and bit 5 of the status register will be set to in-
dicate a wrong sequence of commands. To read
the status register write the RSR command.
Protection Register Program (PRP)
The Protection Register Program uses two write
cycles. The first command written is the protection
program command C0h. The second write opera-
tion latches the Address and the Data to be written
to the Protection Register (see Protection Register
and Security Block) and start the PE/C. Read op-
erations output the Status Register content after
the programming has started. The 64 bits user
programmable Segment (85h to 88h) are pro-
grammed 16 bits at a time, it can be protected by
the user programming bit 1 of the Protection Lock
register. The bit 1 of the Protection Lock register
protect the bit 2 of the Protection Lock Register.
Writing thebit 2 of the Protection Lock Register will
result in a permanent protection of the Security
Block. Attempting to program apreviously protect-
ed protection Register will result in a status regis-
ter error (bit 1and bit 4 of the status register will be
set to ’1’). The protectionof the Protection Register
and/or the Security Block is not reversible.
Block Unprotect (BU)
The instruction use two write cycles. The first com-
mand written is the protection setup 60h. The sec-
ond command is block Unprotect command d0h.
The address within the block being unprotected
must be given in order to write the unprotection
state. If the second command is not recognized by
the C.I the bit 4 and bit 5 of the status register will
be set to indicate a wrong sequence of com-
mands. To read the status register write the RSR
command.
Block Lock (BL)
The instruction use two write cycles. The first com-
mand written is the protection setup 60h. The sec-
ond command is block Lock command 2Fh. The
address within the block being Locked must be
given in order to write the Locking state. If the sec-
ond command is not recognized by the C.Ithe bit 4
and bit 5of the status registerwill be set to indicate
a wrong sequence of commands. To read the sta-
tus register write the RSR command.
The Protection Register Program cannot be sus-
pended.
Block Protect (BP)
The BP instruction use two write cycles. The first
command written is the protection setup 60h. The
Table 13. Program, Erase Times and Program/Erase Endurance Cycles
(T = 0 to 70°C or –40 to 85°C; V = 2.7V to 3.6V)
A
DD
M28W320C
Parameter
Test Conditions
Unit
(1)
Min
Max
200
200
5
Typ
V
= V
DD
Word Program
10
10
µs
µs
PP
V
V
= 12V ±5%
= 12V ±5%
= V
Double Word Program
PP
0.16
0.32
0.02
0.04
1
sec
sec
sec
sec
sec
sec
sec
sec
cycles
PP
Main Block Program
Parameter Block Program
Main Block Erase
V
5
PP
DD
V
V
V
= 12V ±5%
4
PP
V
= V
4
PP
DD
= 12V ±5%
10
10
10
10
PP
V
= V
1
PP
DD
= 12V ±5%
0.8
0.8
PP
Parameter Block Erase
V
= V
PP
DD
Program/Erase Cycles (per Block)
100,000
Note: T = 25 °C.
A
13/42
M28W320CT, M28W320CB
BLOCK PROTECTION
PROTECTION REGISTER
and SECURITY BLOCK
The M28W320C provide a flexible protection of all
the memory providing the protection unprotection
and locking of any blocks. All blocks are protected
at power-up. Each block of the array has two lev-
els of protection against program or erase opera-
tion. The first level is set by the Block Protect
instruction; a protected block cannot be pro-
grammed or erased until a Block Unprotect in-
struction is given for that block. A second level of
protection is set by the Block Lock instruction, and
requires the use of the WP pin, according to the
following scheme:
The M28W320C features a 128-bit protection reg-
ister and a security Block in order to increase the
protection of a system design. The Protection
Register is divided in two 64-bit segment. The first
segment (81h to 84h) is a unique device number,
while the second one (85h to 88h) can be pro-
grammed by the user. When shipped the user pro-
grammable segment is read at ’1’. It can be only
programmed at ’0’;
The user programmable segment can be protect-
ed writing the bit 1 of the Protection Lock register
(80h). The bit 1 protect also the bit 2 of the Protec-
tion Lock Register. The M28W320C feature a se-
curity Block. The security Block is located at
1FF000-1FFFFF (M28W320CT) or at 000000-
000FFF (M28W320CB) of the device. This block
can be permanently protected by the user pro-
gramming the bit 2 of the Protection Lock Register.
– when WP is at V , the Lock status is overridden
IH
and all blocks can be protected or unprotected;
– when WP is at V , Lock status is enabled; the
IL
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status;
The protection Register and the Protection Lock
Register can be read using the RSIG command. A
subsequent read in the address starting from 80h
to 88h, the user will retrieve respectively the Pro-
tection Lock register, the unique device number
segment and the OTP user programmable register
segment (see Table 8).
– the lock status is cleared for all blocks at power
up.
The protection and lock status can be monitored
for each block using the Read Electronic Signature
(RSIG) instruction. Protected blocks will output a
’1’ on DQ0 and locked blocks will output a ’1’ in
DQ1.
Figure 4. Security Block Memory Map
88h
User Programmable OTP
Unique device number
85h
84h
Parameter Block # 0
81h
Protection Register Lock
2
1
0
80h
AI03523
14/42
M28W320CT, M28W320CB
POWER CONSUMPTION
Stand-by or Reset
The M28W320C puts itself in one of four different
modes depending on the status of the control sig-
nals: Active Power, Automatic Stand-by, Stand-by
and Reset define decreasing levels of current con-
sumption. These allow the memory power to be
minimised, in turn decreasing the overall system
power consumption. As different recovery time are
linked to the different modes, please refer to the
AC timing Table to design your system.
Refer to the Device Operations section.
Power Up
The Supply voltage V and the Program Supply
DD
voltage V
can be applied in any order. The
PP
memory Command Interface is reset on power up
to Read Memory Array, but a negative transition of
Chip Enable E or a change of the addresses is re-
quired to ensure valid data outputs. Care must be
taken to avoid writes to the memory when V
is
DD
Active Power
above V
. Writes can be inhibited by driving ei-
LKO
When E is at V and RP is at V , the device is in
ther E or W to V . The memory is disabled if RP
IL
IH
IH
active mode. Refer to DC Characteristics to get
is at V .
IL
the values of the current supply consumption.
Supply Rails
Automatic Stand-by
Normal precautions must be taken for supply volt-
age decoupling, each device in a system should
Automatic Stand-by provides a low power con-
sumption state during read mode. Following a
read operation, after a delay close to the memory
access time, the device enters Automatic Stand-
by: the Supply Current is reduced to ICC1 values.
The device keeps the last output data stable, till a
new location is accessed.
have the V
and V
rails decoupled with a
DD
PP
0.1µF capacitor close to the V and V pins.The
DD
PP
PCB trace widths should be sufficient to carry the
required V program and erase currents.
PP
15/42
M28W320CT, M28W320CB
COMMON FLASH INTERFACE (CFI)
The CFI data structure gives information on the
device, such as the sectorization, the command
set and some electrical specifications. Tables 14,
15, 16 and 17 show the addresses used to retrieve
each data. The CFI data structure contains also a
security area; in this section, a 64 bit unique secu-
rity number is written, starting at address 81h. This
area can be accessed only in read mode and there
are no ways of changing the code after it has been
written by ST. Write a read instruction to return to
Read mode. Refer to the CFI Query instruction to
understand how the M28W320C enters the CFI
Query mode.
The Common Flash Interface (CFI) specification is
a JEDEC approved, standardised data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 14, 15, 16, 17, 18 and 19 show the address
used to retrieve each data.
Table 14. Query Structure Overview
Offset
Sub-section Name
Description
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
00h
Reserved
10h
CFI Query Identification String
System Interface Information
Device Geometry Definition
1Bh
27h
Additional information specific to the Primary
Algorithm (optional)
P
A
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 15, 16, 17, 18 and 19. Query data are always presented on the lowest order data outputs.
Table 15. CFI Query Identification String
Offset
Data
Description
00h
0020h
Manufacturer Code
Device Code
Reserved
88BAh - top
88BBh - bottom
01h
02h-0Fh
10h
reserved
0051h
Query Unique ASCII String ”QRY”
Query Unique ASCII String ”QRY”
Query Unique ASCII String ”QRY”
11h
0052h
12h
0059h
13h
0003h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
14h
0000h
15h
offset = P = 0035h
0000h
Address for Primary Algorithm extended Query table
16h
17h
0000h
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported (note: 0000h means none exists)
18h
0000h
19h
value = A = 0000h
0000h
Address for Alternate Algorithm extended Query table
note: 0000h means none exists
1Ah
Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
16/42
M28W320CT, M28W320CB
Table 16. CFI Query System Interface Information
Offset
Data
Description
V
V
V
Logic Supply Minimum Program/Erase or Write voltage
DD
DD
PP
1Bh
0027h
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
Logic Supply Maximum Program/Erase or Write voltage
1Ch
1Dh
0036h
00B4h
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
[Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
Note: This value must be 0000h if no V pin is present
PP
V
[Programming] Supply Maximum Program/Erase voltage
PP
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
1Eh
00C6h
Note: This value must be 0000h if no V pin is present
PP
n
Typical timeout per single byte/word program (multi-byte program count = 1), 2 µs
(if supported; 0000h = not supported)
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0000h
000Ah
0000h
0004h
0000h
0003h
0000h
n
Typical timeout for maximum-size multi-byte program or page write, 2 µs
(if supported; 0000h = not supported)
n
Typical timeout per individual block erase, 2 ms
(if supported; 0000h = not supported)
n
Typical timeout for full chip erase, 2 ms
(if supported; 0000h = not supported)
n
Maximum timeout for byte/word program, 2 times typical (offset 1Fh)
(0000h = not supported)
n
Maximum timeout for multi-byte program or page write, 2 times typical (offset 20h)
(0000h = not supported)
n
Maximum timeout per individual block erase, 2 times typical (offset 21h)
(0000h = not supported)
n
Maximum timeout for chip erase, 2 times typical (offset 22h)
(0000h = not supported)
17/42
M28W320CT, M28W320CB
Table 17. Device Geometry Definition
Offset Word
Data
Description
Mode
n
27h
28h
29h
2Ah
2Bh
2Ch
0016h
0001h
0000h
0000h
0000h
0002h
Device Size = 2 in number of bytes
Flash Device Interface Code description: Asynchronous x16
n
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within device
bit 7 to 0 = x = number of Erase Block Regions
Note:1. x = 0 means no erase blocking, i.e. the device erases at once in ”bulk.”
2. x specifies the number of regions within the device containing one or more con-
tiguous Erase Blocks of the same size. For example, a 128KB device (1Mb)
having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is consid-
ered to have 5 Erase Block Regions. Even though two regions both contain
16KB blocks, the fact that they are not contiguous means they are separate
Erase Block Regions.
3. By definition, symmetrically block devices have only one blocking region.
M28W320CT M28W320CT Erase Block Region Information
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
001Eh
0000h
0000h
0001h
0007h
0000h
0020h
0000h
bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in
size. The value z = 0 is used for 128 byte block size.
e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K
bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase
Block Region:
e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]
y = 0 means no blocking (# blocks = y+1 = ”1 block”)
Note: y = 0 value must be used with number of block regions of one as indicated
by (x) = 0
M28W320CB M28W320CB
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
0007h
0000h
0020h
0000h
001Eh
0000h
0000h
0001h
18/42
M28W320CT, M28W320CB
Table 18. Primary Algorithm-Specific Extended Query Table
Offset
Data
Description
(P)h = 35h
0050h
0052h
0049h
0031h
0030h
0006h
0000h
0000h
0000h
Primary Algorithm extended Query table unique ASCII string “PRI”
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
Major version number, ASCII
Minor version number, ASCII
Extended Query table contents for Primary Algorithm
bit 0
bit 1
bit 2
bit 3
bit 4
Chip Erase supported
Erase Suspend supported
Program Suspend
Lock/Unlock supported
Quequed Erase supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(P+7)h
(P+8)h
bit 31 to 5 Reserved; undefined bits are ‘0’
(P+9)h = 3Eh
0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported during Erase or
Program operation
bit 0
Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 3Fh
(P+B)h
0000h
0000h
Block Lock Status
Defines which bits in the Block Status Register section of the Query are implemented.
bit 0
bit 1
Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No)
Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
(P+C)h = 41h
(P+D)h = 42h
(P+E)h
0027h
00C0h
0000h
V
V
Logic Supply Optimum Program/Erase voltage (highest performance)
DD
PP
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
Reserved
Table 19. Security Code Area
Offset
80h
81h
82h
83h
84h
85h
86h
87h
88h
Data
00XX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Description
Protection Register Lock
64 bits: unique device number
64 bits: User Programmable OTP
19/42
M28W320CT, M28W320CB
Table 20. DC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = V
= 2.7V to 3.6V)
Test Condition
0V≤ V ≤ V
A
DD
DDQ
Symbol
Parameter
Min
Typ
Max
±1
Unit
µA
I
Input Leakage Current
Output Leakage Current
Supply Current (Read)
LI
IN
DDQ
I
0V≤ V
≤V
OUT DDQ
±10
20
µA
LO
I
E = V , G = V , f = 5MHz
10
15
mA
CC
SS
IH
E = V
RP = V
± 0.2V,
Supply Current (Stand-by or
Automatic Stand-by)
DDQ
I
I
50
50
20
20
20
20
50
400
µA
µA
CC1
CC2
± 0.2V
DDQ
Supply Current
(Reset)
RP = V ± 0.2V
15
10
10
5
SS
Program in progress
mA
mA
mA
mA
µA
V
= 12V ± 5%
PP
I
Supply Current (Program)
Supply Current (Erase)
CC3
Program in progress
= V
V
PP
DD
Erase in progress
= 12V ± 5%
V
PP
I
I
CC4
CC5
Erase in progress
= V
5
V
PP
DD
E = V
Erase suspended
± 0.2V,
Supply Current
(Program/Erase Suspend)
DDQ
Program Current
(Read or Stand-by)
I
V
V
> V
µA
PP
PP
PP
DD
Program Current
(Read or Stand-by)
I
≤ V
5
5
µA
µA
mA
PP1
DD
I
RP = V ± 0.2V
Program Current (Reset)
PP2
SS
Program in progress
10
V
= 12V ± 5%
PP
I
Program Current (Program)
PP3
Program in progress
= V
5
10
5
µA
mA
µA
V
PP
DD
Erase in progress
= 12V ± 5%
V
PP
I
Program Current (Erase)
PP4
Erase in progress
= V
V
PP
DD
–0.5
–0.5
0.4
0.8
V
V
V
V
V
Input Low Voltage
Input High Voltage
IL
V
V
≥ 2.7V
≥ 2.7V
DDQ
DDQ
V
–0.4
V
V
+0.4
DDQ
DDQ
DDQ
V
IH
0.7 V
+0.4
DDQ
I
= 100µA, V = V min,
DD DD
OL
V
Output Low Voltage
Output High Voltage
0.1
V
V
V
OL
V
= V
min
DDQ
DDQ
I
= –100µA, V = V min,
DD DD
OH
V
OH
V
–0.1
DDQ
V
= V
min
DDQ
DDQ
Program Voltage (Program or
Erase operations)
V
1.65
3.6
PP1
PPH
Program Voltage
(Program or Erase
operations)
V
11.4
12.6
V
Program Voltage
(Program and Erase lock-out)
V
1
2
V
V
PPLK
V
Supply Voltage (Program
DD
V
LKO
and Erase lock-out)
20/42
M28W320CT, M28W320CB
Table 21. AC Measurement Conditions
Figure 6. AC Testing Load Circuit
Input Rise and Fall Times
≤ 10ns
0 to V
V
/2
DDQ
Input Pulse Voltages
DDQ
Input and Output Timing Ref. Voltages
V
/2
DDQ
1N914
3.3kΩ
Figure 5. AC Testing Input Output Waveform
DEVICE
UNDER
TEST
OUT
V
DDQ
C
= 50pF
L
V
/2
DDQ
0V
C
includes JIG capacitance
L
AI00610
AI00609B
(1)
Table 22. Capacitance (T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
= 0V
Min
Max
6
Unit
pF
C
IN
V
IN
C
OUT
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
21/42
M28W320CT, M28W320CB
(1)
Table 23. Read AC Characteristics
A
(T = 0 to 70°C or –40 to 85°C)
M28W320C
90
100
Unit
Symbol
Alt
Parameter
V
= 2.7V to 3.6V
V
= 2.7V to 3.6V
DD
DD
V
= 2.7V min
Max
V
= 1.65V min
DDQ
DDQ
Min
100
Min
Max
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
90
ns
ns
AVAV
RC
t
t
90
100
AVQV
ACC
(2)
(2)
(2)
(3)
(2)
(2)
(2)
(3)
(2)
t
t
Address Transition to Output Transition
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
t
OH
OH
AXQX
EHQX
t
t
25
90
30
t
HZ
EHQZ
t
Chip Enable Low to Output Valid
100
t
CE
ELQV
t
Chip Enable Low to Output Transition
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
0
0
0
0
t
LZ
ELQX
t
t
OH
GHQX
t
25
30
30
35
t
DF
GHQZ
t
t
t
OE
GLQV
t
Output Enable Low to Output Transition
Reset High to Output Valid
Reset Pulse Width
0
0
ns
ns
ns
OLZ
GLQX
t
t
PWH
150
150
PHQV
(2,4)
t
100
100
t
RP
PLPH
Note: 1. See AC Testing Measurement conditions for timing measurements.
2. Sampled only, not 100% tested.
3. G may be delayed by up to t
- t
after the falling edge of E without increasing t
.
ELQV
ELQV GLQV
4. The device Reset is possible but not guaranteed if t
< 100ns.
PLPH
22/42
M28W320CT, M28W320CB
Figure 7. Read AC Waveforms
23/42
M28W320CT, M28W320CB
(1)
Table 24. Write AC Characteristics, Write Enable Controlled
A
(T = 0 to 70°C or –40 to 85°C)
M28W320C
90
= 2.7V to 3.6V
100
Symbol
Alt
Parameter
Unit
V
V
= 2.7V to 3.6V
DD
DD
V
= 2.7V min
V
= 1.65V min
DDQ
DDQ
Min
100
50
Min
90
50
50
0
Max
Max
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
AVAV
t
t
Address Valid to Write Enable High
Data Valid to Write Enable High
Chip Enable Low to Write Enable Low
Reset High to Write Enable Low
Reset Pulse Width
AVWH
AS
DS
CS
t
t
t
50
DVWH
t
0
ELWL
PHWL
t
t
t
90
100
PS
(2, 3)
100
100
ns
t
t
RP
PLPH
PLRH
(2, 4)
Reset Low to Program/Erase Abort
30
30
µs
(2, 5)
Output Valid to V Low
0
0
0
0
ns
ns
ns
t
PP
QVVPL
t
Data Valid to Write Protect Low
QVWPL
(2)
t
V
High to Write Enable High
PP
200
200
t
VPS
VPHWH
t
t
t
t
Write Enable High to Address Transition
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Protect High to Write Enable High
Write Cycle Time
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WHAX
AH
0
WHDX
WHEH
DH
t
t
CH
0
0
t
30
30
50
50
90
50
30
30
50
50
100
50
WHGL
t
t
WPH
WHWL
t
t
WLWH
WP
t
WPHWH
t
t
AVAV
WC
t
t
Address Valid to Write Enable High
AVWH
AS
Note: 1. See AC Testing Measurement conditions for timing measurements.
2. Sampled only, not 100% tested.
3. The device Reset is possible but not guaranteed if t
< 100ns.
PLPH
4. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.
5. Applicable if V is seen as a logic input (V < 3.6V).
PP
PP
24/42
M28W320CT, M28W320CB
Figure 8. Write AC Waveforms, W Controlled
25/42
M28W320CT, M28W320CB
(1)
Table 25. Write AC Characteristics, Chip Enable Controlled
A
(T = 0 to 70°C or –40 to 85°C)
M28W320C
90
= 2.7V to 3.6V
100
Symbol
Alt
Parameter
Unit
V
V
= 2.7V to 3.6V
DD
DD
V
= 2.7V min
= 1.65V min
DDQ
VDDQ
Min
100
50
Min
90
50
50
0
Max
Max
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
t
t
t
Address Valid to Chip Enable High
Data Valid to Chip Enable High
AVEH
DVEH
EHAX
AS
t
50
DS
t
Chip Enable High to Address Transition
Chip Enable High to Data Transition
Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Chip Enable Low to Chip Enable High
Reset High to Chip Enable Low
0
AH
DH
t
0
0
EHDX
t
t
CPH
30
30
0
30
EHEL
EHGL
t
30
t
t
WH
0
EHWH
t
t
CP
50
90
50
ELEH
t
t
PS
100
PHEL
(2, 3)
t
Reset Pulse Width
100
100
ns
µs
ns
t
RP
PLPH
(2, 4)
(2, 5)
Reset Low to Program/Erase Abort
30
30
t
PLRH
Output Valid to V Low
0
0
t
PP
QVVPL
t
Data Valid to Write Protect Low
0
200
0
0
200
0
ns
ns
ns
ns
ns
ns
QVWPL
(2)
t
V
High to Chip Enable High
PP
t
VPS
VPHEH
t
t
Write Enable Low to Chip Enable Low
Write Protect High to Chip Enable High
Write Cycle Time
WLEL
CS
t
50
90
50
50
100
50
WPHEH
t
t
WC
AVAV
t
t
AS
Address Valid to Chip Enable High
AVEH
Note: 1. See AC Testing Measurement conditions for timing measurements.
2. Sampled only, not 100% tested.
3. The device Reset is possible but not guaranteed if t
< 100ns.
PLPH
4. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode.
5. Applicable if V is seen as a logic input (V < 3.6V).
PP
PP
26/42
M28W320CT, M28W320CB
Figure 9. Write AC Waveforms, E Controlled
27/42
M28W320CT, M28W320CB
Figure 10. Reset AC Waveform
Reset during Read Mode
tPLPH
RP
tPHQV
Reset during Program with tPLPH ≤ tPLRH
Abort
Complete
tPHWL
tPHEL
tPLRH
tPLPH
RP
Reset during Program/Erase with tPLPH > tPLRH
Abort
Complete
tPLRH
Reset
tPHWL
tPHEL
tPLPH
RP
AI03537
28/42
M28W320CT, M28W320CB
Figure 11. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
Command
Program instruction:
– write 40h or 10h command
– write Address & Data
(memory enters read status state after
the Program instruction)
Write Address
& Data
do:
NO
Read Status
– read status register (E or G must be
toggled) if PES instruction given execute
suspend program loop
Register
Suspend
YES
NO
Suspend
Loop
b7 = 1
YES
while b7 = 1
NO
NO
NO
V
Invalid
If b3 = 1, V
invalid error:
PP
PP
– error handler
b3 = 0
YES
Error (1, 2)
Program
If b4 = 1, Program error:
– error handler
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
If b1 = 1, Program to protected block error:
– error handler
b1 = 0
YES
End
AI03538
Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after
PP
a sequence.
2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
29/42
M28W320CT, M28W320CB
Figure 12. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
Command
DPG instruction:
– write 30h command
– write Address 1 & Data 1 (3)
– write Address 2 & Data 2 (3)
(memory enters read status state after
the Program instruction)
Write Address
& Data 1 (3)
1
2
Write Address
& Data 2 (3)
NO
do:
Read Status
Register
– read status register (E or G must be
toggled) if PES instruction given execute
DPG suspend loop
Suspend
YES
NO
NO
NO
NO
Suspend
Loop
b7 = 1
YES
while b7 = 1
V
Invalid
Error (1, 2)
If b3 = 1, V
invalid error:
PP
PP
– error handler
b3 = 0
YES
Program
Error (1, 2)
If b4 = 1, Program error:
– error handler
b4 = 0
YES
Program to Protected
Block Error (1, 2)
If b1 = 1, Program to protected block error:
– error handler
b1 = 0
YES
End
AI03539
Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after
PP
a sequence.
2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for address bit A0.
30/42
M28W320CT, M28W320CB
Figure 13. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Command
PES instruction:
– write B0h command
do:
Write 70h
Command
– read status register
(E or G must be toggled)
Read Status
Register
NO
NO
b7 = 1
YES
while b7 = 1
b2 = 1
YES
Program Complete
If b2 = 0 Program completed
Write a read
Command
Read data from
another address
PER instruction:
– write D0h command to resume
the program
Write D0h
Command
Write FFh
Command
– if the program operation completed
then this is not necessary.
The device returns to Read Array as
normal (as if the Program/Erase
suspend was not issued).
Read Data
Program Continues
AI03540
31/42
M28W320CT, M28W320CB
Figure 14. Erase Flowchart and Pseudo Code
Start
Write 20h
Command
EE instruction:
– write 20h command
– write Block Address (A12-A20) &
command D0h
(memory enters read status state after
the EE instruction)
Write Block Address
& D0h Command
do:
– read status register (E or G must be
toggled) if PES instruction given execute
suspend erase loop
NO
Read Status
Register
Suspend
YES
NO
Suspend
Loop
b7 = 1
while b7 = 1
YES
NO
NO
NO
NO
V
Invalid
If b3 = 1, V
invalid error:
– error handler
PP
Error (1)
PP
b3 = 0
YES
Command
Sequence Error (1)
If b4, b5 = 1, Command sequence error:
– error handler
b4, b5 = 0
YES
If b5 = 1, Erase error:
– error handler
b5 = 0
YES
Erase Error (1)
Erase to Protected
Block Error (1)
If b1 = 1, Erase to protected block error:
– error handler
b1 = 0
YES
End
AI03541
Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
32/42
M28W320CT, M28W320CB
Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Command
PES instruction:
– write B0h command
do:
Write 70h
Command
– read status register
(E or G must be toggled)
Read Status
Register
NO
NO
b7 = 1
YES
while b7 = 1
b6 = 1
YES
Erase Complete
If b6 = 0, Erase completed
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
PER instruction:
– write D0h command to resume
erasure
Write D0h
Command
Write FFh
Command
– if the erase operation completed
then this is not necessary.
The device returns to Read Array as
normal (as if the Program/Erase
suspend was not issued).
Read Data
Erase Continues
AI03542
33/42
M28W320CT, M28W320CB
Figure 16. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE (1)
NO
90h
YES
READ
SIGNATURE
NO
98h
YES
CFI
QUERY
NO
70h
YES
READ
STATUS
NO
50h
YES
CLEAR
STATUS
NO
60h
YES
BP/BU/BL
SET-UP
NO
C0h
YES
D
READ
ARRAY
READ
STATUS
PRP
SET-UP
NO
40h or
10h
YES
PROGRAM
SET-UP
NO
YES
READY
(2)
30h
YES
PRP
C
NO
DPG
SET-UP
NO
B
20h
YES
B
C
ERASE
SET-UP
NO
FFh
YES
BP/BU/BL
COMMAND
ERROR
NO
NO
NO
01h
YES
D0h
YES
2Fh
YES
NO
D0h
BLOCK
PROTECT
BLOCK
UNPROTECT
BLOCK
LOCK
YES
ERASE
COMMAND
ERROR
A
AI03543
Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or
if V falls below V , the Command Interface defaults to Read Array mode.
DD
LKO
2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
34/42
M28W320CT, M28W320CB
Figure 17. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
(READ STATUS)
YES
READY
(2)
NO
NO
B0h
ERASE
SUSPENDED
NO
YES
READ
STATUS
YES
ERASE
SUSPEND
YES
READ
STATUS
70h
NO
YES
READY
(2)
YES
YES
YES
YES
READ
SIGNATURE
90h
NO
NO
READ
STATUS
CFI
QUERY
98h
NO
PROGRAM
SET-UP
40h or
10h
c
c
NO
DPG
SET-UP
30h
NO
YES
PRP
SET-UP
YES
PRP
READY
(2)
C0h
NO
NO
B
YES
NO
BP/BU/BL
SET-UP
60h
NO
D
YES
(READ STATUS)
READ
ARRAY
ERASE
RESUME
D0h
AI03544
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
35/42
M28W320CT, M28W320CB
Figure 18. Command Interface and Program Erase Controller Flowchart (c)
C
B
PROGRAM
(READ STATUS)
YES
READY
(2)
NO
NO
B0h
YES
READ
STATUS
PROGRAM
SUSPEND
NO
PROGRAM
SUSPENDED
YES
READY
(2)
YES
NO
YES
READ
STATUS
READ
STATUS
70h
NO
YES
YES
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
(READ STATUS)
YES
READ
ARRAY
PROGRAM
RESUME
D0h
AI03545
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
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M28W320CT, M28W320CB
Table 26. Ordering Information Scheme
Example:
M28W320CT
90
N
6
T
Device Type
M28
Operating Voltage
W = V = 2.7V to 3.6V; V
= 1.65V or 2.7V
DDQ
DD
Device Function
320C = 32 Mbit (2 Mb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Random Speed
90 = 90 ns
100 = 100 ns
Package
N = TSOP48: 12 x 20 mm
GB = µBGA47: 0.75 mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
Table 27. Daisy Chain Ordering Scheme
Example:
M28W320C
-GB T
Device Type
M28W320C
Daisy Chain
-GB = µBGA47: 0.75 mm pitch
Option
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
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M28W320CT, M28W320CB
Table 28. Revision History
Date
Revision Details
February 2000
First Issue
Daisy Chain part numbering defined
04/19/00
µBGA Package Outline diagram change (Figure 20)
µBGA Chain diagrams, Package and PCB Connection re-designed (Figure 21, 22)
05/17/00
µBGA Package Outline diagram and Package Mechanical Data change (Figure 20, Table 30)
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M28W320CT, M28W320CB
Table 29. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
12.10
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.4764
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
11.90
–
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.4685
–
C
D
D1
E
e
0.50
0.0197
L
0.50
0°
0.70
5°
0.0197
0°
0.0276
5°
α
N
48
48
CP
0.10
0.0039
Figure 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
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M28W320CT, M28W320CB
Table 30. µBGA47 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data
mm
inch
Min
Symbol
Typ
Min
Max
Typ
Max
A
A1
A2
b
1.000
0.0394
0.180
–
0.0071
–
0.700
0.350
10.500
3.750
–
0.0276
0.0138
0.4134
0.1476
–
0.300
10.450
–
0.400
0.0118
0.4114
–
0.0157
D
10.550
0.4154
D1
ddd
e
–
–
0.080
0.0031
0.750
6.390
5.250
3.375
0.570
–
–
0.0295
0.2516
0.2067
0.1329
0.0224
–
–
E
6.340
6.440
0.2496
0.2535
E1
FD
FE
–
–
–
–
–
–
–
–
–
–
–
–
Figure 20. µBGA47 - 8 x 6 balls, 0.75 mm pitch, Bottom View Package Outline
E
E1
FE
SE
FD
SD
D
D1
e
BALL ”A1”
ddd
e
b
A2
A
A1
BGA-G06
Drawing is not to scale.
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M28W320CT, M28W320CB
Figure 21. µBGA47 Daisy Chain - Package Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
AI03295
Figure 22. µBGA47 Daisy Chain - PCB Connections (Top view through package)
1
2
3
4
5
6
7
8
START
POINT
A
B
C
D
E
F
END
POINT
AI3296
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M28W320CT, M28W320CB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
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http://www.st.com
42/42
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