M28W640ECB10ZB6T_技术文档

M28W640ECT

M28W640ECB

64 Mbit (4Mb x16, Boot Block)

3V Supply Flash Memory

PRELIMINARY DATA

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V = 2.7V to 3.6V Core Power Supply

DD

– V

= 1.65V to 3.6V for Input/Output

DDQ

FBGA

– V = 12V for fast Program (optional)

PP

■ ACCESS TIME: 70, 85, 90,100ns

■ PROGRAMMING TIME:

TFBGA48 (ZB)

6.39 x 10.5mm

– 10µs typical

– Double Word Programming Option

– Quadruple Word Programming Option

■ COMMON FLASH INTERFACE

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

■ BLOCK LOCKING

TSOP48 (N)

12 x 20mm

– All blocks locked at Power Up

– Any combination of blocks can be locked

– WP for Block Lock-Down

■ SECURITY

– 128 bit user Programmable OTP cells

– 64 bit unique device identifier

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W640ECT: 8848h

– Bottom Device Code, M28W640ECB: 8849h

April 2003

1/55

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M28W640ECT, M28W640ECB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DD

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDQ

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PP

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/55

M28W640ECT, M28W640ECB

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 16

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

V

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PP

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12. Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3/55

M28W640ECT, M28W640ECB

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 30

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 30

Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline31

Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 31

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 32

Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 32

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 24. Top Boot Block Addresses, M28W640ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 25. Bottom Boot Block Addresses, M28W640ECB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 27. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 30. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 31. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 18. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 19. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 47

Figure 21. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 23. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 52

Table 32. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 33. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4/55

M28W640ECT, M28W640ECB

SUMMARY DESCRIPTION

The M28W640EC is a 64 Mbit (4 Mbit x 16) non-

volatile Flash memory that can be erased electri-

cally at block level and programmed in-system on

The memory is offered in TSOP48 (12 X 20mm)

and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch)

packages and is supplied with all the bits erased

(set to ’1’).

a Word-by-Word basis using a 2.7V to 3.6V V

DD

supply for the circuitry and a 1.65V to 3.6V V

DDQ

Figure 2. Logic Diagram

er programming.

V

DD DDQ PP

The device features an asymmetrical blocked ar-

chitecture. The M28W640EC has an array of 135

blocks: 8 Parameter Blocks of 4 KWord and 127

Main Blocks of 32 KWord. M28W640ECT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W640ECB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

The M28W640EC features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

22

16

A0-A21

DQ0-DQ15

W

E

M28W640ECT

M28W640ECB

G

RP

WP

V

SS

When V ≤ V

all blocks are protected against

PP

PPLK

program or erase. All blocks are locked at Power

AI04378b

Up.

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

The device includes a 192 bit Protection Register

to increase the protection of a system design. The

Protection Register is divided into a 64 bit segment

and a 128 bit segment. The 64 bit segment con-

tains a unique device number written by ST, while

the second one is one-time-programmable by the

user. The user programmable segment can be

permanently protected. Figure 6, shows the Pro-

tection Register Memory Map.

Table 1. Signal Names

A0-A21

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

E

G

Output Enable

Write Enable

Reset

W

RP

WP

Write Protect

Core Power Supply

V

DD

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

Power Supply for

Input/Output

V

DDQ

Optional Supply Voltage for

Fast Program & Erase

V

PP

Ground

SS

NC

Not Connected Internally

5/55

M28W640ECT, M28W640ECB

Figure 3. TSOP Connections

A15

1

48

A16

A14

A13

A12

A11

A10

A9

V

DDQ

SS

DQ15

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A21

A20

W

DQ12

DQ4

RP

12

13

37

36

V

M28W640ECT

M28W640ECB

DD

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

PP

WP

A19

A18

A17

A7

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI04379b

6/55

M28W640ECT, M28W640ECB

Figure 4. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

WP

A18

A20

DQ2

DQ3

A19

A17

A

B

C

D

E

F

A13

A14

A15

A16

A11

A10

A8

W

V

A7

A5

A4

A2

A1

A0

PP

RP

A12

A9

A21

A6

A3

DQ11

DQ12

DQ4

DQ14

DQ15

DQ7

DQ5

DQ6

DQ13

DQ8

DQ9

DQ10

E

V

DQ0

DQ1

V

DDQ

SS

V

SS

DD

G

AI04380

7/55

M28W640ECT, M28W640ECB

Figure 5. Block Addresses

M28W640ECT

M28W640ECB

Top Boot Block Addresses

Bottom Boot Block Addresses

3FFFFF

4 KWords

3FF000

3FFFFF

32 KWords

3F8000

3F7FFF

Total of 8

4 KWord Blocks

3F0000

Total of 127

32 KWord Blocks

3F8FFF

4 KWords

3F8000

3F7FFF

32 KWords

3F0000

00FFFF

32 KWords

4 KWords

008000

007FFF

Total of 127

007000

32 KWord Blocks

Total of 8

00FFFF

4 KWord Blocks

32 KWords

008000

007FFF

000FFF

000000

32 KWords

4 KWords

000000

AI04386b

Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.

Figure 6. Protection Register Memory Map

PROTECTION REGISTER

8Ch

User Programmable OTP

85h

84h

Unique device number

81h

Protection Register Lock

1

0

80h

AI05520b

8/55

M28W640ECT, M28W640ECB

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Write Bus

operation.

state. When Reset is at V , the device is in normal

IH

operation. Exiting reset mode the device enters

read array mode, but a negative transition of Chip

Enable or a change of the address is required to

ensure valid data outputs.

V

Supply Voltage. V

provides the power

DD

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

V

Supply Voltage. V

provides the

power supply to the I/O pins and enables all Out-

puts to be powered independently from V . V

DDQ

DD DDQ

can be tied to V

or can use a separate supply.

DD

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

V

Program Supply Voltage. V

is both a

PP

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage V

at V and Reset is at V the device is in active

and the

DD

IL

IH

mode. When Chip Enable is at V the memory is

Program Supply Voltage V

any order.

can be applied in

IH

PP

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

If V is kept in a low voltage range (0V to 3.6V)

PP

V

is seen as a control input. In this case a volt-

PP

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable, E, or Write En-

able, W, whichever occurs first.

age lower than V

against program or erase, while V

gives an absolute protection

PPLK

> V

en-

PP1

PP

ables these functions (see Table 15, DC Charac-

teristics for the relevant values). V is only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect on Program or Erase,

however for Double or Quadruple Word Program

the results are uncertain.

PP

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

If V is in the range 11.4V to 12.6V it acts as a

PP

power supply pin. In this condition V

stable until the Program/Erase algorithm is com-

pleted (see Table 17 and 18).

must be

PP

each block. When Write Protect is at V , the Lock-

IL

Down is enabled and the protection status of the

block cannot be changed. When Write Protect is at

V , the Lock-Down is disabled and the block can

be locked or unlocked. (refer to Table 7, Read Pro-

tection Register and Protection Register Lock).

V

Ground. V is the reference for all voltage

SS SS

IH

measurements.

Note: Each device in a system should have

Reset (RP). The Reset input provides a hard-

V

, V

and V decoupled with a 0.1µF ca-

DD DDQ PP

ware reset of the memory. When Reset is at V ,

pacitor close to the pin. See Figure 8, AC Mea-

surement Load Circuit. The PCB trace widths

should be sufficient to carry the required V

program and erase currents.

IL

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

mized. After Reset all blocks are in the Locked

PP

9/55

M28W640ECT, M28W640ECB

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2, Bus Operations, for a summary.

See Figures 10 and 11, Write AC Waveforms, and

Tables 17 and 18, Write AC Characteristics, for

details of the timing requirements.

Output Disable. The data outputs are high im-

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

pedance when the Output Enable is at V .

IH

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at V and the device is in

IH

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

able must be at V in order to perform a read op-

IL

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 9, Read Mode AC Waveforms, and Table

16, Read AC Characteristics, for details of when

the output becomes valid.

V

during a program or erase operation, the de-

IH

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity even if Chip Enable is Low, V , and the supply

IL

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

current is reduced to I

puts will still output data if a bus Read operation is

in progress.

. The data Inputs/Out-

DD1

Reset. During Reset mode when Output Enable

is Low, V , the memory is deselected and the out-

IL

and Write Enable are at V with Output Enable at

V . Commands, Input Data and Addresses are

IH

puts are high impedance. The memory is in Reset

IL

mode when Reset is at V . The power consump-

IL

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

tion is reduced to the Standby level, independently

from the Chip Enable, Output Enable or Write En-

able inputs. If Reset is pulled to V during a Pro-

SS

gram or Erase, this operation is aborted and the

memory content is no longer valid.

Table 2. Bus Operations

V

Operation

Bus Read

E

G

W

RP

WP

X

DQ0-DQ15

Data Output

Data Input

Hi-Z

PP

V

IH

V

Don’t Care

V or V

DD

IL

IH

V

Bus Write

Output Disable

Standby

X

IL

IH

PPH

V

X

Don’t Care

IH

V

X

Hi-Z

IH

V

IL

Reset

X

Hi-Z

Note: X = V or V , V = 12V ± 5%.

PPH

IL

IH

10/55

M28W640ECT, M28W640ECB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time during, to

monitor the progress of the operation, or the Pro-

gram/Erase states. See Table 3, Command

Codes, for a summary of the commands and see

Appendix 22, Table 32, Write State Machine Cur-

rent/Next, for a summary of the Command Inter-

face.

Table 3. Command Codes

Hex Code

01h

Command

Block Lock confirm

10h

Program

20h

Erase

2Fh

Block Lock-Down confirm

30h

Double Word Program

Program

40h

50h

56h

Clear Status Register

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

Quadruple Word Program

Block Lock, Block Unlock, Block Lock-

Down

set or whenever V

is lower than V

. Com-

DD

LKO

60h

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 4, Commands,

in conjunction with the text descriptions below.

70h

90h

98h

B0h

C0h

Read Status Register

Read Electronic Signature

Read CFI Query

Read Memory Array Command

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Program/Erase Suspend

Protection Register Program

Program/Erase Resume, Block Unlock

confirm

D0h

FFh

Read Memory Array

Read Status Register Command

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register at any address, until another

command is issued. See Table 11, Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

Read CFI Query Command

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area, allowing programming equipment or appli-

cations to automatically match their interface to

the characteristics of the device. One Bus Write

cycle is required to issue the Read Query Com-

mand. Once the command is issued subsequent

Bus Read operations read from the Common

Flash Interface Memory Area. See Appendix B,

Common Flash Interface, Tables 26, 27, 28, 29,

30 and 31 for details on the information contained

in the Common Flash Interface memory area.

Read Electronic Signature Command

Block Erase Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code, the

Block Lock and Lock-Down Status, or the Protec-

tion and Lock Register. See Tables 5, 6 and 7 for

the valid address.

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Erase command.

11/55

M28W640ECT, M28W640ECB

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V . As data integrity

IL

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 18, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Erase aborts if Reset turns to V . As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 8, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

IL

Quadruple Word Program Command

This feature is offered to improve the programming

throughput, writing a page of four adjacent words

in parallel.The four words must differ only for the

addresses A0 and A1. Programming should not be

attempted when V is not at V

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

.

PP

PPH

See Appendix C, Figure 21, Erase Flowchart and

Pseudo Code, for a suggested flowchart for using

the Erase command.

Program Command

■ The first bus cycle sets up the Quadruple Word

Program Command.

■ The second bus cycle latches the Address and

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program Command.

the Data of the first word to be written.

■ The first bus cycle sets up the Program

■ The third bus cycle latches the Address and the

command.

Data of the second word to be written.

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 8, Program, Erase

Times and Program/Erase Endurance Cycles.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V . As data integrity

IL

Programming aborts if Reset goes to V . As data

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 19, Quadruple Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Quadruple Word Program

command.

IL

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 17, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Clear Status Register Command

Double Word Program Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when V is not at V

.

PP

PPH

Three bus write cycles are necessary to issue the

Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

Program/Erase Suspend Command

■ The second bus cycle latches the Address and

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

12/55

M28W640ECT, M28W640ECB

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Double Word Program, Quadruple

Word Program, Block Lock, Block Lock-Down or

Protection Program commands will also be ac-

cepted. The block being erased may be protected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programmed correctly.

ter will result in a Status Register error. The pro-

tection of the Protection Register is not reversible.

The Protection Register Program cannot be sus-

pended.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

■ The second Bus Write cycle latches the block

address.

Chip Enable to V . Program/Erase is aborted if

IH

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 10 shows the protection status after issuing

a Block Lock command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation.

Reset turns to V .

IL

See Appendix C, Figure 20, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

22, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See Appendix C, Figure 20, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

22, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Resume command.

Block Unlock Command

The Blocks Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 10 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation.

Protection Register Program Command

The Protection Register Program command is

used to Program the 128 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,

or have its protection status changed when WP is

low, V . When WP is high, V the Lock-Down

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The first bus cycle sets up the Protection

IL

IH,

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The segment can be protected by programming bit

1 of the Protection Lock Register (see Figure 6,

Protection Register Memory Map). Attempting to

program a previously protected Protection Regis-

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

13/55

M28W640ECT, M28W640ECB

locked-down) state when the device is reset on

power-down. Table. 10 shows the protection sta-

tus after issuing a Block Lock-Down command.

Refer to the section, Block Locking, for a detailed

explanation.

Table 4. Commands

Bus Write Operations

Commands

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

Read Memory

Array

1+ Write

X

FFh

RA

X

RD

SRD

IDh

Read

Read Status

Register

70h Read

90h Read

Read Electronic

Signature

(2)

SA

Read CFI Query 1+ Write

X

98h Read QA

20h Write BA

QD

Erase

2

Write

D0h

40h or

Program

X

Write PA

10h

PD

Double Word

3

Write

30h Write PA1 PD1 Write PA2 PD2

(3)

Program

Quadruple Word

(5)

5

1

Write

X

Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

56h

(4)

Program

Clear Status

Register

50h

Program/Erase

Suspend

B0h

D0h

Program/Erase

Resume

Block Lock

2

Write

X

60h Write

01h

D0h

2Fh

BA

Block Unlock

Block Lock-Down

60h Write BA

Protection

Register Program

2

Write

X

C0h Write

PRD

PRA

Note: 1. X = Don’t Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),

QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad-

dress, PRD=Protection Register Data.

2. The signature addresses are listed in Tables 5, 6 and 7.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.

4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

5. To be characterized.

Table 5. Read Electronic Signature

Code

Device

E

G

W

A0

A1

A2-A7

A8-A21

DQ0-DQ7

DQ8-DQ15

Manufacture

Code

V

IL

V

IL

0

Don’t Care

20h

00h

IL

IH

IL

V

M28W640ECT

M28W640ECB

0

Don’t Care

48h

49h

88h

IL

IH

IL

Device Code

V

IH

V

IL

Note:

RP = V .

IH

14/55

M28W640ECT, M28W640ECB

Table 6. Read Block Lock Signature

Block Status

Locked Block

E

G

W

A0

A1 A2-A7

A8-A11

A12-A21

DQ0 DQ1 DQ2-DQ15

V

IL

V

IH

V

IL

V

0

Don’t Care Block Address

1

0

00h

IL

IH

V

IL

V

Unlocked Block

IL

IH

Locked-Down

Block

(1)

V

IL

V

IH

0

Don’t Care Block Address

1

00h

IL

IH

X

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

Table 7. Read Protection Register and Lock Register

Word

E

G

W

A0-A7

A8-A21

DQ0

DQ1

DQ2

DQ3-DQ7 DQ8-DQ15

OTP Prot.

data

V

IL

V

IH

Lock

80h Don’t Care

0

00h

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h Don’t Care

82h Don’t Care

83h Don’t Care

84h Don’t Care

ID data

IL

ID data

85h Don’t Care OTP data

86h Don’t Care OTP data

87h Don’t Care OTP data

88h Don’t Care OTP data

89h Don’t Care OTP data

8Ah Don’t Care OTP data

8Bh Don’t Care OTP data

8Ch Don’t Care OTP data

OTP data

OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

OTP 4

OTP 5

OTP 6

OTP 7

15/55

M28W640ECT, M28W640ECB

Table 8. Program, Erase Times and Program/Erase Endurance Cycles

M28W640EC

Parameter

Test Conditions

Unit

Min

Typ

10

Max

200

5

V

PP

= V

DD

Word Program

µs

V

PP

V

PP

V

PP

V

= 12V ±5%

= V

Double Word Program

10

µs

Quadruple Word Program

10

µs

(1)

s

0.16/0.08

Main Block Program

Parameter Block Program

Main Block Erase

0.32

5

s

PP

DD

(1)

V

= 12V ±5%

= V

4

s

PP

0.02/0.01

V

0.04

1

4

s

PP

DD

= 12V ±5%

= V

10

s

PP

V

1

s

PP

DD

= 12V ±5%

= V

0.4

s

PP

Parameter Block Erase

V

PP

DD

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands

respectively.

BLOCK LOCKING

The M28W640EC features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

■ Lock/Unlock - this first level allows software-

The following sections explain the operation of the

locking system.

Locked State

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

■ V ≤ V

- the third level offers a complete

PP

PPLK

hardware protection against program and erase

on all blocks.

The protection status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 10, de-

fines all of the possible protection states (WP,

DQ1, DQ0), and Appendix C, Figure 23, shows a

flowchart for the locking operations.

Unlocked State

Reading a Block’s Lock Status

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

software commands. A locked block can be un-

locked by issuing the Unlock command.

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 6,

will output the protection status of that block. The

lock status is represented by DQ0 and DQ1. DQ0

indicates the Block Lock/Unlock status and is set

by the Lock command and cleared by the Unlock

16/55

M28W640ECT, M28W640ECB

Lock-Down State

Locking Operations During Erase Suspend

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their protection status can-

not be changed using software commands alone.

A Locked or Unlocked block can be Locked-Down

by issuing the Lock-Down command. Locked-

Down blocks revert to the Locked state when the

device is reset or powered-down.

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

The Lock-Down function is dependent on the WP

input pin. When WP=0 (V ), the blocks in the

IL

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

WP=1 (V ) the Lock-Down function is disabled

IH

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be relocked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is low , blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

resets all blocks , including those in Lock-Down, to

the Locked state.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend. Refer to Appendix D, Com-

mand Interface and Program/Erase Controller

State, for detailed information on which com-

mands are valid during erase suspend.

Table 9. Block Lock Status

Item

Address

Data

Block Lock Configuration

Block is Unlocked

Block is Locked

LOCK

DQ0=0

DQ0=1

DQ1=1

xx002

Block is Locked-Down

17/55

M28W640ECT, M28W640ECB

Table 10. Protection Status

Current

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

Protection Status

(WP, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Current State

After

WP transition

Allowed

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

18/55

M28W640ECT, M28W640ECB

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

or Output Enable returns to V . Either Chip En-

IH

able or Output Enable must be toggled to update

the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

The bits in the Status Register are summarized in

Table 11, Status Register Bits. Refer to Table 11

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

V

Status (Bit 3). The V

Status bit can be

PP

used to identify an invalid voltage on the V pin

during Program and Erase operations. The V

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

PP

cur if V becomes invalid during an operation.

PP

After the Program/Erase Controller completes its

When the V Status bit is Low (set to ‘0’), the volt-

PP

operation the Erase Status, Program Status, V

age on the V pin was sampled at a valid voltage;

PP

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

19/55

M28W640ECT, M28W640ECB

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 11. Status Register Bits

Bit

Name

Logic Level

Definition

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

PP

Status

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

20/55

M28W640ECT, M28W640ECB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 12. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

– 40

– 55

– 0.6

Max

85

(1)

T

°C

V

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

T

125

155

BIAS

T

STG

V

IO

V

+0.6

DDQ

V

, V

DD DDQ

4.1

13

V

PP

Program Voltage

V

Note: 1. Depends on range.

21/55

M28W640ECT, M28W640ECB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 13,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 13. Operating and AC Measurement Conditions

M28W640ECT, M28W640ECB

(1)

85

90

10

70

Parameter

Units

Min

Max

Min

Max

Min

Max

Min

Max

V

Supply Voltage

3.0

3.6

85

3.0

3.6

2.7

3.6

2.7

3.6

V

DD

V

Supply Voltage (V

≤

DDQ

1.65

3.6

1.65

3.6

1.65

3.6

)

DD

Ambient Operating Temperature

– 40

85

– 40

85

– 40

85

°C

pF

ns

V

Load Capacitance (C )

50

L

Input Rise and Fall Times

Input Pulse Voltages

5

0 to V

DDQ

Input and Output Timing Ref.

Voltages

V

DDQ

/2

V

DDQ

/2

V

DDQ

/2

V

/2

DDQ

V

Note: 1. To be characterized.

Figure 7. AC Measurement I/O Waveform

Figure 8. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DDQ

V

0V

DD

25kΩ

AI00610

DEVICE

UNDER

TEST

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI00609C

L

Table 14. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: Sampled only, not 100% tested.

22/55

M28W640ECT, M28W640ECB

Table 15. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V≤ V ≤ V

LI

IN

DDQ

I

0V≤ V

≤V

±10

18

µA

LO

OUT DDQ

I

E = V , G = V , f = 5MHz

9

mA

DD

SS

IH

E = V

RP = V

± 0.2V,

Supply Current (Stand-by or

Automatic Stand-by)

DDQ

I

15

50

10

20

50

400

µA

DD1

± 0.2V

DDQ

Supply Current

(Reset)

I

RP = V ± 0.2V

15

5

DD2

SS

Program in progress

mA

µA

V

PP

= 12V ± 5%

I

Supply Current (Program)

Supply Current (Erase)

DD3

Program in progress

= V

10

5

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

DD4

Erase in progress

= V

10

15

V

PP

DD

E = V

Erase suspended

± 0.2V,

Supply Current

(Program/Erase Suspend)

DDQ

I

DD5

Program Current

(Read or Stand-by)

I

V

> V

µA

PP

DD

Program Current

(Read or Stand-by)

I

V

≤ V

1

5

µA

PP1

DD

I

RP = V ± 0.2V

Program Current (Reset)

PP2

SS

Program in progress

10

mA

V

PP

= 12V ± 5%

I

Program Current (Program)

PP3

Program in progress

= V

1

3

1

5

10

5

µA

mA

µA

V

PP

DD

Erase in progress

= 12V ± 5%

V

PP

I

Program Current (Erase)

PP4

Erase in progress

= V

V

PP

DD

–0.5

0.4

0.8

V

Input Low Voltage

Input High Voltage

IL

V

≥ 2.7V

DDQ

V

–0.4

V

+0.4

DDQ

V

IH

0.7 V

+0.4

DDQ

I

= 100µA, V = V min,

DD DD

OL

V

Output Low Voltage

Output High Voltage

0.1

V

OL

V

= V

min

DDQ

I

= –100µA, V = V min,

DD DD

OH

V

OH

V

–0.1

DDQ

V

DDQ

= V

min

DDQ

Program Voltage (Program or

Erase operations)

V

1.65

3.6

PP1

Program Voltage

(Program or Erase

operations)

V

PPH

11.4

12.6

V

Program Voltage

(Program and Erase lock-out)

V

1

2

V

PPLK

V

DD

Supply Voltage (Program

V

LKO

and Erase lock-out)

23/55

M28W640ECT, M28W640ECB

Figure 9. Read AC Waveforms

tAVAV

VALID

A0-A21

E

tAVQV

tAXQX

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQV

tGHQX

tGHQZ

tGLQX

VALID

DQ0-DQ15

OUTPUTS

ENABLED

ADDR. VALID

CHIP ENABLE

DATA VALID

STANDBY

AI04387

Table 16. Read AC Characteristics

M28W640EC

Symbol

Alt

Parameter

Unit

70

85

90

10

(3)

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

100

0

ns

AVAV

RC

70

(3)

t

ACC

Max

Min

Max

Min

Max

Min

AVQV

70

(1)

t

Address Transition to Output Transition

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

0

t

OH

AXQX

EHQX

(1)

(2)

(1)

(2)

(1)

0

t

OH

t

20

85

0

25

90

0

25

100

0

t

HZ

EHQZ

(3)

Chip Enable Low to Output Valid

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

t

CE

70

ELQV

ELQX

t

LZ

0

t

0

t

OH

GHQX

t

20

0

20

0

25

30

0

25

30

0

t

DF

OE

GHQZ

t

GLQV

t

OLZ

GLQX

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

3. To be characterized.

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

24/55

M28W640ECT, M28W640ECB

Figure 10. Write AC Waveforms, Write Enable Controlled

25/55

M28W640ECT, M28W640ECB

Table 17. Write AC Characteristics, Write Enable Controlled

M28W640EC

Symbol

Alt

Parameter

Unit

70

85

45

0

90

50

0

10

100

50

(3)

t

WC

Write Cycle Time

Min

ns

AVAV

70

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

45

0

AVWH

AS

DS

CS

t

50

DVWH

t

0

ELWL

(3)

t

85

90

100

ELQV

70

(1,2)

Output Valid to V Low

Min

0

ns

t

PP

QVVPL

t

Output Valid to Write Protect Low

QVWPL

(1)

t

V

High to Write Enable High

Min

200

0

200

0

200

0

200

0

ns

t

VPS

PP

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

WHAX

AH

t

0

WHDX

WHEH

DH

CH

t

0

t

25

20

25

45

25

20

25

45

30

50

30

50

WHEL

t

WHGL

t

WHWL

WPH

t

WLWH

WP

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

3. To be characterized.

26/55

M28W640ECT, M28W640ECB

Figure 11. Write AC Waveforms, Chip Enable Controlled

27/55

M28W640ECT, M28W640ECB

Table 18. Write AC Characteristics, Chip Enable Controlled

M28W640EC

Symbol

Alt

Parameter

Unit

70

85

45

90

50

10

100

50

(3)

t

WC

Write Cycle Time

Min

ns

AVAV

70

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

45

AVEH

AS

DS

t

50

DVEH

Chip Enable High to Address

Transition

t

Min

0

ns

EHAX

AH

t

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Min

0

ns

EHDX

DH

t

CPH

25

30

EHEL

Chip Enable High to Output Enable

Low

t

Min

25

30

ns

EHGL

t

WH

Chip Enable High to Write Enable High Min

0

ns

EHWH

t

CP

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

Min

45

85

50

90

50

ELEH

(3)

t

100

ELQV

70

(1,2)

Output Valid to V Low

0

ns

t

PP

QVVPL

t

Data Valid to Write Protect Low

QVWPL

(1)

t

V

High to Chip Enable High

PP

200

0

200

0

200

0

200

0

ns

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

WLEL

t

Write Protect High to Chip Enable High Min

45

50

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

3. To be characterized.

28/55

M28W640ECT, M28W640ECB

Figure 12. Power-Up and Reset AC Waveforms

W, E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI03537b

Table 19. Power-Up and Reset AC Characteristics

M28W640EC

Unit

Symbol

Parameter

Test Condition

70

85

90

10

During Program

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip

Enable Low, Output Enable Low

and Erase

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

29/55

M28W640ECT, M28W640ECB

PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Note: Drawing is not to scale.

A1

α

L

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.4764

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.4685

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0279

5°

α

N

48

CP

0.10

0.0039

30/55

M28W640ECT, M28W640ECB

Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

D

D1

FD

SD

FE

SE

E

E1

e

BALL "A1"

ddd

e

b

A2

A

A1

BGA-Z34

Note: Drawing is not to scale.

Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

1.000

0.0394

0.400

6.390

5.250

0.350

6.290

–

0.450

0.0157

0.2516

0.2067

0.0138

0.2476

–

0.0177

D

6.490

0.2555

D1

ddd

E

–

0.100

0.0039

10.500

3.750

0.750

0.570

3.375

0.375

10.400

10.600

0.4134

0.1476

0.0295

0.0224

0.1329

0.0148

0.4094

0.4173

E1

e

–

FD

FE

SD

SE

31/55

M28W640ECT, M28W640ECB

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

AI04390

Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)

1

2

3

4

5

6

7

8

START

POINT

A

B

C

D

E

F

END

POINT

AI04391

32/55

M28W640ECT, M28W640ECB

PART NUMBERING

Table 22. Ordering Information Scheme

Example:

M28W640ECT

90

N

6

T

Device Type

M28

Operating Voltage

W = V = 2.7V to 3.6V; V

= 1.65V to 3.6V

DDQ

DD

Device Function

640EC = 64 Mbit (4 Mb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns (to be characterized)

85 = 85 ns

90 = 90 ns

10 = 100 ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free Package, Standard Packing

F = Lead-Free Package, Tape & Reel Packing

33/55

M28W640ECT, M28W640ECB

Table 23. Daisy Chain Ordering Scheme

Example:

M28W640EC

-ZB T

Device Type

M28W640EC

Daisy Chain

-ZB = TFBGA48: 6.39 x 10.5mm, 0.75 mm pitch

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free Package, Standard Packing

F = Lead-Free Package, Tape & Reel Packing

Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc...) or for further information on any aspect of this device, please contact

the ST Sales Office nearest to you.

34/55

M28W640ECT, M28W640ECB

APPENDIX A. BLOCK ADDRESS TABLES

Table 24. Top Boot Block Addresses,

M28W640ECT

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

32

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

Size

(KWord)

#

Address Range

0

4

3FF000-3FFFFF

3FE000-3FEFFF

3FD000-3FDFFF

3FC000-3FCFFF

3FB000-3FBFFF

3FA000-3FAFFF

3F9000-3F9FFF

3F8000-3F8FFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

2F8000-2FFFFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

35/55

M28W640ECT, M28W640ECB

84

85

32

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

130

131

132

133

134

32

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

36/55

M28W640ECT, M28W640ECB

Table 25. Bottom Boot Block Addresses,

M28W640ECB

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

32

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

Size

#

Address Range

(KWord)

32

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

3F8000-3FFFFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

2B8000-2BFFFF

2B0000-2B7FFF

98

97

96

95

94

93

37/55

M28W640ECT, M28W640ECB

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32

4

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

007000-007FFF

006000-006FFF

005000-005FFF

004000-004FFF

003000-003FFF

002000-002FFF

001000-001FFF

0

4

000000-000FFF

8

7

6

4

5

4

3

4

2

4

1

4

38/55

M28W640ECT, M28W640ECB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 26, 27,

28, 29, 30 and 31 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 31, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 26. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 27. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

Device Code

ST

8848h

8849h

Top

Bottom

01h

02h-0Fh

10h

reserved Reserved

0051h

"Q"

"R"

"Y"

11h

0052h

0059h

0003h

0000h

0035h

0000h

Query Unique ASCII String "QRY"

12h

13h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

Intel

compatible

14h

15h

Address for Primary Algorithm extended Query table (see Table 29)

P = 35h

NA

16h

17h

Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists)

18h

19h

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

1Ah

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

39/55

M28W640ECT, M28W640ECB

Table 28. CFI Query System Interface Information

Offset

Data

Description

Value

V

DD

V

DD

V

PP

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0027h

2.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0036h

00B4h

00C6h

3.6V

11.4V

12.6V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0005h

0003h

0000h

16µs

1s

Typical time-out per single word program = 2 µs

n

Typical time-out for Double/Quadruple Word Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

512µs

8s

Maximum time-out for Word program = 2 times typical

n

Maximum time-out for Double/Quadruple Word Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

40/55

M28W640ECT, M28W640ECB

Table 29. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0017h

8 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0003h

0000h

n

8

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Ch

0002h

2Dh

2Eh

007Eh

0000h

Region 1 Information

Number of identical-size erase block = 007Eh+1

127

64 KByte

8

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

127

31h

32h

007Eh

0000h

Region 2 Information

Number of identical-size erase block = 007Eh=1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

41/55

M28W640ECT, M28W640ECB

Table 30. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0066h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Chip Erase supported

(1 = Yes, 0 = No)

Suspend Erase supported

Suspend Program supported

Legacy Lock/Unlock supported

Queued Erase supported

No

Yes

No

Instant individual block locking supported (1 = Yes, 0 = No)

No

Protection bits supported

Page mode read supported

Synchronous read supported

(1 = Yes, 0 = No)

Yes

No

bit 31 to 9 Reserved; undefined bits are ‘0’

No

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

(P+B)h = 40h

0003h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

(P+C)h = 41h

(P+D)h = 42h

(P+E)h = 43h

0030h

00C0h

0001h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V

12V

01

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

(P+10)h = 45h

(P+11)h = 46h

(P+12)h = 47h

0080h

0000h

0003h

0004h

Protection Field 1: Protection Description

80h

00h

This field describes user-available One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

8 Byte

16 Byte

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7

Lock/bytes JEDEC-plane physical low address

bit 8 to 15

Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2 = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2 = user programmable bytes

(P+13)h = 48h

Reserved

Note: 1. See Table 27, offset 15 for P pointer definition.

42/55

M28W640ECT, M28W640ECB

Table 31. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

Data

00XX

XXXX

Description

Protection Register Lock

64 bits: unique device number

128 bits: User Programmable OTP

43/55

M28W640ECT, M28W640ECB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 17. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

Write 40h or 10h

writeToFlash (any_address, 0x40) ;

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

44/55

M28W640ECT, M28W640ECB

Figure 18. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03539b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

45/55

M28W640ECT, M28W640ECB

Figure 19. Quadruple Word Program Flowchart and Pseudo Code

Start

quadruple_word_program_command (addressToProgram1, dataToProgram1,

Write 56h

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

Write Address 1

& Data 1 (3)

writeToFlash (any_address, 0x56) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 2

& Data 2 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

Write Address 3

& Data 3 (3)

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

Write Address 4

& Data 4 (3)

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI06233

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

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M28W640ECT, M28W640ECB

Figure 20. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

Write 70h

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI03540b

47/55

M28W640ECT, M28W640ECB

Figure 21. Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

48/55

M28W640ECT, M28W640ECB

Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI03542b

49/55

M28W640ECT, M28W640ECB

Figure 23. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

Write 60h

writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Write 90h

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI04364

50/55

M28W640ECT, M28W640ECB

Figure 24. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0xC0) ;

Write C0h

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

51/55

M28W640ECT, M28W640ECB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 32. Write State Machine Current/Next, sheet 1 of 2.

Command Input (and Next State)

Data

When

Read

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array

“1”

Array

Read Array Prog.Setup Ers. Setup

Read Array

Read Sts. Read Array

Read

Status

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Read

Elect.Sg.

Electronic

Signature

Program

Setup

Erase

Setup

Read

“1”

“0”

“1”

Read Array

Status

Read CFI

Query

Program

Setup

Erase

Setup

Read

CFI

Read Array

Status

Lock

(complete)

Lock Cmd

Error

Lock

(complete)

Lock Setup

Status

Lock Command Error

Program

Lock Command Error

Lock Cmd

Error

Erase

Setup

Read

Read Array

Status

Setup

Lock

(complete)

Program

Setup

Erase

Setup

Read

Read Array

Status

Prot. Prog.

Setup

Protection Register Program

Protection Register Program continue

Prot. Prog.

(continue)

Prot. Prog.

(complete)

Program

Setup

Erase

Setup

Read

Status

Read Array

Program

Read Array

Status

Prog. Setup “1”

Program

“0”

Prog. Sus

Read Sts

Program (continue)

(continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

Status

Array

Status

(continue) Read Array (continue)

Program Prog. Sus Program

(continue) Read Array (continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Prog. Sus Prog. Sus

Read Sts Read Array

Read Array

Prog. Sus

Read

Elect.Sg.

Electronic Prog. Sus

Signature Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

(continue) Read Array (continue)

Prog. Sus

Read CFI

Prog. Sus

CFI

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

“0”

“1”

Read Array

(continue) Read Array (continue)

Program

(complete)

Program

Setup

Erase

Setup

Read

Status

Array

Read Array

Status

Erase

Setup

Erase

Erase Command Error

(continue) CmdError (continue)

Erase

Cmd.Error

Program

Setup

Erase

Setup

Read

Read Array

Status

Erase

(continue)

Erase Sus

Read Sts

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Array

Program

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

Setup

Read Array (continue) Read Array (continue)

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

Erase Sus Erase Erase Sus Erase

Read Array (continue) Read Array (continue)

Erase Sus Erase Sus

Read Sts Read Array

Erase Sus

Read

Elect.Sg.

Electronic Erase Sus

Signature Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array (continue) Read Array (continue)

Erase Sus

Read CFI

Erase Sus

CFI

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array

Read Array (continue) Read Array (continue)

Erase

(complete)

Program

Setup

Erase

Read

Status

Read Array

Setup

Read Array

Status

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

52/55

M28W640ECT, M28W640ECB

Table 33. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Read CFI

Query

(98h)

Unlock

Confirm

(D0h)

Current State

Read Elect.Sg.

(90h)

Lock Setup

(60h)

Prot. Prog.

Setup (C0h)

Lock Confirm

(01h)

Lock Down

Confirm (2Fh)

Prot. Prog.

Setup

Read Array

Read Elect.Sg. Read CFI Query

Lock Setup

Read Array

Prot. Prog.

Setup

Read Status

Prot. Prog.

Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Read CFI Query Read Elect.Sg. Read CFI Query

Prot. Prog.

Setup

Read Array

Lock (complete)

Read Array

Lock Setup

Lock Command Error

Prot. Prog.

Setup

Lock Cmd Error Read Elect.Sg. Read CFI Query

Lock Setup

Prot. Prog.

Setup

Lock (complete) Read Elect.Sg. Read CFI Query

Read Array

Prot. Prog.

Setup

Protection Register Program

Prot. Prog.

(continue)

Protection Register Program (continue)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Setup

Prog. Setup

Program

(continue)

Program (continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Program Suspend Read Array

Read Status

Prog. Suspend Prog. Suspend Prog. Suspend

Read Array Read Elect.Sg. Read CFI Query

Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Read CFI

Read Elect.Sg. Read CFI Query

Program

(complete)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFIQuery

Read Array

Setup

Erase

(continue)

Erase Setup

Erase Command Error

Erase

Cmd.Error

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

Setup

Erase (continue)

Erase Suspend Erase Suspend Erase Suspend

Read Ststus Read Elect.Sg. Read CFI Query

Erase

(continue)

Lock Setup

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read Array Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Erase Suspend Erase Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read CFI Query Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase

Prot. Prog.

Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

53/55

M28W640ECT, M28W640ECB

REVISION HISTORY

Table 34. Document Revision History

Date

Version

Revision Details

17-Jun-2002

-01

First Issue

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 01 equals 1.0).

Document Revision History moved to end of document.

Minimum V

voltage changed from 2.7V to 1.65V. Note removed from Figure 6,

DDQ

03-Oct-2002

1.1

Protection Register Memory Map. Note removed from Table 7, Read Protection

Register and Lock Register, and DQ2 value changed.

“Double Word Program Command” and “Quadruple Word Program Command”

paragraphs clarified.

Part numbers corrected in Figures 2, 3 and 5.

Lead-Free Package options added (see Table 22, Ordering Information Scheme and

Table 23, Daisy Chain Ordering Scheme.)

29-Apr-2003

1.2

54/55

M28W640ECT, M28W640ECB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States

www.st.com

55/55


型号：	M28W640ECB10ZB6T
厂家：	ST
描述：	64 Mbit 4Mb x16, Boot Block 3V Supply Flash Memory 64兆位4Mb的X16 ，引导块3V电源快闪记忆体内存集成电路
文件：	总55页 (文件大小：786K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M28W640ECB10ZB6T [STMICROELECTRONICS]

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