M29F002T-70K1TR中文资料_数据手册_规格书

M29F002T, M29F002NT

M29F002B

2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory

5V ± 10% SUPPLYVOLTAGEfor PROGRAM,

ERASE and READ OPERATIONS

FASTACCESS TIME: 70ns

FAST PROGRAMMING TIME: 10µs typical

PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte

32

– Status Register bits

MEMORY BLOCKS

1

PLCC32 (K)

PDIP32 (P)

– Boot Block (Top or Bottom location)

– Parameterand Main blocks

BLOCK, MULTI-BLOCK and CHIP ERASE

MULTI-BLOCKPROTECTION/TEMPORARY

UNPROTECTION MODES

ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

TSOP32 (N)

8 x 20mm

LOW POWER CONSUMPTION

– Stand-byand AutomaticStand-by

100,000 PROGRAM/ERASE CYCLES per

BLOCK

20 YEARSDATARETENTION

– Defectivity below 1ppm/year

ELECTRONIC SIGNATURE

– ManufacturerCode: 20h

Figure 1. Logic Diagram

V

CC

– Device Code, M29F002T: B0h

– Device Code, M29F002NT: B0h

– Device Code, M29F002B: 34h

18

8

A0-A17

DQ0-DQ7

DESCRIPTION

W

The M29F002 is a non-volatile memory that may

be erased electrically at the block or chiplevel and

programmed in-system on a Byte-by-Byte basis

usingonlyasingle5VV_CCsupply.ForProgramand

Erase operations the necessary high voltages are

generated internally. The device can also be pro-

grammed in standardprogrammers.

M29F002T

M29F002B

M29F002NT

E

G

(*) RPNC

The array matrix organisationallows each block to

be erased and reprogrammed without affecting

other blocks. Blocks can be protectedagainst pro-

graming and erase on programming equipment,

and temporarily unprotected to make changes in

the application. Each block can be programmed

and erased over 100,000 cycles.

V

SS

AI02078C

Note: * RPNC function is not available for the M29F002NT

July 1998

1/29

M29F002T, M29F002NT, M29F002B

Figure 2A. DIP Pin Connections

Figure 2B. LCC Pin Connections

(*) RPNC

A16

A15

A12

A7

1

2

3

4

5

6

7

8

9

32

31

V

CC

W

30 A17

29 A14

28 A13

27 A8

1 32

A7

A14

A13

A8

A6

A5

26 A9

M29F002T

M29F002B

M29F002NT

A4

25 A11

A4

A9

M29F002T

M29F002B

A3

24

23 A10

22

G

A3

A2

9

25 A11

G

A2 10

A1 11

E

A1

A10

E

A0 12

21 DQ7

20 DQ6

19 DQ5

18 DQ4

17 DQ3

A0

DQ0 13

DQ1 14

DQ2 15

DQ0

DQ7

17

V

16

SS

AI02079C

AI02080C

Note: Pin 1 is not connected for the M29F002NT

Figure 2C. TSOP Pin Connections

Table 1. Signal Names

A0-A17

DQ0-DQ7

E

Address Inputs

Data Input/Outputs, Command Inputs

Chip Enable

A11

A9

1

32

G

A10

E

G

Output Enable

A8

A13

A14

A17

W

DQ7

DQ6

DQ5

DQ4

DQ3

W

Write Enable

RPNC ^(*)

V_CC

Reset / Block Temporary Unprotect

Supply Voltage

V

8

9

25

24

M29F002T

M29F002B

CC

V

SS

RPNC

A16

V_SS

Ground

DQ2

DQ1

DQ0

A0

A15

A12

A7

DESCRIPTION (cont’d)

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection

status,Programming, BlockandChip Erase,Erase

Suspend and Resume are written to the device in

cyclesofcommandstoa CommandInterfaceusing

standardmicroprocessor write timings. The device

is offeredin PLCC32,PDIP32and TSOP32(8 x 20

mm) packages.

A6

A1

A5

A2

A4

16

17

A3

AI02361B

2/29

M29F002T, M29F002NT, M29F002B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

–40 to 125

–50 to 125

–65 to 150

–0.6 to 7

Unit

°C

V

Ambient Operating Temperature ⁽³⁾

Temperature Under Bias

Storage Temperature

T_BIAS

T_STG

(2)

V_IO

Input or Output Voltages

Supply Voltage

V_CC

–0.6 to 7

V

(2)

V_{(A9, E, G, RPNC)}

A9, E, G, RPNC Voltage

–0.6 to 13.5

V

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.

3. Depends on range.

Organisation

from or program to any block not being ersased,

and then resumed.Block protection providesaddi-

tional data security. Each block can be separately

protectedor unprotectedagainstProgramor Erase

on programming equipment. All previously pro-

tectedblockscan be temporarilyunprotectedin the

application.

The M29F002 is organised as 256K x 8. Memory

control is provided by Chip Enable E, Output En-

able G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RPNC

(NOTavailable on M29F002NT) tri-level input pro-

videsa hardwareresetwhenpulledLow,andwhen

held High (at V_ID) temporarily unprotects blocks

previously protected allowing them to be progra-

med and erased. Erase and Program operations

are controlled by an internal Program/Erase Con-

troller(P/E.C.).StatusRegisterdataoutputon DQ7

provides a Data Pollingsignal, and DQ6 and DQ2

provide Toggle signals to indicate the state of the

P/E.C operations.

Bus Operations

The following operations can be performed using

theappropriatebus cycles:Read(Array, Electronic

Signature, Block Protection Status), Write com-

mand, Output Disable, Standby,Reset, Block Pro-

tection, Unprotection, Protection Verify,

Unprotection Verify and Block Temporary Unpro-

tection. See Tables4 and 5.

Memory Blocks

Command Interface

The devices feature asymmetricallyblocked archi-

tecture providing system memory integration. The

M29F002has an arrayof 7blocks, one Boot Block

of 16 KBytes, two Parameter Blocks of 8 KBytes,

oneMainBlockof 32KBytesandthreeMainBlocks

of 64 KBytes.

Instructions, made up of commands written in cy-

cles, can be given to the Program/EraseController

through a Command Interface (C.I.). For added

data protection,program or erase execution starts

after4 or6 cycles.The first,second,fourthand fifth

cycles are used to input Coded cycles to the C.I.

This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The ’Com-

mand’ itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quencewill reset the device to Read Array mode.

Thememory map is shownin Figure3. Eachblock

can be erased separately, any combination of

blockscan be specifiedfor multi-blockerase or the

entire chip may be erased. The Erase operations

aremanagedautomaticallybythe P/E.C.Theblock

eraseoperationcan be suspendedin orderto read

3/29

M29F002T, M29F002NT, M29F002B

Figure 3. Memory Map and Block Address Table

M29F002T, M29F002NT

3FFFFh

M29F002B

3FFFFh

16K BOOT BLOCK

64K MAIN BLOCK

32K MAIN BLOCK

8K PARAMETER BLOCK

16K BOOT BLOCK

3C000h

3BFFFh

30000h

2FFFFh

8K PARAMETER BLOCK

3A000h

39FFFh

20000h

1FFFFh

8K PARAMETER BLOCK

38000h

37FFFh

10000h

0FFFFh

32K MAIN BLOCK

30000h

2FFFFh

08000h

07FFFh

64K MAIN BLOCK

20000h

1FFFFh

06000h

05FFFh

64K MAIN BLOCK

10000h

0FFFFh

04000h

03FFFh

64K MAIN BLOCK

00000h

AI02081C

Table 3A. M29F002T, M29F002NTBlock Address Table

Address Range

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-37FFFh

38000h-39FFFh

3A000h-3BFFFh

3C000h-3FFFFh

A17

0

A16

0

A15

A14

X

A13

X

0

1

X

0

1

X

1

0

X

1

X

1

0

1

0

1

X

Table 3B. M29F002B Block Address Table

Address Range

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

A17

0

A16

0

A15

0

A14

0

A13

X

0

1

0

1

0

1

X

0

1

X

1

0

X

1

X

4/29

M29F002T, M29F002NT, M29F002B

Instructions

impedance when the chip is deselected or the

outputs are disabled and when RPNC is at a Low

level.

Seven instructions are defined to perform Read

Array,Auto Select(to readthe ElectronicSignature

or Block ProtectionStatus), Program, BlockErase,

Chip Erase, Erase Suspend and Erase Resume.

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase

operations.The Status Register Data Polling, Tog-

gle, Error bits may be read at any time, during

programming or erase, to monitor the progress of

the operation.

Chip Enable (E). The Chip Enable input activates

the memory control logic, input buffers, decoders

andsenseamplifiers.E Highdeselectsthememory

andreducesthe powerconsumptiontothestandby

level. E can also be used to control writing to the

command register and to the memory array, while

Wremainsat a low level. TheChip Enablemust be

forced to V_IDduringthe Block Unprotection opera-

tion.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

CommandInterfacewhich iscommontoall instruc-

tions (see Table 8). The third cycle inputs the

instruction set-up command. Subsequent cycles

outputthe addressed data, Electronic Signatureor

Block Protection Status for Read operations. In

orderto giveadditionaldata protection,the instruc-

tions for Programand Block or Chip Erase require

furthercommandinputs. ForaPrograminstruction,

the fourth command cycle inputs the address and

data to be programmed. For an Erase instruction

(Block or Chip), the fourth and fifth cycles input a

further Coded sequence before the Erase confirm

command on the sixth cycle. Erasure of a memory

blockmaybe suspended,in orderto readdatafrom

anotherblock or to programdata in another block,

and then resumed.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. When G is High the outputs are High

impedance. G must be forced to V_IDlevel during

Block Protection and Unprotection operations.

WriteEnable (W). This inputcontrols writing to the

CommandRegisterand Addressand Datalatches.

Reset/Block Temporary Unprotect/No Connect

Input (RPNC). The RPNC (not available for the

M29F002NT) input provides hardware reset and

protected block(s) temporary unprotection func-

tions. In read or write mode, the RPNC pin can be

left open (Not Connected) or held at V_IH. Reset of

the memory is acheived by pulling RPNC to V_ILfor

atleast 500ns.When the reset pulseis given,if the

memory is in Read or Standby modes, it will be

availablefor newoperationsin 50nsafter the rising

edge of RPNC. If the memory is in Erase, Erase

Suspend or Program modes the reset will take

10µs.Ahardwareresetduringan Eraseor Program

operation will corrupt the data being programmed

or the sector(s) being erased.

When power is first applied or if V_CCfalls below

V_LKO, the command interface is reset to Read

Array.

SIGNAL DESCRIPTIONS

Temporary block unprotection is made by holding

RPNC at V_ID. Inthis conditionpreviously protected

blocks can be programmed or erased. The transi-

tion of RPNC from V_IHto V_IDmust slower than

500ns. When RPNC is returnedfrom V_IDto V_IHall

blocks temporarily unprotected will be again pro-

tected.

See Figure 1 and Table1.

Address Inputs (A0-A17). The address inputs for

the memory array are latchedduring a write opera-

tion on the falling edge of Chip Enable E or Write

EnableW. When A9 is raisedto V_ID, eithera Read

ElectronicSignatureManufacturerorDeviceCode,

BlockProtectionStatus or a WriteBlock Protection

or Block Unprotectionis enableddependingon the

combinationof levelson A0, A1, A6, A12 and A15.

V_CCSupply Voltage. The power supply for all

operations (Read, Program and Erase).

V_SSGround. V_SSis the reference for all voltage

measurements.

Data Input/Outputs (DQ0-DQ7). Theinput is data

to be programmed in the memory array or a com-

mand to be written to the C.I. Both are latched on

the rising edge of Chip Enable E or Write Enable

W. The output is data from the Memory Array, the

Electronic Signature Manufacturer or Device

codes, the Block Protection Status or the Status

register Data Polling bit DQ7, the ToggleBits DQ6

and DQ2, the Error bit DQ5 or the Erase Timer bit

DQ3. Outputs are valid when Chip Enable E and

Output Enable G are active. The output is high

DEVICE OPERATIONS

See Tables 4, 5 and 6.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature,the Status Register or the BlockProtection

Status. Both Chip Enable E and Output Enable G

must be low in order to read the output of the

memory.

5/29

M29F002T, M29F002NT, M29F002B

Table 4. User Bus Operations ⁽¹⁾

Operation

Read Byte

E

G

V_IL

V_IH

X

W

V_IH

V_IL

V_IH

X

RPNC ⁽⁶⁾

V_IH/NC⁽⁵⁾

V_IL

A0

X

A1

X

A6

X

A9

X

A12

X

A15

X

DQ0-DQ7

Data Output

Data Input

Hi-Z

V_IL

V_IH

X

Write Byte

Output Disable

Standby

X

Hi-Z

Reset ⁽⁶⁾

X

Hi-Z

Block

V_IL

V_IDV_ILPulse V_IH/NC⁽⁵⁾

X

V_ID

X

Protection^(2,4)

Blocks

V_ID

V_IH

Unprotection⁽⁴⁾

Block

Block Protect

Status ⁽³⁾

Protection

V_IL

X

V_IL

X

V_IH

X

V_IH/NC⁽⁵⁾

V_ID

V_IL

X

V_IH

X

V_IL

V_IH

X

V_ID

X

A12

X

A15

X

Verify^(2,4)

Block

Block Protect

Status ⁽³⁾

Unprotection

Verify^(2,4)

Block

Temporary

X

Unprotection ⁽⁶⁾

Notes: 1. X = V_ILor V_IH

2. Block Address must be given on A13-A17 bits.

3. See Table 6.

4. Operation performed on programming equipment.

5. RPNC can be held at V_IHor left open (Not Connected).

6. Not Available on M29F002NT.

Table 5. Read Electronic Signature (following AS instruction or with A9 = V_ID)

Other

Code

Device

E

G

W

A0

V_IL

V_IH

A1

V_IL

DQ0 - DQ7

20h

Addresses

Manufact. Code

V_IL

VIL

V_IH

Don’t Care

M29F002T

M29F002NT

B0h

Device Code

M29F002B

34h

Table 6. Read Block Protection with AS Instruction

Other

Addresses

Code

E

G

W

A0

A1

A13 - A17

DQ0 - DQ7

Protected Block

V_IL

V_IH

V_IL

V_IH

Block Address

Don’t Care

01h

00h

Unprotected Block

6/29

M29F002T, M29F002NT, M29F002B

Write. Writeoperationsareusedto giveInstruction

Commands to the memory or to latch input data to

be programmed.Awrite operationis initiatedwhen

Chip Enable E is Low and Write Enable W is Low

with OutputEnableG High. Addressesare latched

on the fallingedgeof W or E whicheveroccurs last.

Commandsand InputDataarelatchedontherising

edge of W or E whichever occurs first.

previously protected block can be temporarily un-

protected in order to change stored data. The

temporaryunprotectionmode is activatedby bring-

ing RPNC to V_ID. During the temporary unprotec-

tion mode the previously protected blocks are

unprotected.A block can be selectedand data can

be modified by executing the Erase or Program

instruction with the RPNCsignal held atV_ID. When

RPNC is returned to V_IH, all the previously pro-

tected blocks are again protected.

Output Disable. The data outputsare high imped-

ance when the Output Enable G is High with Write

Enable W High.

Block Unprotection. All protected blocks can be

unprotected on programming equipment to allow

updating of bit contents. All blocks must first be

protectedbefore the unprotectionoperation.Block

unprotectionis activated when A9, G and E are at

V_IDand A12, A15 at V_IH. The Block Unprotection

algorithm is shown in Figure 15. Unprotection is

initiatedby the edgeof Wfallingto V_IL. Aftera delay

of 10ms, the unprotection operation is ended by

rising W to V_IH. Unprotection verify is achieved by

bringing G and E to V_ILwhile A0 is at V_IL, A6 and

A1 are at V_IHand A9 remains at V_ID. In these

conditions,reading the output data will yield 00h if

the block defined by the inputs A13-A17 has been

succesfullyunprotected.Eachblockmustbe sepa-

rately verified by giving its address in order to

ensure that it has been unprotected.

Standby. The memory is in standby when Chip

Enable E is High and the P/E.C. is idle. The power

consumption is reduced to the standby level and

the outputs are high impedance, independent of

the Output Enable G or Write Enable W inputs.

Automatic Standby. After 150ns of bus inactivity

and when CMOS levels are driving the addresses,

the chip automatically enters a pseudo-standby

mode whereconsumptionis reducedto the CMOS

standby value, while outputs still drive the bus.

Electronic Signature. Two codes identifying the

manufacturerand the devicecan be read from the

memory. These codes allow programming equip-

ment or applications to automatically match their

interface to the characteristics of the M29F002.

The Electronic Signature is output by a Read op-

erationwhenthe voltageappliedto A9 is at V and

ID

INSTRUCTIONS AND COMMANDS

addressinput A1 is Low.Themanufacturercodeis

output when the Address input A0 is Low and the

devicecodewhen thisinput is High.OtherAddress

inputs are ignored.

The Command Interface latches commands writ-

ten to the memory. Instructions are made up from

one or more commands to perform Read Memory

Array, ReadElectronic Signature,Read Block Pro-

tection, Program, Block Erase, Chip Erase, Erase

Suspend and Erase Resume. Commands are

made of addressand data sequences.

TheElectronic Signaturecan also be read, without

raisingA9 to V , bygiving the memory the Instruc-

ID

tion AS.

Block Protection. Each block can be separately

protected against Program or Erase on program-

ming equipment. Block protection provides addi-

tional data security, as it disables all program or

erase operations. This mode is activated when

both A9 and G are raisedto V_IDand an address in

the blockis appliedon A13-A17.TheBlockProtec-

tion algorithm is shown in Figure 14. Block protec-

tion is initiatedon the edgeof W fallingto V_IL. Then

after a delay of 100µs, the edge of W rising to V_IH

ends the protection operations. Block protection

verify is achieved by bringing G, E, A0 and A6 to

V_ILand A1 to V_IH, while W is at V_IHand A9 at V_ID.

Undertheseconditions,readingthedataoutput will

yield 01h if the block defined by the inputs on

A13-A17 is protected. Any attempt to program or

erase a protected block will be ignored by the

device.

Table 7. Commands

Hex Code

00h

Command

Invalid/Reserved

10h

Chip Erase Confirm

Reserved

20h

30h

Block Erase Resume/Confirm

Set-up Erase

80h

Read Electronic Signature/

Block Protection Status

90h

A0h

B0h

F0h

Program

Erase Suspend

Read Array/Reset

Block Temporary Unprotection. This feature is

available on M29F002T and M29F002B only. Any

7/29

M29F002T, M29F002NT, M29F002B

Table 8. Instructions ⁽¹⁾

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

Addr. ^(3,7)

Data

X

1+

Read Memory Array until a new write cycle is initiated.

Read/Reset

RD ^(2,4)

F0h

Memory Array

Addr. ^(3,7)

555h

AAh

AAAh

55h

555h

F0h

Read Memory Array until a new write

cycle is initiated.

3+

Data

Addr. ^(3,7)

555h

AAAh

555h

Read Electronic Signature or Block

Protection Status until a new write cycle

is initiated. See Note 5 and 6.

AS ⁽⁴⁾Auto Select

Data

AAh

55h

90h

Program

Address

Addr. ^(3,7)

555h

AAAh

555h

Read Data Polling or Toggle

Bit until Program completes.

PG

BE

Program

4

6

Program

Data

AAh

55h

A0h

Block

Additional

Addr. ^(3,7)

555h

AAAh

555h

AAAh

Address Block ⁽⁸⁾

Block Erase

Chip Erase

Data

AAh

555h

AAh

X

55h

AAAh

55h

80h

555h

80h

AAh

555h

AAh

55h

AAAh

55h

30h

555h

10h

30h

Addr. ^(3,7)

CE

ES ⁽¹⁰⁾

ER

6

1

Note 9

Data

Addr. ^(3,7)

Data

Erase

Suspend

Read until Toggle stops, then read all the data needed from

any Block(s) not being erased then Resume Erase.

B0h

X

Addr. ^(3,7)

Erase

Resume

Read Data Polling or Toggle Bits until Erase completes or

Erase is suspended another time

Data

30h

Notes: 1. Commands not interpreted in this table will default to read array mode.

2. Await of t_PLYHis necessary after a Read/Reset command if the memory was in an Erase or Program mode

before starting any new operation (see Table 14 and Figure 9).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after

the command cycles.

5. Signature Address bits A0,A1 at V_ILwilloutput Manufacturer code (20h). Address bits A0 at V_IHand A1 at V_ILwill output

Device code.

6. Block Protection Address: A0 at V_IL, A1 at V_IHand A13-A17 within the Block will output the Block Protection status.

7. For Coded cycles address inputs A12-A17are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,

timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).

When full command is entered, read Data Polling or Togglebit until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

Theinstructions require from 1 to 6 cycles, the first

or first three of which are always write operations

usedtoinitiatethe instruction.Theyare followedby

either further write cycles to confirm the first com-

mand or executethe commandimmediately.Com-

mand sequencing must be followed exactly. Any

invalid combination of commands will reset the

device to Read Array. The increased number of

cycles has been chosen to assure maximum data

security. Instructions are initialised by two initial

Coded cycles which unlock the Command Inter-

face.Inaddition,for Erase,instructionconfirmation

is again preceded by the two Coded cycles.

Status Register Bits

P/E.C.status is indicatedduring executionby Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mandexecutionwill automaticallyoutputthesefive

StatusRegister bits. TheP/E.C. automaticallysets

bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits

(DQ0, DQ1 and DQ4) are reserved for future use

and should be masked. See Tables 9 and 10.

8/29

M29F002T, M29F002NT, M29F002B

Table 9. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase

block in Erase Suspend

’1’

’0’

Indicates the P/E.C. status, check during

Program or Erase, and on completion

before checking bits DQ5 for Program or

Erase Success.

Erase On-going

Data

Polling

7

Program Complete or data

of non erase block during

Erase Suspend

DQ

Program On-going

’-1-0-1-0-1-0-1-’ Erase or Program On-going

Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C. operations are

completed or Erase Suspend is

DQ

Program Complete

6

Toggle Bit

Erase Complete or Erase

’-1-1-1-1-1-1-1-’ Suspend on currently

addressed block

acknowledged.

’1’

’0’

Program or Erase Error

This bit is set to ’1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started. Only

possible command entry is Erase Suspend

(ES).

’1’

’0’

Erase Timeout Period Expired

Erase

Time Bit

3

Erase Timeout Period

On-going

An additional block to be erased in parallel

can be entered to the P/E.C.

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

Erase Error due to the

currently addressed block

(when DQ5 = ’1’).

’-1-0-1-0-1-0-1-’

Indicates the erase status and allows to

identify the erased block

2

Toggle Bit

Program on-going, Erase

on-going on another block or

Erase Complete

1

Erase Suspend read on

non Erase Suspend block

DQ

1

0

Reserved

Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputsa ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programmingor

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocks selectedfor erasureare protected,DQ7 will

be set to ’0’ for about 100µs, and then return to the

previous addressed memory data value.

9/29

M29F002T, M29F002NT, M29F002B

Table 10. Polling and Toggle Bits

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to ’1’ during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to ’1’

during program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to ’1’, DQ2 will toggle if the faulty block

is addressed.

Mode

DQ7

0

DQ6

DQ2

Program

Erase

Toggle

1

Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

N/A

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

thememoryblock.In caseof anerrorin blockerase

or program,the block in which the error occured or

to which the programmed data belongs, must be

discarded. The DQ5 failure condition will also ap-

pear if a usertries to programa ’1’ toa locationthat

is previously programmedto ’0’. OtherBlocks may

stillbe used.Theerrorbit resetsaftera Read/Reset

(RD) instruction. In case of success of Program or

Erase, the error bit will be set to ’0’ .

Erase Suspend Program

Toggle

Note: 1. Toggle if the address is within a block being erased.

’1’ if the address is within a block not being erased.

See Figure 11 for the Data Polling flowchart and

Figure 10 for the Data Polling waveforms.DQ7 will

also flag the Erase Suspend mode by switching

from ’0’ to ’1’ at the start of the Erase Suspend. In

order to monitor DQ7 in the Erase Suspend mode

an address within a block being erased must be

provided. For a Read Operationin Erase Suspend

mode, DQ7 will output ’1’ if the read is attempted

ona blockbeingerasedand thedatavalueon other

blocks. During Program operation in Erase Sus-

pend Mode, DQ7 will have the same behaviour as

in the normal program execution outside of the

suspend mode.

Erase Timer Bit (DQ3). This bit is set to ’0’ by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

periodis finished,after 50µs to120µs, DQ3returns

to ’1’.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address 555h during the

first cycle. During the second cycle the Coded

cycles consist of writing the data 55h at address

AAAh. Theaddresslines A0 to A11are valid,other

address lines are ’don’t care’. The Coded cycles

happenon firstand secondcyclesof thecommand

write or on the fourth and fifth cycles.

Toggle Bit (DQ6). WhenProgramming or Erasing

operationsare in progress,successiveattemptsto

readDQ6willoutputcomplementarydata. DQ6will

toggle following toggling of either G, or E when G

is low. The operationis completed when two suc-

cessivereads yieldthe same output data.Thenext

readwill outputthe bitlastprogrammedora ’1’after

erasing. The toggle bit DQ6 is valid only during

P/E.C. operations, that is after the fourth W pulse

for programming or after the sixth W pulse for

Erase. If the blocks selected for erasure are pro-

Instructions

tected, DQ6 will toggle for about 100 s and then

µ

See Table 8.

returnback toRead. DQ6will be setto ’1’if a Read

operationis attemptedon anEraseSuspendblock.

When erase is suspended DQ6 will toggle during

programming operations in a blockdifferent to the

block in Erase Suspend.Either E or G toggling will

cause DQ6 to toggle. See Figure 12 for Toggle Bit

flowchart and Figure 13 for ToggleBit waveforms.

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

commandF0h.It canbe optionallyprecededbythe

twoCodedcycles.Subsequentreadoperationswill

read the memory array addressed and output the

data read. A wait state of 10 s is necessaryafter

µ

Read/Reset prior to any valid read if the memory

was in an Erase mode when the RD instruction is

given.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

duringthe Erase operations.It can also be usedto

10/29

M29F002T, M29F002NT, M29F002B

Table 11. AC MeasurementConditions

High Speed

10ns

Standard

Input Rise and Fall Times

10ns

≤

Input Pulse Voltages

0 to 3V

1.5V

0.45V to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 4. AC Testing Input Output Waveform

Figure 5. AC Testing Load Circuit

1.3V

High Speed

1N914

3V

1.5V

3.3kΩ

0V

DEVICE

UNDER

TEST

OUT

Standard

C

L

2.4V

2.0V

0.8V

0.45V

C

= 30pF for High Speed

= 100pF for Standard

includes JIG capacitance

L

AI01275B

AI01276B

Table 12. Capacitance⁽¹⁾(T = 25 C, f = 1 MHz )

°

A

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

V_IN= 0V

Min

Max

6

Unit

pF

C_OUT

V_OUT= 0V

12

pF

Note: 1. Sampled only, not 100% tested.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command90h to address555h for

commandset-up.Asubsequentread willoutputthe

manufacturer code and the device code or the

block protection status depending on the levels of

A0 and A1. The manufacturercode, 20h, is output

when the addresses lines A0 and A1 are Low, the

devicecodeis outputwhen A0isHigh withA1 Low.

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address555h on the third cycle after two

Coded cycles. A fourth write operation latches the

Addresson the falling edge of W or E and the Data

to be written on the rising edge and starts the

P/E.C.Read operationsoutput the StatusRegister

bits after the programming has started. Memory

programming is made only by writing ’0’ in place of

’1’.StatusbitsDQ6 and DQ7determineif program-

mingis on-goingand DQ5allowsverificationof any

possible error. Programming at an address not in

blocks being erased is also possible during erase

suspend. In this case, DQ2 will toggle at the ad-

dress being programmed.

The AS instruction also allows access to the block

protectionstatus.Aftergivingthe ASinstruction,A0

is set to V with A1 at V , while A13-A17 define

IL

IH

the address of the block to be verified. A read in

these conditions will output a 01h if the block is

protected and a 00h if the block is not protected.

11/29

M29F002T, M29F002NT, M29F002B

Table 13. DC Characteristics

(T = 0 to 70 C or –40 to 85 C; V = 5V 10%)

°

±

A

CC

Symbol

Parameter

Test Condition

0V ≤ V_IN≤ V_CC

0V ≤ V_OUT≤ V_CC

RPNC = V_CC

Min

Max

±1

Unit

µA

(2)

I_LI

Input Leakage Current

Output Leakage Current

I_LO

±1

µA

I_LR1

I_LR2

I_CC1

I_CC2

I_CC3

RPNC Leakage Current High

RPNC Leakage Current Low

Supply Current (Read) TTL Byte

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

±1

µA

RPNC = V_SS

–0.2

–10

20

µA

E = V_IL, G = V_IH, f = 6MHz

E = V_IH

mA

1

E = V_CC0.2V

100

A

µ

±

Byte program, Block or

Chip Erase in progress

(1)

I_CC4

Supply Current (Program or Erase)

20

mA

V_IL

V_IH

V_OL

Input Low Voltage

–0.5

2

0.8

V_CC+ 0.5

0.45

V

Input High Voltage

Output Low Voltage

I_OL= 5.8mA

Output High Voltage TTL

Output High Voltage CMOS

A9, E, G, RPNC High Voltage

A9, E, G, RPNC High Current

I_OH= –2.5mA

2.4

V_CC–0.4V

11.5

V_OH

I_OH= –100 A

µ

V_ID

I_ID

12.5

100

A9, E, G or RPNC = V_ID

A

µ

Supply Voltage(Erase and

Program lock-out)

V_LKO

3.2

4.2

V

Note: 1. Sampled only, not 100% tested.

2. Except RPNC.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-upcommand80h is writtento address555hon

third cycle after the two Coded cycles. The Block

EraseConfirmcommand 30h is similarly writtenon

the sixth cycle after another two Coded cycles.

During the input of the second command an ad-

dress within the block to be erased is given and

latched into the memory. Additional block Erase

Confirm commands and block addresses can be

written subsequently to erase other blocks in par-

allel, without further Coded cycles. The erase will

start after the erase timeout period (see Erase

Timer Bit DQ3 description). Thus, additionalErase

Confirm commandsfor other blocks mustbe given

within this delay. Theinput of a new EraseConfirm

commandwillrestartthetimeoutperiod.Thestatus

of the internal timer can be monitored through the

level of DQ3, if DQ3 is ’0’ the Block Erase Com-

mand has been given and the timeoutis running,if

DQ3 is ’1’, the timeout has expired and the P/E.C.

is erasing the Block(s). If the second command

givenis not an erase confirmor if theCodedcycles

are wrong, the instruction aborts,and thedevice is

resetto Read Array. It is not necessaryto program

the block with 00h as the P/E.C. will do this auto-

maticallybeforeto erasingto FFh.Readoperations

after the sixth rising edge of W or E output the

status register status bits.

Duringthe executionof theeraseby the P/E.C.,the

memory accepts onlythe Erase Suspend ES and

Read/Reset RD instructions. Data Polling bit DQ7

returns ’0’ while the erasure is in progress and ’1’

when it has completed. The Toggle bit DQ2 and

DQ6 toggle during the erase operation. They stop

when erase is completed. After completion the

StatusRegisterbit DQ5returns’1’ iftherehas been

an erase failure. In such a situation, the Toggle bit

DQ2 can be used to determine which block is not

correctly erased. In the case of erase failure, a

Read/ResetRDinstruction is necessaryin orderto

reset the P/E.C.

12/29

M29F002T, M29F002NT, M29F002B

Table 14. Read AC Characteristics

(T = 0 to 70 C or –40 to 85 C)

°

A

M29F002T / M29F002NT / M29F002B

-70

-90

-120

Symbol

Alt

Parameter

Test Condition

Unit

V_CC= 5V 10% V = 5V 10% V = 5V 10%

±

CC

Standard

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Address Valid to

Next Address Valid

t_AVAV

t_AVQV

t_RC

t_ACC

t_LZ

E = V_IL, G = V_IL

G = V_IL

70

90

120

ns

Address Valid to

Output Valid

70

90

35

20

10

120

Chip Enable Low to

Output Transition

(1)

t_ELQX

0

Chip Enable Low to

Output Valid

(2)

t_ELQV

t_CE

G = V_IL

70

30

20

10

120

50

30

10

Output Enable Low

to Output Transition

(1)

t_GLQX

t_OLZ

t_OE

E = V_IL

0

Output Enable Low

to Output Valid

(2)

t_GLQV

E = V_IL

Chip Enable High to

Output Transition

t_EHQX

t_OH

G = V_IL

0

Chip Enable High to

Output Hi-Z

(1)

t_EHQZ

t_HZ

G = V_IL

Output Enable High

to Output Transition

t_GHQX

t_OH

E = V_IL

0

Output Enable High

to Output Hi-Z

(1)

t_GHQZ

t_DF

E = V_IL

Address Transition

to Output Transition

t_AXQX

t_OH

E = V_IL, G = V_IL

0

RPNC Low to Read

Mode

(1,3)

t_PLEL

t_READY

s

µ

RPNC High to Chip

Enable Low

t_PHEL

t_PLPX

t_RSP

50

ns

t_RPRPNC Pulse Width

500

Notes: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t_ELQV- t_GLQVafterthe falling edge of E without increasing t_ELQV

3. To be considered only if the Reset pulse is given while the memory is in Erase mode.

.

13/29

M29F002T, M29F002NT, M29F002B

Figure 6. Read Mode AC Waveforms

14/29

M29F002T, M29F002NT, M29F002B

Table 15. Write AC Characteristics,Write Enable Controlled

(T = 0 to 70 C or –40 to 85 C)

°

A

M29F002T / M29F002NT / M29F002B

-70

-90

-120

Symbol

Alt

Parameter

Unit

V_CC= 5V 10% V_CC= 5V 10% V_CC= 5V 10%

±

Standard

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Address Validto Next Address

Valid

t_AVAV

t_WC

t_CS

t_WP

70

0

90

0

120

0

ns

Chip Enable Low to Write Enable

Low

t_ELWL

Write Enable Low to Write Enable

High

t_WLWH

t_DVWH

t_WHDX

35

30

0

45

0

50

0

ns

t_DSInput Valid to Write Enable High

Write Enable High to Input

Transition

t_DH

Write Enable High to Chip Enable

High

t_WHEH

t_CH

0

ns

Write Enable High to Write Enable

t_WHWL

t_AVWL

t_WLAX

t_WPH

Low

20

5

20

5

20

5

ns

t_ASAddress Valid to Write Enable Low

Write Enable Low to Address

Transition

t_AH

45

50

Output Enable High to Write

Enable Low

t_GHWL

t_VCHEL

t_WHGL

0

50

0

50

0

50

0

ns

t_VCSV_CCHigh to Chip Enable Low

s

µ

Write Enable High to Output

Enable Low

t_OEH

ns

(1,2)

t_PHPHH

t_VIDRRPNC Rise Time to V_ID

t_RPRPNC Pulse Width

500

ns

t_PLPX

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotectionoperation.

ChipErase(CE)Instruction.Thisinstructionuses

six write cycles. The Erase Set-up command 80h

is written to address 555h on the third cycle after

the two Coded cycles. The Chip Erase Confirm

command10h is similarly writtenon the sixth cycle

after another two Coded cycles. If the second

command given is not an erase confirm or if the

Codedcycles arewrong, the instructionabortsand

thedeviceis resettoReadArray.It is notnecessary

toprogramthearray with00h first astheP/E.C. will

automaticallydo thisbeforeerasingittoFFh. Read

operations after the sixth rising edge of W or E

output the Status Register bits. During the execu-

tionof theeraseby the P/E.C.,DataPollingbit DQ7

returns ’0’, then ’1’ on completion. The Toggle bits

DQ2 and DQ6 toggle during erase operation and

stopwhenerase is completed.Aftercompletionthe

StatusRegisterbit DQ5returns’1’ iftherehas been

an Erase Failure.

15/29

M29F002T, M29F002NT, M29F002B

Figure 7. Write AC Waveforms, W Controlled

tAVAV

VALID

A0-A17

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7

V

CC

tVCHEL

AI02083

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

Erase Suspend (ES) Instruction. The Block

Eraseoperationmay be suspendedbythis instruc-

tion which consists of writing the command B0h

without any specific address. No Codedcycles are

required. It permits reading of data from another

block and programming in another block while an

erase operation is in progress. Erase suspend is

accepted only during the Block Erase instruction

execution. Writing this command during Erase

timeout will, in addition to suspending the erase,

terminate the timeout. The Toggle bit DQ6 stops

togglingwhentheP/E.C.is suspended.The Toggle

bitswill stoptogglingbetween0.1µs and 15µs after

the Erase Suspend (ES) command has been writ-

ten. The device will then automatically be set to

Read Memory Array mode. When erase is sus-

pended, a Read from blocks being erased will

output DQ2 toggling and DQ6 at ’1’. A Read from

a blocknot being erasedreturnsvalid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. It will result in both DQ2 and DQ6 toggling

whenthedatais beingprogrammed.ARead/Reset

command will definitively abort erasure and result

in invalid data in the blocks being erased.

EraseResume(ER)Instruction. Ifan Erase Sus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

POWER SUPPLY

Power Up

ThememoryCommandInterfaceis reset onpower

up to Read Array. Either E or W must be tied to V_IH

during Power Up to allow maximum security and

thepossibility to writea commandon the first rising

edge of E and W. Any write cycle initiation is

blocked when Vcc is below V_LKO

.

Supply Rails

Normal precautionsmust be taken for supply volt-

age decoupling; each device in a system should

havethe V_CCrail decoupledwith a 0.1µF capacitor

close to the V_CCand V_SSpins. The PCB trace

widths should be sufficient to carry the V_CCpro-

gram and erase currents required.

16/29

M29F002T, M29F002NT, M29F002B

Table 16. Write AC Characteristics,Chip Enable Controlled

(T = 0 to 70 C or –40 to 85 C)

°

A

M29F002T / M29F002NT / M29F002B

-70

-90

-120

Symbol

Alt

Parameter

Unit

V_CC= 5V 10% V_CC= 5V 10% V_CC= 5V 10%

±

Standard

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Address Valid to Next Address

Valid

t_AVAV

t_WC

t_WS

70

0

90

0

120

0

ns

Write Enable Low to Chip

Enable Low

t_WLEL

Chip Enable Low to Chip

Enable High

t_ELEH

t_DVEH

t_EHDX

t_CP

t_DS

t_DH

35

30

5

45

5

50

5

ns

Input Valid to Chip Enable High

Chip Enable High to Input

Transition

Chip Enable High to Write

Enable High

t_EHWH

t_EHEL

t_AVEL

t_ELAX

t_WH

0

20

0

ns

Chip Enable High to Chip

Enable Low

t_CPH

t_AS

20

0

20

0

Address Valid to Chip Enable

Low

Chip Enable Low to Address

Transition

t_AH

45

50

Output Enable High Chip

Enable Low

t_GHEL

t_VCHWL

t_EHGL

0

50

0

50

0

50

0

ns

µs

ns

t_VCS

t_OEH

V_CCHigh to Write Enable Low

Chip Enable High to Output

Enable Low

(1,2)

t_PHPHH

t_VIDR

t_RP

RPNC Rise TIme to V_ID

RPNC Pulse Width

500

ns

t_PLPX

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotectionoperation.

17/29

M29F002T, M29F002NT, M29F002B

Figure 8. Write AC Waveforms, E Controlled

tAVAV

VALID

A0-A17

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tDVEH

VALID

tEHDX

DQ0-DQ7

V

CC

tVCHWL

AI02084

Note: Address are latched on the fallingedge of E, Data is latchedon the rising edge of E.

Figure 9. Read and Write AC Characteristics, RP Related

E

tPHEL

tPLPX

RPNC

tPHPHH

tPLEL

AI02085

18/29

M29F002T, M29F002NT, M29F002B

Table 17. Data Polling and Toggle Bit AC Characteristics⁽¹⁾

(T = 0 to 70 C or –40 to 85 C)

°

A

M29F002T / M29F002NT / M29F002B

-70

-90

-120

Sym-

bol

Alt

Parameter

Unit

V_CC= 5V 10% V_CC= 5V 10% V_CC= 5V 10%

±

Standard

Interface

Standard

Interface

Standard

Interface

Min

Max

Min

Max

Min

Max

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

1.0

10

2400

10

1.0

10

2400

10

1.0

10

2400

s

µ

t_WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

30

2400

30

2400

30

2400

30

sec

µs

Chip Enable High to DQ7 Valid

(Program, E Controlled)

t_EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

sec

ns

Q7 Validto Output Valid (Data

Polling)

t_Q7VQV

30

35

50

Write Enable High to Output

Valid (Program)

10

1.0

10

2400

30

10

1.0

10

2400

30

10

1.0

10

2400

30

s

µ

t_WHQV

Write Enable High to Output

Valid (Chip Erase)

sec

µs

Chip Enable High to Output

Valid (Program)

2400

30

2400

30

2400

30

t_EHQV

Chip Enable High to Output

Valid (Chip Erase)

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

19/29

M29F002T, M29F002NT, M29F002B

Figure 10. DataPolling DQ7 AC Waveforms

20/29

M29F002T, M29F002NT, M29F002B

Figure 12. Data Toggle Flowchart

START

Figure 11. DataPolling Flowchart

START

READ

DQ2, DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

NO

DQ2, DQ6

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ2, DQ6

READ DQ7

DQ7

=

DATA

YES

NO

DQ2, DQ6

=

TOGGLE

NO

YES

FAIL

PASS

AI01369

AI01873

Table 18. Program, Erase Times and Program, Erase Endurance Cycles

(T = 0 to 70 C)

°

A

M29F002T / M29F002NT / M29F002B

Parameter

Unit

Typical after

100k W/E Cycles

Min

Typ

Chip Erase (Preprogrammed)

Chip Erase

0.7

2.4

0.6

0.5

0.9

1.0

3.2

11

0.9

2.5

sec

Boot Block Erase

Parameter Block Erase

Main Block (32Kb) Erase

Main Block (64Kb) Erase

Chip Program (Byte)

Byte Program

3.2

11

s

µ

Program/Erase Cycles (per Block)

100,000

cycles

21/29

M29F002T, M29F002NT, M29F002B

Figure 13. DataToggle DQ6, DQ2 AC Waveforms

22/29

M29F002T, M29F002NT, M29F002B

Figure 14. Block Protection Flowchart

START

BLOCK ADDRESS

on A13-A17

W = V

IH

Set-up

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Protect

Verify

Wait 100µs

W = V

IH

E, G = V

IH

VERIFY BLOCK PROTECTION

A0, A6 = V ; A1 = V ; A9 = V

ID

IL

IH

A13-A17 IDENTIFY BLOCK

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

VERIFY BLOCK

PROTECT STATUS

NO

DATA

=

01h

YES

A9 = V

IH

++n

NO

= 25

PASS

YES

A9 = V

IH

FAIL

AI02088B

23/29

M29F002T, M29F002NT, M29F002B

Figure 15. All Blocks Unprotecting Flowchart

START

PROTECT

ALL BLOCKS

n = 0

Set-up

W = V

IH

E, G, A9 = V

ID

A12, A15 = V

IH

Wait 4µs

W = V

IL

Wait 10ms

Unprotect

Verify

W = V

IH

E, G = V

IH

E, A0 = V ; A1, A6 = V ; A9 = V

ID

IL

IH

A13-A17 IDENTIFY BLOCK

Wait 4µs

G = V

IL

Wait 60ns

VERIFY BLOCK

PROTECT STATUS

NO

YES

DATA

=

00h

NO

++n

= 1000

LAST

BLK.

NO

YES

A9 = V

IH

A9 = V

IH

FAIL

PASS

AI02089C

24/29

M29F002T, M29F002NT, M29F002B

ORDERING INFORMATION SCHEME

Example:

M29F002T

-70

X

K

1

TR

Operating Voltage

Option

F

5V

TR Tape & Reel

Packing

Array Matrix

Top Boot

Speed

-70 70ns

Power Supplies

blank V_CC10%

Package

PDIP32

PLCC32

Temp. Range

0 to 70 C

T

B

P

K

N

1

6

±

°

Bottom Boot

-90 90ns

X

V_CC5%

–40 to 85 C

°

±

NT Top Boot

without

-120 120ns

TSOP32

(8 x 20 mm)

RPNC function

Devices are shipped from the factory with the memory content erased (to FFh).

Fora list ofavailableoptions(Speed, Package,etc...)or for furtherinformationon anyaspect of thisdevice,

please contact the STMicroelectronics Sales Office nearest to you.

25/29

M29F002T, M29F002NT, M29F002B

PDIP32 - 32 pin Plastic DIP, 600 mils width

mm

Min

–

inches

Min

–

Symb

Typ

Max

5.08

–

Typ

Max

0.200

–

A

A1

A2

B

0.38

3.56

0.38

–

0.015

0.140

0.015

–

4.06

0.51

–

0.160

0.020

–

B1

C

1.52

0.060

0.20

41.78

–

0.30

42.04

–

0.008

1.645

–

0.012

1.655

–

D

D2

E

38.10

15.24

1.500

0.600

–

E1

e1

eA

eB

L

13.59

–

13.84

–

0.535

–

0.545

–

2.54

0.100

0.600

15.24

–

15.24

3.18

1.78

0°

17.78

3.43

2.03

10°

0.600

0.125

0.070

0°

0.700

0.135

0.080

10°

S

α

N

32

A2

A

A1

e1

L

α

C

B1

B

eA

eB

D2

D

S

N

1

E1

E

PDIP

Drawing is not to scale.

26/29

M29F002T, M29F002NT, M29F002B

PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular

mm

Min

2.54

1.52

–

inches

Min

0.100

0.060

–

Symb

Typ

Max

3.56

2.41

0.38

0.53

0.81

12.57

11.56

10.92

15.11

14.10

13.46

–

Typ

Max

0.140

0.095

0.015

0.021

0.032

0.495

0.455

0.430

0.595

0.555

0.530

–

A

A1

A2

B

0.33

0.66

12.32

11.35

9.91

14.86

13.89

12.45

–

0.013

0.026

0.485

0.447

0.390

0.585

0.547

0.490

–

B1

D

D1

D2

E

E1

E2

e

1.27

0.89

0.050

0.035

F

0.00

–

0.25

–

0.000

–

0.010

–

R

N

32

Nd

Ne

CP

7

9

0.10

0.004

D

A1

D1

A2

1 N

B1

e

Ne

E1 E

D2/E2

F

B

0.51 (.020)

1.14 (.045)

Nd

A

R

CP

PLCC

Drawing is not to scale.

27/29

M29F002T, M29F002NT, M29F002B

TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

8.10

-

Typ

Max

0.047

0.007

0.041

0.011

0.008

0.795

0.728

0.319

-

A

A1

A2

B

0.05

0.95

0.15

0.10

19.80

18.30

7.90

-

0.002

0.037

0.006

0.004

0.780

0.720

0.311

-

C

D

D1

E

e

0.50

0.020

L

0.50

0.70

0.020

0.028

0

°

5

°

0

°

5

°

α

N

32

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Drawing is not to scale.

28/29

M29F002T, M29F002NT, M29F002B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

STMicroelectronics GROUP OF COMPANIES

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Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

29/29

型号	制造商	描述	价格	文档
M29F002T-70K6	STMICROELECTRONICS	暂无描述	获取价格
M29F002T-70K6TR	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002T-70K6TR	NUMONYX	Flash, 256KX8, 70ns, PQCC32, PLASTIC, LCC-32	获取价格
M29F002T-70N1TR	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002T-70N1TR	NUMONYX	暂无描述	获取价格
M29F002T-70N6TR	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002T-70N6TR	NUMONYX	Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32	获取价格
M29F002T-70P1TR	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002T-70P6TR	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格
M29F002T-70XK1TR	STMICROELECTRONICS	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory	获取价格

M29F002T-70K1TR

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