M29F040-150K5TR [STMICROELECTRONICS]
4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory; 4兆位512KB ×8 ，统一座单电源闪存
| 型号： | M29F040-150K5TR |
| 厂家： | 
ST |
| 描述： | 4 Mbit 512Kb x8, Uniform Block Single Supply Flash Memory |
| 文件： | 总31页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29F040
4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory
NOT FOR NEW DESIGN
M29F040 is replaced by the M29F040B
5V ± 10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
BYTE PROGRAMMING TIME: 10µs typical
ERASE TIME
– Block: 1.0 sec typical
– Chip: 2.5 sec typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Data Polling and Toggle bits Protocol for
P/E.C. Status
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
MEMORY ERASE in BLOCKS
– 8 Uniform Blocks of 64 KBytes each
– Block Protection
Figure 1. Logic Diagram
– Multiblock Erase
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION
– Read mode: 8mA typical (at 12MHz)
– Stand-by mode: 25µA typical
– Automatic Stand-by mode
V
CC
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: E2h
19
8
A0-A18
DQ0-DQ7
W
E
M29F040
Table 1. Signal Names
G
A0-A18
Address Inputs
Data Input / Outputs
Chip Enable
DQ0-DQ7
E
V
SS
AI01372
G
Output Enable
Write Enable
Supply Voltage
Ground
W
VCC
VSS
November 1999
1/31
This is information on a product still in production but not recommended for new designs.
M29F040
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
A11
A9
1
32
G
A10
E
A8
1 32
A13
A14
A17
W
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A14
A13
A8
A6
A5
A4
A9
V
8
9
25
24
M29F040
(Normal)
CC
A3
A2
9
M29F040
25 A11
G
A18
V
SS
A16
A15
A12
A7
DQ2
DQ1
DQ0
A0
A1
A10
E
A0
DQ0
DQ7
17
A6
A1
A5
A2
A4
16
17
A3
AI01378
AI01379
Figure 2C. TSOP Reverse Pin Connections
DESCRIPTION
The M29F040 is a non-volatile memory that may
be erased electrically at the block level, and pro-
grammed Byte-by-Byte.
The interface is directly compatible with most mi-
croprocessors. PLCC32 and TSOP32 (8 x 20mm)
packages are available. Both normal and reverse
pin outs are available for the TSOP32 package.
G
A10
E
A11
A9
1
32
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
A17
W
Organisation
The Flash Memory organisation is 512Kx8 bitswith
Address lines A0-A18 and Data Inputs/Outputs
DQ0-DQ7. Memory control is provided by Chip
Enable, Output Enable and Write Enable Inputs.
8
9
25
24
V
M29F040
(Reverse)
CC
V
A18
A16
A15
A12
A7
SS
Erase and Program are performed through the
internal Program/Erase Controller (P/E.C.).
DQ2
DQ1
DQ0
A0
Data Outputs bits DQ7 and DQ6 provide polling or
toggle signals during Automatic Program or Erase
to indicate the Ready/Busy state of the internal
Program/Erase Controller.
A1
A6
Memory Blocks
A2
A5
A3
16
17
A4
Erasure of the memory is in blocks. There are 8
uniform blocks of 64 Kbytes each in the memory
address space. Each block can be programmed
and erased over 100,000 cycles. Each uniform
block may separately be protected and unpro-
AI01174B
2/31
M29F040
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–0.6 to 7
Unit
Ambient Operating Temperature (3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
C
°
TBIAS
TSTG
C
C
°
°
(2)
VIO
V
VCC
–0.6 to 7
V
V
(2)
VA9
A9 Voltage
–0.6 to 13.5
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
tected against program and erase. Block erasure
may be suspended, while data is read from other
blocks of the memory, and then resumed.
tions and provides Data Polling, Toggle, and Status
data to indicate completion of Program and Erase
Operations.
Bus Operations
Instructions are composed of up to six cycles. The
first two cycles input a code sequence to the Com-
mand Interface which is common to all P/E.C.
instructions (see Table 7 for Command Descrip-
tions). The third cycle inputs the instruction set up
command instruction to the Command Interface.
Subsequent cycles output Signature, Block Protec-
tion or the addressed data for Read operations.
For added data protection, the instructions for pro-
gram, and block or chip erase require further com-
mand inputs. For a Program instruction, the fourth
command cycle inputs the address and data to be
programmed. For an Erase instruction (block or
chip), the fourth and fifth cycles input a further code
sequence before the Erase confirm command on
the sixth cycle. Byte programming takes typically
10µs while erase is performed in typically 1.0 sec-
ond.
Seven operations can be performed by the appro-
priate bus cycles, Read Array, Read Electronic
Signature, Output Disable, Standby, Protect Block,
Unprotect Block, and Write the Command of an
Instruction.
Command Interface
Command Bytes can be written to a Command
Interface (C.I.) latch to perform Reading (from the
Array or Electronic Signature), Erasure or Pro-
gramming. For added data protection, command
execution starts after 4 or 6 command cycles. The
first, second, fourth and fifth cycles are used to
input a code sequence to the Command Interface
(C.I.). This sequence is equal for all P/E.C. instruc-
tions. Command itself and its confirmation - if it
applies - are given on the third and fourth or sixth
cycles.
Erasure of a memory block may be suspended, in
order to read data from another block, and then
resumed. Data Polling, Toggle and Error data may
be read at any time, including during the program-
ming or erase cycles, to monitor the progress of
the operation. When power is first applied or if VCC
falls below VLKO, the command interface is reset to
Read Array.
Instructions
Seven instructions are defined to perform Reset,
Read Electronic Signature, Auto Program, Block
Auto Erase, Chip Auto Erase, BlockErase Suspend
and Block Erase Resume. The internal Pro-
gram/Erase Controller (P/E.C.) handles all timing
and verification of the Program and Erase instruc-
3/31
M29F040
Table 3. Operations
Operation
Read
E
G
VIL
VIH
VIH
X
W
VIH
VIL
VIH
X
DQ0 - DQ7
Data Output
Data Input
Hi-Z
VIL
VIL
VIL
VIH
Write
Output Disable
Standby
Hi-Z
Note:
X = VIL or VIH
Table 4. Electronic Signature
Other
Addresses
Code
E
G
W
A0
A1
A6
A9
DQ0 - DQ7
Manufact. Code
Device Code
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIL
VIL
VID
VID
Don’t Care
Don’t Care
20h
E2h
Table 5. Block Protection Status
Other
Addresses
Code
E
G
W
A0
A1
A6
A16 A17 A18
DQ0 - DQ7
Protected Block
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
SA
SA
SA
SA
SA
SA
Don’t Care
Don’t Care
01h
00h
Unprotected Block
Note:
SA = Address of block being checked
DEVICE OPERATION
Signal Descriptions
when the chip is deselected or the outputs are
disabled.
Chip Enable (E). The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High deselects the memory and
reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Addresses are then
latched on the falling edge of E while data is latched
on the rising edge of E. The Chip Enable must be
forced to VID during Block Unprotect operations.
Address Inputs (A0-A18). The address inputs for
the memory array are latched during a write opera-
tion. The A9 address input is used also for the
Electronic Signature read and Block Protect veri-
fication. When A9 is raised to VID, either a Read
Manufacturer Code, Read Device Code or Verify
Block Protection is enabled depending on the com-
bination of levels on A0, A1 and A6. When A0, A1
and A6 are Low, the Electronic Signature Manufac-
turer code is read, when A0 is High and A1 and A6
are Low, the Device code is read, and when A1 is
High and A0 and A6 are low, the Block Protection
Status is read for the block addressed by A16, A17,
A18.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. G must be forced to VID level during
Block Protect and Block Unprotect operations.
Data Input/Outputs (DQ0-DQ7). The data input is
a byte to be programmed or a command written to
the C.I. Both are latched when Chip Enable E and
Write Enable W are active. The data output is from
the memory Array, the Electronic Signature, the
Data Polling bit (DQ7), the Toggle Bit (DQ6), the
Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-
puts are valid when Chip Enable E and Output
Enable G are active. The output is high impedance
Write Enable (W). This input controls writing to the
Command Register and Address and Data latches.
Addresses are latched on the falling edge of W, and
Data Inputs are latched on the rising edge of W.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
4/31
M29F040
Table 6. Instructions (1,2)
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr. (3,7)
Data
X
1+
Read Memory Array until a new write cycle is initiated.
Read Array/
Reset
RST (4,10)
F0h
Addr. (3,7) 5555h
2AAAh
55h
5555h
F0h
Read Memory Array until a new write
cycle is initiated.
3+
3+
3+
Data
AAh
Read
Electronic
Signature
Addr. (3,7) 5555h
2AAAh
5555h
Read Electronic Signature until a new
write cycle is initiated. See Note 5.
RSIG (4)
RBP (4)
Data
Addr. (3,7) 5555h
Data AAh
Addr. (3,7) 5555h
AAh
55h
90h
2AAAh
55h
5555h
90h
Read Block
Protection
Read Block Protection until a new write
cycle is initiated. See Note 6.
Program
2AAAh
55h
5555h
A0h
Address
Read Data Polling or Toggle Bit
until Program completes.
PG
BE
Program
4
6
Program
Data
Data
AAh
Block
Additional
Addr. (3,7) 5555h
2AAAh
5555h
5555h
2AAAh
Address Block (8)
Block Erase
Chip Erase
Data
AAh
55h
2AAAh
55h
80h
5555h
80h
AAh
5555h
AAh
55h
2AAAh
55h
30h
5555h
10h
30h
Addr. (3,7) 5555h
CE
ES
ER
6
1
1
Note 9
Data
AAh
X
Addr. (3,7)
Data
Erase
Suspend
Read until Toggle stops, then read all the data needed from any
uniform block(s) not being erased then Resume Erase.
B0h
X
Addr. (3,7)
Data
Erase
Resume
Read Data Polling or Toggle Bit until Erase completes or Erase
is suspended another time
30h
Notes: 1. Command not interpreted in this table will default to read array mode.
2. While writing any command or during RSG and RSP execution, the P/E.C. can be reset by writing the command 00h to the C.I.
3. X = Don’t Care.
4. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle.
5. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output
Device code.
6. Protection Address: A0, A6 at VIL, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection
status.
7. Address bits A15-A18 are don’t care for coded address inputs.
8. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling or Toggle bit until Erase completes.
10. A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase status, before starting
any operation.
5/31
M29F040
Memory Blocks
where consumption is reduced to the CMOS
standby value, while outputs are still driving the
bus.
The memory blocks of the M29F040 are shown in
Figure 3. The memory array is divided in 8 uniform
blocks of 64 Kbytes. Each block can be erased
separately or any combination of blocks can be
erased simultaneously. The Block Erase operation
is managed automatically by the P/E.C. The opera-
tion can be suspended in order to read from any
other block, and then resumed.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory, the manufacturer’s code for STMicroelec-
tronics is 20h, and the device code is E2h for the
M29F040. These codes allow programming equip-
ment or applications to automatically match their
interface to the characteristics of the particular
manufacturer’s product. The Electronic Signature
is output by a Read operation when the voltage
applied to A9 is at VID and address inputs A1 and
A6 are at Low. The manufacturer code is output
when the Address input A0 is Low and the device
code when this input is High. Other Address inputs
are ignored. The codes are output on DQ0-DQ7.
This is shown in Table 4.
Block Protection provides additional data security.
Each uniform block can be separately protected or
unprotected against Program or Erase. Bringing A9
and G to VID initiates protection, while bringing A9,
G and E to VID cancels the protection. The block
affected during protection is addressed by the in-
puts on A16, A17, and A18. Unprotect operation
affects all blocks.
Operations
The Electronic Signature can also be read, without
raising A9 to VID by giving the memory the instruc-
tion RSIG (see below).
Operations are defined as specific bus cycles and
signals which allow Memory Read, Command
Write, Output Disable, Standby, Read Status Bits,
Block Protect/Unprotect, Block Protection Check
and Electronic Signature Read. They are shown in
Tables 3, 4, 5.
Block Protection. Each uniform block can be
separately protected against Program or Erase.
Block Protection provides additional data security,
as it disables all program or erase operations. This
mode is activated when both A9 and G are set to
Read. Read operations are used to output the
contents of the Memory Array, the Status Register
or the Electronic Signature. Both Chip Enable E
and Output Enable G must be low in order to read
the output of the memory. The Chip Enable input
also provides power control and should be used for
device selection. Output Enable should be used to
gate data onto the outputindependentofthe device
selection. The data read depends on the previous
command written to the memory (see instructions
RST and RSIG, and Status Bits).
VID and the block address is applied on A16-A18.
Block Protection is programmed using a Presto F
program like algorithm. Protection is initiated on the
edge of Wfalling to VIL. Then after a delay of100µs,
the edge of W rising to VIH ends the protection
operation. Protection verify is achieved by bringing
G, E and A6 to VIL while W is at VIH and A9 at VID.
Under these conditions, reading the data output will
yield 01h if the block defined by the inputs on
A16-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the
device.
Write. Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. A write operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs last.
Commands and Input Data are latchedon the rising
edge of W or E whichever occurs first.
Any protected block can be unprotected to allow
updating of bit contents. All blocks must be pro-
tected before an unprotect operation. Block Un-
protect is activated when A9, G and E are at VID.
The addresses inputs A6, A12, A16 must be main-
tained at VIH. Block Unprotect is performed through
a Presto F Erase like algorithm. Unprotect is initi-
ated by the edge of W falling to VIL. After a delay
of 10ms, the edge of W rising to VIH will end the
unprotection operation. Unprotect verify is
achieved by bringing G and E to VIL while A6 and
W are at VIH and A9 at VID. In these conditions,
reading the output data will yield 00h if the block
defined by the inputs on A16-A18 has been suc-
cessfully unprotected. All combinations of A16-
A18 must be addressed in order to ensure that all
of the 8 uniform blocks have been unprotected.
Block Protection Status is shown in Table 5.
Output Disable. The data outputs are high imped-
ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and Program/Erase Controller
P/E.C. is Idle. The power consumption is reduced
to the standby level and the outputs are high im-
pedance, independent of the Output Enable G or
Write Enable W inputs.
Automatic Standby. After 150ns of inactivity and
when CMOS levels are driving the addresses, the
chip automatically enters a pseudo standby mode
6/31
M29F040
Figure 3. Memory Map and Block Address Table
TOP
BOTTOM
ADDRESS ADDRESS
A18
A17
1
A16
1
1
64K Bytes Block
64K Bytes Block
64K Bytes Block
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
0
1
64K Bytes Block
64K Bytes Block
0
0
AI01362B
Instructions and Commands
Table 7. Commands
The Command Interface (C.I.) latches commands
written to the memory. Instructions are made up
from one or more commands to perform Read
Array/Reset, Read Electronic Signature, Block
Erase, Chip Erase, Program, Block Erase Suspend
and Erase Resume. Commands are made of ad-
dress and data sequences. Addresses are latched
on the falling edge of W or E and data is latched
on the rising ofW or E. The instructions require from
1 to 6 cycles, the first or first three of which are
always write operations used to initiate the com-
mand. They are followed by either further write
cycles to confirm the first command or execute the
command immediately. Command sequencing
must be followed exactly. Any invalid combination
of commands will reset the device to Read Array.
The increased number of cycles has been chosen
to assure maximum data security. Commands are
initialised by two preceding coded cycles which
unlock the Command Interface. In addition, for
Erase, command confirmation is again preceeded
by the two coded cycles.
Hex Code
00h
Command
Read
Chip Erase Confirm
10h
30h
Block Erase Resume/Confirm
Set-up Erase
80h
Read Electronic Signature/
Block Protection Status
90h
A0h
B0h
F0h
Program
Erase Suspend
Read Array/Reset
DQ6, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output those four
bits. The P/E.C. automatically sets bits DQ3, DQ5,
DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and
DQ4) are reserved for future use and should be
masked.
P/E.C. status is indicated during command execu-
tion by Data Polling on DQ7, detection of Toggle on
7/31
M29F040
Table 8. Status Register
DQ
Name
Logic Level
Definition
Erase Complete
Note
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Data
Polling
Erase on Going
7
DQ
DQ
Program Complete
Program on Going
’-1-0-1-0-1-0-1-’ Erase or Program on Going
Successive read output complementary
data on DQ6 while Programming or Erase
operations are going on. DQ6 remain at
constant level when P/E.C. operations are
completed or Erase Suspend is
Program (’0’ on DQ6)
’-0-0-0-0-0-0-0-’
6
Toggle Bit
Error Bit
Complete
Erase or Program
’-1-1-1-1-1-1-1-’
acknowledged.
(’1’ on DQ6) Complete
’1’
’0’
’1’
’0’
’1’
Program or Erase Error
This bit is set to ’1’ if P/E.C. has exceded
the specified time limits.
5
4
Program or Erase on Going
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES). An additional block to be erased in
parallel can be entered to the P/E.C.
Erase
Time Bit
3
Erase Timeout Period on
Going
’0’
2
1
0
Reserved
Reserved
Reserved
Note:
Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Data Polling bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid only effective during P/E.C. operation, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at the address being programmed or at an address
within the block being erased. If the byte to be
programmed belongs to a protected block the com-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100µs, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms.
The operation is completed when two successive
reads yield the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing. The toggle bit is valid only effective during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the byte to be programmed belongs to a
protected block the command will be ignored. If the
blocks selected for erasure are protected, DQ6 will
toggle for about 100µs and then return back to
Read. See Figure 11 for Toggle Bit flowchart and
Figure 12 for Toggle Bit waveforms.
Error bit (DQ5). This bit is set to ’1’ by the P/E.C
when there is a failure of byte programming, block
erase, or chip erase that results in invalid data
being programmed in the memory block. In case of
error in block erase or byte program, the block in
which the error occured or to which the pro-
grammed byte belongs, must be discarded. Other
blocks may still be used. Error bit resets after Reset
(RST) instruction. In case of success, the error bit
will set to ’0’ during Program or Erase and to valid
data after write operation is completed.
Toggle bit (DQ6). When Programming operations
are in progress, successive attempts to read DQ6
will output complementary data. DQ6 will toggle
following toggling of either G or E when G is low.
8/31
M29F040
Table 9. AC Measurement Conditions
High Speed
10ns
Standard
10ns
Input Rise and Fall Times
≤
≤
Input Pulse Voltages
0 to 3V
1.5V
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.45V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01275B
AI01276B
Table 10. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Erase Timer bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last Block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the wait period is
finished, after 80 to 120µs, DQ3 returns back to ’1’.
Coded Cycles. The two coded cycles unlock the
Command Interface. They are followed by a com-
mand input or a comand confirmation. The coded
cycles consist of writing the data AAh at address
5555h during the first cycle and data 55h ataddress
2AAAh during the second cycle. Addresses are
latched on the falling edge of W or E while data is
latched on the rising edge of W or E. The coded
cycles happen on first and second cycles of the
command write or on the fourth and fifth cycles.
Read Array/Reset (RST) instruction. The Reset
instruction consists of one write operation giving
the command F0h. It can be optionally preceded
by the two coded cycles. A wait state of 5µs before
read operations is necessary if the Resetcommand
is applied during an Erase operation.
Read Electronic Signature (RSIG) instruction.
This instruction uses the two coded cycles followed
by one write cycle giving the command 90h to
address 5555h for command setup. Asubsequent
read will output the manufacturer code, the device
code or the Block Protection status depending on
the levels of A0, A1, A6, A16, A17 and A18. The
manufacturer code, 20h, is output when the ad-
dresses lines A0, A1 and A6 are Low, the device
code, E2h is output when A0 is High with A1 and
A6 Low.
9/31
M29F040
Table 11. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V
Min
Max
Unit
V
IN
V
CC
1
1
A
A
≤
≤
±
±
µ
µ
ILO
Output Leakage Current
Supply Current (Read)
0V
V
OUT
V
≤
CC
≤
ICC1
ICC2
ICC3
E = VIL, G = VIH, f = 6MHz
E = VIH
15
1
mA
mA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
E = VCC 0.2V
50
A
µ
±
Byte Program,
Block Erase
ICC4
Supply Current (Program or Erase)
20
mA
ICC5
VIL
Supply Current
Chip Erase in progress
40
0.8
mA
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
–0.5
2
VIH
VOL
VCC + 0.5
0.45
V
IOL = 10mA
V
IOH = –2.5mA
2.4
V
VOH
IOH = –100 A
VCC –0.4
0.85 VCC
11.5
V
µ
Output High Voltage CMOS
I
OH = –2.5mA
V
VID
IID
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
12.5
50
V
A9 = VID
A
µ
Supply Voltage (Erase and
Program lock-out)
VLKO
3.2
4.2
V
Read Block Protection (RBP) instruction. The
use of Read Electronic Signature (RSIG) command
also allows access to the Block Protection status
verify. After giving the RSIG command, A0 and A6
are set to VIL with A1 at VIH, while A16, A17 and
A18 define the block of the block to be verified. A
read in these conditions will output a 01h if block is
protected and a 00h if block is not protected.
mand 10h is written at address 5555h on sixth cycle
after another two coded cycles. If the second com-
mand given is not an erase confirm or if the coded
cycles are wrong, the instruction aborts and the
device is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing to FFh. Read
operations after the sixth rising edge of W or E
output the status register bits. During the execu-
tion of the erase by the P/E.C. the memory accepts
only the Reset (RST) command. Read of Data
Polling bit DQ7 returns ’0’, then ’1’ on completion.
The Toggle Bit DQ6 toggles during erase operation
and stops when erase is completed. After comple-
tion the Status Register bit DQ5 returns ’1’ if there
has been an Erase Failure because the erasure
has not been verified even after the maximum
number of erase cycles have been executed.
This Read Block Protection is the only valid way to
check the protection status of a block. Neverthe-
less, it must notbe used during the Block Protection
phase as a method to verify the block protection.
Please refer to Block Protection paragraph.
Chip Erase (CE) instruction. This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on third cycle after the
two coded cycles. The Chip Erase Confirm com-
10/31
M29F040
Table 12A. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3)
M29F040
-70
-90
Symbol
Alt
Parameter
Test Condition
Unit
VCC = 5V 5% VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
Max
Min
Max
tAVAV
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
E = VIL, G = VIL
E = VIL, G = VIL
G = VIL
70
90
ns
ns
ns
ns
tAVQV
70
90
(1)
tELQX
tLZ Chip Enable Low to Output Transition
tCE Chip Enable Low to Output Valid
0
0
(2)
tELQV
G = VIL
70
90
Output Enable Low to Output
Transition
(1)
tGLQX
tOLZ
E = VIL
E = VIL
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(2)
tGLQV
tOE Output Enable Low to Output Valid
30
20
20
35
20
20
Chip Enable High to Output
Transition
tEHQX
tOH
G = VIL
(1)
tEHQZ
tHZ Chip Enable High to Output Hi-Z
G = VIL
Output Enable High to Output
Transition
tGHQX
tOH
E = VIL
0
0
(1)
tGHQZ
tDF Output Enable High to Output Hi-Z
E = VIL
Address Transition to Output
Transition
tAXQX
tOH
E = VIL, G = VIL
20
20
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
.
Block Erase (BE) instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two coded cycles. The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
the block to be erased is given and latched into the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequently to erase other blocks in parallel, without
further coded cycles. The erase will start after an
Erase timeout period of about 100µs. Thus, addi-
tional Block Erase commands must be given within
this delay. The input of a new Block Erase com-
mand will restart the timeout period. The status of
the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C
is erasing the block(s). Before and during Erase
timeout, any command different from 30h will abort
the instruction and reset the device to read array
mode. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register bits.
During the execution of the erase by the P/E.C., the
memory accepts only the ES (Erase Suspend) and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle Bit DQ6 toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure because erasure has not completed even
after the maximum number of erase cycles have
been executed. In this case, it will be necessary to
input a Reset (RST) to the command interface in
order to reset the P/E.C.
11/31
M29F040
Table 12B. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)
M29F040
-120
-150
Symbol
Alt
Parameter
Test Condition
Unit
VCC = 5V 10% VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
Max
120
120
Min
Max
150
150
tAVAV
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
E = VIL, G = VIL
E = VIL, G = VIL
G = VIL
120
150
ns
ns
ns
ns
tAVQV
(1)
tELQX
tLZ Chip Enable Low to Output Transition
tCE Chip Enable Low to Output Valid
0
0
(2)
tELQV
G = VIL
Output Enable Low to Output
Transition
(1)
tGLQX
tOLZ
E = VIL
E = VIL
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(2)
tGLQV
tOE Output Enable Low to Output Valid
50
30
30
55
35
35
Chip Enable High to Output
Transition
tEHQX
tOH
G = VIL
(1)
tEHQZ
tHZ Chip Enable High to Output Hi-Z
G = VIL
Output Enable High to Output
Transition
tGHQX
tOH
E = VIL
0
0
(1)
tGHQZ
tDF Output Enable High to Output Hi-Z
E = VIL
Address Transition to Output
Transition
tAXQX
tOH
E = VIL, G = VIL
20
20
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
.
Program (PG) instruction. The memory can be
programmed Byte-by-Byte. This instruction uses
four write cycles. The Program command A0h is
written on the third cycle after two coded cycles. A
fourth write operation latches the Address on the
falling edge of W or E and the Data to be written
on its rising edge and starts the P/E.C. During the
execution of the program by the P/E.C., the mem-
ory will not accept any instruction. Read operations
output the status bits after the programming has
started. The status bits DQ5, DQ6 and DQ7 allow
a check of the status of the programming operation.
Memory programming is made only by writing ’0’ in
place of ’1’ in a Byte.
block while erase is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution and defaults to read array mode. Writing
this command during Erase timeout will, in addition
to suspending the erase, terminate the timeout.
The Toggle Bit DQ6 stops toggling when the P/E.C.
is suspended. Toggle Bit status must be monitored
at an address out of the block being erased. Toggle
Bit will stop toggling between 0.1µs and 15µs after
the Erase Suspend (ES) command has been writ-
ten.
The M29F040 will then automatically set to Read
Memory Array mode. When erase is suspended,
Read from blocks being erased will output invalid
data, Read from block not being erased is valid.
During the suspension the memory will respond
only to Erase Resume (ER) and Reset (RST) in-
structions. RST command will definitively abort
erasure and result in the invalid data in the blocks
being erased.
Erase Suspend (ES) instruction. The Block
Erase operation may be suspended by this instruc-
tion which consists of writing the command 0B0h
without any specific address code. Nocoded cycles
are required. It allows reading of data from another
12/31
M29F040
Figure 6. Read Mode AC Waveforms
13/31
M29F040
Table 13A. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2)
M29F040
-70
-90
Symbol
Alt
Parameter
Unit
VCC = 5V 10%
VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
70
0
Max
Min
90
0
Max
tAVAV
tELWL
tWC Address Valid to Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
tDS Input Valid to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tVCHEL
35
30
0
45
45
0
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
tWPH Write Enable High to Write Enable Low
tAS Address Valid to Write Enable Low
tAH Write Enable Low to Address Transition
Output Enable High to Write Enable Low
tVCS VCC High to Chip Enable Low
0
0
20
0
20
0
45
0
45
0
50
10
50
10
s
s
µ
µ
(1)
tWHQV1
tWHQV2
tWHGL
Write Enable High to Output Valid (Program)
Write Enable High to Output Valid
(Block Erase)
(1)
1.0
30
1.0
30
sec
ns
tOEH Write Enable High to Output Enable Low
0
0
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
Erase Resume (ER) instruction. If an Erase Sus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
coded cycles.
adge of E or W. Any write cycle initiation is blocked
when VCC is below VLKO
.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling, each device in a system should
have the VCC rail decoupled with a 1.0µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
Power Up
The memory Command Interface is reset on power
up to Read Array. Either E or W must be tied to VIH
during Power-up to allow maximum security and
the possibility to write a command on the first rising
14/31
M29F040
Table 13B. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)
M29F040
-120
-150
Symbol
Alt
Parameter
Unit
VCC = 5V 10%
VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
120
0
Max
Min
150
0
Max
tAVAV
tELWL
tWC Address Valid to Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
tDS Input Valid to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tVCHEL
50
50
0
50
50
0
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
tWPH Write Enable High to Write Enable Low
tAS Address Valid to Write Enable Low
tAH Write Enable Low to Address Transition
Output Enable High to Write Enable Low
tVCS VCC High to Chip Enable Low
0
0
20
0
20
0
50
0
50
0
50
10
50
10
s
s
µ
µ
(1)
tWHQV1
tWHQV2
tWHGL
Write Enable High to Output Valid (Program)
Write Enable High to Output Valid
(Block Erase)
(1)
1.0
0
30
1.0
0
30
sec
ns
tOEH Write Enable High to Output Enable Low
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
15/31
M29F040
Figure 7. Write AC Waveforms, W Controlled
WRITE CYCLE
VALID
A0-A18
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7
V
CC
tVCHEL
AI01365B
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
16/31
M29F040
Table 14A. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2)
M29F040
-70
-90
Symbol
Alt
Parameter
Unit
VCC = 5V 10%
VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
70
0
Max
Min
90
0
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
30
0
45
45
0
tDS
tDH
tWH
tCPH
tAS
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
0
0
20
0
20
0
tELAX
tGHEL
tVCHWL
tAH
45
0
45
0
tVCS
50
10
50
10
s
s
µ
µ
(1)
tEHQV1
Chip Enable High to Output Valid (Program)
Chip Enable High to Output Valid
(Block Erase)
(1)
tEHQV2
1.0
30
1.0
30
sec
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
0
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
.
2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
17/31
M29F040
Table 14B. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)
M29F040
-120
-150
Symbol
Alt
Parameter
Unit
VCC = 5V 10%
VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
120
0
Max
Min
150
0
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
0
50
50
0
tDS
tDH
tWH
tCPH
tAS
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
0
0
20
0
20
0
tELAX
tGHEL
tVCHWL
tAH
50
0
50
0
tVCS
50
10
50
10
s
s
µ
(1)
tEHQV1
Chip Enable High to Output Valid (Program)
µ
Chip Enable High to Output Valid
(Block Erase)
(1)
tEHQV2
1.0
0
30
1.0
0
30
sec
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
.
18/31
M29F040
Figure 8. Write AC Waveforms, E Controlled
WRITE CYCLE
VALID
A0-A18
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7
V
CC
tVCHWL
AI01366B
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
19/31
M29F040
Table 15A. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3)
M29F040
-70
-90
Symbol
Parameter
Unit
VCC = 5V 10%
VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
(2)
tWHQ7V1
tWHQ7V2
tEHQ7V1
tEHQ7V2
10
10
s
µ
Write Enable High to DQ7 Valid
(Block Erase, W Controlled)
(2)
(2)
(2)
1.0
10
30
1.0
10
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
s
µ
Chip Enable High to DQ7 Valid
(Block Erase, E Controlled)
1.0
30
30
1.0
30
35
sec
ns
tQ7VQV
tWHQV1
Q7 Valid to Output Valid (Data Polling)
Write Enable High to Output Valid
(Program)
10
1.0
10
10
1.0
10
s
µ
Write Enable High to Output Valid
(Block Erase)
tWHQV2
tEHQV1
tEHQV2
30
30
30
30
sec
Chip Enable High to Output Valid
(Program)
s
µ
Chip Enable High to Output Valid
(Block Erase)
1.0
1.0
sec
Notes: 1. All other timings are defined in Read AC Characteristics table.
2. tWHQ7V is the Program or Erase time.
3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%.
20/31
M29F040
Table 15B. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)
M29F040
-120
150
Unit
Symbol
Parameter
VCC = 5V 10%
VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
(2)
tWHQ7V1
tWHQ7V2
tEHQ7V1
tEHQ7V2
10
10
s
µ
Write Enable High to DQ7 Valid
(Block Erase, W Controlled)
(2)
(2)
(2)
1.0
10
30
1.0
10
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
s
µ
Chip Enable High to DQ7 Valid
(Block Erase, E Controlled)
1.0
30
50
1.0
30
55
sec
ns
tQ7VQV
tWHQV1
Q7 Valid to Output Valid (Data Polling)
Write Enable High to Output Valid
(Program)
10
1.0
10
10
1.0
10
s
µ
Write Enable High to Output Valid
(Block Erase)
tWHQV2
tEHQV1
tEHQV2
30
30
30
30
sec
Chip Enable High to Output Valid
(Program)
s
µ
Chip Enable High to Output Valid
(Block Erase)
1.0
1.0
sec
Notes: 1. All other timings are defined in Read AC Characteristics table.
2. tWHQ7V is the Program or Erase time.
21/31
M29F040
Figure 9. Data Polling DQ7 AC Waveforms
22/31
M29F040
Figure 10. Data Polling Flowchart
Figure 11. Data Toggle Flowchart
START
START
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ6
NO
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ7
READ DQ6
DQ6
NO
TOGGLE
DQ7
=
DATA
YES
=
YES
FAIL
NO
PASS
FAIL
PASS
AI01370
AI01369
Table 16. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%)
M29F040
Parameter
Unit
Min
Typ
6
Max
30
Chip Program (Byte)
Chip Erase (Preprogrammed)
Chip Erase
sec
sec
sec
sec
sec
2.5
8.5
1
Block Erase (Preprogrammed)
Block Erase
30
1.5
Byte Program
10
1500
s
µ
Program/Erase Cycles (per Block)
100,000
cycles
23/31
M29F040
Figure 12. Data Toggle DQ6 AC Waveforms
24/31
M29F040
Figure 13. Block Protection Flowchart
START
BLOCK ADDRESS
on A16, A17, A18
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
G = V
IH
Wait 4µs
READ DQ0 at PROTECTION
ADDRESS: A0, A6 = V , A1 = V and
IL
IH
A16, A17, A18 DEFINING BLOCK
NO
DQ0
= 1
YES
A9 = V
IH
++n
NO
= 25
PASS
YES
A9 = V
IH
FAIL
AI01368D
25/31
M29F040
Figure 14. Block Unprotecting Flowchart
START
PROTECT
ALL BLOCKS
n = 0
A6, A12, A16 = V
IH
E, G, A9 = V
IH
Wait 4µs
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
Wait 4µs
READ at UNPROTECTION
ADDRESS: A1, A6 = V , A0 = V and
A16, A17, A18 DEFINING BLOCK
(see Note 1)
IH
IL
INCREMENT
BLOCK
NO
YES
DATA
=
00h
NO
++n
LAST
NO
= 1000
SECT.
YES
FAIL
YES
PASS
AI01371E
Note: 1. A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status
reads, A6 must be kept at VIL.
26/31
M29F040
ORDERING INFORMATION SCHEME
Example:
M29F040
-70
X
N
1
TR
Operating Voltage
Option
Reverse Pinout
F
5V
R
TR Tape & Reel
Packing
Speed
Power Supplies
blank VCC 10%
Package
Temp. Range
-70
-90
70ns
K
N
PLCC32
1
3
5
6
0 to 70 C
°
±
90ns
X
VCC 5%
TSOP32
8 x 20mm
–40 to 125 C
°
±
-120
-150
120ns
150ns
–20 to 85 C
°
–40 to 85 C
°
M29F040 is replaced by the new version M29F040B
Device are shipped from the factory with the memory content erased (to FFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
27/31
M29F040
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
–
inches
Min
Symb
Typ
Max
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.100
0.060
–
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
28/31
M29F040
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
8.10
-
Typ
Max
0.047
0.007
0.041
0.011
0.008
0.795
0.728
0.319
-
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
-
0.002
0.037
0.006
0.004
0.780
0.720
0.311
-
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
29/31
M29F040
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.17
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-b
A1
α
L
Drawing is not to scale.
30/31
M29F040
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
31/31
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