M29F100B-T45N1T [STMICROELECTRONICS]
1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory; 1兆位128KB ×8或64Kb的X16 ，引导块单电源闪存
| 型号： | M29F100B-T45N1T |
| 厂家： | 
ST |
| 描述： | 1 Mbit 128Kb x8 or 64Kb x16, Boot Block Single Supply Flash Memory |
| 文件： | 总22页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29F100BT
M29F100BB
1 Mbit (128Kb x8 or 64Kb x16, Boot Block)
Single Supply Flash Memory
■ SINGLE 5V±10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 45ns
■ PROGRAMMING TIME
– 8µs per Byte/Word typical
44
■ 5 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 2 Main Blocks
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
1
TSOP48 (N)
12 x 20mm
SO44 (M)
Figure 1. Logic Diagram
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
V
CC
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
16
15
MODE
A0-A15
DQ0-DQ14
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
W
DQ15A–1
BYTE
RB
■ 100,000 PROGRAM/ERASE CYCLES per
M29F100BT
M29F100BB
E
G
BLOCK
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
RP
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29F100BT: 00D0h
– Bottom Device Code M29F100BB: 00D1h
V
SS
AI02916
July 2000
1/22
M29F100BT, M29F100BB
Figure 2. TSOP Connections
Figure 3. SO Connections
A15
A14
A13
A12
A11
A10
A9
1
48
NC
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
BYTE
2
W
V
SS
3
A8
DQ15A–1
DQ7
4
A9
5
A10
A11
A12
A13
A14
A15
NC
DQ14
DQ6
6
7
A8
DQ13
DQ5
8
NC
NC
W
9
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
21
22
M29F100BT
M29F100BB
RP
NC
NC
RB
NC
NC
A7
12
13
37
36
V
M29F100BT
M29F100BB
CC
BYTE
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
V
SS
DQ15A–1
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
A6
DQ2
A5
DQ10
DQ3
DQ12
DQ4
A4
A3
V
E
SS
DQ11
V
CC
A2
AI02918
A1
24
25
A0
AI02917
Table 1. Signal Names
SUMMARY DESCRIPTION
The M29F100B is a 1 Mbit (128Kbx8 or 64Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single 5V supply. On power-up the
memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM. The
M29F100B is fully backward compatible with the
M29F100.
A0-A15
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
RB
BYTE
V
CC
V
Ground
SS
NC
Not Connected Internally
2/22
M29F100BT, M29F100BB
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
Ambient Operating Temperature (Temperature Range Option 1)
Ambient Operating Temperature (Temperature Range Option 6)
Ambient Operating Temperature (Temperature Range Option 3)
Temperature Under Bias
0 to 70
T
–40 to 85
–40 to 125
–50 to 125
–65 to 150
°C
A
°C
T
°C
BIAS
T
STG
Storage Temperature
°C
(2)
Input or Output Voltage
–0.6 to 6
V
V
IO
V
Supply Voltage
–0.6 to 6
V
V
CC
V
Identification Voltage
–0.6 to 13.5
ID
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
The blocks in the memory are asymmetrically ar-
ranged, seeTables 3 and 4, Block Addresses.The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be
used for small initialization code to start the micro-
processor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
Table 3. Top Boot Block Addresses
M29F100BT
Table 4. Bottom Boot Block Addresses
M29F100BB
Size
(Kbyte
s)
Size
(Kbyte
s)
Address Range Address Range
Address Range Address Range
#
#
(x8)
(x16)
(x8)
(x16)
4
3
2
1
0
16
8
1C000h-1FFFFh
1A000h-1BFFFh
18000h-19FFFh
10000h-17FFFh
00000h-0FFFFh
E000h-FFFFh
D000h-DFFFh
C000h-CFFFh
8000h-BFFFh
0000h-7FFFh
4
3
2
1
0
64
32
8
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
8000h-FFFFh
4000h-7FFFh
3000h-3FFFh
2000h-2FFFh
0000h-1FFFh
8
32
64
8
16
3/22
M29F100BT, M29F100BB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V will temporarily unprotect the
ID
Address Inputs (A0-A15). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
is High, V . When BYTE is Low, V , these pins
IH
IL
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
During Program or Erase operations Ready/Busy
is Low, V . Ready/Busy will remain Low during
OL
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
Data Input/Output or Address Input (DQ15A-1).
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
When BYTE is High, V , this pin behaves as a
IH
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V , this pin behaves as an address
IL
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Se-
lect is Low, V , the memory is in 8-bit mode, when
IL
it is High, V , the memory is in 16-bit mode.
IH
V
CC
Supply Voltage. The V
Supply Voltage
CC
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
High, V , all other pins are ignored.
IH
Supply Voltage is less than the Lockout Voltage,
V . Thisprevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all Blocks that have been pro-
tected.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CC
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
A Hardware Reset is achieved by holding Reset/
erase operations, I
.
CC4
Block Temporary Unprotect Low, V , for at least
IL
Vss Ground. The V
Ground is the reference
SS
t
. After Reset/Block Temporary Unprotect
PLPX
for all voltage measurements.
goes High, V , the memory will be ready for Bus
Read and Bus Write operations after t
IH
or
PHEL
4/22
M29F100BT, M29F100BB
BUS OPERATIONS
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. OutputEn-
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V , to Chip Enable
and Output Enable and keeping Write Enable
able must remain High, V , during the whole Bus
IH
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing require-
ments.
IL
Output Disable. The Data Inputs/Outputs are in
High, V . The Data Inputs/Outputs will output the
IH
the high impedance state when Output Enable is
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
High, V .
IH
Table 5. Bus Operations, BYTE = V
IL
Data Inputs/Outpu ts
Address Inputs
DQ15A–1, A0-A15
Operation
Bus Read
E
G
W
DQ14-DQ8
DQ7-DQ0
Data Output
Data Input
Hi-Z
V
V
V
IH
Cell Address
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IL
IL
IL
IH
IH
V
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
IH
V
X
X
X
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
V
V
Hi-Z
Hi-Z
20h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
D0h (M29F100BT)
D1h (M29F100BB)
IH
IL
ID
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
Table 6. Bus Operations, BYTE = V
IH
Address Inputs
A0-A15
Data Inputs/Outpu ts
Operation
Bus Read
E
G
W
DQ15A–1, DQ14-DQ0
Data Output
Data Input
Hi-Z
V
V
V
Cell Address
IL
IL
IL
IH
IH
IH
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
V
X
X
IH
V
X
X
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
V
V
0020h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
00D0h (M29F100BT)
00D1h (M29F100BB)
IH
IL
ID
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
5/22
M29F100BT, M29F100BB
Standby. When Chip Enable is High, V , the
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
IH
Data Inputs/Outputs pins are placed in the high-
impedance state and the Supply Current is re-
duced to the Standby level.
When Chip Enable is at V the Supply Current is
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 7, or 8, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
IH
reduced to the TTL Standby Supply Current, I
.
CC2
To further reduce the Supply Current to the CMOS
Standby Supply Current, I , Chip Enable should
CC3
be held within V
± 0.2V. For Standby current
CC
levels see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC4
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
are usedto drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
If the Read/Reset command is issued during a
Block Erase operation or following a Programming
or Erase error then the memory will take upto 10µs
to abort. During the abort period no valid data can
be read from the memory. Issuing a Read/Reset
command during a Block Erase operation will
leave invalid data in the memory.
duced to the CMOS Standby Supply Current, I
.
CC3
The Data Inputs/Outputs will still output data if a
Bus Read operation is in progress.
Special Bus Operations
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com-
mand is issued.
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits
IL
IL
may be set to either V or V . The Manufacturer
IL
IH
Block Protection and Blocks Unprotection. Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed.
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V . The
IL
IH
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
Device Code for the M29F100BT is 00D0h and for
the M29F100BB is 00D1h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V ,
IL
A1 = V , and A12-A15 specifying the address of
IH
the block. The other address bits may be set to ei-
ther V or V . If the addressed block is protect-
IL
IH
COMMAND INTERFACE
ed then 01h is output on Data Inputs/Outputs
DQ0-DQ7, otherwise 00h is output.
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
6/22
M29F100BT, M29F100BB
Table 7. Commands, 16-bit mode, BYTE = V
IH
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
555
555
555
555
2AA
2AA
2AA
2AA
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
555
555
555
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
555
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
1
1
X
X
Table 8. Commands, 8-bit mode, BYTE = V
IL
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
AAA
AAA
AAA
AAA
555
555
555
555
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
AAA
AAA
AAA
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
AAA
555
555
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
BA
10
30
Block Erase
6+ AAA
Erase Suspend
Erase Resume
1
1
X
X
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A15, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V
.
IH
IL
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until the Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
7/22
M29F100BT, M29F100BB
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 9. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entirechip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 9. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
8/22
M29F100BT, M29F100BB
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Oncethe Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 9. All Bus Read opera-
tions during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being is-
sued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased will output the Status Register. It
is also possible to enter the Auto Select mode: the
memory will behave as in the Auto Select mode on
all blocks until a Read/Reset command returns the
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Table 9. Program, Erase Times and Program, Erase Endurance Cycles
(T = 0 to 70°C, –40 to 85°C or –40 to 125°C)
A
Typical after
(1)
Parameter
Min
Max
Unit
Typ
(1)
100k W/E Cycles
Chip Erase (All bits in the memory set to ‘0’)
Chip Erase
0.6
0.6
1.3
0.6
8
sec
sec
1.3
0.6
8
6
4
Block Erase (64 Kbytes)
sec
Program (Byte or Word)
150
4.5
2.5
µs
Chip Program (Byte by Byte)
Chip Program (Word by Word)
1.2
0.6
1.2
0.6
sec
sec
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. T = 25°C, V = 5V.
A
CC
9/22
M29F100BT, M29F100BB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within ablock being erased
is accessed.
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so may
or may not set DQ5 at ‘1’. In both cases, a succes-
sive Bus Read operation will show the bit is still ‘0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
The bits in the Status Register are summarized in
Table 10, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
Table 10. Status Register Bits
Operation
Program
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
Note: Unspecified data bits should be ignored.
10/22
M29F100BT, M29F100BB
Figure 4. Data Polling Flowchart
Figure 5. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
YES
DATA
DQ6
=
NO
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
= 1
YES
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
TOGGLE
NO
FAIL
YES
PASS
FAIL
PASS
AI01370B
AI03598
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
within the blocks being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
11/22
M29F100BT, M29F100BB
Table 11. AC Measurement Conditions
Parameter
M29F100B
45
High Speed
30pF
70 / 90 / 120
Standard
AC Test Conditions
Load Capacitance (C )
100pF
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 10ns
0 to 3V
1.5V
≤ 10ns
0.45 to 2.4V
0.8V and 2.0V
Input and Output Timing Ref. Voltages
Figure 6. AC Testing Input Output Waveform
Figure 7. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
L
Standard
C
2.4V
2.0V
0.8V
0.45V
AI01275B
C
includes JIG capacitance
AI03027
L
Table 12. Capacitance
(T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Test Condition
Min
Max
6
Unit
pF
C
Input Capacitance
Output Capacitance
V
= 0V
= 0V
IN
IN
C
OUT
V
OUT
12
pF
Note: Sampled only, not 100% tested.
12/22
M29F100BT, M29F100BB
Table 13. DC Characteristics
(T = 0 to 70°C, –40 to 85°C or –40 to 125°C)
A
(2)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
Typ
I
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V
≤ V
CC
±1
µA
LO
OUT
E = V , G = V ,
IL
IH
I
Supply Current (Read)
6
20
1
mA
mA
µA
CC1
f = 6MHz
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC2
IH
E = V
±0.2V,
CC
I
30
100
CC3
RP = V ±0.2V
CC
Program/Erase
Controller active
(1)
Supply Current (Program/Erase)
20
mA
I
CC4
V
Input Low Voltage
–0.5
2
0.8
V
V
IL
V
V
V
+0.5
CC
Input High Voltage
IH
I
= 5.8mA
= –2.5mA
= –100µA
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
Identification Voltage
Identification Current
0.45
V
OL
OL
I
I
2.4
V
OH
V
OH
V
–0.4
V
CC
OH
V
11.5
12.5
100
V
ID
I
ID
A9 = V
µA
ID
Program/Erase Lockout Supply
Voltage
(1)
3.2
4.2
V
V
LKO
Note: 1. Sampled only, not 100% tested.
2. T = 25°C, V = 5V.
A
CC
13/22
M29F100BT, M29F100BB
Table 14. Read AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F100B
70 / 90 / 120
Symbol
Alt
Parameter
Test Condition
Unit
45
E = V ,
IL
t
t
Address Validto Next Address Valid
Address Valid to Output Valid
Min
45
70
70
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
45
AVQV
G = V
IL
Chip Enable Low to Output
Transition
(1)
t
G = V
Min
Max
Min
0
45
0
0
70
0
ns
ns
ns
t
LZ
IL
ELQX
t
G = V
E = V
Chip Enable Low to Output Valid
t
CE
IL
ELQV
Output Enable Low to Output
Transition
(1)
t
t
t
OLZ
IL
IL
GLQX
t
t
E = V
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Max
Max
25
15
30
20
ns
ns
GLQV
OE
(1)
(1)
t
G = V
HZ
DF
IL
IL
EHQZ
t
E = V
Output Enable High to Output Hi-Z
Max
Min
15
0
20
0
ns
ns
t
GHQZ
t
t
t
EHQX
Chip Enable, Output Enable or
Address Transition to Output
Transition
t
OH
GHQX
AXQX
t
t
ELBL
ELFL
Chip Enable to BYTE Low or High
Max
5
5
ns
t
t
ELBH
ELFH
t
t
BYTE Low to Output Hi-Z
BYTE High to Output Valid
Max
Max
15
30
20
30
ns
ns
BLQZ
FLQZ
t
t
FHQV
BHQV
Note: 1. Sampled only, not 100% tested.
Figure 8. Read Mode AC Waveforms
tAVAV
VALID
A0-A15/
A–1
tAVQV
tAXQX
tEHQX
E
tELQV
tELQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI02919
14/22
M29F100BT, M29F100BB
Table 15. Write AC Characteristics, Write Enable Controlled
(T = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
A
M29F100B
Unit
Symbol
Alt
Parameter
45
45
0
70 / 90 / 120
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
CS
ELWL
t
t
WP
40
25
0
45
30
0
WLWH
t
t
t
DS
DVWH
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
WHDX
DH
t
t
0
0
WHEH
WHWL
CH
t
t
WPH
20
0
20
0
t
t
AVWL
AS
t
t
40
0
45
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
WHGL
(1)
t
Program/Erase Valid to RB Low
Max
Min
30
50
30
50
ns
t
BUSY
WHRL
t
t
V
High to Chip Enable Low
CC
µs
VCHEL
VCS
Note: 1. Sampled only, not 100% tested.
Figure 9. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A15/
VALID
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI01980B
15/22
M29F100BT, M29F100BB
Table 16. Write AC Characteristics, Chip Enable Controlled
(T = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
A
M29F100B
70 / 90 / 120
Symbol
Alt
Parameter
Unit
45
45
0
t
t
WC
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
WS
WLEL
t
t
40
25
0
45
30
0
ELEH
CP
DS
t
t
t
t
DVEH
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
EHDX
DH
t
t
0
0
EHWH
WH
t
t
CPH
20
0
20
0
EHEL
t
t
AVEL
ELAX
AS
t
t
40
0
45
0
AH
t
t
GHEL
EHGL
t
0
0
OEH
(1)
t
Program/Erase Valid to RB Low
Max
Min
30
50
30
50
ns
t
BUSY
EHRL
t
t
V
High to Write Enable Low
CC
µs
VCHWL
VCS
Note: 1. Sampled only, not 100% tested.
Figure 10. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A15/
VALID
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI01981B
16/22
M29F100BT, M29F100BB
Table 17. Reset/Block Temporary Unprotect AC Characteristics
(T = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
A
M29F100B
Unit
Symbol
Alt
Parameter
45
70 / 90 / 120
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
t
t
RH
Min
Min
50
50
ns
ns
PHEL
(1)
t
PHGL
(1)
(1)
(1)
t
RHWL
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
t
0
0
t
RB
RP
RHEL
t
RHGL
t
t
RP Pulse Width
Min
Max
Min
500
10
500
10
ns
µs
ns
PLPX
(1)
t
RP Low to Read Mode
t
READY
PLYH
(1)
t
RP Rise Time to V
500
500
t
VIDR
ID
PHPHH
Note: 1. Sampled only, not 100% tested.
Figure 11. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI02931
17/22
M29F100BT, M29F100BB
Table 18. Ordering Information Scheme
Example:
M29F100BB
55
N
1
T
Device Type
M29
Operating Voltage
F = V = 5V ± 10%
CC
Device Function
100B = 1 Mbit (128Kb x8 or 64Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45 ns
70 = 70 ns
90 = 90 ns
120 = 120 ns
Package
N = TSOP48: 12 x 20 mm
M = SO44
Temperature Range
1 = 0 to 70 °C
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
18/22
M29F100BT, M29F100BB
Table 19. Revision History
Date
Revision Details
July 1999
First Issue
New document template
Document type: from Preliminary Data to Data Sheet
Chip Erase Max. specification added (Table 9)
Block Erase Max. specification added (Table9)
Program Max. specification added (Table 9)
Chip Program Max. specification added (Table 9)
07/28/00
I
and I
Typ. specification added (Table13)
CC1
CC3
I
Test Condition change (Table 13)
CC3
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
Data Toggle Flowchart diagram change (Figure 5)
19/22
M29F100BT, M29F100BB
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
–
A
A1
A2
B
0.100
1.000
0.050
0.950
0.170
0.100
19.800
18.300
–
0.0039
0.0394
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
–
C
D
D1
e
0.500
0.0197
E
11.900
0.500
0°
12.100
0.700
5°
0.4685
0.0197
0°
0.4764
0.0276
5°
L
α
N
48
48
CP
0.100
0.0039
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
20/22
M29F100BT, M29F100BB
Table 21. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
2.620
0.242
2.350
0.500
0.250
28.300
–
Typ
Max
0.1031
0.0095
0.0925
0.0197
0.0098
1.1142
–
A
A1
A2
B
2.420
0.0953
0.0087
0.0886
0.220
2.250
C
0.100
28.100
–
0.0039
1.1063
–
D
e
1.270
0.0500
E
13.200
15.900
–
13.400
16.100
–
0.5197
0.6260
–
0.5276
0.6339
–
H
L
0.800
0.0315
α
3°
–
–
3°
–
–
N
44
44
CP
0.100
0.0039
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
21/22
M29F100BT, M29F100BB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
22/22
相关型号：
©2020 ICPDF网 联系我们和版权申明