M29F400B-120N3RTR [STMICROELECTRONICS]
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| 型号： | M29F400B-120N3RTR |
| 厂家： | 
ST |
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M29F400T
M29F400B
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
Single Supply Flash Memory
NOT FOR NEW DESIGN
M29F400T and M29F400B are replaced
respectively by the M29F400BT and
M29F400BB
5V±10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READOPERATIONS
FAST ACCESS TIME: 55ns
44
FAST PROGRAMMING TIME
– 10µs by Byte / 16µs by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
1
TSOP48 (N)
12 x 20 mm
SO44 (M)
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
Figure 1. Logic Diagram
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
V
CC
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
18
15
A0-A17
DQ0-DQ14
– Manufacturer Code: 0020h
– Device Code, M29F400T: 00D5h
– Device Code, M29F400B: 00D6h
W
E
DQ15A–1
BYTE
RB
M29F400T
M29F400B
G
DESCRIPTION
RP
The M29F400 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or Word-
by-Word basis using only a single 5V VCC supply.
For Program and Erase operations the necessary
high voltages are generated internally. The device
can also be programmed in standard program-
mers.
V
SS
AI01726B
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
November 1999
1/34
This is information on a productstil l in production but not recommendedfor new designs.
M29F400T, M29F400B
Figure 2A. TSOP Pin Connections
Figure 2B. TSOP Reverse Pin Connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
A16
1
48
A15
A14
A13
A12
A11
A10
A9
BYTE
BYTE
V
V
SS
SS
DQ15A–1
DQ15A–1
DQ7
DQ7
DQ14
DQ6
DQ14
DQ6
A8
DQ13
DQ5
DQ13
DQ5
A8
NC
NC
W
NC
NC
W
DQ12
DQ4
DQ12
DQ4
M29F400T
M29F400B
(Normal)
M29F400T
M29F400B
(Reverse)
RP
NC
NC
RB
NC
A17
A7
12
13
37
36
V
V
12
13
37
36
RP
NC
NC
RB
NC
A17
A7
CC
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
A6
A6
A5
A5
A4
A4
A3
V
E
V
A3
SS
SS
E
A2
A2
A1
24
25
A0
A0
24
25
A1
AI01727B
AI01728B
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. SO Pin Connections
Table 1. Signal Names
A0-A17
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
Address Inputs
NC
RB
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP
Data Input/Outputs, Command Inputs
Data Input/Outputs
2
W
3
A8
4
A9
5
A10
A11
A12
A13
A14
A15
A16
BYTE
Data Input/Output or Address Input
Chip Enable
6
7
8
9
G
Output Enable
10
11
12
13
14
15
16
17
18
19
20
21
22
M29F400T
M29F400B
W
Write Enable
V
V
RP
Reset / Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organisation
Supply Voltage
SS
G
SS
DQ15A–1
DQ0
DQ8
DQ7
RB
DQ14
DQ6
BYTE
VCC
DQ1
DQ9
DQ13
DQ5
DQ2
DQ10
DQ3
DQ12
DQ4
VSS
Ground
DQ11
V
CC
AI01729B
Warning: NC = Not Connected.
2/34
M29F400T, M29F400B
(1)
Table 2. Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature(3)
Temperature Under Bias
Storage Temperature
Value
Unit
–40 to 125
–50 to 125
–65 to 150
–0.6 to 7
C
°
TBIAS
C
°
TSTG
°C
V
(2)
VIO
Input or Output Voltages
Supply Voltage
VCC
–0.6 to 7
V
(2)
V(A9, E, G, RP)
A9, E, G, RP Voltage
–0.6 to 13.5
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
DESCRIPTION (Cont’d)
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application.
Memory Blocks
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status,Programming, Blockand Chip Erase,Erase
Suspend and Resume are written to the device in
cyclesof commandsto a CommandInterfaceusing
standard microprocessor write timings.
The devices feature asymmetrically blocked archi-
tectureproviding system memory integration. Both
M29F400T and M29F400B devices have an array
of 11 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and seven Main Blocksof 64 KBytesor 32
KWords. The M29F400T has the Boot Blockat the
top of the memory address space and the
M29F400B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3. Each block can be erased separately, any com-
bination of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed.
The device is offered in TSOP48 (12 x 20mm) and
SO44 packages. Both normal and reverse pinouts
are available for the TSOP48 package.
Organisation
The M29F400 is organisedas512Kx8 or 256Kx16
bits selectable by the BYTE signal. When BYTEis
Low the Byte-wide x8 organisation is selected and
the address lines are DQ15A–1 and A0-A17. The
Data Input/Output signal DQ15A–1 acts as ad-
dress line A–1 which selects the lower or upper
Byte of the memory word for output on DQ0-DQ7,
DQ8-DQ14 remain at High impedance. When
BYTEis High the memoryuses the address inputs
A0-A17 and the Data Input/Outputs DQ0-DQ15.
Memory control is provided by Chip Enable E,
Output Enable G and Write Enable W inputs.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
AReset/Block TemporaryUnprotection RPtri-level
input provides a hardware reset when pulled Low,
andwhenheld High(at VID) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
tection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
3/34
M29F400T, M29F400B
Figure 3. Memory Map and Block Address Table (x8)
M29F400T
7FFFFh
M29F400B
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
32K MAIN BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
16K BOOT BLOCK
7FFFFh
16K BOOT BLOCK
7C000h
7BFFFh
70000h
6FFFFh
8K PARAMETER BLOCK
7A000h
79FFFh
60000h
5FFFFh
8K PARAMETER BLOCK
78000h
77FFFh
50000h
4FFFFh
32K MAIN BLOCK
70000h
6FFFFh
40000h
3FFFFh
64K MAIN BLOCK
60000h
5FFFFh
30000h
2FFFFh
64K MAIN BLOCK
50000h
4FFFFh
20000h
1FFFFh
64K MAIN BLOCK
40000h
3FFFFh
10000h
0FFFFh
64K MAIN BLOCK
30000h
2FFFFh
08000h
07FFFh
64K MAIN BLOCK
06000h
05FFFh
20000h
1FFFFh
64K MAIN BLOCK
10000h
0FFFFh
04000h
03FFFh
64K MAIN BLOCK
00000h
00000h
AI01730
Command Interface
any time, duringprogramming or erase, to monitor
the progress of the operation.
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles.The first,second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
CommandInterface whichis common to all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to giveadditional data protection, the instruc-
tions for Program and Block or Chip Erase require
furthercommand inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
blockmay be suspended, inorderto read datafrom
another block or to program data in another block,
and then resumed.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to readthe ElectronicSignature
or BlockProtection Status), Program, BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations. The Status Register Data Polling, Tog-
gle, Error bits and the RB output may be read at
When power is first applied or if VCC falls below
VLKO, the command interface is reset to Read
Array.
4/34
M29F400T, M29F400B
Table 3A. M29F400T Block Address Table
Address Range (x8)
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-77FFFh
78000h-79FFFh
7A000h-7BFFFh
7C000h-7FFFFh
Address Range (x16)
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3BFFFh
3C000h-3CFFFh
3D000h-3DFFFh
3E000h-3FFFFh
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
0
A13
X
A12
X
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
X
Table 3B. M29F400B Block Address Table
Address Range (x8)
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
Address Range (x16)
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
X
X
0
0
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
5/34
M29F400T, M29F400B
SIGNAL DESCRIPTIONS
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
See Figure 1 and Table 1.
Write Enable (W). This input controls writing to the
Address Inputs (A0-A17). The address inputs for
the memory arrayare latchedduring a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. In Word-wide organisation the address
lines are A0-A17, in Byte-wide organisation
DQ15A–1 acts as an additional LSB address line.
When A9 is raised to VID, either a Read Electronic
Signature Manufacturer or Device Code, Block
Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
CommandRegisterand Addressand Datalatches.
Byte/Word Organization Select (BYTE). The
BYTE input selects the output configuration for the
device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTE is Low, the Byte-wide mode is
selected and the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
Data Input/Outputs (DQ0-DQ7). These In-
puts/Outputs are used in the Byte-wide and Word-
wide organisations. The input is data to be
programmed in the memory array or a command
to be written to the C.I. Both are latched on the
rising edge of Chip Enable E or Write Enable W.
The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsare disabled and when RP isata Lowlevel.
Ready/Busy Output (RB). Ready/Busy is an
open-drainoutput andgivesthe internal state of the
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructions except the Erase Suspend instruction.
WhenRB isHigh, the device is readyfor anyRead,
Program or Erase operation. The RB will also be
High when the memory is put in EraseSuspend or
Standby modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
VIL for at least 500ns. When the reset pulse is
given, if the memory is in Read or Standby modes,
it will be available for new operations in 50ns after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take 10µs during which the RB signal will be held
at VIL. Theend ofthe memoryreset willbe indicated
by the rising edge of RB. A hardware reset during
an Eraseor Program operationwill corruptthe data
being programmed or the sector(s) being erased.
Data Input/Outputs (DQ8-DQ14 and DQ15A–1).
These Inputs/Outputs are additionally used in the
Word-wide organisation. When BYTEis High DQ8-
DQ14 and DQ15A–1 act as the MSB of the Data
Input or Output, functioning as described for DQ0-
DQ7 above, and DQ8-DQ15 are ’don’t care’ for
command inputs or status outputs. When BYTE is
Low, DQ8-DQ14 are high impedance, DQ15A–1 is
the Address A–1 input.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers. E Highdeselects thememory
andreducesthe powerconsumption to thestandby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The ChipEnable must be
forced to VID during the Block Unprotection opera-
tion.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slower than 500ns.
When RP is returned from VID to VIH all blocks
temporarily unprotected will be again protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
VSS Ground. VSS is the reference for all voltage
measurements.
6/34
M29F400T, M29F400B
DEVICE OPERATIONS
at High impedance; if the Word-wide configuration
is selected the codes are output on DQ0-DQ7 with
DQ8-DQ15 at 00h.
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Block Protection. Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
eraseoperations. Thismode isactivatedwhenboth
A9 and G are raised to VID and an address in the
block is applied on A12-A17. The Block Protection
algorithm is shownin Figure 14. Blockprotection is
initiated on the edge of W fallingto VIL. Then after
a delay of 100µs, the edge of W rising to VIH ends
the protection operations. Blockprotection verify is
achieved by bringing G, E, A0 and A6to VIL and A1
to VIH, whileW isat VIH and A9 at VID. Under these
conditions, reading the data output will yield 01h if
the block defined by the inputs on A12-A17 is
protected. Any attempt to program or erase a pro-
tected block will be ignored by the device.
Write. Write operations are used to giveInstruction
Commands to the memory or to latch input data to
be programmed. Awrite operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the fallingedge of W or E whichever occurs last.
Commands andInputDataare latchedon the rising
edge of W or E whichever occurs first.
OutputDisable. The data outputs are high imped-
ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
orderto change storeddata.The temporary unpro-
tection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by
executingthe Erase or Program instruction with the
RP signal held at VID. When RP isreturned to VIH,
all the previously protected blocks are again pro-
tected.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to theCMOS
standby value, while outputs still drive the bus.
Electronic Signature. Two codes identifying the
manufacturer andthe device can be read fromthe
memory. The manufacturer’s code for STMi-
croelectronics is 20h,the devicecode is D5hfor the
M29F400T (Top Boot) and D6h for the M29F400B
(Bottom Boot). These codes allow programming
equipment or applications to automatically match
their interface to the characteristics of the
M29F400. The Electronic Signature is output by a
Read operation when the voltage applied to A9 is
at VID and address inputsA1 is Low. The manufac-
turer code is output when the Address input A0 is
Low and the device code when this input is High.
Other Address inputs are ignored. The codes are
output on DQ0-DQ7.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. The Block Unprotection
algorithm is shown in Figure 15. Unprotection is
initiatedby the edge of Wfallingto VIL. Aftera delay
of 10ms, the unprotection operation will end. Un-
protection verify is achievedby bringing G and E to
VIL while A0 is at VIL, A6 and A1 are at VIH and A9
remains at VID. In these conditions, reading the
output data will yield 00h if the blockdefined by the
inputs A12-A17 has been succesfully unprotected.
Each block mustbe separately verified by giving its
address in order to ensure that it has been unpro-
tected.
The Electronic Signature can also be read, without
raisingA9 to VID, by giving the memory the Instruc-
tion AS. If the Byte-wide configuration is selected
the codes are output onDQ0-DQ7with DQ8-DQ14
7/34
M29F400T, M29F400B
(1)
Table 4. User Bus Operations
DQ15
A–1
DQ8-
DQ14
Operation
Read Word
Read Byte
Write Word
Write Byte
E
G
W
RP
BYTE
VIH
A0
A0
A0
A0
A0
A1
A1
A1
A1
A1
A6
A6
A6
A6
A6
A9
A9
A9
A9
A9
A12 A15
A12 A15
A12 A15
DQ0-DQ7
Data
Output
Data
Output
Data
Output
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIH
VIH
Address
Input
Data
Output
VIL
Hi-Z
Data
Input
VIH
A12 A15 Data Input Data Input
Address
Data
Input
VIL
A12 A15
Hi-Z
Input
Hi-Z
Hi-Z
Hi-Z
Output Disable
Standby
VIL
VIH
X
VIH
X
VIH
X
VIH
VIH
VIL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Reset
X
X
Block
VIL
VID
VID VIL Pulse VIH
VID VIL Pulse VIH
X
X
X
X
X
X
X
X
VID
VID
X
X
X
X
X
X
X
X
Protection(2,4)
Blocks
VIH
VIH
Unprotection(4)
Block
Block
Protect
Status (3)
VIL
VIL
X
VIL
VIL
X
VIH
VIH
X
VIH
VIH
VID
X
X
X
VIL
VIL
X
VIH
VIH
X
VIL
VIH
X
VID
VID
X
A12 A15
A12 A15
X
X
X
X
X
X
Protection
Verify(2,4)
Block
Block
Protect
Status (3)
Unprotection
Verify(2,4)
Block
Temporary
Unprotection
X
X
X
Notes: 1. X = VIL or VIH
2. Block Address must be given on A12-A17bits.
3. See Table 6.
4. Operation performed on programming equipment.
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
Other
Addresses
DQ15 DQ8 -
DQ0 -
DQ7
Org.
Code
Device
E
G
W
BYTE
A0
A1
A–1
DQ14
Manufact.
Code
VIL
VIL
VIH
VIH
VIL
VIL
Don’t Care
0
00h
20h
Word-
wide
M29F400T VIL
M29F400B VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
Don’t Care
Don’t Care
0
0
00h
00h
D5h
D6h
Device
Code
Manufact.
Code
Don’t
Care
VIL
M29F400T VIL
M29F400B VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIL
Don’t Care
Don’t Care
Don’t Care
Hi-Z
Hi-Z
Hi-Z
20h
D5h
D6h
Byte-
wide
Don’t
Care
Device
Code
Don’t
Care
Table 6. Read Block Protection with AS Instruction
Other
Code
E
G
W
A0
A1
A12 - A17
DQ0 - DQ7
Addresses
Don’t Care
Don’t Care
Protected Block
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
Block Address
Block Address
01h
00h
Unprotected Block
8/34
M29F400T, M29F400B
INSTRUCTIONS AND COMMANDS
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
onablockbeing erasedand thedata valueonother
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Erasing
operations are in progress, successive attempts to
readDQ6will output complementary data. DQ6 will
toggle following toggling of either G, or E when G
is low. The operation is completed when two suc-
cessivereads yieldthe sameoutput data.The next
readwill outputthe bitlastprogrammed or a ’1’ after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100µs and then
returnback to Read. DQ6 will be setto ’1’ if a Read
operation is attempted onan EraseSuspend block.
When erase is suspended DQ6 will toggle during
programming operations in a block different to the
block in Erase Suspend. Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structionsrequire from 1 to 6 cycles,the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirmthe first command or
execute the commandimmediately. Command se-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cles which unlock the Command Interface. In addi-
tion, for Erase, instruction confirmation is again
preceded by the two Coded cycles.
Status Register Bits
P/E.C.status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand executionwill automatically output thesefive
Status Register bits. The P/E.C. automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Table 7. Commands
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100µs, and then return to the
previous addressed memory data value. See Fig-
ure 11 for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
Hex Code
00h
Command
Invalid/Reserved
10h
Chip Erase Confirm
Reserved
20h
30h
Block Erase Resume/Confirm
Set-up Erase
80h
Read Electronic Signature/
Block Protection Status
90h
A0h
B0h
F0h
Program
Erase Suspend
Read Array/Reset
9/34
M29F400T, M29F400B
Table 8. Instructions (1)
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr. (3,7)
Data
X
1+
Read Memory Array until a new write cycle is initiated.
F0h
Read/Reset
Memory Array
RD (2,4)
Byte
AAAAh
5555h
AAh
5555h
2AAAh
55h
AAAAh
5555h
F0h
Addr. (3,7)
Read Memory Array until a new write cycle
is initiated.
3+
3+
Word
Data
Byte
AAAAh
5555h
AAh
5555h
2AAAh
55h
AAAAh
5555h
90h
Addr. (3,7)
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
AS (4)
Auto Select
Program
Word
Data
Byte
AAAAh
5555h
5555h
2AAAh
AAAAh
5555h
Program
Address
Addr. (3,7)
Read Data Polling or Toggle Bit
until Program completes.
PG
4
Word
Program
Data
Data
AAh
55h
A0h
Byte
AAAAh
5555h
AAh
AAAAh
5555h
AAh
X
5555h
2AAAh
55h
AAAAh
5555h
80h
AAAAh
5555h
AAh
5555h
2AAAh
55h
Block
Additional
Addr. (3,7)
Address Block (8)
BE
CE
Block Erase
Chip Erase
6
6
Word
Data
30h
AAAAh
5555h
10h
30h
Byte
5555h
2AAAh
55h
AAAAh
5555h
80h
AAAAh
5555h
AAh
5555h
2AAAh
55h
Addr. (3,7)
Note 9
Word
Data
Addr. (3,7)
Data
Erase
Suspend
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
ES (10)
1
1
B0h
Addr. (3,7)
Data
X
Erase
Resume
Read Data Polling or Toggle Bits until Erase completes or Erase is
suspended another time
ER
30h
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH andA1 at VIL will output
Device code.
6. Block Protection Address:A0 atVIL, A1 at VIH and A12-A17 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A17 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,
timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).
When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
10/34
M29F400T, M29F400B
Table 9. Status Register Bits
DQ
Name
Logic Level
Definition
Note
Erase Complete or erase
block in Erase Suspend
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Erase On-going
Data
Polling
7
Program Complete or data
of non erase block during
Erase Suspend
DQ
DQ
Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
DQ
Program Complete
6
Toggle Bit
Erase Complete or Erase
’-1-1-1-1-1-1-1-’ Suspend on currently
acknowledged.
addressed block
’1’
’0’
Program or Erase Error
This bit is set to ’1’ in the case of
Programming or Erase failure.
5
4
Error Bit
Program or Erase On-going
Reserved
P/E.C. Erase operation has started. Only
Erase Timeout Period Expired possible command entry is Erase Suspend
(ES).
’1’
’0’
Erase
Time Bit
3
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ’1’).
’-1-0-1-0-1-0-1-’
Indicates the erase status and allows to
identify the erased block
2
Toggle Bit
Program on-going, Erase
on-going on another block or
Erase Complete
1
Erase Suspend read on
non Erase Suspend block
DQ
1
0
Reserved
Reserved
Note:
Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
11/34
M29F400T, M29F400B
Table 10. Polling and Toggle Bits
the Word-wide configuration during the first cycle.
During the second cycle the Coded cycles consist
of writing the data 55h at address 5555h in the
Byte-wide configuration and at address 2AAAh in
the Word-wide configuration. In the Byte-widecon-
figuration the address lines A–1 to A14 are valid, in
Word-wide A0 to A14 are valid, other address lines
are ’don’t care’. The Coded cycles happen on first
and second cycles of the command write or on the
fourth and fifth cycles.
Mode
DQ7
DQ7
0
DQ6
DQ2
Program
Erase
Toggle
1
Toggle Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
Instructions
DQ7
DQ7
DQ6
DQ2
N/A
See Table 8.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
commandF0h. It can be optionally preceded by the
two Codedcycles.Subsequent read operationswill
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Erase Suspend Program
Toggle
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can alsobe used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and whenerase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configuration for command set-up.
A subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code, 20h, is output when the ad-
dresses lines A0 and A1 are Low, the device code,
D5h for Top Boot, D6h for Bottom Boot is output
when A0 is High with A1 Low.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memoryblock. In case of anerrorin blockerase
or program, the blockin whichthe error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pear if a usertries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
stillbeused. Theerror bit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
The AS instruction also allows access to the block
protectionstatus. After givingthe ASinstruction, A0
is set to VIL with A1 at VIH, while A12-A17 define
the address of the block to be verified. A read in
these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to address AAAAh in the
Byte-wide configuration or to address 5555h in the
Word-wide configuration on the thirdcycle after two
Coded cycles. A fourth write operation latches the
Addresson the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing’0’ in place of
’1’. Status bits DQ6and DQ7determineif program-
ming is on-goingand DQ5allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dress being programmed.
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
periodis finished, after 80µs to 120µs, DQ3returns
to ’1’.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address AAAAh in the
Byte-wide configuration and at address 5555h in
12/34
M29F400T, M29F400B
Table 11. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 10ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.45V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01275B
AI01276B
Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAAh
in the Byte-wide configuration or address 5555h in
the Word-wide configuration on third cycleafter the
two Coded cycles. The Block Erase Confirm com-
mand30h is similarly writtenon thesixthcycle after
another two Coded cycles. During the input of the
secondcommand an address withinthe blocktobe
erasedis given and latchedinto the memory. Addi-
tional block Erase Confirm commands and block
addresses can be written subsequently to erase
other blocks in parallel, without further Coded cy-
cles. The erase will start after the erase timeout
period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for
other blocks must be given within this delay. The
input of a newErase Confirm command will restart
the timeout period. The status of the internal timer
can be monitored through the level of DQ3, if DQ3
is ’0’ the Block Erase Command has been given
and the timeout is running, if DQ3 is’1’, the timeout
has expired and the P/E.C.is erasing the Block(s).
If the second command given is not an erase
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
status bits.
13/34
M29F400T, M29F400B
Table 13. DC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)
Symbol
ILI
Parameter
Test Condition
0V
Min
Max
Unit
Input Leakage Current
V
V
CC
1
A
A
≤
≤
±
±
µ
µ
IN
ILO
Output Leakage Current
0V
V
V
≤
CC
1
≤
OUT
ICC1
ICC1
ICC2
ICC3
Supply Current (Read) TTL Byte
Supply Current (Read) TTL Word
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
E = VIL, G = VIH, f = 6MHz
E = VIL, G = VIH, f = 6MHz
E = VIH
20
20
1
mA
mA
mA
E = VCC 0.2V
100
A
µ
±
Byte program, Block or
Chip Erase in progress
(1)
ICC4
Supply Current (Program or Erase)
20
mA
VIL
VIH
VOL
Input Low Voltage
–0.5
2
0.8
VCC + 0.5
0.45
V
V
V
V
V
V
Input High Voltage
Output Low Voltage
IOL = 5.8mA
Output High Voltage TTL
Output High Voltage CMOS
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
IOH = –2.5mA
2.4
VCC –0.4V
11.0
VOH
IOH = –100 A
µ
VID
IID
12.0
100
A9 = VID
A
µ
Supply Voltage (Erase and
Program lock-out)
VLKO
3.2
4.2
V
Note: 1. Sampled only, not 100% tested.
Duringthe executionof theeraseby theP/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
StatusRegisterbit DQ5returns’1’ ifthere has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in orderto
reset the P/E.C.
configuration on the third cycle after the two Coded
cycles. The Chip Erase Confirm command 10h is
similarly written on the sixth cycleafter another two
Coded cycles. If the second command given is not
an erase confirm or if the Codedcycles are wrong,
the instruction aborts and the device is reset to
ReadArray. It isnot necessaryto programthe array
with 00h first as theP/E.C.willautomatically do this
before erasing it to FFh. Read operations after the
sixth rising edge of W or E output the Status
Register bits. During the execution of the erase by
the P/E.C.,Data Polling bit DQ7 returns ’0’, then ’1’
on completion. The Toggle bits DQ2 and DQ6
toggle duringerase operation andstopwhen erase
is completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure.
ChipErase(CE)Instruction. This instructionuses
six write cycles. The Erase Set-up command 80h
is written to address AAAAh in the Byte-wide con-
figuration or the address 5555h in the Word-wide
14/34
M29F400T, M29F400B
Table 14A. Read AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-55
-70
Test
Condition
Symbol
Alt
Parameter
Unit
High Speed
Interface
Standard
Interface
Min
Max
Min
Max
E = VIL,
G = VIL
tAVAV
tRC
Address Valid to Next Address Valid
55
70
ns
ns
E = VIL,
G = VIL
tAVQV
tACC Address Valid to Output Valid
55
70
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
G = VIL
G = VIL
E = VIL
E = VIL
G = VIL
G = VIL
E = VIL
E = VIL
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tELQV
tCE
55
30
15
15
70
30
20
20
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
(2)
tGLQV
tOE
tOH
tHZ
tOH
tDF
Output Enable Low to Output Valid
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
tEHQX
(1)
tEHQZ
tGHQX
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
(1)
tGHQZ
E = VIL,
G = VIL
tAXQX
tOH
Address Transition to Output Transition
RP Low to Read Mode
0
0
ns
tRRB
tREADY
(1,3)
tPLYH
10
10
µs
tPHEL
tPLPX
tELBL
tELBH
tBLQZ
tBHQV
tRH
tRP
RP High to Chip Enable Low
RP Pulse Width
50
50
ns
ns
500
500
tELFL Chip Enable to BYTESwitching Low or
tELFH High
5
5
ns
ns
ns
BYTESwitching Low to Output
High Z
tFLQZ
15
30
20
30
BYTESwitching High to Output
tFHQV
Valid
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
.
15/34
M29F400T, M29F400B
Table 14B. Read AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-90
-120
Test
Condition
Symbol
Alt
Parameter
Unit
Standard
Interface
Standard
Interface
Min
Max
Min
Max
E = VIL,
G = VIL
tAVAV
tRC
Address Valid to Next Address Valid
90
120
ns
ns
E = VIL,
G = VIL
tAVQV
tACC Address Valid to Output Valid
90
120
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
G = VIL
G = VIL
E = VIL
E = VIL
G = VIL
G = VIL
E = VIL
E = VIL
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tELQV
tCE
90
35
20
20
120
50
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
(2)
tGLQV
tOE
tOH
tHZ
tOH
tDF
Output Enable Low to Output Valid
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
tEHQX
(1)
tEHQZ
30
tGHQX
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
(1)
tGHQZ
30
E = VIL,
G = VIL
tAXQX
tOH
Address Transition to Output Transition
RP Low to Read Mode
0
0
ns
tRRB
tREADY
(1,3)
tPLYH
10
10
µs
tPHEL
tPLPX
tELBL
tELBH
tBLQZ
tBHQV
tRH
tRP
RP High to Chip Enable Low
RP Pulse Width
50
50
ns
ns
500
500
tELFL Chip Enable to BYTESwitching Low or
tELFH High
5
5
ns
ns
ns
BYTESwitching Low to Output
High Z
tFLQZ
20
40
30
40
BYTESwitching High to Output
tFHQV
Valid
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
.
16/34
M29F400T, M29F400B
Figure 6. Read Mode AC Waveforms
17/34
M29F400T, M29F400B
Table 15A. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-55
-70
Symbol
Alt
Parameter
Unit
High Speed
Interface
Standard
Interface
Min
Max
Min
Max
tAVAV
tELWL
tWC
tCS
tWP
tDS
tDH
tCH
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
55
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
30
25
0
35
30
0
Write Enable High to Input Transition
Write Enable High to Chip Enable High
0
0
tWPH Write Enable High to Write Enable Low
20
0
20
0
tAS
tAH
Address Valid to Write Enable Low
tWLAX
tGHWL
tVCHEL
tWHGL
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
45
0
45
0
tVCS VCC High to Chip Enable Low
tOEH Write Enable High to Output Enable Low
tVIDR RP Rise Time to VID
50
0
50
0
(1,2)
tPHPHH
500
500
500
500
tPLPX
tRP
RP Pulse Width
(1)
tWHRL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
30
30
(1)
tPHWL
4
4
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Erase Suspend (ES) Instruction. The Block
Eraseoperation may be suspended by thisinstruc-
tion which consists of writing the command B0h
without any specific address. No Coded cycles are
required. It permits reading of data from another
block and programming in another block while an
erase operation is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution. Writing this command during Erase
timeout will, in addition to suspending the erase,
terminate the timeout. The Toggle bit DQ6 stops
togglingwhen the P/E.C.is suspended. The Toggle
bitswill stop togglingbetween0.1µs and 15µs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
18/34
M29F400T, M29F400B
Table 15B. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-90
-120
Symbol
Alt
Parameter
Unit
Standard
Interface
Standard
Interface
Min
Max
Min
Max
tAVAV
tELWL
tWC
tCS
tWP
tDS
tDH
tCH
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
90
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
45
45
0
50
50
0
Write Enable High to Input Transition
Write Enable High to Chip Enable High
0
0
tWPH Write Enable High to Write Enable Low
20
0
20
0
tAS
tAH
Address Valid to Write Enable Low
tWLAX
tGHWL
tVCHEL
tWHGL
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
45
0
50
0
tVCS VCC High to Chip Enable Low
tOEH Write Enable High to Output Enable Low
tVIDR RP Rise Time to VID
50
0
50
0
(1,2)
tPHPHH
500
500
500
500
tPLPX
tRP
RP Pulse Width
(1)
tWHRL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
35
50
(1)
tPHWL
4
4
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
pended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at ’1’. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
whenthe dataisbeingprogrammed. ARead/Reset
command will definitively abort erasure and result
in invalid data in the blocks being erased.
Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
19/34
M29F400T, M29F400B
Figure 7. Write AC Waveforms, W Controlled
tAVAV
VALID
A0-A17/
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI01869C
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
POWER SUPPLY
Power Up
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have theVCC rail decoupled with a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
The memoryCommand Interfaceis reseton power
up to Read Array. Either E or W must be tied to VIH
during Power Up to allow maximum security and
the possibility to write a commandon the first rising
edge of E and W. Any write cycle initiation is
blocked when Vcc is below VLKO
.
20/34
M29F400T, M29F400B
Table 16A. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-55
-70
Symbol
Alt
Parameter
Unit
High Speed
Interface
Standard
Interface
Min
Max
Min
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
55
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
30
25
0
35
30
0
tDS
tDH
tWH
tCPH
tAS
0
0
20
0
20
0
tELAX
tGHEL
tVCHWL
tEHGL
tAH
45
0
45
0
tVCS
tOEH
tVIDR
tRP
50
0
50
0
Chip Enable High to Output Enable Low
RP Rise TIme to VID
(1,2)
tPHPHH
500
500
500
500
tPLPX
RP Pulse Width
(1)
(1)
tEHRL
tPHWL
tBUSY
tRSP
Program Erase Valid to RB Delay
RP High to Write Enable Low
30
30
4
4
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
21/34
M29F400T, M29F400B
Table 16B. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-90
-120
Symbol
Alt
Parameter
Unit
Standard
Interface
Standard
Interface
Min
Max
Min
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
90
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
45
45
0
50
50
0
tDS
tDH
tWH
tCPH
tAS
0
0
20
0
20
0
tELAX
tGHEL
tVCHWL
tEHGL
tAH
45
0
50
0
tVCS
tOEH
tVIDR
tRP
50
0
50
0
Chip Enable High to Output Enable Low
RP Rise TIme to VID
(1,2)
tPHPHH
500
500
500
500
tPLPX
RP Pulse Width
(1)
(1)
tEHRL
tPHWL
tBUSY
tRSP
Program Erase Valid to RB Delay
RP High to Write Enable Low
35
50
4
4
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
22/34
M29F400T, M29F400B
Figure 8. Write AC Waveforms, E Controlled
tAVAV
VALID
A0-A17/
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI01870C
Note:
Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Figure 9. Read and Write AC Characteristics, RP Related
E
tPHEL
W
tPHWL
RB
tPLPX
RP
tPHPHH
tPLYH
AI02091
23/34
M29F400T, M29F400B
(1)
Table 17A. Data Polling and Toggle Bit AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-55
-70
Symbol
Parameter
Unit
High Speed
Interface
Standard
Interface
Min
10
Max
2400
30
Min
Max
2400
30
Write Enable High to DQ7 Valid (Program, W Controlled)
Write Enable High to DQ7 Valid (Chip Erase, WControlled)
Chip Enable High to DQ7 Valid (Program, E Controlled)
Chip Enable High to DQ7 Valid (Chip Erase, E Controlled)
10
1.0
10
µs
tWHQ7V
1.0
10
sec
2400
30
2400
30
s
µ
tEHQ7V
1.0
1.0
sec
ns
tQ7VQV Q7 Valid to Output Valid (Data Polling)
30
30
Write Enable High to Output Valid (Program)
tWHQV
10
1.0
10
2400
30
10
1.0
10
2400
30
s
µ
Write Enable High to Output Valid (Chip Erase)
sec
µs
Chip Enable High to Output Valid (Program)
tEHQV
2400
30
2400
30
Chip Enable High to Output Valid (Chip Erase)
1.0
1.0
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
(1)
Table 17B. Data Polling and Toggle Bit AC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)
M29F400T / M29F400B
-90 -120
Symbol
Parameter
Unit
Standard
Interface
Standard
Interface
Min
Max
2400
30
Min
Max
2400
30
Write Enable High to DQ7 Valid (Program, W Controlled)
Write Enable High to DQ7 Valid (Chip Erase, WControlled)
Chip Enable High to DQ7 Valid (Program, E Controlled)
Chip Enable High to DQ7 Valid (Chip Erase, E Controlled)
10
1.0
10
10
1.0
10
µs
sec
µs
tWHQ7V
2400
30
2400
30
tEHQ7V
1.0
1.0
sec
ns
tQ7VQV Q7 Valid to Output Valid (Data Polling)
35
50
Write Enable High to Output Valid (Program)
tWHQV
10
1.0
10
2400
30
10
1.0
10
2400
30
µs
Write Enable High to Output Valid (Chip Erase)
sec
Chip Enable High to Output Valid (Program)
tEHQV
2400
30
2400
30
s
µ
Chip Enable High to Output Valid (Chip Erase)
1.0
1.0
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
24/34
M29F400T, M29F400B
Figure 10. Data Polling DQ7 AC Waveforms
25/34
M29F400T, M29F400B
Figure 11. Data Polling Flowchart
Figure 12. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
NO
DQ2, DQ6
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ7
READ DQ2, DQ6
DQ7
=
DATA
YES
NO
DQ2, DQ6
=
TOGGLE
NO
YES
FAIL
FAIL
PASS
PASS
AI01369
AI01873
Table 18. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%)
M29F400T / M29F400B
Parameter
Unit
Typical after
100k W/E Cycles
Min
Typ
Chip Erase (Preprogrammed)
Chip Erase
1.2
4.3
0.6
0.5
0.9
1.0
5.5
11
1.7
4.4
sec
sec
sec
sec
sec
sec
sec
µs
Boot Block Erase
Parameter Block Erase
Main Block (32Kb) Erase
Main Block (64Kb) Erase
Chip Program (Byte)
Byte Program
5.5
11
Word Program
20
20
µs
Program/Erase Cycles (per Block)
100,000
cycles
26/34
M29F400T, M29F400B
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms
27/34
M29F400T, M29F400B
Figure 14. Block Protection Flowchart
START
BLOCK ADDRESS
on A12-A17
W = V
IH
Set-up
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Protect
Verify
Wait 100µs
W = V
IH
E, G = V
IH
VERIFY BLOCK PROTECTION
A0, A6 = V ; A1 = V ; A9 = V
ID
IL
IH
A12-A17 IDENTIFY BLOCK
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
NO
DATA
=
01h
YES
A9 = V
IH
++n
NO
= 25
PASS
YES
A9 = V
IH
FAIL
AI01875E
28/34
M29F400T, M29F400B
Figure 15. All Blocks Unprotecting Flowchart
START
PROTECT
ALL BLOCKS
n = 0
Set-up
W = V
IH
E, G, A9 = V
ID
A12, A15 = V
IH
Wait 4µs
W = V
IL
Wait 10ms
Unprotect
Verify
W = V
IH
E, G = V
IH
E, A0 = V ; A1, A6 = V ; A9 = V
ID
IL
IH
A12-A17 IDENTIFY BLOCK
NEXT
BLOCK
Wait 4µs
G = V
IL
Wait 60ns
VERIFY BLOCK
PROTECT STATUS
NO
YES
DATA
=
00h
NO
++n
= 1000
LAST
BLK.
NO
YES
YES
A9 = V
A9 = V
IH
IH
FAIL
PASS
AI01876C
29/34
M29F400T, M29F400B
ORDERING INFORMATION SCHEME
Example:
M29F400T -55
N
1
TR
Operating Voltage
Option
F
5V ± 10%
R
Reverse
Pinout
TR Tape & Reel
Packing
Array Matrix
Top Boot
Speed
-55(1) 55ns
Package
Temp. Range
T
B
N
TSOP48
12 x 20mm
1
6
3
0 to 70 °C
Bottom Boot
-70 70ns
-90 90ns
-120 120ns
–40 to 85 °C
–40 to 125 °C
M
SO44
Note: 1. Speed obtained with High Speed Measurement Conditions.
M29F400T and M29F400Bare replacedrespectively by the newversionM29F400BT andM29F400BB
Devices are shipped from the factory with the memory content erased (to FFh).
For a list of availableoptions(Speed, Package, etc...) or forfurther informationon any aspect of thisdevice,
please contact the STMicroelectronics Sales Office nearest to you.
30/34
M29F400T, M29F400B
TSOP48 Normal Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
12.10
-
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.476
-
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
11.90
-
0.002
0.037
0.007
0.004
0.780
0.720
0.469
-
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
48
48
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
31/34
M29F400T, M29F400B
TSOP48 Reverse Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
12.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.476
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
11.90
–
0.002
0.037
0.007
0.004
0.780
0.720
0.469
–
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
48
48
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-b
A1
α
L
Drawing is not to scale.
32/34
M29F400T, M29F400B
SO44 - 44 lead Plastic Small Outline, 525 mils body width
mm
Min
2.42
0.22
2.25
inches
Min
Symb
Typ
Max
2.62
0.23
2.35
0.50
0.25
28.30
13.40
–
Typ
Max
0.103
0.010
0.093
0.020
0.010
1.114
0.528
–
A
A1
A2
B
0.095
0.009
0.089
C
0.10
28.10
13.20
–
0.004
1.106
0.520
–
D
E
e
1.27
0.80
0.050
0.031
H
15.90
–
16.10
–
0.626
–
0.634
–
L
3
3
α
°
°
N
44
44
CP
0.10
0.004
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
33/34
M29F400T, M29F400B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
34/34
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