M29KW032E110N1 [STMICROELECTRONICS]
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| 型号： | M29KW032E110N1 |
| 厂家： | 
ST |
| 描述： | 暂无描述 闪存 存储 内存集成电路 光电二极管 |
| 文件： | 总30页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29KW032E
32 Mbit (2Mb x16, Uniform Block)
3V Supply LightFlash™ Memory
PRODUCT PREVIEW
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 2.7V to 3.6V for Read
CC
– V = 11.4V to 12.6V for Program and Erase
PP
■ ACCESS TIME: 90, 110ns
■ PROGRAMMING TIME
– 9µs per Word typical
– Multiple Word Programming Option (4s
typical Chip Program)
TSOP48 (N)
12 x 20mm
■ ERASE TIME
– 21s typical factory Chip Erase
■ UNIFORM BLOCKS
FBGA
– 16 blocks of 2 Mbits
■ PROGRAM/ERASE CONTROLLER
– Embedded Word Program algorithms
TFBGA48 (ZA)
6 x 9mm
■ 10,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code : 88ACh
July 2002
1/30
This is preliminary information on a new product now in development. Details are subject to change without notice.
M29KW032E
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CC
PP
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 11
Table 7. Multiple Word Program Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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M29KW032E
Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 24
Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 24
Figure 15. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline . . . . 25
Table 18. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . . 25
Figure 16. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 26
Figure 17. TFBGA48 Daisy Chain - PCB Connections (Top view through package) . . . . . . . . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
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M29KW032E
SUMMARY DESCRIPTION
The M29KW032E LightFlash™ is a 32 Mbit (2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. Read operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. Program and Erase operations require an
The M29KW032E LightFlash™ features a new
command, Multiple Word Program, used to pro-
gram large streams of data. It greatly reduces the
total programming time when a large number of
Words are written to the memory at any one time.
Using this command the entire memory can be
programmed in 2s, compared to 9s using the stan-
dard Word Program.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and TFBGA48 (6 x 9mm, 0.8mm pitch) packages.
The memory is supplied with all the bits erased
(set to ’1’).
additional V
(11.4 to 12.6) power supply. On
PP
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 16 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased (see
Figures 2, Block Addresses). Program and Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase Con-
troller (P/E.C.) simplifies the process of program-
ming or erasing the memory by taking care of all of
the special operations that are required to update
the memory contents.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
Address Inputs
V
V
PP
CC
DQ0-DQ15
Data Inputs/Outputs
Chip Enable
E
21
16
G
Output Enable
A0-A20
DQ0-DQ15
W
RP
RB
Write Enable
W
E
M29KW032E
Reset
Ready/Busy Output
Supply Voltage read
Supply Voltage program erase
Ground
G
RB
V
CC
RP
V
PP
V
SS
NC
Not Connected Internally
V
SS
AI04370
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M29KW032E
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
B
A3
A4
A7
A17
A6
A13
A12
A14
A15
A16
NC
RB
W
A9
A8
V
RP
PP
A18
NC
C
D
E
F
A2
A1
A0
E
A10
A11
A20
DQ2
A19
DQ5
A5
DQ7
DQ0
DQ8
DQ10
DQ11
DQ3
DQ12
DQ14
DQ13
DQ6
V
DQ15
G
H
G
DQ9
DQ1
CC
V
DQ4
V
SS
SS
AI04372
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M29KW032E
Figure 4. TSOP Connections
Table 2. Block Addresses
Block Number
Address Range
16
15
14
13
12
11
10
9
1E0000h-1FFFFFh
1C0000h-1DFFFFh
1A0000h-1BFFFFh
180000h-19FFFFh
160000h-17FFFFh
140000h-15FFFFh
120000h-13FFFFh
100000h-11FFFFh
0E0000h-0FFFFFh
0C0000h-0DFFFFh
0A0000h-0BFFFFh
080000h-09FFFFh
060000h-07FFFFh
040000h-05FFFFh
020000h-03FFFFh
000000h-01FFFFh
A15
A14
A13
A12
A11
A10
A9
1
48
A16
NC
V
SS
DQ15
DQ7
DQ14
DQ6
A8
DQ13
DQ5
A19
A20
DQ12
DQ4
8
W
RP
NC
7
12
13
37
36
V
CC
M29KW032E
DQ11
6
V
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
PP
5
RB
A18
4
A17
A7
3
2
A6
A5
A4
A3
A2
A1
1
DQ0
G
V
E
SS
24
25
A0
AI04374
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M29KW032E
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Ready/Busy becomes high-impedance. See Table
16 and Figure 13, Reset AC Characteristics.
During Program or Erase operations Ready/Busy
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs outputs the data stored at the select-
ed address during a Bus Read operation. During
Bus Write operations they represent the com-
mands sent to the Command Interface of the Pro-
gram/Erase Controller.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
is Low, V . Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
OL
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for Read operations.
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
. This prevents Bus Write operations from ac-
V
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CC
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
High, V , all other pins are ignored.
IH
Output Enable (G). The Output Enable, G, con-
erase operations, I
.
CC3
trols the Bus Read operation of the memory.
V
Program Supply Voltage. V
is both a
PP
PP
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin. The Supply Voltage V
before the Program Supply Voltage V
must be applied
CC
.
PP
Reset (RP). The Reset pin can be used to apply
a Hardware Reset to the memory.
A Hardware Reset is achieved by holding Reset
If V is in the range 11.4V to 12.6V it acts as a
power supply pin for program and erase opera-
PP
tions. V must be stable until the Program/Erase
PP
Low, V , for at least t
. After Reset goes High,
PLPX
IL
algorithm is completed.
V , the memory will be ready for Bus Read and
IH
Bus Write operations after t
or t
, which-
If V is kept in a low voltage range (0V to 3.6V)
PP
PHEL
RHEL
ever occurs last. See the Ready/Busy Output sec-
tion, Table 16 and Figure 13, Reset AC
Characteristics for more details.
V
is seen as a Write Protect pin. In this case a
PP
voltage lower than V
gives an absolute protec-
HH
tion against program or erase, while V
in the
PP
range of V
enables these functions (see Table
HH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode and Auto
Select mode. After a Hardware Reset, Bus Read
and Bus Write operations cannot begin until
12, DC Characteristics for the relevant values).
Note that V must not be left floating or uncon-
nected as the device may become unreliable.
Vss Ground. The V
PP
Ground is the reference
SS
for all voltage measurements.
7/30
M29KW032E
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
be held within V ± 0.2V. For the Standby current
CC
level see Table 12, DC Characteristics.
Inputs, applying a Low signal, V , to Chip Enable
IL
During program or erase operations the memory
will continue to use the Program/Erase Supply
and Output Enable and keeping Write Enable
High, V . The Data Inputs/Outputs will output the
IH
Current, I
, for Program or Erase operations un-
CC3
value, see Figure 10, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
duced to the Standby Supply Current, I
. The
CC2
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3, Bus Operations.
able must remain High, V , during the whole Bus
IH
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 14 and 15, Write AC
Table 3. Bus Operations
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15-DQ0
V
Operation
Bus Read
E
G
W
PP
(4)
V
IL
V
V
IH
Cell Address
Data Output
IL
IH
IH
XX
(3)
V
IL
V
V
V
V
Bus Write
Command Address
Data Input
Hi-Z
V
HH
IL
X
Output Disable
Standby
X
X
IH
V
X
X
X
X
Hi-Z
IH
A0 = V , A1 = V ,
Read Manufacturer
Code
IL
IL
V
V
V
V
V
XX
XX
0020h
88ACh
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V ,
IH
IL
V
Read Device Code
Others V or V
IL
IH
Note: 1. X = V or V
.
IH
IL
2. XX = V , V or V
IL
IH
HH
3. Not necessary for Auto Select or Read/Reset commands.
4. When reading the Status Register during Program or Erase operations, V must be kept at V
.
HH
PP
8/30
M29KW032E
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Refer to Tables 4 and 5, for a summary of the com-
mands.
Read/Reset Command.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command is executed
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written to the memory at any
one time. V must be set to V
during Multiple
PP
HH
Word Program. If V is set to either V or V the
PP
IL
IH
command will be ignored, the data will remain un-
changed and the device will revert to Read/Reset
mode.
regardless of the value of V (V , V or V ).
PP
IL
IH
HH
Auto Select Command.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 5, Multiple Word
Program Command and Figure 5, Multiple Word
Program Flowchart). The Status Register Toggle
bit (DQ6) should be checked to verify that the op-
eration has started and the Multiple Word Program
bit (DQ0) checked to verify that the P/E.C. is ready
for the first Word.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. Three
consecutive Bus Write operations are required to
issue the Auto Select command. Once the Auto
Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is
issued, all other commands are ignored. The Auto
Select command is executed regardless of the val-
ue of V (V , V or V ).
PP
IL
IH
HH
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits
IL
IL
may be set to either V or V .
IL
IH
Program Phase. The Program Phase requires
n+1 cycles, where n is the number of Words, to ex-
ecute the programming phase (refer to Table 5,
Multiple Word Program Command and Figure 5,
Multiple Word Program Flowchart).
Three successive steps are required to issue and
execute the Program Phase of the command.
1. The fourth Bus Write operation of the command
latches the Start Address and the first Word to
be programmed. The Status Register Multiple
Word Program bit (DQ0) should be read to
check that the P/E.C. is ready for the next Word.
2. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address can remain the Start Address, be
incremented or be any address in the same
block, as the device automatically increments
the address with each sucssesive Bus Write
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V .
IL
IH
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. V must be
PP
set to V during Word Program. If V is set to ei-
HH
PP
ther V or V the command will be ignored, the
IL
IH
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the Program/Erase Controller.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
9/30
M29KW032E
cycle. If the command is used to program in
more than one block then the address must
remain in the starting block as any address that
is not in the same block as the Start Address
terminates the Program operation. The Status
Register Multiple Word Program bit (DQ0) must
be read between each Bus Write cycle to check
that the P/E.C. is ready for the next Word.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole memory from ’0’ to ’1’.
Block Erase Command.
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
3. Finally, after all Words have been programmed,
write one Bus Write operation to any address
outside the block containing the Start Address,
to terminate the programming phase.
V
must be set to V during Block Erase. If V
HH PP
PP
is set to either V or V the command will be ig-
IL
IH
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode.
The memory is now set to enter the Verify Phase.
Six Bus Write operations are required to select the
block . The Block Erase operation starts the Pro-
gram/Erase Controller after the last Bus Write op-
eration. The Status Register can be read after the
sixth Bus Write operation. See the Status Register
for details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data. If the check fails the P/E.C will
try to reprogram the correct data. The P/E.C will
remain busy until the correct data has been suc-
cessfully programmed. The Verify Phase is man-
datory. If the Verify Phase is not executed the
programmed data cannot be guaranteed.
Three successive steps are required to execute
the Verify Phase of the command.
1. Use one Bus Write operation to latch the Start
Address and the first Word, to be verified. The
Status Register Multiple Word Program bit
(DQ0) should be read to check that the P/E.C. is
ready for the next Word.
2. Each subsequent Word to be verified is latched
with a new Bus Write operation. If any address
that is not in the same block as the Start
Address is given, the Verify operation
Chip Erase Command.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
terminates. The Status Register Multiple Word
Program (DQ0) must be read to check that the
P/E.C. is ready for the next Word.
V
must be set to V
during Chip Erase. If V
HH PP
PP
3. Finally, after all Words have been verified, write
one Bus Write operation to any address outside
the block containing the Start Address, to
terminate the Verify Phase.
Exit Phase . Read the Status Register to verify
that DQ6 has stopped toggling. If the Verify Phase
is successfully completed the memory returns to
the Read mode. If the P/E.C. fails to reprogram a
given location, the Verify Phase will terminate and
Error bit DQ5 will be set in the Status Register. If
is set to either V or V the command will be ig-
IL
IH
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the Program/Erase Control-
ler.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
the error is due to a V failure DQ4 will also be
PP
set. If the operation fails a Read/Reset command
must be issued to return the device to Read mode.
It is not possible to issue any command to abort or
pause the operation. Typical program times are
given in Table 6. Bus Read operations during the
program operation will output the Status Register
on the Data Inputs/Outputs. See the section on the
Status Register for more details.
10/30
M29KW032E
Table 4. Standard Commands
Bus Write Operations
3rd 4th
Command
1st
2nd
Data
5th
6th
Add
X
Data
F0
Add
Add
Data
Add
Data
Add
Data
Add
Data
1
3
Read/Reset
555
555
555
555
555
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
X
F0
90
A0
80
80
Auto Select
Word Program
Block Erase
Chip Erase
3
555
555
555
555
4
PA
PD
AA
AA
6+
6
555
555
2AA
2AA
55
55
BA
30
10
555
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Bus Write Operations
Phase
1st
2nd
3rd
4th
5th
Final -1
Final
Add Data Add Data Add Data Add Data Add Data
Add Data Add Data
3+n
+1
NOT
PA1
Program
Verify
555
AA 2AA
55
555
20
PD1 PA1 PD2
PA1 PAn
PA1 PAn
X
X
PA1
NOT
PA1
n+1 PA1 PD1 PA1 PD2 PA1 PD3 PA1 PD4 PA1 PD5
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. NOT PA1 is any address that is not in the same block as PA1. X Don’t Care, n =
number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Typical after
(1)
Parameter
Min
Max
Unit
Typ
21
(1)
10k W/E Cycles
Chip Erase
25
120
6
s
Block Erase (128 KWords)
Program (Word)
1.5
9
s
250
35
35
µs
Chip Program (Multiple Word)
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
4
s
s
18
10,000
cycles
Note: 1. T = 25°C, V = 12V.
A
PP
Table 7. Multiple Word Program Timings
Symbol
Parameter
Min
Typ
Max
500
250
20
Unit
ns
t
t
t
t
MWP Setup time
MWP-SETUP
MWP Program Time
9
10
2
µs
MWP-PROG
MWP-TRAN
MWP-END
MWP Program to Verify transition
MWP Verify to End transition
2
µs
3
µs
Note: 1. MWP = Multiple Word Program.
11/30
M29KW032E
Figure 5. Multiple Word Program Flowchart
Start
Setup
Verify
Phase
Phase
Read Status
Register
Write AAh
Address 555h
(1)
(tMWP-TRAN
)
Write 55h
Address 2AAh
NO
DQ0 = 0?
YES
Write 20h
Address 555h
Write Data1 (PD )
1
Start Address (PA )
1
Read Status
Register
Read Status
Register
NO
NO
NO
DQ6
Setup time
exceeded?
Word
program time
exceeded?
NO
toggling?
DQ0 = 0?
YES
YES
YES
YES
(1)
(tMWP-SETUP
)
YES
(1)
YES
(tMWP-PROG
)
NO
Write Data 2 (PD )
2
EXIT (setup failed
)
DQ0 = 0?
YES
Address in Start Block
Write Data1(PD )
1
Start Address (PA )
1
Read Status
Register
Program
Phase
NO
Word
Read Status
Register
NO
program time
exceeded?
DQ0 = 0?
YES
(1)
(tMWP-PROG
)
NO
DQ0 = 0?
YES
Write Data n (PD )
n
Address in Start Block
Write Data 2 (PD )
2
Address in Start Block
Read Status
Register
NO
Read Status
Register
Word
NO
program time
exceeded?
DQ0 = 0?
Exit
Phase
(1)
(tMWP-PROG
)
YES
NO
DQ0 = 0?
YES
Write XX
Any Address
NOT in Start Block
Read Status
Register
Write Data n (PD )
n
Address in Start Block
YES
NO
DQ5 = 1
DQ4 = 0?
Read Status
Register
Fail error
Fail, VPP error
Read Status
Register
YES
DQ6
toggling?
(1)
(tMWP-END
)
NO
Write F0h
Address XX
NO
DQ0 = 0?
YES
Write XX
Any Address
NOT in Start Block
Exit (read mode)
AI05554c
Note: 1. Refer to Table 7, Multiple Word Program Timings, for the values.
12/30
M29KW032E
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. The bits in the Status Register
are summarized in Table 8, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion. The Data Polling Bit is output on DQ7 when
the Status Register is read.
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
V
Status Bit (DQ4). The V Status Bit can be
PP
PP
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement. The Data Polling Bit is not available dur-
ing a Multiple Word Program operation.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
Figure 6, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation. The Toggle
Bit is output on DQ6 when the Status Register is
read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
Figure 7, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
used to identify if any Program or Erase operation
has failed due to a V error. If V falls below V
HH
PP
PP
during any Program or Erase operation, the oper-
ation aborts and DQ4 is set to ‘1’. If V remains at
PP
V
throughout the Program or Erase operation,
HH
the operation completes and DQ4 is set to ‘0’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. The Erase
Timer Bit is output on DQ3 when the Status Reg-
ister is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Block and Chip Erase op-
erations. The Alternative Toggle Bit is output on
DQ2 when the Status Register is read.
During Erase operations the Toggle Bit changes
from ’0’ to ’1’ to ’0’, etc., with successive Bus Read
operations to any address. Once the operation
completes the memory returns to Read mode.
If an Erase operation fails and the Error Bit is set,
the Alternative Toggle Bit will continue to toggle
with successive Bus Read operations to any ad-
dress. The Alternative Toggle Bit does not change
if the addressed block has erased correctly.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the Program/Erase Controller is active or inactive
during Multiple Word Program. When the Pro-
gram/Erase Controller has written one Word and is
ready to accept the next Word, the bit is set to ‘0’.
Status Register Bit DQ1 is reserved.
13/30
M29KW032E
Table 8. Status Register Bits
Operation
Condition
DQ7
DQ7
DQ7
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ0
RB
0
Word Program
Any Address
Toggle
Toggle
Toggle
0
1
1
–
0
1
–
–
–
–
–
–
–
–
–
V
V
= V
0
PP
HH
HH
Word Program
Error
PP < V
0
Block/ Chip
Erase
(2)
Any Address
0
Toggle
0
–
1
–
0
Toggle
(2)
(2)
V
V
= V
0
0
–
Toggle
Toggle
Toggle
1
1
0
0
1
–
1
1
–
–
–
1
0
0
0
PP
HH
HH
Toggle
Erase Error
PP < V
Toggle
–
P/E.C. active
Multiple Word
Program
P/E.C. inactive,
waiting for next
Word
–
Toggle
0
–
–
–
0
1
Multiple Word
Program
Error
V
V
= V
PP
–
–
Toggle
Toggle
1
1
0
1
–
–
–
–
1
1
0
0
HH
HH
PP < V
Note: 1. Unspecified data bits should be ignored.
2. DQ2 toggles on any address during Block or Chip Erase and after an Erase error.
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
PASS
YES
FAIL
PASS
AI03598
AI01370B
14/30
M29KW032E
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 9. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
–65
Max
125
150
Unit
°C
T
Temperature Under Bias
BIAS
T
Storage Temperature
°C
STG
(1,2)
V
+0.6
–0.6
–0.6
–0.6
V
V
V
V
Input or Output Voltage
Read Supply Voltage
CC
IO
V
CC
4
V
Program/Erase Supply Voltage
13.5
PP
Note: 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V for less than 20ns during transitions.
CC
3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. V must not remain at V for more than a total
PP
HH
of 80hrs.
15/30
M29KW032E
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 10, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
M29KW032E
Parameter
90
110
Unit
Min
2.7
11.4
0
Max
Min
2.7
11.4
0
Max
3.6
V
V
Read Supply Voltage
3.6
12.6
70
V
V
CC
Program/Erase Supply Voltage
12.6
70
PP
Ambient Operating Temperature
°C
pF
ns
V
Load Capacitance (C )
30
30
L
Input Rise and Fall Times
10
10
0 to V
0 to V
Input Pulse Voltages
CC
CC
V
/2
V
CC
/2
Input and Output Timing Ref. Voltages
V
CC
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
V
V
CC
CC
V
CC
V
/2
25kΩ
25kΩ
CC
0V
DEVICE
UNDER
TEST
AI05565
0.1µF
C
L
C
includes JIG capacitance
L
AI05566
Table 11. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
OUT
V
OUT
12
pF
Note: Sampled only, not 100% tested.
16/30
M29KW032E
Table 12. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
±1
µA
LO
E = V , G = V ,
IL
IH
I
Supply Current (Read)
10
mA
CC1
f = 6MHz
E = V
RP = V ±0.2V
±0.2V,
CC
I
Supply Current (Standby)
100
µA
CC2
CC
I
Supply Current (Program/Erase)
Input Low Voltage
P/E.C. active
20
mA
V
CC3
V
–0.5
0.8
IL
V
IH
0.7V
V
+0.3
CC
Input High Voltage
V
CC
V
OL
I
OL
= 1.8mA
Output Low Voltage
0.45
V
V
OH
V
–0.4
CC
Output High Voltage
I
= –100µA
V
OH
V
V
V
V
Program/Erase Voltage
Current (Read/Standby)
Current (Program/Erase)
11.4
12.6
100
10
V
HH
PP
PP
PP
I
V
= V
HH
µA
mA
HH1
PP
I
P/E.C. Active
HH2
Program/Erase Lockout Supply
Voltage
1.8
2.3
V
V
LKO
17/30
M29KW032E
Figure 10. Read AC Waveforms
tAVAV
VALID
A0-A20
E
tAVQV
tAXQX
tEHQX
tELQV
tELQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ15
VALID
AI05567
Table 13. Read AC Characteristics
M29KW032E
Symbol
Alt
Parameter
Test Condition
Unit
90
110
E = V ,
IL
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
90
110
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
90
110
AVQV
G = V
G = V
G = V
IL
IL
IL
(1)
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Min
0
0
ns
ns
t
LZ
ELQX
t
t
Max
90
110
ELQV
CE
Output Enable Low to Output
Transition
(1)
t
E = V
Min
0
0
ns
t
OLZ
IL
GLQX
t
t
E = V
G = V
E = V
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Max
Max
35
30
35
30
ns
ns
GLQV
OE
IL
(1)
t
t
t
HZ
DF
IL
EHQZ
(1)
t
t
Output Enable High to Output Hi-Z
Max
Min
30
0
30
0
ns
ns
IL
GHQZ
t
t
EHQX
Chip Enable, Output Enable or
Address Transition to Output Transition
GHQX
OH
t
AXQX
Note: 1. Sampled only, not 100% tested.
18/30
M29KW032E
Figure 11. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
W
tGHWL
tWLWH
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ15
V
CC
tVCHEL
V
PP
tVPHEL
RB
tWHRL
AI05568
19/30
M29KW032E
Table 14. Write AC Characteristics, Write Enable Controlled
M29KW032E
Symbol
Alt
Parameter
Unit
90
90
0
110
110
0
t
t
WC
Address Valid to Next Address Valid
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
CS
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
ELWL
t
t
35
35
0
35
35
0
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
WHDX
t
0
0
WHEH
t
t
WPH
30
0
30
0
WHWL
t
t
AS
AVWL
t
t
AH
45
0
45
0
WLAX
Read mode
Output Enable High to Write
Enable Low
t
t
GHWL
Read SR Toggle bits
Read mode
10
0
10
0
Read SR Toggle bits in
Multiple Word Program
Write Enable High to Output
Enable Low
Min
Min
20
30
20
30
ns
ns
t
WHGL
OEH
Read SR Toggle bits
other operations
(1)
t
Program/Erase Valid to RB Low
Max
Min
Min
35
50
35
50
ns
µs
ns
t
BUSY
WHRL
t
t
V
CC
High to Chip Enable Low
VCHEL
VCS
(2)
VPHEL
t
V
PP
High to Chip Enable Low
500
500
t
VCS
Note: 1. Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
20/30
M29KW032E
Figure 12. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ15
V
CC
tVCHWL
V
PP
tVPHWL
RB
tEHRL
AI05569
21/30
M29KW032E
Table 15. Write AC Characteristics, Chip Enable Controlled
M29KW032E
Symbol
Alt
Parameter
Unit
90
90
0
110
110
0
t
t
WC
Address Valid to Next Address Valid
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
WS
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
WLEL
t
t
35
35
0
35
35
0
ELEH
CP
DS
t
t
t
DVEH
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
EHDX
DH
t
t
WH
0
0
EHWH
t
t
CPH
30
0
30
0
EHEL
t
t
AS
AVEL
t
t
45
0
45
0
ELAX
AH
Read mode
Output Enable High Chip Enable
Low
t
t
GHEL
EHGL
Read SR Toggle bits
Read mode
10
0
10
0
Read SR Toggle bits in
Multiple Word Program
Chip Enable High to Output
Enable Low
Min
Min
20
30
20
30
ns
ns
t
OEH
Read SR Toggle bits
other operations
(1)
t
Program/Erase Valid to RB Low
Max
Min
Min
35
50
35
50
ns
µs
ns
t
BUSY
EHRL
t
t
V
CC
High to Write Enable Low
VCHWL
VCS
(2)
VPHWL
t
V
PP
High to Write Enable Low
500
500
t
VCS
Note: 1. Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
22/30
M29KW032E
Figure 13. Reset AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
RP
tRHWL, tRHEL, tRHGL
tPLPX
tPLYH
AI05570
Table 16. Reset AC Characteristics
M29KW032E
Symbol
Alt
Parameter
Unit
90
110
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
t
Min
Min
50
50
ns
PHEL
RH
(1)
t
PHGL
(1)
(1)
(1)
t
t
RHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
0
0
ns
t
RB
RHEL
RHGL
t
t
RP Pulse Width
Min
500
10
500
10
ns
PLPX
(1)
RP
t
RP Low to Read Mode
Max
µs
t
READY
PLYH
Note: 1. Sampled only, not 100% tested.
23/30
M29KW032E
PACKAGE MECHANICAL
Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
α
L
Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
12.10
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.4764
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
11.90
–
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.4685
–
C
D
D1
E
e
0.50
0.0197
L
0.50
0°
0.70
5°
0.0197
0°
0.0276
5°
α
N
48
48
CP
0.10
0.0039
24/30
M29KW032E
Figure 15. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z00
Note: Drawing is not to scale.
Table 18. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
A
Typ
Max
Typ
Max
1.200
0.0472
A1
A2
b
0.200
0.0079
1.000
0.0394
0.400
6.000
4.000
0.350
5.900
–
0.450
0.0157
0.2362
0.1575
0.0138
0.2323
–
0.0177
D
6.100
0.2402
D1
ddd
E
–
–
0.100
0.0039
9.000
0.800
5.600
1.000
1.700
0.400
0.400
8.900
9.100
0.3543
0.0315
0.2205
0.0394
0.0669
0.0157
0.0157
0.3504
0.3583
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E1
FD
FE
SD
SE
25/30
M29KW032E
Figure 16. TFBGA48 Daisy Chain - Package Connections (Top view through package)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
AI05552b
26/30
M29KW032E
Figure 17. TFBGA48 Daisy Chain - PCB Connections (Top view through package)
END
POINT
START
POINT
1
2
3
4
5
6
A
B
C
D
E
F
G
H
AI05553b
27/30
M29KW032E
PART NUMBERING
Table 19. Ordering Information Scheme
Example:
M29KW032E
90
N
1
T
Device Type
M29K = LightFlash™
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
032E = 32 Mbit (x16)
Speed
90 = 90 ns
110 = 110 ns
Package
N = TSOP48: 12 x 20 mm
ZA = TFBGA48: 6 x 9mm - 0.80mm pitch
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Table 20. Daisy Chain Ordering Scheme
Example:
M29K
DCL3-32
T
Device Type
M29K
Daisy Chain
DCL3-32 = Daisy Chain Level 3 for 32 Mbit parts
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
28/30
M29KW032E
REVISION HISTORY
Table 21. Document Revision History
Date
Version
Revision Details
09-Oct-2001
-01
First Issue
LFBGA changed to TFBGA package. Write AC Characteristics t
t
t
WLWH, DVWH, WLAX,
t
t
t
t
t
t
and t
modified. Typical Chip Program
GHWL, WHGL, ELEH, DVEH, ELAX, GHEL
EHGL
07-May-2002
12-Jul-2002
23-Jul-2002
-02
-03
3.1
and Erase times modified, Multiple Word Program description and flowchart clarified,
Alternative Toggle Bit DQ2 description clarified, Status Register Bits Table modified.
Document classed as Product Preview.
Figure 7 modified.
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot.
(revision version 03 becomes 3.0).
Figure 5, Multiple Word Program Flowchart, modified; Table 7, Multiple Word
Program Timings, added.
29/30
M29KW032E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
LightFlash is a trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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30/30
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