M29W008B-100N1TR [STMICROELECTRONICS]
8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory; 8兆位1Mb的X8 ，引导块低电压单电源闪存
| 型号： | M29W008B-100N1TR |
| 厂家： | 
ST |
| 描述： | 8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory |
| 文件： | 总30页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29W008T
M29W008B
8 Mbit (1Mb x8, Boot Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W008T and M29W008B are replaced
respectively by the M29W008AT and
M29W008AB
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
FAST PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
TSOP40 (N)
10 x 20 mm
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
Figure 1. Logic Diagram
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
V
CC
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code, M29W008T: D2h
– Device Code, M29W008B: DCh
20
8
A0-A19
DQ0-DQ7
RB
W
E
M29W008T
M29W008B
G
DESCRIPTION
The M29W008 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V VCC supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
RP
V
SS
AI02189
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
June 1999
1/30
This is information on a product still in production but not recommended for new designs.
M29W008T, M29W008B
Figure 2. TSOP Pin Connections
Table 1. Signal Names
A0-A19
Address Inputs
A16
A15
A14
A13
A12
A11
A9
1
40
A17
DQ0-DQ7
Data Input/Outputs, Command Inputs
Chip Enable
V
SS
E
NC
G
Output Enable
A19
A10
DQ7
DQ6
DQ5
DQ4
W
Write Enable
RP
RB
VCC
VSS
Reset / Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
A8
W
RP
NC
RB
A18
A7
10 M29W008T 31
V
Ground
CC
M29W008B
11
30
V
CC
NC
Suspend and Resume are written to the device in
cyclesofcommands to a Command Interface using
standard microprocessor write timings. The device
is offered in TSOP40 (10 x 20mm) package.
DQ3
DQ2
DQ1
DQ0
G
A6
A5
Organisation
A4
The M29W008 is organised as 1Mb x 8. The mem-
ory uses the address inputs A0-A19 and the Data
Input/Outputs DQ0-DQ7. Memory control is pro-
vided by Chip EnableE, Output EnableG and Write
Enable W inputs.
A3
V
E
SS
A2
A1
20
21
A0
AI02190
AReset/Block Temporary Unprotection RPtri-level
input provides a hardware reset when pulled Low,
and when held High (atVID) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
Warning: NC = Not Connected.
DESCRIPTION (Cont’d)
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature (3)
Temperature Under Bias
Storage Temperature
Value
–40 to 85
–50 to 125
–65 to 150
–0.6 to 5
Unit
C
°
TBIAS
TSTG
C
C
°
°
(2)
VIO
Input or Output Voltages
Supply Voltage
V
V
V
VCC
–0.6 to 5
(2)
V(A9, E, G, RP)
A9, E, G, RP Voltage
–0.6 to 13.5
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
2/30
M29W008T, M29W008B
Memory Blocks
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W008Tand M29W008B devices have an array
of 19 blocks, one Boot Block of 16 Kbytes, two
Parameter Blocks of 8 Kbytes, one Main Block of
32 Kbytes and fifteen Main Blocks of 64 Kbytes.
The M29W008T has the Boot Block at the top of
the memory address space and the M29W008B
locates the Boot Block starting at the bottom. The
memory maps are showed in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automaticallyby the P/E.C. The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed.
When power is first applied or if Vcc falls below
VLKO, the command interface is reset to Read
Array.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
SIGNAL DESCRIPTIONS
Bus Operations
See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to VID, either a Read
Electronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A12 and A15.
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
tection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
Command Interface
Data Input/Outputs (DQ0-DQ7). The input is data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and whenRP is at a Low level.
Chip Enable (E). The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselectsthe memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to VID during the Block Unprotection opera-
tion.
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations. The Status Register Data Polling, Tog-
gle, Error bits and the RB output may be read at
any time, during programming or erase, to monitor
the progress of the operation.
3/30
M29W008T, M29W008B
Figure 3A. Top Boot Block Memory Map and Block Address Table
TOP BOOT BLOCK
Byte-Wide
FFFFFh
Byte-Wide
FFFFFh
16K BOOT BLOCK
F0000h
EFFFFh
FC000h
FBFFFh
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
32K MAIN BLOCK
E0000h
DFFFFh
FA000h
F9FFFh
D0000h
CFFFFh
F8000h
F7FFFh
C0000h
BFFFFh
F0000h
B0000h
AFFFFh
A0000h
9FFFFh
90000h
8FFFFh
80000h
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
00000h
AI02135
4/30
M29W008T, M29W008B
Figure 3B. Bottom Boot Block Memory Map and Block Address Table
BOTTOM BOOT BLOCK
Byte-Wide
FFFFFh
64K MAIN BLOCK
F0000h
EFFFFh
64K MAIN BLOCK
E0000h
DFFFFh
64K MAIN BLOCK
D0000h
CFFFFh
64K MAIN BLOCK
C0000h
BFFFFh
64K MAIN BLOCK
B0000h
AFFFFh
64K MAIN BLOCK
A0000h
9FFFFh
64K MAIN BLOCK
90000h
8FFFFh
64K MAIN BLOCK
80000h
7FFFFh
64K MAIN BLOCK
70000h
6FFFFh
64K MAIN BLOCK
60000h
5FFFFh
64K MAIN BLOCK
50000h
4FFFFh
Byte-Wide
0FFFFh
64K MAIN BLOCK
40000h
3FFFFh
64K MAIN BLOCK
64K MAIN BLOCK
64K MAIN BLOCK
32K MAIN BLOCK
30000h
2FFFFh
08000h
07FFFh
8K PARAMETER BLOCK
8K PARAMETER BLOCK
16K BOOT BLOCK
20000h
1FFFFh
06000h
05FFFh
10000h
0FFFFh
04000h
03FFFh
00000h
00000h
AI02136
5/30
M29W008T, M29W008B
Table 3A. M29W008T Block Address Table
Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-F7FFFh
F8000h-F9FFFh
FA000h-FBFFFh
FC000h-FFFFFh
A19
0
A18
0
A17
0
A16
0
A15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
X
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
When RB is High, the device is ready for any Read,
Program or Erase operation. The RB will also be
High when the memory is put in Erase Suspend or
Standby modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
VIL for at least tPLPX. When the reset pulse is given,
if the memory is in Read or Standby modes, it will
be available for new operations in tPHEL after the
rising edge of RP.
Write Enable (W). This input controls writing to the
Command Register and Address and Data latches.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state ofthe
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructions except the Erase Suspend instruction.
6/30
M29W008T, M29W008B
Table 3B. M29W008B Block Address Table
Address Range
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-6FFFFh
F0000h-FFFFFh
A19
0
A18
0
A17
0
A16
0
A15
0
A14
0
A13
X
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
X
X
X
X
X
X
X
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
X
X
X
X
X
X
X
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
If the memory is in Erase, Erase Suspend or Pro-
gram modes the reset will take tPLYH during which
the RB signal will be held at VIL. The end of the
memory reset will be indicated by the rising edge
of RB. A hardware reset during an Erase or Pro-
gram operation will corrupt the data being pro-
grammed or the sector(s) being erased. See Table
14 and Figure 9.
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slower than tPHPHH
(See Table 15 and Figure 9). When RP is returned
from VID to VIH all blocks temporarily unprotected
will be again protected.
.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
7/30
M29W008T, M29W008B
DEVICE OPERATIONS
Electronic Signature can also be read, without rais-
ing A9 to VID, by giving the memory the Instruction
AS.
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Block Protection. Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
erase operations. Thismode isactivated when both
A9 and G are raised to VID and an address in the
block is applied on A13-A19. Block protection is
initiated on the edge of W falling to VIL. Then after
a delay of 100µs, the edge of W rising to VIH ends
the protection operations. Block protection verify is
achieved by bringing G, E, A0 and A6 to VIL and A1
to VIH, while W is at VIH and A9 at VID. Under these
conditions, reading the data output will yield 01h if
the block defined by the inputs on A13-A19 is
protected. Any attempt to program or erase a pro-
tected block will be ignored by the device.
Write. Write operations are used to give Instruction
Commands to the memory or to latch input data to
be programmed. Awrite operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the rising
edge of W or E whichever occurs first.
Output Disable. The data outputs are high imped-
ance when the Output Enable G is High with Write
Enable W High.
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
order to change stored data. The temporary unpro-
tection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by
executing the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again pro-
tected.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. Unprotection is initiated
bythe edge of Wfalling toVIL. After adelayof10ms,
the unprotection operation will end. Unprotection
verify is achieved by bringing G and E to VIL while
A0 is at VIL, A6 and A1 are at VIH and A9 remains
at VID. In these conditions, reading the output data
will yield 00h if the block defined by the inputs
A13-A19 has been succesfully unprotected. Each
block must be separately verified by giving its ad-
dress in order to ensure that it has been unpro-
tected.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMi-
croelectronics is 20h, the device code is D2h for the
M29W008T (Top Boot) and DCh for the
M29W008B (Bottom Boot). These codes allow pro-
gramming equipment or applications to automat-
ically match their interface to the characteristics of
the M29W008. The Electronic Signature is output
by a Read operation when the voltage applied to
A9 is at VID and address inputs A1 is Low. The
manufacturer code is output when the Address
input A0 is Low and the device code when this input
is High. Other Address inputs are ignored. The
8/30
M29W008T, M29W008B
Table 4. User Bus Operations (1)
Operation
Read Byte
Write Byte
Output Disable
Standby
E
G
VIL
VIH
VIH
X
W
VIH
VIL
VIH
X
RP
VIH
VIH
VIH
VIH
VIL
A0
A0
A0
X
A1
A1
A1
X
A6
A6
A6
X
A9
A9
A9
X
A12
A12
A12
X
A15
DQ0-DQ7
VIL
VIL
VIL
VIH
X
A15 Data Output
A15
X
Data Input
Hi-Z
X
X
X
X
X
X
Hi-Z
Reset
X
X
X
X
X
X
X
X
Hi-Z
Block
VIL
VID
VID
VID
VIL Pulse
VIL Pulse
VIH
VIH
X
X
X
X
X
X
VID
VID
X
X
X
X
Protection(2,4)
Blocks
VIH
VIH
Unprotection(4)
Block
Block
Protect
Status (3)
Protection
VIL
VIL
X
VIL
VIL
X
VIH
VIH
X
VIH
VIH
VID
VIL
VIL
X
VIH
VIH
X
VIL
VIH
X
VID
VID
X
A12
A12
X
A15
A15
X
Verify(2,4)
Block
Block
Protect
Status (3)
Unprotection
Verify(2,4)
Block
Temporary
Unprotection
X
Notes: 1. X = VIL or VIH
2. Block Address must be given on A13-A19 bits.
3. See Table 6.
4. Operation performed on programming equipment.
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
Other
Addresses
DQ0-
DQ7
Code
Device
E
G
W
A0
A1
Manufact. Code
Device Code
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIH
VIH
VIL
VIL
VIL
Don’t Care
Don’t Care
Don’t Care
20h
D2h
DCh
M29W008T
M29W008B
Table 6. Read Block Protection with AS Instruction
Other
Addresses
Code
E
G
W
A0
A1
A13-A19
DQ0-DQ7
Protected Block
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
Block Address
Block Address
Don’t Care
Don’t Care
01h
00h
Unprotected Block
9/30
M29W008T, M29W008B
INSTRUCTIONS AND COMMANDS
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command se-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cles which unlock the Command Interface. In addi-
tion, for Erase, instruction confirmation is again
preceded by the two Coded cycles.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100µs, and then return to the
previous addressed memory data value. See Fig-
ure 11 for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a blockbeing erased and the data value on other
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output these five
Status Register bits. The P/E.C. automatically sets
Table 7. Commands
Toggle Bit (DQ6). When Programming or Erasing
operations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6 will
toggle following toggling of either G, or E when G
is low. The operation is completed when two suc-
cessive reads yield the same output data. The next
read will output the bit last programmed or a ’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100µs and then
return back to Read. DQ6 will be set to ’1’ if a Read
operation is attempted on an Erase Suspend block.
When erase is suspended DQ6 will toggle during
programming operations in a block different to the
block in Erase Suspend. Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
Hex Code
00h
Command
Invalid/Reserved
10h
Chip Erase Confirm
Reserved
20h
30h
Block Erase Resume/Confirm
Set-up Erase
80h
Read Electronic Signature/
Block Protection Status
90h
A0h
B0h
F0h
Program
Erase Suspend
Read Array/Reset
10/30
M29W008T, M29W008B
Table 8. Instructions (1)
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr. (3,7)
Data
X
1+
Read Memory Array until a new write cycle is initiated.
Read/Reset
RD (2,4) Memory
Array
F0h
Addr. (3,7) 5555h
Data AAh
Addr. (3,7) 5555h
2AAAh
55h
5555h
F0h
Read Memory Array until a new write cycle
is initiated.
3+
3+
2AAAh
5555h Read Electronic Signature or Block
Protection Status until a new write cycle is
90h
AS (4) Auto Select
initiated. See Note 5 and 6.
Data
Addr. (3,7) 5555h
Data AAh
Addr. (3,7) 5555h
AAh
55h
Program
Address
2AAAh
5555h
Read Data Polling or Toggle Bit
until Program completes.
PG
BE
Program
4
Program
Data
55h
A0h
Block
Additional
6
6
2AAAh
5555h
5555h
2AAAh
Address Block (8)
Block Erase
Chip Erase
Data
AAh
55h
2AAAh
55h
80h
5555h
80h
AAh
5555h
AAh
55h
2AAAh
55h
30h
5555h
10h
30h
Addr. (3,7) 5555h
CE
ES (10)
ER
Note 9
Data
AAh
X
Addr. (3,7)
Erase
Suspend
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
1
1
Data
B0h
X
Addr. (3,7)
Data
Erase
Resume
Read Data Polling or Toggle Bits until Erase completes or Erase
is suspended another time
30h
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation. (See Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code.
6. Block Protection Address: A0 at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A19 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered,
read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
11/30
M29W008T, M29W008B
Table 9. Status Register Bits
DQ
Name
Logic Level
Definition
Note
Erase Complete or erase
block in Erase Suspend
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Erase On-going
Data
Polling
7
Program Complete or data
of non erase block during
Erase Suspend
DQ
DQ
Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
DQ
Program Complete
6
Toggle Bit
Erase Complete or Erase
’-1-1-1-1-1-1-1-’ Suspend on currently
addressed block
acknowledged.
’1’
’0’
Program or Erase Error
This bit is set to ’1’ in the case of
Programming or Erase failure.
5
4
Error Bit
Program or Erase On-going
Reserved
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’1’
’0’
Erase Timeout Period Expired
Erase
Time Bit
3
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ’1’).
’-1-0-1-0-1-0-1-’
Indicates the erase status and allows to
identify the erased block
2
Toggle Bit
Program on-going, Erase
on-going on another block or
Erase Complete
1
Erase Suspend read on
non Erase Suspend block
DQ
1
0
Reserved
Reserved
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
12/30
M29W008T, M29W008B
Table 10. Polling and Toggle Bits
confirmation command. The Coded cycles consist
of writing the data AAh at address 5555h during the
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
2AAAh. A0 to A15 are valid, other address lines are
’don’t care’. The Coded cycles happen on first and
second cycles of the command write or on the
fourth and fifth cycles.
Mode
DQ7
DQ7
0
DQ6
DQ2
Program
Erase
Toggle
1
Toggle Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Instructions
See Table 8.
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ7
DQ6
DQ2
N/A
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by the
two Coded cycles. Subsequent read operations will
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. Asubsequent read will output the
manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the ASinstruction, A0
and A6 are set to VIL
define the address of the block to be verified. Aread
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 5555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if program-
ming is on-going and DQ5 allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dress being programmed.
Erase Suspend Program
Toggle
Note: 1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block erase
or program, the block in which the error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pear if a user tries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
still be used. The error bit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
with A1 at VIH, while A13-A19
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to ’1’.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
13/30
M29W008T, M29W008B
Table 11. AC Measurement Conditions
Figure 5. AC Testing Load Circuit
Input Rise and Fall Times
10ns
≤
0.8V
Input Pulse Voltages
0 to 3V
1.5V
1N914
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
3.3kΩ
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
3V
C
L
1.5V
0V
AI01417
C
includes JIG capacitance
L
AI01968
Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 13. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V
Min
Max
Unit
V
IN
V
CC
1
1
A
A
≤
≤
±
±
µ
µ
ILO
Output Leakage Current
Supply Current (Read) Byte
Supply Current (Standby)
0V ≤ VOUT ≤ VCC
ICC1
ICC3
E = VIL, G = VIH, f = 6MHz
10
mA
E = VCC 0.2V
100
A
µ
±
Byte program, Block or
Chip Erase in progress
(1)
ICC4
Supply Current (Program or Erase)
20
mA
VIL
VIH
VOL
VOH
VID
IID
Input Low Voltage
–0.5
0.8
V
V
V
V
V
Input High Voltage
0.7 VCC
VCC + 0.3
0.45
Output Low Voltage
IOL = 1.8mA
Output High Voltage CMOS
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
IOH = –100 A
VCC –0.4V
11.5
µ
12.5
100
A9 = VID
A
µ
Supply Voltage (Erase and
Program lock-out)
VLKO
2.0
2.3
V
Note: 1. Sampled only, not 100% tested.
14/30
M29W008T, M29W008B
Table 14A. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-90 -100
CC = 3.0V to 3.6V VCC = 2.7V to 3.6V
Test
Condition
Symbol
Alt
Parameter
Unit
V
CL = 30pF CL = 30pF
Min
Max
Min
Max
E = VIL,
G = VIL
tAVAV
tAVQV
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
90
100
ns
ns
E = VIL,
G = VIL
90
100
Chip Enable Low to Output
(1)
tELQX
tLZ
G = VIL
G = VIL
E = VIL
E = VIL
G = VIL
G = VIL
E = VIL
E = VIL
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transition
(2)
tELQV
tCE Chip Enable Low to Output Valid
90
35
30
30
100
40
Output Enable Low to Output
Transition
(1)
tGLQX
tOLZ
(2)
tGLQV
tOE Output Enable Low to Output Valid
Chip Enable High to Output
Transition
tEHQX
tOH
(1)
tEHQZ
tHZ Chip Enable High to Output Hi-Z
30
Output Enable High to Output
Transition
tGHQX
tOH
(1)
tGHQZ
tDF Output Enable High to Output Hi-Z
30
Address Transition to Output
Transition
E = VIL,
G = VIL
tAXQX
tOH
tRRB
(1,3)
tPLYH
RP Low to Read Mode
tREADY
10
10
s
µ
tPHEL
tPLPX
tRH RP High to Chip Enable Low
tRP RP Pulse Width
50
50
ns
ns
500
500
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
3. To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program mode.
.
15/30
M29W008T, M29W008B
Table 14B. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-120 -150
VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V
Test
Condition
Symbol
Alt
Parameter
Unit
Min
Max
Min
Max
E = VIL,
G = VIL
tAVAV
tAVQV
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
120
150
ns
ns
E = VIL,
G = VIL
120
150
Chip Enable Low to Output
Transition
(1)
tELQX
tLZ
G = VIL
G = VIL
E = VIL
E = VIL
G = VIL
G = VIL
E = VIL
E = VIL
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tELQV
tCE Chip Enable Low to Output Valid
120
50
150
55
Output Enable Low to Output
Transition
(1)
tGLQX
tOLZ
(2)
tGLQV
tOE Output Enable Low to Output Valid
Chip Enable High to Output
Transition
tEHQX
tOH
(1)
tEHQZ
tHZ Chip Enable High to Output Hi-Z
30
40
Output Enable High to Output
Transition
tGHQX
tOH
(1)
tGHQZ
tDF Output Enable High to Output Hi-Z
30
40
Address Transition to Output
Transition
E = VIL,
G = VIL
tAXQX
tOH
tRRB
(1,3)
tPLYH
RP Low to Read Mode
tREADY
10
10
s
µ
tPHEL
tPLPX
tRH RP High to Chip Enable Low
tRP RP Pulse Width
50
50
ns
ns
500
500
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
3. To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program mode.
.
16/30
M29W008T, M29W008B
Figure 6. Read Mode AC Waveforms
17/30
M29W008T, M29W008B
Table 15A. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-90
-100
Symbol
Alt
Parameter
Unit
V
CC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Min
90
0
Max
Min
100
0
Max
tAVAV
tELWL
tWC Address Valid to Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
tDS Input Valid to Write Enable High
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
tWPH Write Enable High to Write Enable Low
tAS Address Valid to Write Enable Low
tAH Write Enable Low to Address Transition
Output Enable High to Write Enable Low
tVCS VCC High to Chip Enable Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tVCHEL
tWHGL
45
45
0
50
50
0
0
0
30
0
30
0
45
0
50
0
50
0
50
0
s
µ
tOEH Write Enable High to Output Enable Low
tVIDR RP Rise Time to VID
ns
ns
ns
ns
(1,2)
tPHPHH
500
500
500
500
tPLPX
tRP RP Pulse Width
(1)
tWHRL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
90
90
(1)
tPHWL
4
4
s
µ
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
onthirdcycleafter thetwoCoded cycles. TheBlock
Erase Confirm command 30h is similarly written on
the sixth cycle after another two Coded cycles.
During the input of the second command an ad-
dress within the block to be erased is given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequently to erase other blocks in par-
allel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
Timer Bit DQ3 description). Thus, additional Erase
Confirm commands for other blocks must be given
within this delay. The input of a new Erase Confirm
commandwill restart the timeout period. Thestatus
of the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C.
is erasing the Block(s). If the second command
given is not an erase confirm or if the Coded cycles
are wrong, the instruction aborts, and the device is
reset to Read Array. It is not necessary to program
the block with 00h as the P/E.C. will do this auto-
matically beforetoerasingtoFFh. Read operations
after the sixth rising edge of W or E output the
status register status bits.
18/30
M29W008T, M29W008B
Table 15B. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-120
-150
Symbol
Alt
Parameter
Unit
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
Min
120
0
Max
Min
150
0
Max
tAVAV
tELWL
tWC Address Valid to Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
tDS Input Valid to Write Enable High
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
tWPH Write Enable High to Write Enable Low
tAS Address Valid to Write Enable Low
tAH Write Enable Low to Address Transition
Output Enable High to Write Enable Low
tVCS VCC High to Chip Enable Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tVCHEL
tWHGL
50
50
0
65
65
0
0
0
30
0
35
0
50
0
65
0
50
0
50
0
s
µ
tOEH Write Enable High to Output Enable Low
tVIDR RP Rise Time to VID
ns
ns
ns
ns
(1,2)
tPHPHH
tPLPX
500
500
500
500
tRP RP Pulse Width
(1)
tWHRL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
90
90
(1)
tPHWL
4
4
s
µ
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
During the execution of the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
the two Coded cycles. The Chip Erase Confirm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts and
the device is reset to Read Array. It is notnecessary
to program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh. Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tion of the erase by the P/E.C., Data Polling bit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stop when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has been
an Erase Failure.
Chip Erase (CE) Instruction. This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on the third cycle after
19/30
M29W008T, M29W008B
Figure 7. Write AC Waveforms, W Controlled
tAVAV
VALID
A0-A19
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7
V
CC
tVCHEL
RB
tWHRL
AI02192
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Erase Suspend (ES) Instruction. The Block
Erase operation may be suspended by this instruc-
tion which consists of writing the command B0h
without any specific address. No Coded cycles are
required. It permits reading of data from another
block and programming in another block while an
erase operation is in progress. Erase suspend is
accepted only during the Block Erase instruction
execution. Writing this command during Erase
timeout will, in addition to suspending the erase,
terminate the timeout. The Toggle bit DQ6 stops
toggling when the P/E.C. is suspended. The Toggle
bits will stop toggling between 0.1µs and 15µs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
pended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at ’1’. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data is being programmed. ARead/Reset
command will definitively abort erasure and result
in invalid data in the blocks being erased.
Erase Resume (ER) Instruction. If an Erase Sus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
20/30
M29W008T, M29W008B
Table 16A. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-90
-100
Unit
Symbol
Alt
Parameter
V
CC = 3.0V to 3.6V
VCC = 2.7V to 3.6V
CL = 30pF
CL = 30pF
Min
90
0
Max
Min
100
0
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
45
0
50
50
0
tDS
tDH
tWH
tCPH
tAS
0
0
30
0
30
0
tELAX
tGHEL
tVCHWL
tEHGL
tAH
45
0
50
0
tVCS
tOEH
tVIDR
tRP
50
0
50
0
s
µ
Chip Enable High to Output Enable Low
RP Rise TIme to VID
ns
ns
ns
ns
(1,2)
tPHPHH
500
500
500
500
tPLPX
RP Pulse Width
(1)
(1)
tEHRL
tPHWL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
90
90
4
4
s
µ
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
POWER SUPPLY
Power Up
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the VCC rail decoupled with a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
The memory Command Interface is reset on power
up to Read Array. Either E or W must be tied to VIH
during Power Up to allow maximum security and
the possibility to write a command on the first rising
edge of E and W. Any write cycle initiation is
blocked when Vcc is below VLKO
.
21/30
M29W008T, M29W008B
Table 16B. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
Unit
-120
CC = 2.7V to 3.6V
-150
Symbol
Alt
Parameter
V
VCC = 2.7V to 3.6V
Min
120
0
Max
Min
150
0
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
0
50
50
0
tDS
tDH
tWH
tCPH
tAS
0
0
20
0
20
0
tELAX
tGHEL
tVCHWL
tEHGL
tAH
50
0
50
0
tVCS
tOEH
tVIDR
tRP
50
0
50
0
s
µ
Chip Enable High to Output Enable Low
RP Rise TIme to VID
ns
ns
ns
ns
(1,2)
tPHPHH
tPLPX
500
500
500
500
RP Pulse Width
(1)
tEHRL
tPHWL
tBUSY Program Erase Valid to RB Delay
tRSP RP High to Write Enable Low
90
90
(1)
4
4
s
µ
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
22/30
M29W008T, M29W008B
Figure 8. Write AC Waveforms, E Controlled
tAVAV
VALID
A0-A19
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7
V
CC
tVCHWL
RB
tEHRL
AI02193
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Figure 9. Read and Write AC Characteristics, RP Related
E
tPHEL
W
tPHWL
RB
tPLPX
RP
tPHPHH
tPLYH
AI02091
23/30
M29W008T, M29W008B
Table 17A. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-90
-100
Sym-
Parameter
bol
Unit
V
CC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
ms
tWHQ7V
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
10
60
2400
60
1.0
10
60
2400
60
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
s
µ
tEHQ7V
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
1.0
sec
ns
tQ7VQV Q7 Valid to Output Valid (Data Polling)
35
2400
60
40
2400
60
Write Enable High to Output Valid (Program)
tWHQV
10
1.0
10
10
1.0
10
s
µ
Write Enable High to Output Valid (Chip Erase)
sec
Chip Enable High to Output Valid (Program)
tEHQV
2400
60
2400
60
s
µ
Chip Enable High to Output Valid (Chip Erase)
1.0
1.0
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
Table 17B. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
-120 -150
Sym-
bol
Parameter
Unit
V
CC = 2.7V to 3.6V
V
CC = 2.7V to 3.6V
CL = 100pF
CL = 100pF
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
ms
tWHQ7V
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
10
60
2400
60
1.0
10
60
2400
60
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
s
µ
tEHQ7V
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
1.0
sec
ns
tQ7VQV Q7 Valid to Output Valid (Data Polling)
50
2400
60
55
2400
60
Write Enable High to Output Valid (Program)
tWHQV
10
1.0
10
10
1.0
10
s
µ
Write Enable High to Output Valid (Chip Erase)
sec
Chip Enable High to Output Valid (Program)
tEHQV
2400
60
2400
60
s
µ
Chip Enable High to Output Valid (Chip Erase)
1.0
1.0
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
24/30
M29W008T, M29W008B
Figure 10. Data Polling DQ7 AC Waveforms
25/30
M29W008T, M29W008B
Figure 11. Data Polling Flowchart
Figure 12. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
NO
DQ2, DQ6
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ7
READ DQ2, DQ6
DQ7
=
DATA
YES
NO
DQ2, DQ6
=
TOGGLE
NO
YES
FAIL
PASS
FAIL
PASS
AI01369
AI01873
Table 18. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 2.7V to 3.6V)
M29W008T / M29W008B
Parameter
Unit
Typical after
100k W/E Cycles
Min
Typ
Max
Chip Erase (Preprogrammed)
Chip Erase
5
3.3
sec
sec
sec
sec
sec
sec
sec
12
2.4
2.3
2.7
3.3
8
Boot Block Erase
Parameter Block Erase
Main Block (32Kb) Erase
Main Block (64Kb) Erase
Chip Program (Byte)
Byte Program
15
8
10
10
s
µ
100,000
Program/Erase Cycles (per Block)
cycles
26/30
M29W008T, M29W008B
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms
27/30
M29W008T, M29W008B
ORDERING INFORMATION SCHEME
Example:
M29W008T
-90
N
1
TR
Operating Voltage
Option
W
2.7V to 3.6V
TR Tape & Reel
Packing
Array Matrix
Top Boot
Speed
-90 90ns
Package
Temp. Range
T
B
N
TSOP40
10 x 20mm
1
5
6
0 to 70 °C
Bottom Boot
-100 100ns
-120 120ns
-150 150ns
–20 to 85 °C
–40 to 85 °C
M29W008T and M29W008B are replaced respectively by the new version M29W008AT and
M29W008AB
Devices are shipped from the factory with the memory content erased (to FFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
28/30
M29W008T, M29W008B
TSOP40 Normal Pinout - 40 lead Plastic Thin Small Outline, 10 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
10.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.398
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
9.90
–
0.002
0.037
0.007
0.004
0.780
0.720
0.390
–
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
40
40
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
29/30
M29W008T, M29W008B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
30/30
相关型号：
©2020 ICPDF网 联系我们和版权申明