M29W008DT90N6F [STMICROELECTRONICS]
Flash, 1MX8, 90ns, PDSO40, 10 X 20 MM, LEAD FREE, PLASTIC, TSOP-40;
| 型号： | M29W008DT90N6F |
| 厂家： | 
ST |
| 描述： | Flash, 1MX8, 90ns, PDSO40, 10 X 20 MM, LEAD FREE, PLASTIC, TSOP-40 光电二极管 |
| 文件： | 总34页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29W008DT
M29W008DB
8 Mbit (1Mb x 8, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
■
SUPPLY VOLTAGE
Figure 1. Package
–
2.7V to 3.6V for Program, Erase and Read
■
■
■
ACCESS TIMES: 70ns, 90ns
PROGRAMMING TIME: 10µs per Byte typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
–
–
Embedded Byte Program Algorithm
Status Register bits and Ready/Busy
Output
■
19 MEMORY BLOCKS
–
–
1 Boot Block (Top or Bottom location)
2 Parameter and 16 Main Blocks
TSOP40 (N)
10 x 20mm
■
■
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTIPLE BLOCK PROTECTION/
TEMPORARY UNPROTECTION MODE
■
■
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION
–
Standby and Automatic Standby modes
■
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
–
Defectivity below 1ppm/year
■
ELECTRONIC SIGNATURE
–
–
–
Manufacturer Code: 20h
M29W008DT Device Code: D2h
M29W008DB Device Code: DCh
August 2004
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M29W008DT, M29W008DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block Addresses (Top Boot Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Addresses (Bottom Boot Block). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset/Block Temporary Unprotect Input (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
SS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standard Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protection and Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29W008DT, M29W008DB
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 15
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC AND AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10.Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Write AC Characteristics, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11.Write AC Waveforms, E Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Write AC Characteristics, E Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13.TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . 25
Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Top Boot Block Addresses, M29W008DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. Bottom Boot Block Addresses, M29W008DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APPENDIX B.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/34
M29W008DT, M29W008DB
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/34
M29W008DT, M29W008DB
SUMMARY DESCRIPTION
The M29W008D is a 8 Mbit (1Mb x 8) non-volatile
Flash memory that can be read, erased at block,
multi-block or chip level and programmed at Byte
level. These operations are performed using a sin-
gle 2.7V to 3.6V VCC supply voltage. For Program
and Erase operations the necessary high voltages
are generated internally. The device can also be
programmed using standard programming equip-
ment.
The memory is divided into blocks that are asym-
metrically arranged. Both M29W008DT and
M29W008DB devices have an array of 19 blocks
composed of one Boot Block of 16 KBytes, two
Parameter Blocks of 8 KBytes, one Main Block of
32 KBytes and fifteen Main Blocks of 64 KBytes. In
the M29W008DT, the Boot Block is located at the
top of the memory address space while in the
M29W008DB, it is located at the bottom. The
memory maps are showed in Figure 4., Block Ad-
dresses (Top Boot Block) and Figure 5., Block Ad-
dresses (Bottom Boot Block). Each block can be
erased and reprogrammed independently so it is
possible to preserve valid data while old data is
erased. Program and Erase commands are written
to the Command Interface of the memory. An on-
chip Program/Erase Controller simplifies the pro-
cess of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. Erase opera-
tions in one block can be temporarily suspended in
order to read from or program in blocks that are
not being erased. Each block can be programmed
and erased over 100,000 cycles.
Each block can be protected independently to pre-
vent accidental Program or Erase commands from
modifying the memory. All previously protected
blocks can be temporarily unprotected.
The device is offered in TSOP40 (10 x 20mm)
package and supplied with all the bits erased (set
to ’1’).
Table 1. Signal Names
Figure 2. Logic diagram
A0-A19
Address Inputs
V
CC
DQ0-DQ7
Data Input/Outputs, Command Inputs
Chip Enable
20
15
E
A0-A19
DQ0-DQ7
G
Output Enable
W
E
W
Write Enable
M29W008DT
M29W00DB
RP
RB
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
G
RB
RP
V
CC
V
Ground
SS
NC
Not Connected Internally
V
SS
AI08169
5/34
M29W008DT, M29W008DB
Figure 3. TSOP Connections
A16
A15
A14
A13
A12
A11
A9
1
40
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
A8
W
RP
NC
RB
A18
A7
10 M29W008DT 31
M29W008DB
V
V
CC
CC
11
30
NC
DQ3
DQ2
DQ1
DQ0
G
A6
A5
A4
A3
V
E
SS
A2
A1
20
21
A0
AI09440
6/34
M29W008DT, M29W008DB
Figure 4. Block Addresses (Top Boot Block)
M29W008DT
Top Boot Block Addresses
FFFFFh
FFFFFh
16 KByte BOOT BLOCK
FC000h
FBFFFh
F0000h
EFFFFh
8 KByte PARAMETER BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
FA000h
F9FFFh
E0000h
DFFFFh
8 KByte PARAMETER BLOCK
F8000h
D0000h
CFFFFh
F7FFFh
32 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
F0000h
AI09441
7/34
C0000h
BFFFFh
B0000h
AFFFFh
A0000h
9FFFFh
90000h
8FFFFh
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
Total of 16
64 KByte Blocks
80000h
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
10000h
0FFFFh
00000h
M29W008DT, M29W008DB
Figure 5. Block Addresses (Bottom Boot Block)
M29W008DB
Bottom Boot Block Addresses
FFFFFh
64 KByte MAIN BLOCK
F0000h
EFFFFh
64 KByte MAIN BLOCK
E0000h
DFFFFh
64 KByte MAIN BLOCK
D0000h
CFFFFh
64 KByte MAIN BLOCK
C0000h
BFFFFh
64 KByte MAIN BLOCK
B0000h
AFFFFh
64 KByte MAIN BLOCK
A0000h
9FFFFh
64 KByte MAIN BLOCK
90000h
8FFFFh
64 KByte MAIN BLOCK
Total of 16
64 KByte Blocks
80000h
7FFFFh
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
70000h
6FFFFh
60000h
5FFFFh
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK
50000h
4FFFFh
40000h
3FFFFh
0FFFFh
32 KByte MAIN BLOCK
08000h
07FFFh
30000h
2FFFFh
8 KByte PARAMETER BLOCK
8 KByte PARAMETER BLOCK
06000h
05FFFh
20000h
1FFFFh
64 KByte MAIN BLOCK
10000h
0FFFFh
04000h
03FFFh
16 KByte BOOT BLOCK
00000h
00000h
AI09442a
8/34
M29W008DT, M29W008DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The address inputs
for the memory array are latched during a Bus
Write operation on the falling edge of Chip Enable,
E or Write Enable, W. When A9 is raised to VID, ei-
ther a Read Electronic Signature Manufacturer or
Device Code, Block Protection Status or a Write
Block Protection or Block Unprotection is enabled
depending on the combination of levels on A0, A1
A6, A12 and A15.
is high impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high impedance. See Table 14., Reset/
Block Temporary Unprotect AC Characteristics
and Figure 12., Reset/Block Temporary Unprotect
AC Waveforms.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
Data Input/Outputs (DQ0-DQ7). During
Bus
Reset/Block Temporary Unprotect Input (RP).
Write operations, the Data Inputs/Outputs input
the data to be programmed in the memory array or
a command to be written to the Command Inter-
face. Both are latched on the rising edge of Chip
Enable, E or Write Enable, W. The Data Inputs/
Outputs output the data stored at the selected ad-
dress during a Bus Read operation, the Electronic
Signature (Manufacturer or Device codes), the
Block Protection Status or the Data Polling bit
(DQ7), Toggle Bits (DQ6) and DQ2), Error bit
(DQ5) or Erase Timer bit (DQ3) of the Status Reg-
ister. Outputs are valid when Chip Enable, E and
Output Enable, G are active. The output is high im-
pedance when the chip is deselected or the out-
puts are disabled and when RP is Low.
Chip Enable (E). The Chip Enable, E, activates
the memory control logic, input buffers, decoders
and sense amplifiers. When Chip Enable is High,
VIH, the memory is deselected and the power con-
sumption is reduced to the Standby level. The
Chip Enable, E, can also be used to control Write
operations to the command register and to the
memory array, while W remains Low. The Chip
Enable must be forced to VID during Block Unpro-
tection operations.
The Reset/Block Temporary Unprotect input, RP,
can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all blocks that
have been previously protected.
A Hardware Reset is achieved by holding RP Low,
VIL for at least tPLPX. After Reset/Block Temporary
Unprotect goes High, VIH, if the device is in Read
or Standby mode, it will be ready for new opera-
tions tPHEL after the rising edge of RP. If the device
is in Erase, Erase Suspend or Program mode, the
Hardware Reset will last tPLYH during which the
RB signal will be held at VIL. The end of the mem-
ory Hardware Reset will be indicated by the rising
edge of RB. A Hardware Reset during an Erase or
Program operation will corrupt the data being pro-
grammed or the blocks being erased. See Table
14., Reset/Block Temporary Unprotect AC Char-
acteristics and Figure 12., Reset/Block Temporary
Unprotect AC Waveforms.
Holding RP at VID will temporarily unprotect the
previously protected blocks in the memory. Pro-
gram and Erase operations on all blocks will be
possible. The transition of RP from VIH to VID must
slower than tPHPHH
.
When RP is returned from VID to VIH all blocks
temporarily unprotected will be again protected.
VCC Supply Voltage. The power supply for all
Output Enable (G). The Output Enable, G, gates
the outputs through the data buffers during a Bus
Read operation. When G is High, VIH, the outputs
are high impedance. G must be forced to VID dur-
ing Block Protection and Unprotection operations.
Write Enable (W). This Write Enable, W, controls
write operations of the memory’s Command Inter-
face.
operations (Read, Program and Erase).
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC3
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
VSS Ground. VSS is the reference for all voltage
measurements.
9/34
M29W008DT, M29W008DB
BUS OPERATIONS
There are 5 standard bus operations that control
the device. These are Bus Read, us Write, Output
Disable, Standby and Automatic Standby. See Ta-
ble 2., Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect the bus operations.
are high impedance, independent of the Output
Enable G or Write Enable W inputs.
Automatic Standby. If CMOS levels (VCC
±
0.2V) are used to drive the bus and if the bus is in-
active (no address transition, E = VIL) during
150ns or more, the memory automatically enters a
Automatic Standby mode where the Supply Cur-
rent is reduced to the Standby Supply Current,
Standard Bus Operations
I
CC2. The Inputs/Outputs will still output data if a
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register or the Block
Protection Status. Both Chip Enable E and Output
Enable G must be Low in order to read the output
of the memory. A new Bus Read operation is initi-
ated either on the falling edge of Chip Enable, E,
or on any address transition with E at VIL.
Bus Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require VID to be applied to some pins.
Read Electronic Signature. The memory has
two codes, the Manufacturer code and the Device
code, that can be read to identify the memory.
These codes allow programming equipment or ap-
plications to automatically match their interface to
the characteristics of the M29W008D.
The electronic Signature is output either by apply-
ing the signals listed in Table 2., Bus Operations
or by issuing an Auto Select command (see Auto
Select command description in the XX section).
Block Protection and Unprotection. Each
block can be individually protected against acci-
dental Program or Erase using programming
equipment. Protected blocks can be unprotected
to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment (Programmer Technique)
and the other for in-system use (In-System Tech-
nique). Block Protect and Chip Unprotect opera-
tions are described in APPENDIX B., BLOCK
PROTECTION.
See Figure 9., Read Mode AC Waveforms, and
Tables Table 11., Read AC Characteristics for de-
tails of the timing requirements.
Bus Write. Bus Write operations are used to write
to the Command Interface or to latch input data to
be programmed. A valid Bus Write operation be-
gins by setting the desired address on the Address
Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip En-
able or Write Enable, whichever occurs last. The
Data Inputs/Outputs are latched by the Command
Interface on the rising edge of Chip Enable or
Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation.
See Figures 10 and 11, Write AC Waveforms and
Tables 12 and 13, Write AC Characteristics, for
details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is High with
Write Enable W High.
Standby. The memory is in Standby mode when
Chip Enable, E, is High and the Program/Erase
Controller is idle. The Supply Current is reduced to
the Standby Supply Current, ICC2, and the outputs
10/34
M29W008DT, M29W008DB
Table 2. Bus Operations
Operation
DQ0-
DQ7
E
G
W
RP
Address Inputs A0-A19
Data
Output
V
V
V
V
Byte Read
Byte Write
Cell Address
IL
IL
IH
IH
Data
Input
V
V
V
V
V
V
IH
Command Address
IL
IL
IH
IH
IL
V
V
V
IH
Output Disable
Standby
X
X
Hi-Z
Hi-Z
IH
V
IH
X
X
IH
A0= V , A1= V , A9=V ,
others address bits are ‘Don’t Care’
IL
IL
ID
V
V
V
V
V
V
Manufacturer Code
Read
20h
IL
IL
IL
IL
IH
IH
IH
Electronic
M29W008DT
M29W008DB
D2h
DCh
A0= V , A1= V , A9=V ,
Device
Code
IH
IL
ID
signature
V
V
IH
others address bits are ‘Don’t Care’
Note: 1. X = V or V
.
IH
IL
11/34
M29W008DT, M29W008DB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface.
eration latches the address and data and starts the
Program/Erase Controller.
Commands consist of one or more sequential Bus
Write operations. Failure to observe a valid se-
quence of Bus Write operations will result in the
memory returning to Read mode. The long com-
mand sequences are imposed to maximize data
security. All commands start with two coded cycles
which unlock the Command Interface.
Seven commands are available: Read/Reset,
Auto Select (to read the Electronic Signature and
the Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re-
sume (see Table 3., Commands).
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4., Program,
Erase Times and Program, Erase Endurance Cy-
cles. Bus Read operations during the program op-
eration will output the Status Register on the Data
Inputs/Outputs. See STATUS REGISTER section
for more details.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another com-
mand is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
and starts the Program/Erase Controller.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL, A1
= VIH, and A13-A19 specifying the address of the
block. The other address bits may be set to either
VIL or VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
12/34
M29W008DT, M29W008DB
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical program
times are given in Table 4., Program, Erase Times
and Program, Erase Endurance Cycles. All Bus
Read operations during the Chip Erase operation
will output the Status Register on the Data Inputs/
Outputs. See the section on the Status Register
for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency Time after the Erase
Suspend Command is issued (see Table
4., Program, Erase Times and Program, Erase
Endurance Cycles). Once the Program/Erase
Controller has stopped the memory will be set to
Read mode and the Erase will be suspended. If
the Erase Suspend command is issued during the
period when the memory is waiting for an addition-
al block (before the Program/Erase Controller
starts) then the Erase is suspended immediately
and will start immediately when the Erase Resume
Command is issued. It is not possible to select any
further blocks to erase after the Erase Resume.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical program times are given in Ta-
ble 4., Program, Erase Times and Program, Erase
Endurance Cycles. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
13/34
M29W008DT, M29W008DB
Table 3. Commands
(3,7)
Bus Write Operations
3rd 4th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data
F0h Read Memory Array until a new write cycle is initiated.
Command
1st
2nd
5th
6th
7th
1+
X
(2,4)
Read/Reset
3+ 555h AAh 2AAh 55h 555h F0h Read Memory Array until a new write cycle is initiated.
Read Electronic Signature or Block Protection Status
3+ 555h AAh 2AAh 55h 555h 90h
(4)
Auto Select
Program
until a new write cycle is initiated. See Note 5 and 6.
Read Data Polling or Toggle Bit until
Program completes.
4
3
2
555h AAh 2AAh 55h 555h A0h
555h AAh 2AAh 55h 555h 20h
PA
PD
Unlock Bypass
Unlock Bypass
Program
X
X
A0h
90h
PA
X
PD
Unlock Bypass
Reset
2
6
00h
Chip Erase
Block Erase
555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
BA 30h
Note 9
(8)
6+ 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h
30h
AB
Read until Toggle stops, then read all the data needed from any Block(s) not being
erased then Resume Erase.
(10)
1
1
X
X
B0h
30h
Erase Suspend
Erase Resume
Read Data Polling or Toggle Bits until Erase completes or Erase is suspended
another time.
Note: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of t is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
PLYH
operation (see Table 11., Read AC Characteristics).
3. X = Don't Care. PA = Program Address, PD = Program Data, BA = Block Address, AB = Additional Block
4. The first cycles of the Read/Reset and Auto Select commands are followed by read operations. Any number of read cycles can
occur after the command cycles.
5. Signature Address bits A0, A1, at V will output the Manufacturer Code (20h). Address bits A0 at V and A1, at V will output the
IL
IH
IL
Device Code.
6. Block Protection Address: A0, at V , A1 at V and A13-A19 within the Block will output the Block Protection status.
IL
IH
7. For Coded cycles address inputs A15-A19 are don't care.
8. Optional, Additional Block (AB) addresses must be entered within the erase time-out delay after last write entry, time-out status can
be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle
bit until Erase has completed or is suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
14/34
M29W008DT, M29W008DB
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
(1, 2)
(2)
Parameter
Min
Unit
s
Typ
12
Max
(3)
Chip Erase
60
(4)
Block Erase (64 KBytes)
0.8
15
10
12
s
6
(3)
Erase Suspend Latency Time
Program (Byte)
µs
µs
25
(3)
200
(3)
Chip Program (Byte by Byte)
Program/Erase Cycles (per Block)
Data Retention
s
60
100,000
20
cycles
years
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.
CC
4. Maximum value measured at worst case conditions for both temperature and V
.
CC
15/34
M29W008DT, M29W008DB
STATUS REGISTER
The status of the Program/Erase Controller during
command execution is indicated by bit DQ7 (Data
Polling bit), Toggle bits DQ6 and DQ2 and Error
bits DQ3 and DQ5. Any attempt to read the memo-
ry array during Program or Erase command execu-
tion will automatically output these five Status
Register bits. The Program/Erase Controller auto-
matically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7.
Other bits (DQ0, DQ1 and DQ4) are reserved for
future use and should be masked (see Table
5., Status Register Bits).
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation
or if it has responded to an Erase Suspend. The
Data Polling Bit is output on DQ7 when the Status
Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to Read
mode and Bus Read operations from the address
just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 6., Data Polling Flowchart gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
suspended block, the operation is aborted, no error
is signalled and DQ6 toggles for approximately
1µs.
Figure 7., Data Toggle Flowchart gives an exam-
ple of how to use the Data Toggle bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase Con-
troller. The Error Bit is set to ’1’ when a Program,
Block Erase or Chip Erase operation fails to write
the correct data to the memory. If the Error Bit is set
a Read/Reset command must be issued before
other commands are issued. The Error bit is output
on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase Con-
troller operation during a Block Erase command.
Once the Program/Erase Controller starts erasing
the Erase Timer Bit is set to ’1’. Before the Pro-
gram/Erase Controller starts the Erase Timer Bit is
set to ’0’ and additional blocks to be erased may be
written to the Command Interface. The Erase Tim-
er Bit is output on DQ3 when the Status Register is
read.
Alternative Toggle Bit (DQ2). The
Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the Sta-
tus Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block is
treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memory
returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations
from addresses within blocks that have not erased
correctly. The Alternative Toggle Bit does not
change if the addressed block has erased correct-
ly.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
16/34
M29W008DT, M29W008DB
Table 5. Status Register Bits
Operation
Program
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Any Address
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
Note: 1. Unspecified data bits should be ignored.
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
= 1
YES
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
YES
FAIL
PASS
PASS
AI03598
AI01370C
17/34
M29W008DT, M29W008DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
T
Temperature Under Bias
Storage Temperature
–50 to 125
–65 to 150
BIAS
T
°C
STG
(1)
(2)
T
°C
LEAD
Lead Temperature during Soldering
Input or Output Voltage
Supply Voltage
260
(3)
–0.6 to 5
–0.6 to 5
V
V
V
V
IO
V
CC
(4)
Identification Voltage
–0.6 to 13.5
V
ID
1. Compliant with the ST 7191395 specification for Lead-free soldering processes.
2. Not exceeding 250°C for more than 30s, and peaking at 260°C.
3.
V
and V may undershoot to –2V during transition and for less than 20ns during transitions.
ID IO
18/34
M29W008DT, M29W008DB
DC AND AC CHARACTERISTICS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 7, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 7. Operating and AC Measurement Conditions
M29W008D
Parameter
70
90
Unit
Min
Max
3.6
85
Min
2.7
–40
0
Max
3.6
85
V
Supply Voltage
2.7
–40
0
V
CC
Ambient Operating Temperature (range 6)
Ambient Operating Temperature (range 1)
°C
70
70
Load Capacitance (C )
30
100
pF
ns
V
L
Input Rise and Fall Times
10
10
0 to V
0 to V
Input Pulse Voltages
CC
CC
V
CC
/2
V
/2
CC
Input and Output Timing Ref. Voltages
V
Table 8. AC Testing Input Output Waveform
Figure 8. AC Testing Load Circuit
0.8V
V
CC
1N914
V
CC/2
0V
3.3kΩ
AI09444
DEVICE
UNDER
TEST
OUT
C
L
C
includes JIG capacitance
L
AI09445
Table 9. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
IN
= 0V
= 0V
IN
C
V
OUT
12
pF
OUT
Note: 1. Sampled only, not 100% tested.
19/34
M29W008DT, M29W008DB
Table 10. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Test Condition
Min
Max
±1
Unit
µA
I
LI
0V ≤ V ≤ V
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
±1
µA
I
E = V , G = V , f = 6MHz
IL IH
10
mA
CC1
E = V ±0.2V
CC
I
Supply Current (Standby)
100
µA
CC2
RP = V ±0.2V
CC
Supply Current
(Program or Erase)
Program,/ Erase Controller
active
(1)
20
mA
I
CC3
V
Input Low Voltage
–0.5
0.8
V
V
IL
V
V
0.7 V
V
+ 0.3
CC
Input High Voltage
IH
CC
I
OL
= 1.8mA
Output Low Voltage
0.45
V
OL
V
I
= –100µA
V
–0.4V
CC
Output High Voltage CMOS
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
V
OH
OH
V
11.5
12.5
100
V
ID
ID
I
A9 = V
µA
ID
Supply Voltage (Erase and Program
lock-out)
(1)
1.8
2.3
V
V
LKO
Note: 1. Sampled only, not 100% tested.
Figure 9. Read Mode AC Waveforms
tAVAV
VALID
A0-A19
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
VALID
DQ0-DQ7
AI09446
20/34
M29W008DT, M29W008DB
Table 11. Read AC Characteristics
M29W008D
Symbol
Alt
Parameter
Test Condition
Unit
70
90
E = V ,
IL
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
70
90
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
70
90
AVQV
G = V
G = V
G = V
E = V
IL
IL
IL
(1)
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Min
Max
Min
0
0
ns
ns
ns
ns
ns
t
LZ
ELQX
t
t
70
0
90
0
ELQV
CE
(1)
t
t
t
OLZ
IL
IL
GLQX
t
t
E = V
Max
Max
30
25
35
30
GLQV
OE
(1)
t
G = V
HZ
DF
IL
IL
EHQZ
GHQZ
(1)
t
E = V
Output Enable High to Output Hi-Z
Max
Min
25
0
30
0
ns
ns
t
t
t
EHQX
Chip Enable, Output Enable or Address
Transition to Output Transition
t
GHQX
OH
t
AXQX
Note: 1. Sampled only, not 100% tested.
2. Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Figure 10. Write AC Waveforms, W Controlled
tAVAV
A0-A19
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
W
tGHWL
tWLWH
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7
V
CC
tVCHEL
RB
AI02192
tWHRL
21/34
M29W008DT, M29W008DB
Table 12. Write AC Characteristics, W Controlled
M29W008D
Symbol
Alt
Parameter
Unit
70
70
0
90
90
0
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
CS
ELWL
t
t
45
45
0
50
50
0
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
WHDX
t
0
0
WHEH
t
t
WPH
30
0
30
0
WHWL
t
t
AS
AVWL
t
t
45
0
50
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
WHGL
(1)
t
30
50
35
50
t
BUSY
WHRL
t
t
V
High to Chip Enable Low
CC
Min
µs
VCHEL
VCS
Note: 1. Sampled only, not 100% tested.
Figure 11. Write AC Waveforms, E Controlled
tAVAV
VALID
A0-A19
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7
V
CC
tVCHWL
RB
tEHRL
Note: 1. Address are latched on the falling edge of E, Data is latched on the rising edge of E.
AI02193
22/34
M29W008DT, M29W008DB
Table 13. Write AC Characteristics, E Controlled
M29W008D
Unit
Symbol
Alt
Parameter
70
70
0
90
90
0
t
t
WC
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
WS
WLEL
t
t
45
45
0
50
50
0
ELEH
CP
DS
DH
t
t
t
DVEH
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
Program/Erase Valid to RB Low
EHDX
t
t
WH
0
0
EHWH
t
t
30
0
30
0
EHEL
CPH
t
t
AS
AVEL
t
t
45
0
50
0
ELAX
AH
t
GHEL
t
t
0
0
EHGL
OEH
(1)
t
30
50
35
50
t
BUSY
EHRL
t
t
V
High to Write Enable Low
CC
Min
µs
VCHWL
VCS
Note: 1. Sampled only, not 100% tested.
Figure 12. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI09447
23/34
M29W008DT, M29W008DB
Table 14. Reset/Block Temporary Unprotect AC Characteristics
M29W008D
Symbol
Alt
Parameter
Unit
70
90
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
t
Min
Min
50
50
ns
PHEL
RH
(1)
t
PHGL
(1)
(1)
(1)
t
t
RHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
0
0
ns
t
RB
RHEL
RHGL
t
t
RP Pulse Width
Min
500
10
500
10
ns
µs
PLPX
RP
(1)
t
RP Low to Read Mode
Max
t
READY
PLYH
(1)
t
RP Rise Time to V
Min
500
500
ns
t
VIDR
ID
PHPHH
Note: 1. Sampled only, not 100% tested.
24/34
M29W008DT, M29W008DB
PACKAGE MECHANICAL
Figure 13. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
α
L
Table 15. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
0.100
20.200
18.500
–
Typ
Max
0
A
A1
A2
B
0.050
0.950
0.170
0.100
0
0
0
0
0
0
0
C
0
CP
D
0
19.800
18.300
–
1
1
–
0
0
0
1
D1
e
1
0.500
0
–
E
9.900
0.500
0
10.100
0.700
5
0
L
0
5
α
N
40
40
25/34
M29W008DT, M29W008DB
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M29W008DT
70
N
1
T
Device Type
M29
Operating Voltage
W = 2.7 to 3.6V
Device Function
008D = 8 Mbit (1Mb x8), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70ns
90 = 90ns
Package
N = TSOP40: 10 x 20 mm
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing, 24mm
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing, 24mm
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
26/34
M29W008DT, M29W008DB
APPENDIX A. BLOCK ADDRESS TABLE
Table 17. Top Boot Block Addresses,
M29W008DT
Table 18. Bottom Boot Block Addresses,
M29W008DB
Size
(Kbytes)
Address Range
(x8)
Size
(Kbytes)
Address Range
(x8)
#
#
18
17
16
15
14
13
12
11
10
9
16
8
FC000h-FFFFFh
FA000h-FBFFFh
F8000h-F9FFFh
F0000h-F7FFFh
E0000h-EFFFFh
D0000h-DFFFFh
C0000h-CFFFFh
B0000h-BFFFFh
A0000h-AFFFFh
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
18
17
16
15
14
13
12
11
10
9
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
8
F0000h-FFFFFh
E0000h-EFFFFh
D0000h-DFFFFh
C0000h-CFFFFh
B0000h-BFFFFh
A0000h-AFFFFh
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
8
0
0
16
27/34
M29W008DT, M29W008DB
APPENDIX B. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the tech-
niques for AMD parts will not work on STMicro-
electronics parts. Care should be taken when
changing drivers for one part to work on another.
Technique Bus Operations, gives a summary of
each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the Flash has been fitted to the sys-
tem.
To protect a block follow the flowchart in Figure 16,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Fig-
ure 17, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Programmer Technique
The Programmer technique uses high (VID) volt-
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 14,
Programmer Equipment Block Protect Flowchart.
To unprotect the whole chip it is necessary to pro-
tect all of the blocks first, then all blocks can be un-
protected at the same time. To unprotect the chip
follow Figure 15, Programmer Equipment Chip
Unprotect Flowchart. Table 19, Programmer
Table 19. Programmer Technique Bus Operations
Address Inputs
A0-A18
Data Inputs/Outputs
DQ7-DQ0
Operation
E
G
W
A9 = V , A13-A19= Block Address
ID
V
V
V
V
Pulse
Pulse
Block Protect
X
X
IL
ID
IL
Others = X
A9 = V , A13 = V , A16 = V
ID
IH
IH
V
V
ID
Chip Unprotect
ID
IL
Others = X
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IL
ID
Block Protection
Verify
Pass = 01h
Retry = 00h
V
V
V
V
A13-A19= Block Address
Others = X
IL
IL
IL
IL
IH
IH
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IH
ID
Block Unprotection
Verify
Retry = 01h
Pass = 00h
V
V
A13-A19= Block Address
Others = X
28/34
M29W008DT, M29W008DB
Figure 14. Programmer Equipment Block Protect Flowchart
START
ADDRESS = BLOCK ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
,
IH
A0, A6 = V
A1 = V
,
IL
IH
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
E, G = V
IH
IH
YES
PASS
A9 = V
IH
E, G = V
IH
AI09448
FAIL
29/34
M29W008DT, M29W008DB
Figure 15. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
(1)
A6, A13, A16 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1, A6 = V
IL
IH
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT BLOCK
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
BLOCK
NO
NO
++n
= 1000
YES
YES
A9 = V
IH
A9 = V
IH
E, G = V
E, G = V
IH
IH
FAIL
PASS
AI09449
30/34
M29W008DT, M29W008DB
Figure 16. In-System Equipment Block Protect Flowchart
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
Wait 100µs
WRITE 40h
IL
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
DATA
NO
=
01h
YES
++n
= 25
NO
RP = V
IH
YES
ISSUE READ/RESET
COMMAND
RP = V
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI09450
31/34
M29W008DT, M29W008DB
Figure 17. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 4µs
INCREMENT
CURRENT BLOCK
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
DATA
NO
YES
=
00h
++n
= 1000
NO
NO
LAST
BLOCK
YES
YES
RP = V
IH
RP = V
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI09451
32/34
M29W008DT, M29W008DB
REVISION HISTORY
Table 20. Document Revision History
Date
Version
Revision Details
16-Apr-2004
0.1
First Issue.
Figure 5., Block Addresses (Bottom Boot Block), modified.
Unlock Bypass command addresses and data modified in Table 3., Commands.
08-Jun-2004
05-Aug-2004
0.2
1.0
Datasheet status changed to “Full Datasheet”.
33/34
M29W008DT, M29W008DB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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34/34
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