M29W040-100N6TR [STMICROELECTRONICS]
4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory; 4兆位512KB ×8 ，统一座低压单电源闪存
| 型号： | M29W040-100N6TR |
| 厂家： | 
ST |
| 描述： | 4 Mbit 512Kb x8, Uniform Block Low Voltage Single Supply Flash Memory |
| 文件： | 总31页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29W040
4 Mbit (512Kb x8, Uniform Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W040 is replaced by the M29W040B
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
BYTE PROGRAMMING TIME: 12µs typical
ERASE TIME
– Block: 1.5 sec typical
– Chip: 2.5 sec typical
PLCC32 (K)
TSOP32 (N)
8 x 20mm
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Data Polling and Toggle bits Protocol for
P/E.C. Status
MEMORY ERASE in BLOCKS
– 8 Uniform Blocks of 64 KBytes each
– Block Protection
TSOP32 (NZ)
8 x 14mm
– Multiblock Erase
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION
– Read mode: 8mAtypical (at 12MHz)
– Stand-by mode: 20µAtypical
– AutomaticStand-by mode
Figure 1. Logic Diagram
POWER DOWN SOFTWARE COMMAND
– Power-down mode: 1µA typical
100,000PROGRAM/ERASE CYCLES per
BLOCK
V
CC
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: E3h
19
8
A0-A18
DQ0-DQ7
W
E
M29W040
Table 1. Signal Names
A0-A18
Address Inputs
Data Input / Outputs
Chip Enable
G
DQ0-DQ7
E
V
SS
G
Output Enable
Write Enable
Supply Voltage
Ground
AI02074
W
VCC
VSS
November 1999
1/31
This is informationon a product still in productionbut not recommendedfor new designs.
M29W040
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
A11
A9
1
32
G
A10
E
A8
1 32
A13
A14
A17
W
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A14
A13
A8
A6
A5
A4
A9
V
8
9
25
24
M29W040
(Normal)
CC
A3
A2
9
M29W040
25 A11
G
A18
V
SS
A16
A15
A12
A7
DQ2
DQ1
DQ0
A0
A1
A10
E
A0
DQ0
DQ7
17
A6
A1
A5
A2
A4
16
17
A3
AI02075
AI02076
Figure 2C. TSOP Reverse Pin Connections
DESCRIPTION
The M29W040 is a non-volatile memory that may
be erased electrically at the block level, and pro-
grammed Byte-by-Byte.
The interface is directly compatible with most mi-
croprocessors. PLCC32,TSOP32(8 x 20mm)and
TSOP32 (8 x 14mm) packagesare available. Both
normal and reverse pin outs are available for the
TSOP32 (8 x 20mm) package.
G
A10
E
A11
A9
1
32
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
A17
W
Organisation
TheFlashMemoryorganisationis512Kx8 bitswith
Address lines A0-A18 and Data Inputs/Outputs
DQ0-DQ7. Memory control is provided by Chip
Enable, Output Enable and Write Enable Inputs.
8
9
25
24
V
M29W040
(Reverse)
CC
V
A18
A16
A15
A12
A7
SS
DQ2
DQ1
DQ0
A0
Erase and Program are performed through the
internal Program/Erase Controller (P/E.C.).
Data Outputs bits DQ7 and DQ6 provide polling or
toggle signals during Automatic Program or Erase
to indicate the Ready/Busy state of the internal
Program/EraseController.
A1
A6
A2
A5
Memory Blocks
A3
16
17
A4
Erasure of the memory is in blocks. There are 8
uniform blocks of 64 Kbytes each in the memory
address space. Each block can be programmed
and erased over 100,000 cycles. Each uniform
AI02077
2/31
M29W040
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
–40 to 85
–50 to 125
–65 to 150
–0.6 to 5
Unit
Ambient Operating Temperature(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
C
°
TBIAS
TSTG
°C
C
°
(2)
VIO
V
VCC
–0.6 to 5
V
V
(2)
VA9
A9 Voltage
–0.6 to 13.5
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in theTable ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltagemay undershootto –2V during transition and for less than 20ns.
3. Depends on range.
block may separately be protected and unpro-
tected against program and erase. Block erasure
may be suspended, while data is read from other
blocks of the memory, and then resumed.
instructionsandprovidesData Polling,Toggle,and
Statusdata to indicate completion of Programand
Erase Operations.
Instructionsare composed of up to six cycles. The
first two cycles input a code sequenceto theCom-
mand Interface which is common to all P/E.C.
instructions (see Table 7 for Command Descrip-
tions). The third cycle inputs the instruction set up
command instruction to the Command Interface.
Subsequentcycles outputSignature,BlockProtec-
tion or the addressed data for Read operations.
For added data protection,the instructions for pro-
gram, and blockor chiperase require furthercom-
mand inputs. For a Programinstruction, the fourth
command cycle inputs the address and data to be
programmed. For an Erase instruction (block or
chip),the fourthand fifthcyclesinputa furthercode
sequence before the Erase confirm command on
the sixth cycle. Byte programming takes typically
12µs while erase is performed in typically 1.5 sec-
ond.
Erasure of a memory block may be suspended,in
order to read data from another block, and then
resumed.Data Polling, Toggleand Errordata may
be read at any time, including during the program-
ming or erase cycles, to monitor the progress of
the operation.When power is first applied or if VCC
fallsbelowVLKO, the command interfaceis resetto
Read Array.
Bus Operations
Seven operations can be performed by the appro-
priate bus cycles, Read Array, Read Electronic
Signature,Output Disable, Standby,ProtectBlock,
Unprotect Block, and Write the Command of an
Instruction.
Command Interface
Command Bytes can be written to a Command
Interface(C.I.) latch to perform Reading (from the
Array or Electronic Signature), Erasure or Pro-
gramming. For added data protection, command
execution starts after 4 or 6 command cycles. The
first, second, fourth and fifth cycles are used to
input a code sequence to the Command Interface
(C.I.). Thissequence is equal for all P/E.C. instruc-
tions. Command itself and its confirmation - if it
applies - are given on the third and fourth or sixth
cycles.
Instructions
Eight instructions are defined to perform Reset,
Read Electronic Signature, Auto Program, Block
Auto Erase, Chip Auto Erase, Block Erase Sus-
pend, Block Erase Resumeand Power Down. The
internalProgram/EraseController(P/E.C.)handles
all timingand verificationof theProgramandErase
3/31
M29W040
Table 3. Operations
Operation
Read
E
G
VIL
VIH
VIH
X
W
VIH
VIL
VIH
X
DQ0 - DQ7
Data Output
Data Input
Hi-Z
VIL
VIL
VIL
VIH
Write
Output Disable
Standby
Hi-Z
Note:
X = VIL or VIH
Table 4. Electronic Signature
Other
Addresses
Code
E
G
W
A0
A1
A6
A9
DQ0 - DQ7
Manufact. Code
Device Code
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIL
VIL
VID
VID
Don’t Care
Don’t Care
20h
E3h
Table 5. Block Protection Status
Other
Addresses
Code
E
G
W
A0
A1
A6
A16 A17 A18
DQ0 - DQ7
Protected Block
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
SA
SA
SA
SA
SA
SA
Don’t Care
Don’t Care
01h
00h
Unprotected Block
Note: SA = Address of block being checked
DEVICE OPERATION
Signal Descriptions
when the chip is deselected or the outputs are
disabled.
Chip Enable (E). The Chip Enable activates the
memory control logic, input buffers, decoders and
senseamplifiers.EHighdeselectsthememoryand
reduces the power consumption to the standby
level. E can also be used to control writing to the
command registerand to the memory array, while
W remains at a low level. Addresses are then
latchedon thefallingedgeofEwhiledataislatched
on the rising edge of E. The Chip Enable must be
forced to VID during Block Unprotect operations.
Address Inputs (A0-A18). Theaddress inputs for
the memory arrayare latchedduring a write opera-
tion. The A9 address input is used also for the
Electronic Signature read and BlockProtect veri-
fication. When A9 is raised to VID, either a Read
Manufacturer Code, Read Device Code or Verify
Block Protectionis enableddependingon thecom-
bination of levelson A0, A1 and A6. When A0, A1
and A6 areLow,the ElectronicSignatureManufac-
turer code is read,when A0 is High and A1 and A6
are Low, the Device code is read, and when A1 is
High and A0 and A6 are low, the Block Protection
Status with protect/unprotectalgorithm is read for
the blockaddressed by A16, A17, A18.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read
operation. G must be forced to VID level during
Block Protect and Block Unprotectoperations.
Data Input/Outputs (DQ0-DQ7). Thedata inputis
a byte to be programmed or a command written to
the C.I. Both are latched when Chip Enable E and
Write EnableW are active. The dataoutput is from
the memory Array, the Electronic Signature, the
Data Polling bit (DQ7), the Toggle Bit (DQ6), the
Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-
puts are valid when Chip Enable E and Output
EnableG are active.The outputis highimpedance
Write Enable(W). This input controlswritingto the
CommandRegisterand AddressandData latches.
Addressesare latchedon thefallingedgeofW, and
Data Inputs are latched on the rising edge of W.
VCC Supply Voltage. The power supply for all
operations(Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
4/31
M29W040
Table 6. Instructions (1)
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Addr. (2,6)
Data
X
1+
Read Memory Array until a new write cycle is initiated.
Read Array/
Reset
RST (3,9)
F0h
Addr. (2,6) 5555h
2AAAh
55h
5555h
F0h
Read Memory Array until a new write
cycle is initiated.
3+
3+
3+
Data
AAh
Read
Electronic
Signature
Addr. (2,6) 5555h
2AAAh
5555h
Read Electronic Signature until a new
write cycle is initiated. See Note 4.
RSIG (3)
RBP (3)
Data
Addr. (2,6) 5555h
Data AAh
Addr. (2,6) 5555h
AAh
55h
90h
2AAAh
55h
5555h
90h
Read Block
Protection
Read Block Protection until a new write
cycle is initiated. See Note 5.
Program
2AAAh
55h
5555h
A0h
Address
Read Data Polling or Toggle Bit
until Program completes.
PG
BE
Program
4
6
Program
Data
Data
AAh
Block
Additional
Addr. (2,6) 5555h
2AAAh
5555h
5555h
2AAAh
Address Block (7)
Block Erase
Chip Erase
Data
AAh
55h
2AAAh
55h
80h
5555h
80h
AAh
5555h
AAh
55h
2AAAh
55h
30h
5555h
10h
30h
Addr. (2,6) 5555h
CE
ES
6
1
1
1
Note 8
Data
AAh
X
Addr. (2,6)
Data
Erase
Suspend
Read until Toggle stops, then read all the data needed from any
uniform block(s) not being erased then Resume Erase.
B0h
X
Addr. (2,6)
Data
Erase
Resume
Read Data Polling or Toggle Bit until Erase completes or Erase
is suspended another time
ER
30h
Addr. (2,6) 5555h
Data 20h
Power
Down
Puts the memory in Power Down mode where power
consumption is reduced to typically less than 1µA
PD (10)
Notes:
1. Command not interpreted in this table will default to read array mode.
2. X = Don’t Care.
3. The first cycle of the RST,RBP or RSIG instruction is followed by read operations to read memory array,Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle.
4. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output
Device code.
5. Protection Address: A0, A6 at VIL, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will outputthe
Block Protection status.
6. Address bits A15-A18 are don’t care for coded address inputs.
7. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
8. Read Data Polling or Toggle bit until Erase completes.
9. Await time of 5µs is necessary after a Reset command, if the memory is in a Block Erase or Power Down status, before
starting any operation.
10. Writing an RST command to theP/E.C. is mandatory prior to any new operation when the memory is in Power Down mode.
5/31
M29W040
Memory Blocks
on the fallingedge of W or E whicheveroccurslast.
CommandsandInputDataarelatchedon therising
edge of W or E whichever occurs first.
The memory blocks of the M29W040are shownin
Figure 3. Thememory array is dividedin 8 uniform
blocks of 64 Kbytes. Each block can be erased
separately or any combination of blocks can be
erased simultaneously.The BlockErase operation
is managedautomaticallyby theP/E.C.Theopera-
tion can be suspended in order to read from any
other block, and then resumed.
Output Disable. Thedata outputsare high imped-
ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and Program/Erase Controller
P/E.C. is Idle. The power consumption is reduced
to the standby level and the outputs are high im-
pedance, independent of the Output Enable G or
Write Enable W inputs.
Block Protectionprovides additionaldata security.
Each uniformblock can be separatelyprotectedor
unprotectedagainstProgramor Erase.BringingA9
and G to VID initiates protection,while bringing A9,
G and E to VID cancels the protection. The block
affected during protection is addressed by the in-
puts on A16, A17, and A18. Unprotect operation
affects all blocks.
Automatic Standby. After 150ns of inactivity and
when CMOS levels are driving the addresses,the
chip automaticallyenters a pseudo standby mode
where consumption is reduced to the CMOS
standby value, while outputs are still driving the
bus.
Operations
Operations are defined as specific bus cycles and
signals which allow Memory Read, Command
Write, Output Disable, Standby, Read Status Bits,
Block Protect/Unprotect, Block Protection Check
and ElectronicSignatureRead. Theyare shownin
Tables 3, 4, 5.
Power Down. When the PD command is written
to the P/E.C. the memory enters a power down
status where the power consumptionis reducedto
ICC6 (typicallyless than 1.0µA).
Electronic Signature. Two codes identifying the
manufacturer andthe devicecan be read fromthe
memory,the manufacturer’scodefor STMicroelec-
tronics is 20h, and the device code is E3h for the
M29W040. These codes allow programming
equipment or applications to automatically match
theirinterfaceto thecharacteristicsof theparticular
manufacturer’s product. TheElectronic Signature
is output by a Read operation when the voltage
applied to A9 is at VID and address inputs A1 and
A6 are at Low. The manufacturer code is output
when the Address input A0 is Low and the device
code when thisinputis High.Other Addressinputs
are ignored. The codes are output on DQ0-DQ7.
This is shown in Table 4.
Read. Read operations are used to output the
contents of the Memory Array, the Status Register
or the Electronic Signature. Both Chip Enable E
and Output Enable G must be low in order to read
the output of the memory. The Chip Enable input
also providespowercontroland shouldbe usedfor
device selection. OutputEnable shouldbe usedto
gatedataontothe outputindependentof thedevice
selection. The data read dependson the previous
command written to the memory (seeinstructions
RST and RSIG, and Status Bits).
Write. Writeoperationsare used togiveInstruction
Commandsto the memory or to latch input data to
be programmed.Awrite operationis initiatedwhen
Chip Enable E is Low and Write Enable W is Low
with OutputEnableG High. Addressesare latched
The ElectronicSignature can alsobe read, without
raising A9 to VID by giving the memory the instruc-
tion RSIG (see below).
6/31
M29W040
Figure 3. Memory Map and Block Address Table
TOP
BOTTOM
ADDRESS ADDRESS
A18
A17
1
A16
1
1
64K Bytes Block
64K Bytes Block
64K Bytes Block
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
0
1
64K Bytes Block
64K Bytes Block
0
0
AI01362B
Table 7. Commands
Block Protection. Each uniform block can be
separately protected against Program or Erase.
Block Protectionprovides additionaldata security,
as it disables all programor erase operations.This
mode is activated when both A9 and G are set to
VID and the block address is applied on A16-A18.
Block Protection is programmed using a Presto F
programlike algorithm.Protectionisinitiatedon the
Hex Code
10h
Command
Chip Erase Confirm
Power Down
20h
30h
Block Erase Resume/Confirm
Reserved
edge ofW fallingto V .Thenafteradelayof100µs,
IL
50h
the edge of W rising to VIH ends the protection
operation.Protection verify is achieved by bringing
G, E andA6 to VIL while W is at VIH and A9 at VID.
Undertheseconditions,readingthe dataoutputwill
yield 01h if the block defined by the inputs on
A16-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the
device.
Any protected block can be unprotected to allow
updating of bit contents. All blocks must be pro-
tected before an unprotect operation. Block Un-
protect is activated when A9, G and E are at VID.
The addressesinputs A6, A12, A16 mustbe main-
tainedatVIH. BlockUnprotectis performedthrough
a Presto F Erase like algorithm. Unprotect is initi-
ated by the edge of W falling to VIL. After a delay
of 10ms, the edge of W rising to VIH will end the
unprotection operation. Unprotect verify is
achieved by bringing G and E to VIL while A6 and
80h
Set-up Erase
Read Electronic Signature/
Block Protection Status
90h
A0h
B0h
F0h
Program
Erase Suspend
Read Array/Reset
W are at VIH and A9 at VID. In these conditions,
reading the output data will yield 00h if the block
defined by the inputs on A16-A18 has been suc-
cessfullyunprotected.AllcombinationsofA16-A18
must be addressedin orderto ensurethatall of the
8 uniform blocks have been unprotected. Block
Protection Status is shown in Table 5.
7/31
M29W040
Table 8. Status Register
DQ
Name
Logic Level
Definition
Erase Complete
Note
’1’
’0’
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
Data
Polling
Erase on going
7
DQ
DQ
Program Complete
Program on going
’-1-0-1-0-1-0-1-’ Erase or Program on going
Successive read output complementary
data on DQ6 while Programming or Erase
operations are going on. DQ6 remain at
constant level when P/E.C. operations are
completed or Erase Suspend is
Program (’0’ on DQ6)
’-0-0-0-0-0-0-0-’
6
Toggle Bit
Error Bit
Complete
Erase or Program
’-1-1-1-1-1-1-1-’
acknowledged.
(’1’ on DQ6) Complete
’1’
’0’
’1’
’0’
’1’
Program or Erase Error
This bit is set to ’1’ if P/E.C. has exceded
the specified time limits.
5
4
Program or Erase on going
Erase Timeout Period Expired P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
Erase
3
Time Bit
(ES). An additional block to be erased in
parallel can be entered to the P/E.C.
Erase Timeout Period on
going
’0’
2
1
0
Reserved
Reserved
Reserved
Note:
Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
DQ6, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand executionwillautomaticallyoutputthosefour
bits. TheP/E.C. automaticallysetsbits DQ3, DQ5,
DQ6 and DQ7. Other bits (DQ0, DQ1, DQ2 and
DQ4) are reserved for future use and should be
masked.
Instructions and Commands
The Command Interface (C.I.) latches commands
written to the memory. Instructions are made up
from one or more commands to perform Read
Array/Reset, Read Electronic Signature, Power
Down, Block Erase, Chip Erase, Program, Block
Erase Suspend and Erase Resume. Commands
are made of address and data sequences. Ad-
dresses are latched on the falling edge of W or E
and data is latched on the rising of W or E. The
instructions require from 1 to 6 cycles, the first or
first three of which are always write operations
used to initiate thecommand.Theyarefollowed by
either further write cycles to confirm the first com-
mand orexecute the commandimmediately. Com-
mand sequencing must be followed exactly. Any
invalid combination of commands will reset the
device to Read Array. The increased number of
cycles has been chosen to assure maximum data
security. Commands are initialised by two preced-
ing codedcycleswhich unlockthe CommandInter-
face.In addition,for Erase,command confirmation
is againpreceeded by the two coded cycles.
Data Polling bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation,it outputsa ’0’. After com-
pletion of the operation,DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid only effective during P/E.C. operation, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. It must be performed
at theaddressbeing programmedor at an address
within the block being erased. If the byte to be
programmedbelongsto a protectedblock thecom-
mand is ignored. If all the blocks selected for era-
sure are protected, DQ7 will set to ’0’ for about
100µs, and then return to previous addressed
memory data. See Figure 9 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms.
P/E.C. status is indicated during command execu-
tionby DataPolling onDQ7, detectionofToggleon
8/31
M29W040
Table 9. AC Measurement Conditions
Figure 5. AC Testing Load Circuit
Input Rise and Fall Times
10ns
≤
0.8V
Input Pulse Voltages
0 to 3V
1.5V
1N914
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
3.3kΩ
DEVICE
UNDER
TEST
OUT
3V
C
= 30pF or 100pF
L
1.5V
0V
AI01417
C
includes JIG capacitance
L
AI01968
Table 10. Capacitance(1) (TA = 25 °C, f = 1 MHz)
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note:
1. Sampled only, not 100% tested.
Table 11. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
ILI
Parameter
Input Leakage Current
Test Condition
0V ≤ VIN ≤ VCC
Min
Max
±1
Unit
µA
ILO
Output Leakage Current
Supply Current (Read)
0V ≤ VOUT ≤ VCC
E = VIL, G = VIH, f = 6MHz
E = VIH
±1
µA
ICC1
ICC2
ICC3
20
mA
mA
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
0.2
50
E = VCC 0.2V
A
µ
±
Byte Program,
Block Erase
ICC4
Supply Current (Program or Erase)
20
mA
mA
ICC5
ICC6
VIL
Supply Current
Chip Erase in progress
40
5
Power Down Current
Input Low Voltage
Input High Voltage
Output Low Voltage
E = VCC 0.2V
A
µ
±
–0.5
0.8
V
VIH
0.7 VCC
VCC + 0.5
0.45
V
V
VOL
IOL = 2mA
I
OH = –100µA
VCC –0.4
0.85 VCC
11.5
V
VOH
Output High Voltage CMOS
IOH = –2.0mA
A9 = VID
V
VID
IID
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
12.5
50
V
µA
Supply Voltage (Erase and
Program lock-out)
VLKO
1.9
2.2
V
9/31
M29W040
Table 12A. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-100
-120
VCC = 3.3V 0.3V
Symbol
Alt
Parameter
Test Condition
Unit
VCC = 3.3V±0.3V
±
CL = 30pF
Min
Max
100
100
Min
Max
120
120
tAVAV
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
E = VIL, G = VIL
E = VIL, G = VIL
G = VIL
100
120
ns
ns
ns
ns
tAVQV
(1)
tELQX
tLZ Chip Enable Low to Output Transition
tCE Chip Enable Low to Output Valid
0
0
0
0
(2)
tELQV
G = VIL
Output Enable Low to Output
Transition
(1)
tGLQX
tOLZ
E = VIL
E = VIL
ns
ns
ns
ns
ns
ns
ns
(2)
tGLQV
tOE Output Enable Low to Output Valid
40
20
20
50
30
30
Chip Enable High to Output
Transition
tEHQX
tOH
G = VIL
0
0
0
0
0
0
(1)
tEHQZ
tHZ Chip Enable High to Output Hi-Z
G = VIL
Output Enable High to Output
Transition
tGHQX
tOH
E = VIL
(1)
tGHQZ
tDF Output Enable High to Output Hi-Z
E = VIL
Address Transition to Output
Transition
tAXQX
tOH
E = VIL, G = VIL
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
.
Toggle bit (DQ6). When Programming operations
are in progress, successive attempts to read DQ6
will output complementary data. DQ6 will toggle
following toggling of either G or E when G is low.
The operation is completed when two successive
reads yield the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing. Thetogglebit is validonlyeffectiveduring
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the byte to be programmed belongs to a
protectedblockthe commandwill be ignored.If the
blocks selectedfor erasure are protected,DQ6will
toggle for about 100µs and then return back to
Read. See Figure 11 for Toggle Bit flowchart and
Figure 12 for Toggle Bit waveforms.
grammed byte belongs,must be discarded. Other
blocksmaystill be used.Errorbitresetsafter Reset
(RST) instruction. In case of success, the error bit
will set to ’0’ during Program or Erase and to valid
data after write operation is completed.
Erase Timer bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the last Block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 80 to 120µs, DQ3 returns
back to ’1’.
Coded Cycles. The two coded cycles unlock the
Command Interface. They are followed by a com-
mand input or a comand confirmation. The coded
cycles consist of writing the data AAh at address
5555hduringthefirstcycleanddata55hataddress
2AAAh during the second cycle. Addresses are
latched on the falling edge of W or E while data is
latched on the rising edge of W or E. The coded
cycles happen on first and second cycles of the
command write or on the fourth and fifth cycles.
Error bit (DQ5). This bit is set to ’1’ by the P/E.C
when there is a failure of byte programming, block
erase, or chip erase that results in invalid data
being programmedin thememory block. In case of
error in block erase or byte program, the block in
which the error occured or to which the pro-
10/31
M29W040
Table 12B. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-150
-200
Symbol
Alt
Parameter
Test Condition
Unit
V
CC = 2.7V to 3.6V VCC = 2.7V to 3.6V
Min
Max
150
150
Min
Max
200
200
Address Valid to Next Address
Valid
tAVAV
tRC
E = VIL, G = VIL
E = VIL, G = VIL
G = VIL
150
200
ns
ns
ns
ns
ns
tAVQV
tACC Address Valid to Output Valid
Chip Enable Low to Output
Transition
(1)
tELQX
tLZ
0
0
0
0
(2)
tELQV
tCE Chip Enable Low to Output Valid
G = VIL
Output Enable Low to Output
Transition
(1)
tGLQX
tOLZ
E = VIL
Output Enable Low to Output
Valid
(2)
tGLQV
tOE
E = VIL
55
40
40
70
50
50
ns
Chip Enable High to Output
Transition
tEHQX
tOH
G = VIL
G = VIL
E = VIL
0
0
0
0
ns
ns
ns
(1)
tEHQZ
tHZ Chip Enable High to Output Hi-Z
Output Enable High to Output
Transition
tGHQX
tOH
Output Enable High to Output
Hi-Z
(1)
tGHQZ
tDF
E = VIL
ns
ns
Address Transition to Output
Transition
tAXQX
tOH
E = VIL, G = VIL
0
0
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
.
Read Array/Reset (RST) instruction. The Reset
instruction consists of one write operation giving
the command F0h. It can be optionally preceded
by the two coded cycles. A wait state of 5µs before
read operationsisnecessaryif theResetcommand
is applied during an Erase or Power Down opera-
tion.
Read Electronic Signature (RSIG) instruction.
Thisinstructionuses thetwo codedcyclesfollowed
by one write cycle giving the command 90h to
address5555h for command setup. Asubsequent
read will output the manufacturercode, the device
code or the Block Protection status depending on
the levels of A0, A1, A6, A16, A17 and A18. The
manufacturer code, 20h, is output when the ad-
dresses lines A0, A1 and A6 are Low, the device
code, E2h is output when A0 is High with A1 and
A6 Low.
Read Block Protection (RBP) instruction. The
useof ReadElectronicSignature(RSIG)command
also allows access to the Block Protection status
verify. After giving the RSIGcommand, A0 and A6
are set to VIL with A1 at VIH, while A16, A17 and
A18 define the block of the block to be verified. A
read in theseconditions will output a 01hif blockis
protected and a 00h if block is not protected.
This Read BlockProtectionis the onlyvalid way to
check the protection status of a block. Neverthe-
less, it mustnot beused duringthe blockprotection
phase as a method to verify the Block Protection.
Please refer to Block Protection paragraph.
Power Down (PD) instruction. ThePower Down
instructionuses one write cycle to put the memory
into a power down mode where current consump-
tion is typically reduced to less than 1.0µA. Once
in this state, a Reset (RST) command must be
written to the P/E.C. prior to any operation.
11/31
M29W040
Figure 6. Read Mode AC Waveforms
12/31
M29W040
Table 13A. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-100
-120
VCC = 3.3V 0.3V
Symbol
Alt
Parameter
Unit
VCC = 3.3V±0.3V
±
CL = 30pF
Min
100
0
Max
Min
120
0
Max
tAVAV
tELWL
tWC Address Valid to Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
tDS Input Valid to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tVCHEL
45
45
0
50
50
0
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
tWPH Write Enable High to Write Enable Low
tAS Address Valid to Write Enable Low
tAH Write Enable Low to Address Transition
Output Enable High to Write Enable Low
tVCS VCC High to Chip Enable Low
0
0
25
0
30
0
45
0
50
0
50
12
50
12
s
µ
(1)
tWHQV1
tWHQV2
tWHGL
Write Enable High to Output Valid (Program)
µs
sec
ns
Write Enable High to Output Valid
(Block Erase)
(1)
1.5
0
30
1.5
0
30
tOEH Write Enable High to Output Enable Low
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
.
Chip Erase(CE) instruction. Thisinstructionuses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on third cycle after the
two coded cycles. The Chip Erase Confirm com-
mand 10hiswrittenat address5555honsixthcycle
after another two coded cycles. If the secondcom-
mand given is not an erase confirm or if the coded
cycles are wrong, the instruction aborts and the
device is reset to Read Array. It is not necessaryto
program the array with 00h first as the P/E.C. will
automatically do this before erasing to FFh. Read
operations after the sixth rising edge of W or E
output the status register bits. During the execu-
tion of the erase by the P/E.C. the memory will not
accept any instruction.
Read of DataPolling bit DQ7returns’0’, then’1’ on
completion. The Toggle Bit DQ6 toggles during
erase operation and stops when erase is com-
pleted. After completion the Status Register bit
DQ5 returns ’1’ if there has been an Erase Failure
because the erasure has not been verified even
after the maximum number of erase cycles have
been executed.
13/31
M29W040
Table 13B. Write AC Characteristics,Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-150
-200
Symbol
Alt
Parameter
Unit
V
CC = 2.7V to 3.6V VCC = 2.7V to 3.6V
Min
150
0
Max
Min
200
0
Max
tAVAV
tELWL
tWC Address Validto Next Address Valid
tCS Chip Enable Low to Write Enable Low
tWP Write Enable Low to Write Enable High
tDS Input Valid to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tVCHEL
65
65
0
80
80
0
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
tWPH Write Enable High to Write Enable Low
tAS Address Validto Write Enable Low
tAH Write Enable Low to Address Transition
Output Enable High to Write Enable Low
tVCS VCC High to Chip Enable Low
0
0
35
0
35
0
65
0
65
0
50
12
50
12
(1)
tWHQV1
tWHQV2
tWHGL
Write Enable High to Output Valid (Program)
Write Enable High to Output Valid
(Block Erase)
(1)
1.5
0
30
1.5
0
30
sec
ns
tOEH Write Enable High to Output Enable Low
Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV = tWHQ7V + tQ7VQV
.
Block Erase (BE) instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on thirdcycleafter the twocodedcycles.The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
the blockto be erasedis given and latchedinto the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequently to erase other blocks in parallel, without
further coded cycles. The erase will start after the
Erase timeout period (see Erase Timer Bit DQ3
description). Thus, additional Block Erase com-
mands mustbe givenwithin this delay.The inputof
a newBlockErasecommandwillrestartthetimeout
period. The status of the internal timer can be
monitoredthroughthe levelofDQ3, ifDQ3 is’0’the
Block Erase Command has been given and the
timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C is erasing the block(s).
DuringErase timeout, any commanddifferentfrom
30h will abort the instruction and reset the device
to read array mode. It is not necessary to program
the block with 00h as the P/E.C. will do this auto-
matically before erasing to FFh. Read operations
after the sixth rising edge of W or E output the
status register bits.
Duringtheexecutionof theerasebytheP/E.C.,the
memoryaccepts onlythe ES(Erase Suspend)and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
whenit has completed.TheToggleBitDQ6toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure because erasure has not completedeven
after the maximum number of erase cycles have
been executed. In this case, it will be necessary to
input a Reset (RST) to the command interface in
order to reset the P/E.C.
14/31
M29W040
Figure 7. WriteAC Waveforms, W Controlled
WRITE CYCLE
VALID
A0-A18
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7
V
CC
tVCHEL
AI01365B
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Program (PG) instruction. The memory can be
programmed Byte-by-Byte. This instruction uses
four write cycles. The Program command A0h is
written on the thirdcycle after two codedcycles. A
fourth write operation latches the Address on the
falling edge of W or E and the Data to be written
on its rising edge and starts the P/E.C. During the
execution of the programby the P/E.C., the mem-
ory willnot acceptanyinstruction.Read operations
output the status bits after the programming has
started. The status bits DQ5, DQ6 and DQ7 allow
a checkof thestatusof theprogrammingoperation.
Memory programmingis madeonly by writing ’0’ in
place of ’1’ in a Byte.
Erase Suspend (ES) instruction. The Block
Eraseoperationmaybe suspended bythisinstruc-
tion which consists of writing the command B0h
withoutanyspecificaddresscode.No codedcycles
are required.It allowsreading of datafromanother
block while erase is in progress. Erase suspend is
accepted only during the Block Erase instruction
executionand defaultsto read arraymode. Writing
thiscommandduring Erase timeoutwill, in addition
to suspending the erase, terminate the timeout.
The ToggleBit DQ6stopstogglingwhenthe P/E.C.
is suspended. ToggleBit statusmust be monitored
at anaddressout ofthe blockbeingerased.Toggle
Bit will stop toggling between 0.1µs and 15µs after
the Erase Suspend (ES) command has been writ-
ten.
The M29W040 will then automatically set to Read
Memory Array mode. When erase is suspended,
Read from blocks being erased will output invalid
data, Read from block not being erased is valid.
During the suspension the memory will respond
only to Erase Resume (ER) and Reset (RST) in-
structions. RST command will definitively abort
erasure and result in the invalid data in the blocks
being erased.
EraseResume (ER)instruction. If an Erase Sus-
pend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
coded cycles.
15/31
M29W040
Table 14A. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-100
-120
VCC = 3.3V 0.3V
Symbol
Alt
Parameter
Unit
VCC = 3.3V±0.3V
±
CL = 30pF
Min
100
0
Max
Min
120
0
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Validto Chip Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
45
0
50
50
0
tDS
tDH
tWH
tCPH
tAS
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
0
0
25
0
30
0
tELAX
tGHEL
tVCHWL
tAH
45
0
50
0
tVCS
50
12
50
12
s
µ
(1)
tEHQV1
Chip Enable High to Output Valid(Program)
µs
sec
ns
Chip Enable High to Output Valid
(Block Erase)
(1)
tEHQV2
1.5
0
30
1.5
0
30
tEHGL
tOEH
Chip Enable High to Output Enable Low
Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV = tWHQ7V + tQ7VQV
.
Power Up
Supply Rails
ThememoryCommandInterfaceis reseton power
up to Read Array. EitherE or W must be tied to VIH
during Power-up to allow maximum security and
the possibilityto writea commandon the firstrising
adge of E or W. Anywrite cycle initiationis blocked
Normal precautionsmust be taken for supply volt-
age decoupling, each device in a system should
havethe VCC rail decoupledwith a 1.0µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
when VCC is below VLKO
.
16/31
M29W040
Table 14B. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-150
-200
Symbol
Alt
Parameter
Unit
V
CC = 2.7V to 3.6V VCC = 2.7V to 3.6V
Min
150
0
Max
Min
200
0
Max
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tWC
tWS
tCP
tDS
tDH
tWH
tCPH
tAS
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
65
65
0
80
80
0
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
VCC High to Write Enable Low
0
0
35
0
35
0
tELAX
tAH
65
0
65
0
tGHEL
tVCHWL
tVCS
50
12
50
12
(1)
tEHQV1
Chip Enable High to Output Valid (Program)
Chip Enable High to Output Valid
(Block Erase)
(1)
tEHQV2
1.5
0
30
1.5
0
30
sec
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV
.
17/31
M29W040
Figure 8. WriteAC Waveforms, E Controlled
WRITE CYCLE
VALID
A0-A18
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7
V
CC
tVCHWL
AI01366B
Note:
Address are latched on the falling edge of E, Data is latched on the rising edge of E.
18/31
M29W040
Table 15A. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-100
-120
VCC = 3.3V 0.3V
Symbol
Alt
Parameter
Unit
VCC = 3.3V±0.3V
±
CL = 30pF
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
(2)
tWHQ7V1
tWHQ7V2
tEHQ7V1
tEHQ7V2
12
12
s
µ
Write Enable High to DQ7 Valid
(Block Erase, W Controlled)
(2)
(2)
(2)
1.5
12
30
1.5
12
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
µs
Chip Enable High to DQ7 Valid
(Block Erase, E Controlled)
1.5
30
45
1.5
30
50
sec
ns
tQ7VQV
tWHQV1
Q7 Validto Output Valid(Data Polling)
Write Enable High to Output Valid
(Program)
12
1.5
12
12
1.5
12
s
µ
Write Enable High to Output Valid
(Block Erase)
tWHQV2
tEHQV1
tEHQV2
30
30
30
30
sec
Chip Enable High to Output Valid
(Program)
s
µ
Chip Enable High to Output Valid
(Block Erase)
1.5
1.5
sec
Notes: 1. All other timings are defined in Read AC Characteristics table.
2. tWHQ7V is the Program or Erase time.
19/31
M29W040
Table 15B. Data Polling and Toggle Bit AC Characteristics(1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W040
-150
VCC = 2.7V to 3.6V
-200
Symbol
Alt
Parameter
Unit
VCC = 2.7V to 3.6V
Min
Max
Min
Max
Write Enable High to DQ7 Valid
(Program, W Controlled)
(2)
tWHQ7V1
tWHQ7V2
tEHQ7V1
tEHQ7V2
12
12
s
µ
Write Enable High to DQ7 Valid
(Block Erase, W Controlled)
(2)
(2)
(2)
1.5
12
30
1.5
12
30
sec
Chip Enable High to DQ7 Valid
(Program, E Controlled)
s
µ
Chip Enable High to DQ7 Valid
(Block Erase, E Controlled)
1.5
30
55
1.5
30
70
sec
ns
tQ7VQV
tWHQV1
Q7 Valid to Output Valid (Data Polling)
Write Enable High to Output Valid
(Program)
12
1.5
12
12
1.5
12
µs
Write Enable High to Output Valid
(Block Erase)
tWHQV2
tEHQV1
tEHQV2
30
30
30
30
sec
Chip Enable High to Output Valid
(Program)
s
µ
Chip Enable High to Output Valid
(Block Erase)
1.5
1.5
sec
Notes: 1. All other timings are defined in Read AC Characteristics table.
2. tWHQ7V is the Program or Erase time.
20/31
M29W040
Figure 9. Data Polling DQ7 AC Waveforms
21/31
M29W040
Figure 10. Data Polling Flowchart
Figure 11. Data Toggle Flowchart
START
START
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ6
NO
=
DQ7
=
DATA
YES
TOGGLE
NO
YES
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ7
READ DQ6
DQ6
NO
TOGGLE
DQ7
=
DATA
YES
=
NO
YES
FAIL
FAIL
PASS
PASS
AI01369
AI01370
Table 16. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 2.7V to 3.6V)
M29W040
Parameter
Unit
Min
Typ
Max
30
Chip Program (Byte)
Chip Erase (Preprogrammed)
Chip Erase
6
sec
sec
2.5
8.5
1.5
2
sec
Block Erase (Preprogrammed)
Block Erase
30
sec
sec
Byte Program
12
2200
µs
Program/Erase Cycles (per Block)
100,000
cycles
22/31
M29W040
Figure 12. DataToggle DQ6 AC Waveforms
23/31
M29W040
Figure 13. Block Protection Flowchart
START
BLOCK ADDRESS
on A16, A17, A18
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
G = V
IH
Wait 4µs
READ DQ0 at PROTECTION
ADDRESS: A0, A6 = V , A1 = V and
IL
IH
A16, A17, A18 DEFINING BLOCK
NO
DQ0
= 1
YES
A9 = V
IH
++n
NO
= 25
PASS
YES
A9 = V
IH
FAIL
AI01368D
24/31
M29W040
Figure 14. Block Unprotecting Flowchart
START
PROTECT
ALL BLOCKS
n = 0
A6, A12, A16 = V
IH
E, G, A9 = V
IH
Wait 4µs
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
Wait 4µs
READ at UNPROTECTION
ADDRESS: A1, A6 = V , A0 = V and
A16, A17, A18 DEFINING BLOCK
(see Note 1)
IH
IL
INCREMENT
BLOCK
NO
YES
DATA
=
00h
NO
++n
LAST
NO
= 1000
SECT.
YES
FAIL
YES
PASS
AI01371E
Note:
1. A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status
reads, A6 must be kept at VIL.
25/31
M29W040
ORDERING INFORMATION SCHEME
Example:
M29W040
-120
N
1
TR
Operating Voltage
Speed
Package
Temp. Range
0 to 70 °C
–20 to 85 C
Option
W
2.7V to 3.6V
-100 (1)
100ns
120ns
150ns
200ns
K
N
PLCC32
1
R
Reverse
Pinout
-120
-150
-200
TSOP32
8 x 20mm
5
6
°
TR Tape & Reel
Packing
–40 to 85 C
°
NZ TSOP32
8 x 14mm
Note: 1. This speed is obtainedwith a supply voltage range of VCC = 3.3V ± 0.3V and a load capacitance at 30pF.
M29W040 is replaced by the new version M29W040B
Device are shipped from the factory with the memory content erased (to FFh).
Fora list ofavailableoptions(Speed, Package,etc...) orfor furtherinformationon any aspect of thisdevice,
please contact the STMicroelectronics Sales Office nearest to you.
26/31
M29W040
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
–
inches
Min
Symb
Typ
Max
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.100
0.060
–
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
27/31
M29W040
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
8.10
-
Typ
Max
0.047
0.007
0.041
0.011
0.008
0.795
0.728
0.319
-
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
-
0.002
0.037
0.006
0.004
0.780
0.720
0.311
-
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
28/31
M29W040
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.17
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-b
A1
α
L
Drawing is not to scale.
29/31
M29W040
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
14.20
12.50
8.10
-
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.559
0.492
0.319
-
A
A1
A2
B
0.05
0.95
0.17
0.10
13.80
12.30
7.90
-
0.002
0.037
0.007
0.004
0.543
0.484
0.311
-
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
0
°
5
°
α
°
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
30/31
M29W040
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use ofsuch informationnor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
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31/31
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