M29W320ET90ZA1_技术文档

M29W320ET

M29W320EB

32 Mbit (4Mb x8 or 2Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Packages

–

V

= 2.7V to 3.6V for Program, Erase

CC

and Read

–

V

=12V for Fast Program (optional)

PP

■

ACCESS TIMES: 70, 90ns

PROGRAMMING TIME

–

10µs per Byte/Word typical

Double Word/ Quadruple Byte Program

■

MEMORY BLOCKS

–

Memory Array: 63 Main Blocks

8 Parameter Blocks (Top or Bottom

Location)

TSOP48 (N)

12 x 20mm

■

ERASE SUSPEND and RESUME MODES

–

Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND

FBGA

–

V

Faster Production/Batch Programming

/WP PIN for FAST PROGRAM and

■

PP

WRITE PROTECT

TEMPORARY BLOCK UNPROTECTION

MODE

TFBGA48 (ZA)

6 x 8mm

COMMON FLASH INTERFACE

–

64 bit Security Code

■

EXTENDED MEMORY BLOCK

–

Extra block used as security block or to

store additional information

LOW POWER CONSUMPTION

Standby and Automatic Standby

–

■

100,000 PROGRAM/ERASE CYCLES per

BLOCK

ELECTRONIC SIGNATURE

–

Manufacturer Code: 0020h

Top Device Code M29W320ET: 2256h

Bottom Device Code M29W320EB: 2257h

April 2004

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M29W320ET, M29W320EB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V

Write Protect (V WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PP/ PP/

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2. Bus Operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IL

Table 3. Bus Operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IH

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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M29W320ET, M29W320EB

Fast Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Enter Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Commands, 16-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

IH

Table 5. Commands, 8-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

IL

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled . . . . . . . . . . . . 27

Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 27

Table 15. Toggle and Alternative Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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M29W320ET, M29W320EB

Table 16. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . . 29

Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 29

Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 30

Table 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 30

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 20. Top Boot Block Addresses, M29W320ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 21. Bottom Boot Block Addresses, M29W320EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29. Programmer Technique Bus Operations, BYTE = V or V

IH

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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M29W320ET, M29W320EB

SUMMARY DESCRIPTION

The M29W320E is a 32 Mbit (4Mb x8 or 2Mb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode.

The device features an asymmetrical block archi-

tecture. The M29W320E has an array of 8 param-

eter and 63 main blocks. M29W320ET locates the

Parameter Blocks at the top of the memory ad-

dress space while the M29W320EB locates the

Parameter Blocks starting from the bottom.

erased. The blocks can be protected to prevent

accidental Program or Erase commands from

modifying the memory. Program and Erase com-

mands are written to the Command Interface of

the memory. An on-chip Program/Erase Controller

simplifies the process of programming or erasing

the memory by taking care of all of the special op-

erations that are required to update the memory

contents. The end of a program or erase operation

can be detected and any error conditions identi-

fied. The command set required to control the

memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP48 (12x20mm), and

TFBGA48 (6x8mm, 0.8mm pitch) packages. The

memory is supplied with all the bits erased (set to

’1’).

M29W320E has an extra 32 KWord (x16 mode) or

64 KByte (x8 mode) block, the Extended Block,

that can be accessed using a dedicated com-

mand. The Extended Block can be protected and

so is useful for storing security information. How-

ever the protection is irreversible, once protected

the protection cannot be undone.

Each block can be erased independently so it is

possible to preserve valid data while old data is

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A20

DQ0-DQ7

DQ8-DQ14

DQ15A–1

E

Address Inputs

Data Inputs/Outputs

Data Input/Output or Address Input

Chip Enable

V

/WP

CC PP

21

15

A0-A20

DQ0-DQ14

G

Output Enable

W

E

DQ15A–1

BYTE

RB

W

Write Enable

M29W320ET

M29W320EB

RP

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

G

RB

RP

BYTE

V

CC

V

/Write Protect

V

/WP

PP

V

SS

Ground

AI09346

SS

NC

Not Connected Internally

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M29W320ET, M29W320EB

Figure 3. TSOP Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

V

SS

DQ15A–1

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A19

A20

W

M29W320ET

M29W320EB

DQ12

DQ4

RP

NC

/WP

RB

A18

A17

A7

12

13

37

36

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

PP

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI09347

6/46

M29W320ET, M29W320EB

Figure 4. TFBGA48 Connections (Top view through package)

1

2

3

4

5

6

RB

W

A

B

A3

A4

A7

A17

A6

A9

A8

A13

A12

V

/

WP

RP

NC

PP

A2

A1

A0

E

A18

A10

A14

C

D

A5

A20

A19

A11

A15

DQ2

DQ5

DQ0

DQ8

DQ9

DQ1

DQ7

DQ14

DQ13

DQ6

A16

E

F

BYTE

DQ10

DQ11

DQ3

DQ12

DQ15

A–1

G

V

G

H

CC

V

DQ4

V

SS

AI08084

7/46

M29W320ET, M29W320EB

Figure 5. Block Addresses (x8)

Top Boot Block (x8)

Bottom Boot Block (x8)

Address lines A20-A0, DQ15A-1

000000h

64 KByte or

32 KWord

8 KByte or

4 KWord

00FFFFh

001FFFh

Total of 8

Parameter

Blocks ⁽¹⁾

2F0000h

00E000h

64 KByte or

32 KWord

8 KByte or

4 KWord

Total of 63

Main Blocks

2FFFFFh

300000h

00FFFFh

010000h

64 KByte or

32 KWord

64 KByte or

32 KWord

30FFFFh

01FFFFh

3E0000h

0F0000h

64 KByte or

32 KWord

64 KByte or

32 KWord

Total of 63

Main Blocks

3EFFFFh

3F0000h

0FFFFFh

100000h

8 KByte or

4 KWord

64 KByte or

32 KWord

3F1FFFh

10FFFFh

Total of 8

Parameter

Blocks ⁽¹⁾

3FE000h

3F0000h

3FFFFFh

8 KByte or

4 KWord

64 KByte or

32 KWord

3FFFFFh

Note 1. Used as Extended Block Addresses in Extended Block mode.

Note: Also see APPENDIX A., Table 20. and Table 21. for a full listing of the Block Addresses.

AI09348

8/46

M29W320ET, M29W320EB

Figure 6. Block Addresses (x16)

Top Boot Block (x16)

Address lines A20-A0

Bottom Boot Block (x16)

Address lines A20-A0

000000h

000FFFh

64 KByte or

32 KWord

8 KByte or

4 KWord

007FFFh

Total of 8

Parameter

Blocks ⁽¹⁾

178000h

007000h

64 KByte or

32 KWord

8 KByte or

4 KWord

17FFFFh

180000h

Total of 63

Main Blocks

007FFFh

008000h

64 KByte or

32 KWord

64 KByte or

32 KWord

187FFFh

00FFFFh

078000h

1F0000h

64 KByte or

32 KWord

1F7FFFh

1F8000h

07FFFFh

080000h

Total of 63

Main Blocks

64 KByte or

8 KByte or

4 KWord

32 KWord

1F8FFFh

087FFFh

Total of 8

Parameter

Blocks ⁽¹⁾

1FF000h

1F8000h

1FFFFFh

8 KByte or

4 KWord

64 KByte or

32 KWord

1FFFFFh

Note 1. Used as Extended Block Addresses in Extended Block mode.

Note: Also see APPENDIX A., Table 20. and Table 21. for a full listing of the Block Addresses.

AI09349

9/46

M29W320ET, M29W320EB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device.

and Erase operations in these blocks are ignored

while V /Write Protect is Low, even when RP is

PP

at V .

ID

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

When V /Write Protect is High, V , the memory

PP IH

reverts to the previous protection status of the two

outermost boot blocks. Program and Erase oper-

ations can now modify the data in these blocks un-

less the blocks are protected using Block

Protection.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the Program/Erase

Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation when BYTE is High,

When V /Write Protect is raised to V the mem-

PP PP

ory automatically enters the Unlock Bypass mode.

When V /Write Protect returns to V or V nor-

PP

IH

IL

mal operation resumes. During Unlock Bypass

Program operations the memory draws I from

PP

the pin to supply the programming circuits. See the

description of the Unlock Bypass command in the

Command Interface section. The transitions from

V

than t

to V

VHVPP

and from V

, see Figure 17.

to V must be slower

IH

PP

PP IH

V . When BYTE is Low, V , these pins are not

IH

IL

used and are high impedance. During Bus Write

operations the Command Register does not use

these bits. When reading the Status Register

these bits should be ignored.

Never raise V /Write Protect to V

mode except Read mode, otherwise the memory

may be left in an indeterminate state.

from any

PP

The V /Write Protect pin must not be left floating

PP

Data Input/Output or Address Input (DQ15A–1).

or unconnected or the device may become unreli-

able. A 0.1µF capacitor should be connected be-

When BYTE is High, V , this pin behaves as a

IH

tween the V /Write Protect pin and the V

PP

SS

Data Input/Output pin (as DQ8-DQ14). When

Ground pin to decouple the current surges from

the power supply. The PCB track widths must be

sufficient to carry the currents required during

BYTE is Low, V , this pin behaves as an address

IL

pin; DQ15A–1 Low will select the LSB of the ad-

dressed Word, DQ15A–1 High will select the MSB.

Throughout the text consider references to the

Data Input/Output to include this pin when BYTE is

High and references to the Address Inputs to in-

clude this pin when BYTE is Low except when

stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

Unlock Bypass Program, I

.

PP

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

Note that if V /WP is at V , then the two outer-

PP

IL

most boot blocks will remain protected even if RP

High, V , all other pins are ignored.

is at V .

IH

ID

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V , for at least

IL

t

. After Reset/Block Temporary Unprotect

PLPX

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

goes High, V , the memory will be ready for Bus

Read and Bus Write operations after t

IH

or

PHEL

t

, whichever occurs last. See the Ready/Busy

RHEL

V

Write Protect (V /WP). The

V

PP

/Write

PP/

PP

Output section, Table 16. and Figure 16., Reset/

Block Temporary Unprotect AC Waveforms, for

more details.

Protect pin provides two functions. The V func-

PP

tion allows the memory to use an external high

voltage power supply to reduce the time required

for Program operations. This is achieved by by-

passing the unlock cycles and/or using the Dou-

ble Word or Quadruple Byte Program commands.

The Write Protect function provides a hardware

method of protecting the two outermost boot

blocks.

Holding RP at V will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V to V must be slower than

ID

IH

ID

t

.

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

When V /Write Protect is Low, V , the memory

PP

IL

protects the two outermost boot blocks; Program

10/46

M29W320ET, M29W320EB

operation. During Program or Erase operations

V

Supply Voltage (2.7V to 3.6V). V

pro-

CC

Ready/Busy is Low, V . Ready/Busy is high-im-

vides the power supply for all operations (Read,

Program and Erase).

The Command Interface is disabled when the V

OL

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

CC

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 16. and Figure

16., Reset/Block Temporary Unprotect AC Wave-

forms.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Supply Voltage is less than the Lockout Voltage,

. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

V

LKO

A 0.1µF capacitor should be connected between

the V

Supply Voltage pin and the V Ground

CC

SS

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during Program and

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the x8 and x16 Bus modes of the

memory. When Byte/Word Organization Select is

Erase operations, I

.

CC3

Low, V , the memory is in x8 mode, when it is

V

Ground. V is the reference for all voltage

SS SS

IL

High, V , the memory is in x16 mode.

measurements. The device features two V pins

IH

SS

which must be both connected to the system

ground.

11/46

M29W320ET, M29W320EB

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby.

See Table 2. and Table 3., Bus Operations, for a

summary. Typically glitches of less than 5ns on

Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

be held within V ± 0.2V. For the Standby current

level see Table 11., DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

CC

Current, I

, for Program or Erase operations un-

CC3

til the operation completes.

Automatic Standby. If CMOS levels (V ± 0.2V)

CC

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

are used to drive the bus and the bus is inactive for

300ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, I

. The

CC2

Inputs, applying a Low signal, V , to Chip Enable

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

IL

and Output Enable and keeping Write Enable

High, V . The Data Inputs/Outputs will output the

IH

Special Bus Operations

value, see Figure 11., Read Mode AC Waveforms,

and Table 12., Read AC Characteristics, for de-

tails of when the output becomes valid.

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

They require V to be applied to some pins.

ID

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Table 2. and Table 3., Bus Operations.

Block Protect and Chip Unprotect. Groups

of

able must remain High, V , during the whole Bus

IH

blocks can be protected against accidental Pro-

gram or Erase. The Protection Groups are shown

in APPENDIX A., Table 20. and Table 21., Block

Addresses. The whole chip can be unprotected to

allow the data inside the blocks to be changed.

Write operation. See Figure 12. and Figure 13.,

Write AC Waveforms, and Table 13. and Table

14., Write AC Characteristics, for details of the tim-

ing requirements.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

The V /Write Protect pin can be used to protect

PP

the two outermost boot blocks. When V /Write

PP

High, V .

IH

Protect is at V the two outermost boot blocks are

IL

Standby. When Chip Enable is High, V , the

IH

protected and remain protected regardless of the

Block Protection Status or the Reset/Block Tem-

porary Unprotect pin status.

Block Protect and Chip Unprotect operations are

described in APPENDIX D.

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, I

, Chip Enable should

CC2

12/46

M29W320ET, M29W320EB

Table 2. Bus Operations, BYTE = V

IL

Data Inputs/Outputs

Address Inputs

DQ15A–1, A0-A20

Operation

E

G

W

DQ14-DQ8

Hi-Z

DQ7-DQ0

Data Output

Data Input

Hi-Z

V

IL

V

IH

Bus Read

Cell Address

IL

IH

V

IL

V

Bus Write

Command Address

Hi-Z

IL

Output Disable

Standby

X

Hi-Z

IH

V

IH

X

Hi-Z

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

Hi-Z

20h

IL

Others V or V

IL

IH

A0 = V , A1 = V ,

56h (M29W320ET)

57h (M29W320EB)

IH

IL

Read Device Code

A9 = V , Others V or V

IH

ID

IL

A0 = V , A1 = V , A6 = V ,

Extended Memory

Block Verify Code

81h (factory locked)

01h (not factory locked)

IH

IL

A9 = V , Others V or V

IH

ID

IL

Note: X = V or V

.

IH

IL

Table 3. Bus Operations, BYTE = V

IH

Address Inputs

A0-A20

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

Bus Read

E

G

W

V

IL

V

IH

Cell Address

Data Output

Data Input

Hi-Z

IL

IH

V

IL

V

Bus Write

Command Address

IL

V

IH

Output Disable

Standby

X

V

IH

X

Hi-Z

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

0020h

IL

Others V or V

IL

IH

A0 = V , A1 = V , A9 = V ,

2256h (M29W320ET)

2257h (M29W320EB)

IH

IL

ID

Read Device Code

Others V or V

IL

IH

A0 = V , A1 = V , A6 = V ,

Extended Memory

Block Verify Code

81h (factory locked)

01h (not factory locked)

IH

IL

A9 = V , Others V or V

IH

ID

IL

Note: X = V or V

.

IH

IL

13/46

M29W320ET, M29W320EB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 4., or Table 5., depend-

ing on the configuration that is being used, for a

summary of the commands.

vice is in the Read Array mode, or when the device

is in Auto Select mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequent Bus Read operations read from

the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Auto Select mode). A second Read/

Reset command would be needed if the device is

to be put in the Read Array mode from Auto Select

mode.

Read/Reset Command

See APPENDIX B., Tables 22, 23, 24, 25, 26 and

27 for details on the information contained in the

Common Flash Interface (CFI) memory area.

The Read/Reset command returns the memory to

its Read mode. It also resets the errors in the Sta-

tus Register. Either one or three Bus Write opera-

tions can be used to issue the Read/Reset

command.

The Read/Reset command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. If the Read/Reset command is issued

during the time-out of a Block erase operation then

the memory will take up to 10µs to abort. During

the abort period no valid data can be read from the

memory. The Read/Reset command will not abort

an Erase operation when issued while in Erase

Suspend.

Program Command

The Program command can be used to program a

value to one address in the memory array at a

time. The command requires four Bus Write oper-

ations, the final write operation latches the ad-

dress and data, and starts the Program/Erase

Controller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the memory will ig-

nore all commands. It is not possible to issue any

command to abort or pause the operation. After

programming has started, Bus Read operations

output the Status Register content. See the sec-

tion on the STATUS REGISTER for more details.

Typical program times are given in Table 6.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

Register. A Read/Reset command must be issued

to reset the error condition and return to Read

mode.

Auto Select Command

The Auto Select command is used to read the

Manufacturer Code, the Device Code, the Block

Protection Status and the Extended Memory Block

Verify Code. Three consecutive Bus Write opera-

tions are required to issue the Auto Select com-

mand. The memory remains in Auto Select mode

until a Read/Reset or CFI Query command is is-

sued.

In Auto Select mode the Manufacturer Code can

be read using a Bus Read operation with A0 = V

IL

and A1 = V . The other address bits may be set to

IL

either V or V .

IL

IH

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

The Device Code can be read using a Bus Read

operation with A0 = V and A1 = V . The other

IH

IL

address bits may be set to either V or V .

IL

IH

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = V ,

Fast Program Commands

IL

There are two Fast Program commands available

to improve the programming throughput, by writing

several adjacent words or bytes in parallel. The

Quadruple Byte Program command is available for

x8 operations, while the Double Word Program

command is available for x16 operations.

Quadruple Byte Program Command. The Qua-

druple Byte Program command is used to write a

page of four adjacent Bytes in parallel. The four

bytes must differ only for addresses A0, DQ15A-1.

A1 = V and A12-A20 specifying the block ad-

IH

dress. The other address bits may be set to either

V or V . If the addressed block is protected then

IL

IH

01h is output on Data Inputs/Outputs DQ0-DQ7,

otherwise 00h is output.

Read CFI Query Command

The Read CFI Query Command is used to read

data from the Common Flash Interface (CFI)

Memory Area. This command is valid when the de-

14/46

M29W320ET, M29W320EB

Five bus write cycles are necessary to issue the

Quadruple Byte Program command.

Once the Unlock Bypass command has been is-

sued the memory enters Unlock Bypass mode.

The Unlock Bypass Program command can then

be issued to program addresses or the Unlock By-

pass Reset command can be issued to return to

Read mode. In Unlock Bypass mode the memory

can be read as if in Read mode.

■

The first bus cycle sets up the Quadruple Byte

Program Command.

The second bus cycle latches the Address and

the Data of the first byte to be written.

The third bus cycle latches the Address and

the Data of the second byte to be written.

The fourth bus cycle latches the Address and

the Data of the third byte to be written.

When V is applied to the V /Write Protect pin

PP

the memory automatically enters the Unlock By-

pass mode and the Unlock Bypass Program com-

mand can be issued immediately.

The fifth bus cycle latches the Address and the

Data of the fourth byte to be written and starts

the Program/Erase Controller.

Unlock Bypass Program Command

The Unlock Bypass Program command can be

used to program one address in the memory array

at a time. The command requires two Bus Write

operations, the final write operation latches the ad-

dress and data, and starts the Program/Erase

Controller.

Double Word Program Command. The Double

Word Program command is used to write a page

of two adjacent words in parallel. The two words

must differ only for the address A0.

Three bus write cycles are necessary to issue the

Double Word Program command.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. The

operation cannot be aborted, a Bus Read opera-

tion outputs the Status Register. See the Program

command for details on the behavior.

■

The first bus cycle sets up the Double Word

Program Command.

The second bus cycle latches the Address and

the Data of the first word to be written.

The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

Unlock Bypass Reset Command

The Unlock Bypass Reset command can be used

to return to Read/Reset mode from Unlock Bypass

Mode. Two Bus Write operations are required to

issue the Unlock Bypass Reset command. Read/

Reset command does not exit from Unlock Bypass

Mode.

Programming should not be attempted when V

PP

is not at V

.

PPH

After programming has started, Bus Read opera-

tions output the Status Register content.

Chip Erase Command

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

Register. A Read/Reset command must be issued

to reset the error condition and return to Read

mode.

Note that the Fast Program commands cannot

change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

The Chip Erase command can be used to erase

the entire chip. Six Bus Write operations are re-

quired to issue the Chip Erase Command and start

the Program/Erase Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

leaving the data unchanged. No error condition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all commands, including the Erase Suspend com-

mand. It is not possible to issue any command to

abort the operation. Typical chip erase times are

given in Table 6.. All Bus Read operations during

the Chip Erase operation will output the Status

Register on the Data Inputs/Outputs. See the sec-

tion on the Status Register for more details.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

Typical Program times are given in Table 6., Pro-

gram, Erase Times and Program, Erase Endur-

ance Cycles.

Unlock Bypass Command

The Unlock Bypass command is used in conjunc-

tion with the Unlock Bypass Program command to

program the memory faster than with the standard

program commands. When the cycle time to the

device is long, considerable time saving can be

made by using these commands. Three Bus Write

operations are required to issue the Unlock By-

pass command.

15/46

M29W320ET, M29W320EB

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

ed. If the Erase Suspend command is issued dur-

ing the period when the memory is waiting for an

additional block (before the Program/Erase Con-

troller starts) then the Erase is suspended immedi-

ately and will start immediately when the Erase

Resume Command is issued. It is not possible to

select any further blocks to erase after the Erase

Resume.

Block Erase Command

The Block Erase command can be used to erase

a list of one or more blocks. It sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protected block or in the suspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not read and no error condition is given. Read-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

Six Bus Write operations are required to select the

first block in the list. Each additional block in the

list can be selected by repeating the sixth Bus

Write operation using the address of the additional

block. The Block Erase operation starts the Pro-

gram/Erase Controller after a time-out period of

50µs after the last Bus Write operation. Once the

Program/Erase Controller starts it is not possible

to select any more blocks. Each additional block

must therefore be selected within 50µs of the last

block. The 50µs timer restarts when an additional

block is selected. After the sixth Bus Write opera-

tion a Bus Read operation will output the Status

Register. See the Status Register section for de-

tails on how to identify if the Program/Erase Con-

troller has started the Block Erase operation.

During Erase Suspend a Bus Read operation to

the Extended Block will output the Extended Block

data.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Block Erase operation the memory will

ignore all commands except the Erase Suspend

command and the Read/Reset command which is

only accepted during the 50µs time-out period.

Typical block erase times are given in Table 6.

Erase Resume Command

The Erase Resume command must be used to re-

start the Program/Erase Controller after an Erase

Suspend. The device must be in Read Array mode

before the Resume command will be accepted. An

erase can be suspended and resumed more than

once.

Enter Extended Block Command

The M29W320E has an extra 64KByte block (Ex-

tended Block) that can only be accessed using the

Enter Extended Block command. Three Bus write

cycles are required to issue the Extended Block

command. Once the command has been issued

the device enters Extended Block mode where all

Bus Read or Program operations to the Boot Block

addresses access the Extended Block. The Ex-

tended Block (with the same address as the boot

block) cannot be erased, and can be treated as

one-time programmable (OTP) memory. In Ex-

tended Block mode the Boot Blocks are not acces-

sible.

After the Erase operation has started all Bus Read

operations will output the Status Register on the

Data Inputs/Outputs. See the section on the Sta-

tus Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

Register. A Read/Reset command must be issued

to reset the error condition and return to Read

mode.

Erase Suspend Command

To exit from the Extended Block mode the Exit Ex-

tended Block command must be issued.

The Extended Block can be protected, however

once protected the protection cannot be undone.

The Erase Suspend Command may be used to

temporarily suspend a Block Erase operation and

return the memory to Read mode. The command

requires one Bus Write operation.

The Program/Erase Controller will suspend within

the Erase Suspend Latency time of the Erase Sus-

pend Command being issued. Once the Program/

Erase Controller has stopped the memory will be

set to Read mode and the Erase will be suspend-

Exit Extended Block Command

The Exit Extended Block command is used to exit

from the Extended Block mode and return the de-

16/46

M29W320ET, M29W320EB

vice to Read mode. Four Bus Write operations are

required to issue the command.

Block Protect and Chip Unprotect Commands

21., Block Addresses. The whole chip can be un-

protected to allow the data inside the blocks to be

changed.

Block Protect and Chip Unprotect operations are

described in APPENDIX D.

Groups of blocks can be protected against acci-

dental Program or Erase. The Protection Groups

are shown in APPENDIX A., Table 20. and Table

Table 4. Commands, 16-bit mode, BYTE = V

IH

Bus Write Operations

Command

1st

2nd

3rd

4th

5th

6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1

3

X

F0

Read/Reset

555

AA

2AA

55

X

F0

90

(BA)

555

Auto Select

3

555

AA

Program

4

3

555

AA

50

555

PA1

555

A0

PD1

20

PA

PD

Double Word Program

Unlock Bypass

PA0 PD0

AA

2AA

PA

55

Unlock Bypass

Program

2

X

A0

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase Suspend

Erase Resume

1

3

4

BA

55

Read CFI Query

Enter Extended Block

Exit Extended Block

98

555

AA

2AA

55

555

88

90

X

00

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

17/46

M29W320ET, M29W320EB

Table 5. Commands, 8-bit mode, BYTE = V

IL

Bus Write Operations

3rd 4th

Command

1st

2nd

5th

6th

Add Data Add Data Add Data Add Data Add Data Add Data

1

3

X

F0

Read/Reset

AAA

AA

555

55

X

F0

90

A0

(BA)

AAA

Auto Select

3

AAA

AA

Program

4

5

3

2

6

AAA

X

AA

55

AAA

PA1

AAA

PA

PD

Quadruple Byte Program

Unlock Bypass

PA0 PD0

PD1 PA2 PD2 PA3 PD3

20

AA

A0

90

555

PA

55

PD

00

55

Unlock Bypass Program

Unlock Bypass Reset

Chip Erase

X

AAA

AA

B0

30

555

AAA

80

AAA

AA

555

55

AAA

BA

10

30

Block Erase

6+ AAA

Erase Suspend

1

3

4

BA

Erase Resume

Read CFI Query

Enter Extended Block

Exit Extended Block

AA

98

AAA

AA

555

55

AAA

88

90

X

00

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

(1, 2)

(2)

Parameter

Min

Unit

s

Typ

40

Max

(3)

Chip Erase

200

(3)

Block Erase (64 KBytes)

0.8

s

6

(4)

Erase Suspend Latency Time

Program (Byte or Word)

µs

s

50

(4)

(3)

10

40

20

10

200

100

Double Word Program (Byte or Word)

Chip Program (Byte by Byte)

Chip Program (Word by Word)

s

Chip Program (Quadruple Byte or Double Word)

Program/Erase Cycles (per Block)

Data Retention

s

100,000

20

cycles

years

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.

CC

4. Maximum value measured at worst case conditions for both temperature and V

.

CC

18/46

M29W320ET, M29W320EB

STATUS REGISTER

The M29W320E has one Status Register. It pro-

vides information on the current or previous Pro-

gram or Erase operations. The various bits convey

information and errors on the operation. Bus Read

operations from any address, always read the Sta-

tus Register during Program and Erase opera-

tions. It is also read during Erase Suspend when

an address within a block being erased is access-

ed.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress will show the bit is still ‘0’. One of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Register is read.

The bits in the Status Register are summarized in

Table 7., Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 7., Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 14. and Figure 15. describe Alternative

Toggle Bit timing waveform.

Figure 8., Toggle Flowchart, gives an example of

how to use the Data Toggle Bit. Figure 14. and

Figure 15. describe Toggle Bit timing waveform.

19/46

M29W320ET, M29W320EB

Table 7. Status Register Bits

Operation

Program

Address

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Any Address

DQ7

Toggle

0

–

0

Program During Erase

Suspend

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Any Address

DQ7

Toggle

1

0

–

1

0

1

–

0

1

Toggle

Erasing Block

Toggle

0

Block Erase before

timeout

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

0

Toggle

0

Block Erase

Erase Suspend

Erase Error

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

0

No Toggle

Hi-Z

0

Non-Erasing Block

Good Block Address

Faulty Block Address

Data read as normal

0

Toggle

1

No Toggle

Toggle

1

0

Note: Unspecified data bits should be ignored.

Figure 7. Data Polling Flowchart

START

Figure 8. Toggle Flowchart

START

READ DQ6

ADDRESS = BA

READ DQ5 & DQ7

at VALID ADDRESS

READ

DQ5 & DQ6

ADDRESS = BA

DQ7

=

DATA

YES

DQ6

=

NO

TOGGLE

NO

YES

DQ5

= 1

NO

DQ5

YES

= 1

YES

READ DQ7

at VALID ADDRESS

READ DQ6

TWICE

ADDRESS = BA

DQ7

=

YES

DQ6

=

DATA

NO

TOGGLE

NO

FAIL

YES

FAIL

PASS

AI90194

AI08929b

Note: BA = Address of Block being Programmed or Erased.

20/46

M29W320ET, M29W320EB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Symbol

Parameter

Min

–50

–65

Max

125

150

Unit

°C

T

Temperature Under Bias

Storage Temperature

BIAS

T

°C

STG

(1)

(2)

T

°C

LEAD

Lead Temperature during Soldering

260

V +0.6

CC

(3,4)

V

–0.6

V

IO

Input or Output Voltage

V

Supply Voltage

4

CC

V

Identification Voltage

13.5

ID

(5)

Program Voltage

–0.6

V

PP

®

Note: 1. Compliant with the ECOPACK 7191395 specification for Lead-free soldering processes.

2. Not exceeding 250°C for more than 30s, and peaking at 260°C.

3. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

4. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.

CC

5. V must not remain at 12V for more than a total of 80hrs.

PP

21/46

M29W320ET, M29W320EB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9., Operating and

AC Measurement Conditions. Designers should

check that the operating conditions in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 9. Operating and AC Measurement Conditions

M29W320E

Parameter

70

90

Unit

Min

2.7

Max

3.6

85

Min

2.7

Max

3.6

85

V

Supply Voltage

V

°C

pF

ns

V

CC

Ambient Operating Temperature

–40

Load Capacitance (C )

30

L

Input Rise and Fall Times

10

0 to V

Input Pulse Voltages

CC

V

CC

/2

V

CC

/2

Input and Output Timing Ref. Voltages

V

Figure 9. AC Measurement I/O Waveform

Figure 10. AC Measurement Load Circuit

V

CC

PP

CC

V

CC

V

/2

CC

25kΩ

0V

DEVICE

UNDER

TEST

AI05557

C

L

0.1µF

C

includes JIG capacitance

L

AI05558

Table 10. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

Unit

C

V

= 0V

6

pF

IN

C

V

OUT

12

OUT

Note: Sampled only, not 100% tested.

22/46

M29W320ET, M29W320EB

Table 11. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Max

±1

Unit

µA

I

0V ≤ V ≤ V

LI

IN

CC

I

LO

0V ≤ V ≤ V

OUT CC

±1

µA

E = V , G = V ,

IL

IH

(2)

Supply Current (Read)

10

100

20

mA

µA

mA

I

CC1

f = 6MHz

E = V ±0.2V,

CC

I

Supply Current (Standby)

CC2

RP = V ±0.2V

CC

V

/WP =

or V

PP

Supply Current (Program/

Erase)

Program/Erase

Controller active

(1,2)

IL

IH

I

CC3

V

/WP = V

PP

20

mA

V

PP

V

Input Low Voltage

Input High Voltage

–0.5

0.8

IL

0.7V

V

+0.3

CC

V

IH

CC

Voltage for V /WP Program

PP

Acceleration

V

I

V

= 2.7V ±10%

11.5

12.5

V

PP

CC

Current for V /WP Program

PP

Acceleration

= 2.7V ±10%

= 1.8mA

15

mA

PP

V

OL

I

Output Low Voltage

Output High Voltage

Identification Voltage

0.45

V

OL

V

OH

V

–0.4

= –100µA

CC

OH

V

11.5

1.8

12.5

2.3

ID

Program/Erase Lockout Supply

Voltage

V

LKO

V

Note: 1. Sampled only, not 100% tested.

2. In Dual operations the Supply Current will be the sum of I

(read) and I

CC1

(program/erase).

CC3

23/46

M29W320ET, M29W320EB

Figure 11. Read Mode AC Waveforms

tAVAV

VALID

A0-A20/

A–1

tAVQV

tAXQX

tEHQX

E

tELQV

tELQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI05559

Table 12. Read AC Characteristics

M29W320E

Symbol

Alt

Parameter

Test Condition

Unit

70

90

E = V ,

IL

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

70

90

ns

AVAV

RC

G = V

IL

E = V ,

IL

t

ACC

Max

90

AVQV

G = V

E = V

G = V

E = V

IL

(1)

t

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Min

Max

Min

0

ns

t

LZ

ELQX

t

70

0

90

0

ELQV

CE

(1)

t

OLZ

GLQX

t

OE

Max

30

25

35

30

GLQV

(1)

t

HZ

DF

EHQZ

GHQZ

t

IL

t

EHQX

Chip Enable, Output Enable or Address

Transition to Output Transition

t

Min

0

5

0

5

ns

GHQX

OH

AXQX

t

ELBL

ELFL

Chip Enable to BYTE Low or High

Max

ELBH

ELFH

t

BYTE Low to Output Hi-Z

BYTE High to Output Valid

Max

25

30

40

ns

BLQZ

FLQZ

t

FHQV

BHQV

Note: 1. Sampled only, not 100% tested.

24/46

M29W320ET, M29W320EB

Figure 12. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/

VALID

A–1

tWLAX

tAVWL

tWHEH

tWHGL

E

tELWL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI05560

Table 13. Write AC Characteristics, Write Enable Controlled

M29W320E

Unit

Symbol

Alt

Parameter

70

0

90

0

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Min

Max

Min

ns

µs

AVAV

t

CS

ELWL

t

WP

45

0

50

0

WLWH

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

Program/Erase Valid to RB Low

WHDX

t

0

WHEH

t

WPH

30

0

30

0

WHWL

t

AVWL

AS

t

45

0

50

0

WLAX

AH

t

GHWL

t

OEH

0

WHGL

(1)

t

30

50

35

50

t

BUSY

WHRL

t

V

CC

High to Chip Enable Low

VCHEL

VCS

Note: 1. Sampled only, not 100% tested.

25/46

M29W320ET, M29W320EB

Figure 13. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/

VALID

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

DQ0-DQ7/

DQ8-DQ15

VALID

V

CC

tVCHWL

RB

tEHRL

AI05561

Table 14. Write AC Characteristics, Chip Enable Controlled

M29W320E

Symbol

Alt

Parameter

Unit

70

0

90

0

t

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

Max

ns

AVAV

WC

t

WLEL

WS

t

45

0

50

0

ELEH

CP

DS

DH

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

Program/Erase Valid to RB Low

EHDX

t

WH

0

EHWH

t

30

0

30

0

EHEL

CPH

t

AVEL

AS

t

45

0

50

0

ELAX

AH

t

GHEL

t

0

EHGL

OEH

(1)

t

30

50

35

50

t

BUSY

EHRL

t

V

CC

High to Write Enable Low

Min

µs

VCHWL

VCS

Note: 1. Sampled only, not 100% tested.

26/46

M29W320ET, M29W320EB

Figure 14. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled

A0-A20

VALID ADDRESS

tAXEL

E

G

tELQV

Alternative Toggle/

Toggle Bit

Alternative Toggle/

Toggle Bit

Data

DQ2⁽¹⁾/DQ6⁽²⁾

AI09350

Note: 1. The Toggle bit is output on DQ6.

2. The Alternative Toggle bit is output on DQ2.

Figure 15. Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled

A0-A20

G

VALID ADDRESS

tAXGL

E

tGLQV

Alternative Toggle/

Toggle Bit

Alternative Toggle/

Toggle Bit

DQ2⁽¹⁾/DQ6⁽²⁾

Data

AI09351

Note: 1. The Toggle bit is output on DQ6.

2. The Alternative Toggle bit is output on DQ2.

Table 15. Toggle and Alternative Toggle Bits AC Characteristics

M29W320E

Symbol

Alt

Parameter

Unit

70

10

90

10

t

Address Transition to Chip Enable Low

Address Transition to Output Enable Low

Min

ns

AXEL

t

AXGL

Note: t

and t

values are presented in Table 12., Read AC Characteristics.

GLQV

ELQV

27/46

M29W320ET, M29W320EB

Figure 16. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPHPHH

tPLPX

RP

tPLYH

AI02931B

Table 16. Reset/Block Temporary Unprotect AC Characteristics

M29W320E

Symbol

Alt

Parameter

Unit

70

90

(1)

t

PHWL

RP High to Write Enable Low, Chip Enable Low,

Output Enable Low

t

Min

50

0

ns

PHEL

RH

(1)

t

PHGL

(1)

t

RHWL

RB High to Write Enable Low, Chip Enable Low,

Output Enable Low

t

0

ns

t

RB

RHEL

RHGL

t

RP Pulse Width

Min

500

50

500

50

ns

µs

PLPX

RP

t

READY

RP Low to Read Mode

Max

PLYH

(1)

t

RP Rise Time to V

Min

500

250

500

250

ns

t

VIDR

ID

PHPHH

V

PP

Rise and Fall Time

t

VHVPP

Note: 1. Sampled only, not 100% tested.

Figure 17. Accelerated Program Timing Waveforms

V

PP

V

/WP

PP

V

or V

IH

IL

tVHVPP

AI05563

28/46

M29W320ET, M29W320EB

PACKAGE MECHANICAL

Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

α

L

DIE

C

CP

TSOP-G

Note: Drawing not to scale.

Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.080

12.100

20.200

18.500

–

Typ

Max

A

A1

A2

B

0.0472

0.0059

0.0413

0.0106

0.0083

0.0031

0.4764

0.7953

0.7283

–

0.100

1.000

0.220

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0087

0.0020

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

α

0

5

0

5

29/46

M29W320ET, M29W320EB

Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z32

Note: Drawing not to scale.

Table 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

5.900

–

0.450

0.0138

0.2323

–

0.0177

D

6.000

4.000

6.100

0.2362

0.1575

0.2402

D1

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.000

1.200

0.400

7.900

8.100

0.3150

0.2205

0.0315

0.0394

0.0472

0.0157

0.3110

0.3189

E1

e

–

FD

FE

SD

SE

30/46

M29W320ET, M29W320EB

PART NUMBERING

Table 19. Ordering Information Scheme

Example:

M29W320EB

70

N

1

T

Device Type

M29

Operating Voltage

W = V = 2.7 to 3.6V

CC

Device Function

320E = 32 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6 x 8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

Note: This product is also available with the Extended Block factory locked. For further details and ordering

information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

31/46

M29W320ET, M29W320EB

APPENDIX A. BLOCK ADDRESSES

Table 20. Top Boot Block Addresses, M29W320ET

Block

0

(Kbytes/Kwords)

64/32

Protection Block Group

(x8)

(x16)

Protection Group

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

000000h–07FFFh

008000h–0FFFFh

010000h–17FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

1

2

Protection Group

3

4

5

6

7

8

9

Protection Group

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

32/46

M29W320ET, M29W320EB

Block

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

(Kbytes/Kwords)

64/32

8/4

Protection Block Group

(x8)

(x16)

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

Protection Group

(1)

Protection Group

3F0000h–3F1FFFh

3F2000h–3F3FFFh

3F4000h–3F5FFFh

3F6000h–3F7FFFh

3F8000h–3F9FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

(1)

64

65

66

67

68

69

70

8/4

1FA000h–1FAFFFh

1FB000h–1FBFFFh

(1)

1FC000h–1FCFFFh

1FD000h–1FDFFFh

(1)

3FA000h–3FBFFFh

3FC000h–3FDFFFh

(1)

1FE000h–1FEFFFh

(1)

3FE000h–3FFFFFh

1FF000h–1FFFFFh

Note: 1. Used as the Extended Block Addresses in Extended Block mode.

33/46

M29W320ET, M29W320EB

Table 21. Bottom Boot Block Addresses, M29W320EB

Block

(Kbytes/Kwords) Protection Block Group

(x8)

(x16)

(1)

0

1

2

3

4

5

6

8/4

Protection Group

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

00A000h-00BFFFh

00C000h-00DFFFh

(1)

7

8/4

00E000h-00FFFFh

8

64/32

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

9

Protection Group

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

Protection Group

34/46

M29W320ET, M29W320EB

Block

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

(Kbytes/Kwords) Protection Block Group

(x8)

(x16)

64/32

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

64/32

Protection Group

Note: 1. Used as the Extended Block Addresses in Extended Block mode.

35/46

M29W320ET, M29W320EB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

is read from the memory. Tables 22, 23, 24, 25, 26

and 27 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 27., Security Code Area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

Table 22. Query Structure Overview

Address

Sub-section Name

Description

x16

10h

1Bh

27h

x8

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific Extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

61h

80h

C2h

Security Code Area

64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Table 23. CFI Query Identification String

Address

Data

Description

Value

x16

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

x8

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h

0059h

0002h

0000h

0040h

0000h

“Q”

"R"

"Y"

Query Unique ASCII String "QRY"

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

AMD

Compatible

Address for Primary Algorithm extended Query table (see Table 26.)

P = 40h

NA

Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

NA

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

36/46

M29W320ET, M29W320EB

Table 24. CFI Query System Interface Information

Address

Data

Description

Value

x16

x8

V

Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

CC

1Bh

36h

0027h

0036h

00B5h

00C5h

2.7V

3.6V

Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

CC

1Ch

1Dh

1Eh

38h

3Ah

3Ch

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

PP

11.5V

12.5V

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in volts

PP

bit 3 to 0BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0004h

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

16µs

NA

Typical timeout per single byte/word program = 2 µs

n

Typical timeout for minimum size write buffer program = 2 µs

n

1s

Typical timeout per individual block erase = 2 ms

n

NA

Typical timeout for full Chip Erase = 2 ms

n

256 µs

NA

Maximum timeout for byte/word program = 2 times typical

n

Maximum timeout for write buffer program = 2 times typical

n

8 s

Maximum timeout per individual block erase = 2 times typical

n

NA

Maximum timeout for Chip Erase = 2 times typical

Table 25. Device Geometry Definition

Address

Data

Description

Value

x16

x8

n

27h

4Eh

0016h

4 MByte

Device Size = 2 in number of bytes

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface Code description

2Ah

2Bh

54h

56h

0000h

n

NA

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions. It specifies the number of

2Ch

58h

0002h

regions containing contiguous Erase Blocks of the same size.

2Dh

2Eh

5Ah

5Ch

0007h

0000h

Region 1 Information

Number of Erase Blocks of identical size = 0007h+1

8

2Fh

30h

5Eh

60h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8Kbyte

63

31h

32h

62h

64h

003Eh

0000h

Region 2 Information

Number of Erase Blocks of identical size = 003Eh+1

33h

34h

66h

68h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64Kbyte

Note: For the M29W320EB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to 1FFFFFh. For

the M29W320ET, Region 1 corresponds to addresses 1F8000h to 1FFFFFh and Region 2 to addresses 000000h to 1F7FFFh.

37/46

M29W320ET, M29W320EB

Table 26. Primary Algorithm-Specific Extended Query Table

Address

Data

Description

Value

x16

40h

41h

42h

43h

44h

45h

x8

80h

82h

84h

86h

88h

8Ah

0050h

0052h

0049h

0031h

0030h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Yes

Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

46h

47h

48h

49h

8Ch

8Eh

90h

92h

0002h

0001h

0004h

Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write

2

1

Block Protection

00 = not supported, x = number of blocks in per group

Temporary Block Unprotect

00 = not supported, 01 = supported

Yes

04

Block Protect /Unprotect

04 = M29W320E

4Ah

4Bh

4Ch

4Dh

94h

96h

98h

9Ah

0000h

00B5h

No

Simultaneous Operations, 00 = not supported

Burst Mode, 00 = not supported, 01 = supported

Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word

No

V

Supply Minimum Program/Erase voltage

11.5V

PP

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

4Eh

4Fh

9Ch

9Eh

00C5h

000xh

V

Supply Maximum Program/Erase voltage

12.5V

–

PP

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Top/Bottom Boot Block Flag

02h = Bottom Boot device, 03h = Top Boot device

Table 27. Security Code Area

Address

Data

Description

x16

61h

62h

63h

64h

x8

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

38/46

M29W320ET, M29W320EB

APPENDIX C. EXTENDED MEMORY BLOCK

The M29W320E has an extra block, the Extended

Block, that can be accessed using a dedicated

command.

This Extended Block is 32 KWords in x16 mode

and 64 KBytes in x8 mode. It is used as a security

block (to provide a permanent security identifica-

tion number) or to store additional information.

Factory Locked Extended Block

In devices where the Extended Block is factory

locked, the Security Identification Number is writ-

ten to the Extended Block address space (see Ta-

ble 28., Extended Block Address and Data) in the

factory. The DQ7 bit is set to ‘1’ and the Extended

Block cannot be unprotected.

The Extended Block is either Factory Locked or

Customer Lockable, its status is indicated by bit

DQ7. This bit is permanently set to either ‘1’ or ‘0’

at the factory and cannot be changed. When set to

‘1’, it indicates that the device is factory locked and

the Extended Block is protected. When set to ‘0’, it

indicates that the device is customer lockable and

the Extended Block is unprotected. Bit DQ7 being

permanently locked to either ‘1’ or ‘0’ is another

security feature which ensures that a customer

lockable device cannot be used instead of a facto-

ry locked one.

Customer Lockable Extended Block

A device where the Extended Block is customer

lockable is delivered with the DQ7 bit set to ‘0’ and

the Extended Block unprotected. It is up to the

customer to program and protect the Extended

Block but care must be taken because the protec-

tion of the Extended Block is not reversible.

There are two ways of protecting the Extended

Block:

■

Issue the Enter Extended Block command to

place the device in Extended Block mode,

then use the In-System Technique with RP

Bit DQ7 is the most significant bit in the Extended

Block Verify Code and a specific procedure must

be followed to read it. See “Extended Memory

Block Verify Code” in Table 2. and Table 3., Bus

either at V or at V (refer to APPENDIX D.,

IH

ID

In-System Technique and to the

corresponding flowcharts, Figure 22. and

Figure 23., for a detailed explanation of the

technique).

Operations, BYTE = V and Bus Operations,

IL

BYTE = V , respectively, for details of how to read

IH

■

Issue the Enter Extended Block command to

place the device in Extended Block mode,

then use the Programmer Technique (refer to

APPENDIX D., Programmer Technique and to

the corresponding flowcharts, Figure 20. and

Figure 21., for a detailed explanation of the

technique).

bit DQ7.

The Extended Block can only be accessed when

the device is in Extended Block mode. For details

of how the Extended Block mode is entered and

exited, refer to the Enter Extended Block Com-

mand and Exit Extended Block Command para-

graphs, and to Table 4. and Table 5., “Commands,

Once the Extended Block is programmed and pro-

tected, the Exit Extended Block command must be

issued to exit the Extended Block mode and return

the device to Read mode.

16-bit mode, BYTE = V ” and “Commands, 8-bit

IH

mode, BYTE = V ”, respectively.

IL

Table 28. Extended Block Address and Data

(1)

Data

Address

Device

x8

x16

Factory Locked

Customer Lockable

Security Identification

Number

3F0000h-3F000Fh

3F0010h-3FFFFFh

000000h-00000Fh

000010h-00FFFFh

1F8000h-1F8007h

1F8008h-1FFFFFh

000000h-000007h

000008h-007FFFh

Determined by

Customer

M29W320ET

M29W320EB

Unavailable

Security Identification

Number

Determined by

Customer

Unavailable

Note: 1. See Table 20. and Table 21., Top and Bottom Boot Block Addresses.

39/46

M29W320ET, M29W320EB

APPENDIX D. BLOCK PROTECTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the memo-

ry. The blocks are protected in groups, refer to

APPENDIX A., Table 20. and Table 21. for details

of the Protection Groups. Once protected, Pro-

gram and Erase operations within the protected

group fail to change the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In-System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is described in the Signal De-

scriptions section.

specified, it is followed as closely as possible. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

(1)

pin, RP . This can be achieved without violating

the maximum ratings of the components on the mi-

croprocessor bus, therefore this technique is suit-

able for use after the memory has been fitted to

the system.

To protect a group of blocks follow the flowchart in

Figure 22., In-System Equipment Group Protect

Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all the

groups can be unprotected at the same time. To

unprotect the chip follow Figure 23., In-System

Equipment Chip Unprotect Flowchart.

Programmer Technique

The Programmer technique uses high (V ) volt-

ID

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a group of blocks follow the flowchart in

Figure 20., Programmer Equipment Block Protect

Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all

groups can be unprotected at the same time. To

unprotect the chip follow Figure 21., Programmer

Equipment Chip Unprotect Flowchart. Table 29.,

Programmer Technique Bus Operations, BYTE =

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do

not allow the microprocessor to service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

V

or V , gives a summary of each operation.

IH

IL

Note: 1. RP can be either at V or at V when using the In-Sys-

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

IH

ID

tem Technique to protect the Extended Block.

Table 29. Programmer Technique Bus Operations, BYTE = V or V

IH

IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A20

Block (Group)

A9 = V , A12-A20 Block Address

ID

V

Pulse

X

IL

ID

IL

(1)

Others = X

Protect

A9 = V , A12 = V , A15 = V

ID

IH

V

ID

V

Chip Unprotect

Others = X

A0 = V , A1 = V , A6 = V , A9 = V ,

IL

IH

IL

ID

Block (Group)

Protection Verify

Pass = XX01h

Retry = XX00h

V

A12-A20 Block Address

Others = X

IL

IH

A0 = V , A1 = V , A6 = V , A9 = V ,

IL

IH

ID

Block (Group)

Unprotection Verify

Retry = XX01h

Pass = XX00h

V

A12-A20 Block Address

Others = X

Note: 1. Block Protection Groups are shown in APPENDIX A., Table 20. and Table 21.

40/46

M29W320ET, M29W320EB

Figure 20. Programmer Equipment Group Protect Flowchart

START

ADDRESS = GROUP ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = V

,

IH

A0, A6 = V

A1 = V

,

IL

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

NO

YES

++n

= 25

NO

A9 = V

E, G = V

IH

YES

PASS

A9 = V

IH

E, G = V

IH

AI05574

FAIL

Note: Block Protection Groups are shown in APPENDIX A., Table 20. and Table 21.

41/46

M29W320ET, M29W320EB

Figure 21. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1, A6 = V

IL

IH

E = V

IL

Wait 4µs

G = V

IL

INCREMENT

CURRENT GROUP

Wait 60ns

Read DATA

NO

YES

DATA

=

00h

LAST

GROUP

NO

++n

= 1000

YES

A9 = V

IH

A9 = V

IH

E, G = V

IH

FAIL

PASS

AI05575

Note: Block Protection Groups are shown in APPENDIX A., Table 20. and Table 21.

42/46

M29W320ET, M29W320EB

Figure 22. In-System Equipment Group Protect Flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 100µs

WRITE 40h

IL

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

Wait 4µs

READ DATA

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

DATA

NO

=

01h

YES

++n

= 25

NO

RP = V

IH

YES

ISSUE READ/RESET

COMMAND

RP = V

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI05576

Note: 1. Block Protection Groups are shown in APPENDIX A., Table 20. and Table 21.

2. RP can be either at V or at V when using the In-System Technique to protect the Extended Block.

IH

ID

43/46

M29W320ET, M29W320EB

Figure 23. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 4µs

INCREMENT

CURRENT GROUP

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

DATA

NO

YES

=

00h

++n

= 1000

NO

LAST

GROUP

YES

RP = V

IH

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PASS

FAIL

AI05577

Note: Block Protection Groups are shown in APPENDIX A., Table 20. and Table 21.

44/46

M29W320ET, M29W320EB

REVISION HISTORY

Table 30. Document Revision History

Date

Version

Revision Details

15-Apr-2004

1.0

First Issue.

45/46

M29W320ET, M29W320EB

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron

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46/46


型号：	M29W320ET90ZA1
厂家：	ST
描述：	2MX16 FLASH 3V PROM, 90ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, TFBGA-48 可编程只读存储器
文件：	总46页 (文件大小：820K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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