M29W512B55K1 [STMICROELECTRONICS]
64KX8 FLASH 3V PROM, 55ns, PQCC32, PLASTIC, LCC-32;型号: | M29W512B55K1 |
厂家: | ST |
描述: | 64KX8 FLASH 3V PROM, 55ns, PQCC32, PLASTIC, LCC-32 可编程只读存储器 内存集成电路 |
文件: | 总16页 (文件大小:136K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M29W512B
512 Kbit (64Kb x8, Bulk)
Low Voltage Single Supply Flash Memory
PRELIMINARY DATA
■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 55ns
■ PROGRAMMING TIME
– 10µs per Byte typical
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Chip Erase algorithm
– Status Register Polling and Toggle Bits
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
TSOP32 (NZ)
8 x 14mm
PLCC32 (K)
Figure 1. Logic Diagram
– Manufacturer Code: 20h
– Device Code: 27h
V
CC
16
8
A0-A15
DQ0-DQ7
W
E
M29W512B
G
V
SS
AI02743
July 1999
1/16
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M29W512B
Figure 2A. TSOP Connections
Figure 2B. PLCC Connections
A11
A9
1
32
G
A10
E
A8
A13
A14
NC
W
DQ7
DQ6
DQ5
DQ4
DQ3
1 32
A7
A14
A13
A8
A6
A5
A4
V
8
9
25
24
CC
A9
M29W512B
V
NC
NC
SS
A3
A2
9
25 A11
G
M29W512B
DQ2
DQ1
DQ0
A0
A15
A12
A7
A1
A10
E
A0
DQ0
DQ7
17
A6
A1
A5
A2
A4
16
17
A3
AI02755
AI02976
Table 1. Signal Names
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
required to control the memory is consistent with
JEDEC standards.
A0-A15
Address Inputs
Data Inputs/Outputs
DQ0-DQ7
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP32 (8 x 14mm) and
PLCC32 packages. Access times of 55ns, 70ns
90ns and 120ns are available. The memory is sup-
plied with all the bits erased (set to ’1’).
E
Chip Enable
G
W
Output Enable
Write Enable
V
CC
Supply Voltage
Ground
V
SS
SIGNAL DESCRIPTIONS
NC
Not Connected Internally
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
SUMMARY DESCRIPTION
The M29W512B is a 512 Kbit (64Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (2.7 to 3.6V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
Address Inputs (A0-A15). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
2/16
M29W512B
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
A
T
–50 to 125
–65 to 150
°C
BIAS
T
°C
STG
(2)
–0.6 to 4
–0.6 to 4
V
V
V
V
IO
V
CC
V
Identification Voltage
–0.6 to 13.5
ID
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 3, Bus Operations, for a summary. Typically
glitches of less than 5ns are ignored by the mem-
ory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
High, V , all other pins are ignored.
IH
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
Inputs, applying a Low signal, V , to Chip Enable
and Output Enable and keeping Write Enable
IL
The Command Interface is disabled when the V
CC
High, V . The Data Inputs/Outputs will output the
IH
Supply Voltage is less than the Lockout Voltage,
value, see Figure 7, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CC
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
.
CC3
able must remain High, V , during the whole Bus
IH
Vss Ground. The V
Ground is the reference
SS
Write operation. See Figures 8 and 9, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require-
ments.
for all voltage measurements.
3/16
M29W512B
Table 3. Bus Operations
Operation
Data
Inputs/Outputs
E
G
W
Address Inputs
Cell Address
V
V
V
IH
Bus Read
Bus Write
Output Disable
Standby
Data Output
Data Input
Hi-Z
IL
IL
IL
IH
IH
V
V
V
V
V
Command Address
IL
X
X
IH
V
X
X
X
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
20h
27h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
IH
IL
ID
V
V
Read Device Code
Others V or V
IL
IH
Note: X = V or V
.
IH
IL
Output Disable. The Data Inputs/Outputs are in
COMMAND INTERFACE
the high impedance state when Output Enable is
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
be held within V ± 0.2V. For the Standby current
level see Table 9, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
CC
The commands are summarized in Table 4, Com-
mands. Refer to Table 4 in conjunction with the
text descriptions below.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Chip Erase operation the memory will take about
10µs to abort the Chip Erase. During the abort pe-
riod no valid data can be read from the memory.
Issuing a Read/Reset command during a Chip
Erase operation will leave invalid data in the mem-
ory.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code and
the Device Code. Three consecutive Bus Write op-
erations are required to issue the Auto Select com-
mand. Once the Auto Select command is issued
the memory remains in Auto Select mode until an-
other command is issued.
Current, I
, for Program or Erase operations un-
CC3
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
. The
CC2
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 3, Bus Operations.
4/16
M29W512B
Table 4. Commands
Command
Bus Write Operations
3rd 4th
1st
2nd
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
555
555
555
555
2AA
2AA
2AA
2AA
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
555
555
555
PA
PD
AA
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
X
00
55
555
AA
2AA
555
80
555
2AA
55
555
10
Note: X Don’t Care, PA Program Address, PD Program Data.
All values in the table are in hexadecimal.
The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID or Device ID.
Program, Unlock Bypass Program, Chip Erase. After these commands read the Status Register until the Program/Erase Controller com-
pletes and the memory returns to Read Mode.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
After the program operation has completed the
From the Auto Select mode the Manufacturer
memory will return to the Read mode, unless an
Code can be read using a Bus Read operation
error has occurred. When an error occurs the
with A0 = V and A1 = V . The other address bits
IL
IL
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so will
cause an error. The Chip Erase command must be
used to set all the bits in the memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
may be set to either V or V . The Manufacturer
IL
IH
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V . The
IL
IH
Device Code for the M29W512B is 27h.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 5. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
5/16
M29W512B
Table 5. Program, Erase Times and Program, Erase Endurance Cycles
(T = 0 to 70°C)
A
Typical after
(1)
Parameter
Min
Max
Unit
Typ
(1)
100k W/E Cycles
Chip Erase (All bits in the memory set to ‘0’)
Chip Erase
0.5
0.5
1
sec
sec
1
6
200
4
Program
10
10
0.7
µs
Chip Program
0.7
sec
Program/Erase Cycles
100,000
cycles
Note: 1. T = 25°C, V = 3.3V.
A
CC
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted and the Status Reg-
ister is read. Errors must be reset using the Read/
Reset command, which leaves the device in Un-
lock Bypass Mode. See the Program command for
details on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the memory. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
All Bus Read operations during the Chip Erase op-
eration will output the Status Register on the Data
Inputs/Outputs. See the section on the Status
Register for more details. Typical chip erase times
are given in Table 5.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in
Table 6, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion. The Data Polling Bit is output on DQ7 when
the Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
Figure 3, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or any
address while erasing the chip.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation. The Toggle
Bit is output on DQ6 when the Status Register is
read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
The Chip Erase command sets all of the bits in the
memory to ’1’. All previous data is lost.
Figure 4, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
6/16
M29W512B
Table 6. Status Register Bits
Operation
Address
DQ7
DQ7
DQ7
0
DQ6
DQ5
Program
Any Address
Any Address
Any Address
Any Address
Toggle
Toggle
Toggle
Toggle
0
1
0
1
Program Error
Chip Erase
Erase Error
0
Note: Unspecified data bits should be ignored.
Figure 3. Data Polling Flowchart
Figure 4. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ6
NO
=
DQ7
=
DATA
YES
TOGGLE
YES
NO
NO
NO
DQ5
= 1
DQ5
= 1
YES
YES
READ DQ6
READ DQ7
DQ6
=
NO
DQ7
=
DATA
YES
TOGGLE
YES
FAIL
NO
PASS
FAIL
PASS
AI01370
AI01369
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram or Chip Erase operation fails to write the cor-
rect data to the memory. If the Error Bit is set a
Read/Reset command must be issued before oth-
er commands are issued. The Error bit is output on
DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’ and attempting to do so will
cause an error. The Chip Erase command must be
used to set all the bits the memory from ’0’ to ’1’.
7/16
M29W512B
Table 7. AC Measurement Conditions
Parameter
M29W512B
55
3.0 to 3.6V
30pF
70 / 90 / 120
2.7 to 3.6V
30pF
V
CC
Supply Voltage
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 10ns
0 to 3V
1.5V
≤ 10ns
Input Pulse Voltages
0 to 3V
1.5V
Input and Output Timing Ref. Voltages
Figure 6. AC Testing Load Circuit
Figure 5. AC Testing Input Output Waveform
0.8V
1N914
3V
1.5V
0V
3.3kΩ
AI01417
DEVICE
UNDER
TEST
OUT
C
= 30pF
L
C
includes JIG capacitance
AI02978
L
Table 8. Capacitance
(T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
OUT
V
OUT
12
pF
Note: Sampled only, not 100% tested.
8/16
M29W512B
Table 9. DC Characteristics
(T = 0 to 70°C)
A
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Supply Current (Standby)
Test Condition
Min
Max
Unit
µA
I
0V ≤ V ≤ V
±1
±1
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
µA
I
E = V , G = V , f = 6MHz
IL IH
10
mA
µA
CC1
I
E = V ± 0.2V
100
CC2
CC
Program/Erase
Controller active
(1)
Supply Current (Program/Erase)
20
mA
I
CC3
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Identification Voltage
Identification Current
–0.5
2
0.8
V
V
IL
V
V
V
+ 0.5
IH
CC
I
= 1.8mA
OL
0.45
V
OL
OH
V
I
= –100µA
V
– 0.4
V
OH
CC
V
ID
11.5
1.8
12.5
100
V
I
A9 = V
µA
ID
ID
Program/Erase Lockout Supply
Voltage
(1)
2.3
V
V
LKO
Note: 1. Sampled only, not 100% tested.
9/16
M29W512B
Table 10. Read AC Characteristics
(TA = 0 to 70°C)
M29W512B
70
Symbol
Alt
Parameter
Test Condition
Unit
55
90 / 120
E = V ,
Address Valid to Next Address
Valid
IL
t
t
Min
55
70
70
90
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
Max
55
90
AVQV
G = V
G = V
G = V
E = V
IL
IL
IL
Chip Enable Low to Output
Transition
(1)
t
Min
Max
Min
0
55
0
0
70
0
0
90
0
ns
ns
ns
t
LZ
ELQX
t
t
Chip Enable Low to Output Valid
ELQV
CE
Output Enable Low to Output
Transition
(1)
t
t
OLZ
IL
IL
GLQX
t
t
E = V
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Max
Max
Max
30
20
20
30
25
25
35
30
30
ns
ns
ns
GLQV
OE
(1)
t
G = V
t
HZ
DF
IL
IL
EHQZ
(1)
t
t
E = V
t
GHQZ
t
Chip Enable, Output Enable or
Address Transition to Output
Transition
EHQX
t
Min
0
0
0
ns
GHQX
OH
t
AXQX
Note: 1. Sampled only, not 100% tested.
Figure 7. Read Mode AC Waveforms
tAVAV
VALID
A0-A15
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
VALID
DQ0-DQ7
AI02977
10/16
M29W512B
Table 11. Write AC Characteristics, Write Enable Controlled
(T = 0 to 70 °C)
A
M29W512B
Symbol
Alt
Parameter
Unit
55
55
0
70
70
0
90 / 120
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
t
t
CS
ELWL
t
t
40
25
0
45
30
0
45
45
0
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
WHDX
t
0
0
0
WHEH
t
t
WPH
30
0
30
0
30
0
WHWL
t
t
AS
AVWL
t
t
40
0
45
0
45
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
0
WHGL
t
t
V
High to Chip Enable Low
CC
50
50
50
VCHEL
VCS
Figure 8. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A15
VALID
tWLAX
tAVWL
tWHEH
tWHGL
E
tELWL
G
W
tGHWL
tWLWH
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7
V
CC
tVCHEL
AI02757
11/16
M29W512B
Table 12. Write AC Characteristics, Chip Enable Controlled
(T = 0 to 70 °C)
A
M29W512B
Unit
Symbol
Alt
Parameter
55
55
0
70
70
0
90 / 120
t
t
WC
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
t
t
WS
WLEL
t
t
40
25
0
45
30
0
45
45
0
ELEH
CP
DS
t
t
t
DVEH
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
EHDX
DH
t
t
WH
0
0
0
EHWH
t
t
30
0
30
0
30
0
EHEL
CPH
t
t
AS
AVEL
t
t
40
0
45
0
45
0
ELAX
AH
t
GHEL
t
t
0
0
0
EHGL
OEH
t
t
V
High to Write Enable Low
CC
50
50
50
VCHWL
VCS
Figure 9. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A15
VALID
tELAX
tAVEL
tEHWH
tEHGL
W
G
E
tWLEL
tGHEL
tELEH
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7
V
CC
tVCHWL
AI02758
12/16
M29W512B
Table 13. Ordering Information Scheme
Example:
M29W512B
70 NZ
1
T
Device Type
M29
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
512B = 512 Kbit (64Kb x8), Bulk
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
120 = 120 ns
Package
NZ = TSOP32: 8 x 14 mm
K = PLCC32
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factory with the memory content erased (to FFh).
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
13/16
M29W512B
Table 14. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
14.20
12.50
8.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.559
0.492
0.319
–
A
A1
A2
B
0.05
0.95
0.17
0.10
13.80
12.30
7.90
–
0.002
0.037
0.007
0.004
0.543
0.484
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
Figure 10. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
14/16
M29W512B
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
mm
Min
2.54
1.52
inches
Symbol
Typ
Max
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Min
Max
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.100
0.060
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
0.89
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
15/16
M29W512B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved
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