M29W640DB70ZA1E_技术文档

M29W640DT

M29W640DB

64 Mbit (8Mb x8 or 4Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Packages

–

V_CC= 2.7V to 3.6V for Program, Erase,

Read

–

V_PP=12 V for Fast Program (optional)

■

ACCESS TIME: 90 ns

PROGRAMMING TIME

–

10 µs per Byte/Word typical

Double Word Programming Option

■

135 MEMORY BLOCKS

–

1 Boot Block and 7 Parameter Blocks,

8 KBytes each (Top or Bottom Location)

127 Main Blocks, 64 KBytes each

TSOP48 (N)

12 x 20mm

–

■

PROGRAM/ERASE CONTROLLER

–

Embedded Byte/Word Program

algorithms

FBGA

ERASE SUSPEND and RESUME MODES

–

Read and Program another Block during

Erase Suspend

TFBGA63 (ZA)

63 ball array

UNLOCK BYPASS PROGRAM COMMAND

Faster Production/Batch Programming

–

■

V_PP/WP Pin for FAST PROGRAM and WRITE

PROTECT

TEMPORARY BLOCK UNPROTECTION

MODE

COMMON FLASH INTERFACE

–

64-bit Security Code

■

EXTENDED MEMORY BLOCK

–

Extra block used as security block or to

store additional information

LOW POWER CONSUMPTION

Standby and Automatic Standby

–

■

100,000 PROGRAM/ERASE CYCLES per

BLOCK

ELECTRONIC SIGNATURE

–

Manufacturer Code: 0020h

Top Device Code M29W640DT: 22DEh

Bottom Device Code M29W640DB:

22DFh

December 2004

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M29W640DT, M29W640DB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

_PP/Write Protect (V_PP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

_CCSupply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Bus Operations, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Bus Operations, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Fast Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M29W640DT, M29W640DB

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Enter Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Commands, 16-bit mode, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Commands, 8-bit mode, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 16

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 13.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . . 26

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M29W640DT, M29W640DB

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26

Figure 15.TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline. . . . . . . . . . . 27

Table 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 27

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Top Boot Block Addresses, M29W640DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Bottom Boot Block Addresses, M29W640DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 27. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 28. Programmer Technique Bus Operations, BYTE = V_IHor V_{IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 43}

Figure 16.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 19.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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M29W640DT, M29W640DB

SUMMARY DESCRIPTION

The M29W640D is a 64 Mbit (8Mb x8 or 4Mb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode.

Figure 2. Logic Diagram

V

/WP

CC PP

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected in units of 256 KByte (generally groups

of four 64 KByte blocks), to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

22

15

A0-A21

DQ0-DQ14

W

E

DQ15A–1

BYTE

RB

M29W640DT

M29W640DB

G

RP

The device features an asymmetrical blocked ar-

chitecture. The device has an array of 135 blocks:

V

SS

AI05733

■

8 Parameters Blocks of 8 KBytes each (or

4 KWords each)

■

127 Main Blocks of 64 KBytes each (or

32 KWords each)

Table 1. Signal Names

M29W640DT has the Parameter Blocks at the top

of the memory address space while the

M29W640DB locates the Parameter Blocks start-

ing from the bottom.

The M29W640D has an extra block, the Extended

Block, (of 32 KWords in x16 mode or of 64 KBytes

in x8 mode) that can be accessed using a dedicat-

ed command. The Extended Block can be protect-

ed and so is useful for storing security information.

However the protection is not reversible, once pro-

tected the protection cannot be undone.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The V_PP/WP signal is used to enable faster pro-

gramming of the device, enabling double word

programming. If this signal is held at V_SS, the boot

block, and its adjacent parameter block, are pro-

tected from program and erase operations.

A0-A21

Address Inputs

DQ0-DQ7

DQ8-DQ14

Data Inputs/Outputs

DQ15A–1

(or DQ15)

Data Input/Output or Address Input

(or Data Input/Output)

E

Chip Enable

G

Output Enable

W

Write Enable

RP

RB

BYTE

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

V

CC

The memory is delivered with all the bits erased (set

to 1).

Supply Voltage for Fast Program

(optional) or Write Protect

V_PP/WP

V

Ground

SS

NC

Not Connected Internally

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M29W640DT, M29W640DB

Figure 3. TSOP Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

V

SS

DQ15A–1

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A19

A20

W

M29W640DT

M29W640DB

DQ12

DQ4

RP

A21

/WP

RB

A18

A17

A7

12

13

37

36

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

PP

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI05734

6/49

M29W640DT, M29W640DB

Figure 4. TFBGA Connections (Top view through package)

NC⁽¹⁾

8

DQ15

A–1

V

A13

A9

W

A12

A8

A14

A10

A21

A18

A6

A15

A11

A19

A20

A5

A16

DQ7

DQ5

DQ2

DQ0

A0

BYTE

DQ14

DQ12

DQ10

DQ8

E

SS

7

6

DQ13

DQ6

DQ4

DQ3

DQ1

V

RP

5

4

3

2

1

CC

V

/WP

RB

A7

A3

DQ11

DQ9

G

PP

A17

A4

NC⁽¹⁾

V

A2

A1

SS

NC⁽¹⁾

A

B

C

D

E

F

G

H

J

K

L

M

AI05735

Note: 1. Balls are shorted together via the substrate but not connected to the die.

7/49

M29W640DT, M29W640DB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.

Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the Program/Erase

Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation when BYTE is High,

V_IH. When BYTE is Low, V_IL, these pins are not

used and are high impedance. During Bus Write

operations the Command Register does not use

these bits. When reading the Status Register

these bits should be ignored.

and Erase operations in this block are ignored

while V_PP/Write Protect is Low.

When V_PP/Write Protect is High, V_IH, the memory

reverts to the previous protection status of the two

outermost boot blocks. Program and Erase opera-

tions can now modify the data in the two outermost

boot blocks unless the block is protected using

Block Protection.

When V_PP/Write Protect is raised to V_PPthe mem-

ory automatically enters the Unlock Bypass mode.

When V_PP/Write Protect returns to V_IHor V_ILnor-

mal operation resumes. During Unlock Bypass

Program operations the memory draws I_PPfrom

the pin to supply the programming circuits. See the

description of the Unlock Bypass command in the

Command Interface section. The transitions from

V_IHto V_PPand from V_PPto V_IHmust be slower

than t_VHVPP, see Figure 13..

Never raise V_PP/Write Protect to V_PPfrom any

mode except Read mode, otherwise the memory

may be left in an indeterminate state.

A 0.1µF capacitor should be connected between

the V_PP/Write Protect pin and the V_SSGround pin

to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during Unlock Bypass

Data Input/Output or Address Input (DQ15A–1).

When BYTE is High, V_IH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, V_IL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the ad-

dressed Word, DQ15A–1 High will select the MSB.

Throughout the text consider references to the

Data Input/Output to include this pin when BYTE is

High and references to the Address Inputs to in-

clude this pin when BYTE is Low except when

stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, V_IH, all other pins are ignored.

Program, I_PP

.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

Note that if V_PP/WP is at V_IL, then the two outer-

most boot blocks will remain protected even if RP

is at V_ID.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V_IL, for at least

t_PLPX. After Reset/Block Temporary Unprotect

Output Enable (G). The Output Enable, G, con-

goes High, V_IH, the memory will be ready for Bus

Read and Bus Write operations after t_PHELor

t_RHEL, whichever occurs last. See the Ready/Busy

Output section, Table 15. and Figure 12., Reset/

Block Temporary Unprotect AC Waveforms, for

more details.

Holding RP at V_IDwill temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V_IHto V_IDmust be slower than

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

V

_PP/Write Protect (V_PP/WP). The

V_PP/Write

Protect pin provides two functions. The V_PPfunc-

tion allows the memory to use an external high

voltage power supply to reduce the time required

for Unlock Bypass Program operations. The

Write Protect function provides a hardware meth-

od of protecting the two outermost boot blocks.

The V_PP/Write Protect pin must not be left floating

or unconnected.

t_PHPHH

.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, V_OL. Ready/Busy is high-im-

When V_PP/Write Protect is Low, V_IL, the memory

protects the two outermost boot blocks; Program

8/49

M29W640DT, M29W640DB

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 15. and Figure

12., Reset/Block Temporary Unprotect AC Wave-

forms, for more details.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the x8 and x16 Bus modes of the

memory. When Byte/Word Organization Select is

Low, V_IL, the memory is in x8 mode, when it is

High, V_IH, the memory is in x16 mode.

The Command Interface is disabled when the V_CC

Supply Voltage is less than the Lockout Voltage,

V_LKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the V_CCSupply Voltage pin and the V_SSGround

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during Program and

Erase operations, I_CC3

.

V_SSGround. V_SSis the reference for all voltage

measurements. The device features two V_SSpins

which must be both connected to the system

ground.

V_CCSupply Voltage (2.7V to 3.6V). V_CC

pro-

vides the power supply for all operations (Read,

Program and Erase).

9/49

M29W640DT, M29W640DB

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Table 2. and Table 3., Bus Operations, BYTE =

V_IH, for a summary. Typically glitches of less than

5ns on Chip Enable or Write Enable are ignored by

the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V_IL, to Chip Enable

and Output Enable and keeping Write Enable

High, V_IH. The Data Inputs/Outputs will output the

value, see Figure 9., Read Mode AC Waveforms,

and Table 12., Read AC Characteristics, for de-

tails of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, V_IH, during the whole Bus

Write operation. See Figure 10. and Figure

11., Write AC Waveforms, Chip Enable Con-

trolled, and Table 13. and Table 14., Write AC

Characteristics, Chip Enable Controlled, for de-

tails of the timing requirements.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I_CC3, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (V_CC± 0.2V)

are used to drive the bus and the bus is inactive for

300ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, I_CC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require V_IDto be applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Table 2. and Table 3., Bus Operations,

BYTE = V_IH.

Block Protect and Chip Unprotect. Groups

of

blocks can be protected against accidental Pro-

gram or Erase. The Protection Groups are shown

in APPENDIX A., Table 19. and Table 20., Bottom

Boot Block Addresses, M29W640DB. The whole

chip can be unprotected to allow the data inside

the blocks to be changed.

The V_PP/Write Protect pin can be used to protect

the two outermost boot blocks. When V_PP/Write

Protect is at V_ILthe two outermost boot blocks are

protected and remain protected regardless of the

Block Protection Status or the Reset/Block Tem-

porary Unprotect pin status.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, V_IH.

Standby. When Chip Enable is High, V_IH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, I_CC2, Chip Enable should

be held within V_CC± 0.2V. For the Standby current

level see Table 11., DC Characteristics.

Block Protect and Chip Unprotect operations are

described in APPENDIX D..

Table 2. Bus Operations, BYTE = V_IL

Data Inputs/Outputs

Address Inputs

DQ15A–1, A0-A21

Operation

E

G

W

DQ14-DQ8

Hi-Z

DQ7-DQ0

Data Output

Data Input

Hi-Z

V

IH

Bus Read

Cell Address

IL

IH

V

Bus Write

Command Address

Hi-Z

IL

Output Disable

Standby

X

Hi-Z

IH

V

IH

X

Hi-Z

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

IL

V

IH

Hi-Z

20h

IL

Others V or V

IL

IH

10/49

M29W640DT, M29W640DB

A0 = V , A1 = V ,

DEh (M29W640DT)

Hi-Z

IH

IL

V

Read Device Code

IL

IH

A9 = V , Others V or V

IH

DFh (M29W640DB)

ID

IL

M29W640DT

98h (factory locked)

18h (not factory locked)

A0 = V , A1 = V , A6 = V ,

Extended Memory

Block Verify Code

IH

IL

Hi-Z

IL

IH

A9 = V , Others V or V

IH

ID

IL

M29W640DB

88h (factory locked)

08h (not factory locked)

Note: X = V or V

.

IH

IL

Table 3. Bus Operations, BYTE = V_IH

Address Inputs

A0-A21

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

Bus Read

E

G

W

V

IH

Cell Address

Data Output

Data Input

Hi-Z

IL

IH

V

Bus Write

Command Address

IL

Output Disable

Standby

X

IH

V

X

Hi-Z

IH

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

0020h

IL

IH

Others V or V

IL

IH

A0 = V , A1 = V , A9 = V ,

22DEh (M29W640DT)

22DFh (M29W640DB)

IH

IL

ID

V

Read Device Code

Others V or V

IL

IH

M29W640DT

98h (factory locked)

18h (not factory locked)

A0 = V , A1 = V , A6 = V ,

Extended Memory

Block Verify Code

IH

IL

V

IH

IL

A9 = V , Others V or V

IH

ID

IL

M29W640DB

88h (factory locked)

08h (not factory locked)

Note: X = V or V

.

IH

IL

11/49

M29W640DT, M29W640DB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 4., or Table 5., depend-

ing on the configuration that is being used, for a

summary of the commands.

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Read CFI Query Command

The Read CFI Query Command is used to read

data from the Common Flash Interface (CFI)

Memory Area. This command is valid when the de-

vice is in the Read Array mode, or when the device

is in Autoselected mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequent Bus Read operations read from

the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Autoselected mode). A second Read/

Reset command would be needed if the device is

to be put in the Read Array mode from Autoselect-

ed mode.

Read/Reset Command.

The Read/Reset command returns the memory to

its Read mode. It also resets the errors in the Sta-

tus Register. Either one or three Bus Write opera-

tions can be used to issue the Read/Reset

command.

The Read/Reset command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. If the Read/Reset command is issued

during the timeout of a Block Erase operation then

the memory will take up to 10µs to abort. During

the abort period no valid data can be read from the

memory. The Read/Reset command will not abort

an Erase operation when issued while in Erase

Suspend.

See APPENDIX B., Table 21. to Table 26. for de-

tails on the information contained in the Common

Flash Interface (CFI) memory area.

Program Command.

The Program command can be used to program a

value to one address in the memory array at a

time. The command requires four Bus Write oper-

ations, the final write operation latches the ad-

dress and data, and starts the Program/Erase

Controller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the memory will ig-

nore all commands. It is not possible to issue any

command to abort or pause the operation. Typical

program times are given in Table 6.. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Auto Select Command.

The Auto Select command is used to read the

Manufacturer Code, the Device Code, the Block

Protection Status and the Extended Memory Block

Verify Code. Three consecutive Bus Write opera-

tions are required to issue the Auto Select com-

mand. Once the Auto Select command is issued

the memory remains in Auto Select mode until a

Read/Reset command is issued. Read CFI Query

and Read/Reset commands are accepted in Auto

Select mode, all other commands are ignored.

In Auto Select mode the Manufacturer Code can

be read using a Bus Read operation with A0 = V_IL

and A1 = V_IL. The other address bits may be set to

either V_ILor V_IH. The Manufacturer Code for ST-

Microelectronics is 0020h.

The Device Code can be read using a Bus Read

operation with A0 = V_IHand A1 = V_IL. The other

address bits may be set to either V_ILor V_IH. The

Device Code for the M29W640DT is 22DEh and

for the M29W640DB is 22DFh.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = V_IL,

A1 = V_IH, and A12-A21 specifying the address of

the block. The other address bits may be set to ei-

ther V_ILor V_IH. If the addressed block is protected

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Fast Program Commands

There are two Fast Program commands available

to improve the programming throughput, by writing

several adjacent words or bytes in parallel. The

12/49

M29W640DT, M29W640DB

Quadruple Byte Program command is available for

x8 operations, while the Double Word Program

command is available for x16 operations.

Quadruple Byte Program Command. The Qua-

druple Byte Program command is used to write a

page of four adjacent Bytes in parallel. The four

bytes must differ only for addresses A0, DQ15A-1.

Five bus write cycles are necessary to issue the

Quadruple Byte Program command.

program commands. When the cycle time to the

device is long, considerable time saving can be

made by using these commands. Three Bus Write

operations are required to issue the Unlock By-

pass command.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

■

The first bus cycle sets up the Quadruple Byte

Program Command.

The second bus cycle latches the Address and

the Data of the first byte to be written.

The third bus cycle latches the Address and

the Data of the second byte to be written.

The fourth bus cycle latches the Address and

the Data of the third byte to be written.

When V_PPis applied to the V_PP/Write Protect pin

the memory automatically enters the Unlock By-

pass mode and the Unlock Bypass Program com-

mand can be issued immediately.

Unlock Bypass Program Command.

The Unlock Bypass command is used in conjunc-

tion with the Unlock Bypass Program command to

program the memory. When the cycle time to the

device is long, considerable time saving can be

made by using these commands. Three Bus Write

operations are required to issue the Unlock By-

pass command.

The fifth bus cycle latches the Address and the

Data of the fourth byte to be written and starts

the Program/Erase Controller.

Double Word Program Command.

The Double Word Program command is used to

write a page of two adjacent words in parallel. The

two words must differ only for the address A0. Pro-

gramming should not be attempted when V_PPis

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

not at V_PPH

.

The memory offers accelerated program opera-

tions through the V_PP/Write Protect pin. When the

system asserts V_PPon the V_PP/Write Protect pin,

the memory automatically enters the Unlock By-

pass mode. The system may then write the two-

cycle Unlock Bypass program command se-

quence. The memory uses the higher voltage on

the V_PP/Write Protect pin, to accelerate the Unlock

Bypass Program operation.

Three bus write cycles are necessary to issue the

Double Word Program command.

■

The first bus cycle sets up the Double Word

Program Command.

The second bus cycle latches the Address and

the Data of the first word to be written.

The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

Never raise V_PP/Write Protect to V_PPfrom any

mode except Read mode, otherwise the memory

may be left in an indeterminate state.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus

Read operations will continue to output the Status

Register. A Read/Reset command must be issued

to reset the error condition and return to Read

mode.

Note that the Fast Program commands cannot

change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Reset Command.

The Unlock Bypass Reset command can be used

to return to Read/Reset mode from Unlock Bypass

Mode. Two Bus Write operations are required to

issue the Unlock Bypass Reset command. Read/

Reset command does not exit from Unlock Bypass

Mode.

Chip Erase Command.

The Chip Erase command can be used to erase

the entire chip. Six Bus Write operations are re-

quired to issue the Chip Erase Command and start

the Program/Erase Controller.

Typical Program times are given in Table

6., Program, Erase Times and Program, Erase

Endurance Cycles.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

Unlock Bypass Command.

The Unlock Bypass command is used in conjunc-

tion with the Unlock Bypass Program command to

program the memory faster than with the standard

13/49

M29W640DT, M29W640DB

leaving the data unchanged. No error condition is

given when protected blocks are ignored.

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

During the erase operation the memory will ignore

all commands, including the Erase Suspend com-

mand. It is not possible to issue any command to

abort the operation. Typical chip erase times are

given in Table 6.. All Bus Read operations during

the Chip Erase operation will output the Status

Register on the Data Inputs/Outputs. See the sec-

tion on the Status Register for more details.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

Erase Suspend Command.

The Erase Suspend Command may be used to

temporarily suspend a Block Erase operation and

return the memory to Read mode. The command

requires one Bus Write operation.

The Program/Erase Controller will suspend within

the Erase Suspend Latency time of the Erase Sus-

pend Command being issued. Once the Program/

Erase Controller has stopped the memory will be

set to Read mode and the Erase will be suspend-

ed. If the Erase Suspend command is issued dur-

ing the period when the memory is waiting for an

additional block (before the Program/Erase Con-

troller starts) then the Erase is suspended immedi-

ately and will start immediately when the Erase

Resume Command is issued. It is not possible to

select any further blocks to erase after the Erase

Resume.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command.

The Block Erase command can be used to erase

a list of one or more blocks. Six Bus Write opera-

tions are required to select the first block in the list.

Each additional block in the list can be selected by

repeating the sixth Bus Write operation using the

address of the additional block. The Block Erase

operation starts the Program/Erase Controller

about 50µs after the last Bus Write operation.

Once the Program/Erase Controller starts it is not

possible to select any more blocks. Each addition-

al block must therefore be selected within 50µs of

the last block. The 50µs timer restarts when an ad-

ditional block is selected. The Status Register can

be read after the sixth Bus Write operation. See

the Status Register section for details on how to

identify if the Program/Erase Controller has start-

ed the Block Erase operation.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protected block or in the suspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not read and no error condition is given. Read-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

Erase Resume Command.

The Erase Resume command must be used to re-

start the Program/Erase Controller after an Erase

Suspend. The device must be in Read Array mode

before the Resume command will be accepted. An

erase can be suspended and resumed more than

once.

During the Block Erase operation the memory will

ignore all commands except the Erase Suspend

command. Typical block erase times are given in

Table 6.. All Bus Read operations during the Block

Erase operation will output the Status Register on

the Data Inputs/Outputs. See the section on the

Status Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Enter Extended Block Command

The device has an extra 64 KByte block (Extended

Block) that can only be accessed using the Enter

Extended Block command. Three Bus write cycles

are required to issue the Extended Block com-

mand. Once the command has been issued the

device enters Extended Block mode where all Bus

Read or Write operations to the Boot Block ad-

dresses access the Extended Block. The Extend-

ed Block (with the same address as the Boot

Blocks) cannot be erased, and can be treated as

one-time programmable (OTP) memory. In Ex-

14/49

M29W640DT, M29W640DB

tended Block mode the Boot Blocks are not acces-

sible.

vice to Read mode. Four Bus Write operations are

required to issue the command.

To exit from the Extended Block mode the Exit Ex-

tended Block command must be issued.

The Extended Block can be protected, however

once protected the protection cannot be undone.

Exit Extended Block Command

The Exit Extended Block command is used to exit

from the Extended Block mode and return the de-

Block Protect and Chip Unprotect Commands

Groups of blocks can be protected against acci-

dental Program or Erase. The Protection Groups

are shown in APPENDIX A., Table 19. and Table

20., Bottom Boot Block Addresses, M29W640DB.

The whole chip can be unprotected to allow the

data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are

described in APPENDIX D..

Table 4. Commands, 16-bit mode, BYTE = V_IH

Bus Write Operations

Command

1st

2nd

3rd

4th

5th

6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1

3

4

3

X

F0

AA

50

Read/Reset

555

2AA

55

X

F0

90

Auto Select

555

PA1

555

Program

A0

PA

PD

Double Word Program

Unlock Bypass

PA0 PD0

PD1

20

AA

2AA

PA

55

Unlock Bypass

Program

2

X

A0

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase Suspend

Erase Resume

1

3

4

X

Read CFI Query

Enter Extended Block

Exit Extended Block

55

98

555

AA

2AA

55

555

88

90

X

00

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IL

IH

Table 5. Commands, 8-bit mode, BYTE = V_IL

Bus Write Operations

3rd 4th

Add Data Add Data Add Data Add Data Add Data Add Data

Command

1st

2nd

5th

6th

1

3

X

F0

AA

Read/Reset

Auto Select

AAA

555

55

X

F0

90

AAA

15/49

M29W640DT, M29W640DB

Bus Write Operations

3rd 4th

Add Data Add Data Add Data Add Data Add Data Add Data

Command

1st

2nd

5th

6th

Program

4

5

3

2

6

AAA

X

AA

55

555

55

AAA

PA1

AAA

A0

PA

PD

Quadruple Byte Program

Unlock Bypass

PA0 PD0

PD1 PA2 PD2 PA3 PD3

20

AA

A0

90

555

PA

55

PD

00

55

Unlock Bypass Program

Unlock Bypass Reset

Chip Erase

X

AAA

AA

B0

30

555

AAA

80

AAA

AA

555

55

AAA

BA

10

30

Block Erase

6+ AAA

Erase Suspend

1

3

4

X

Erase Resume

X

Read CFI Query

Enter Extended Block

Exit Extended Block

AA

AAA

98

AA

555

55

AAA

88

90

X

00

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

(1, 2)

(2)

Parameter

Min

Unit

s

Typ

80

Max

(3)

Chip Erase

400

(4)

Block Erase (64 KBytes)

0.8

s

6

(4)

Erase Suspend Latency Time

µs

s

50

(3)

Program (Byte or Word)

10

80

40

20

200

400

200

100

Double Word Program (Byte or Word)

Chip Program (Byte by Byte)

Chip Program (Word by Word)

Chip Program (Quadruple Byte or Double Word)

s

Program/Erase Cycles (per Block)

Data Retention

100,000

20

cycles

years

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.

CC

4. Maximum value measured at worst case conditions for both temperature and V

.

CC

16/49

M29W640DT, M29W640DB

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is accessed.

The bits in the Status Register are summarized in

Table 7., Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress will show the bit is still ‘0’. One of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Register is read.

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Figure 5., Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 6., Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

17/49

M29W640DT, M29W640DB

Table 7. Status Register Bits

Operation

Program

Address

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Any Address

DQ7

Toggle

0

–

0

Program During Erase

Suspend

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Any Address

DQ7

Toggle

1

0

–

1

0

1

–

Hi-Z

0

1

Toggle

Erasing Block

Toggle

Block Erase before

timeout

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

0

Toggle

Hi-Z

0

Block Erase

Erase Suspend

Erase Error

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

No Toggle

Hi-Z

0

Non-Erasing Block

Good Block Address

Faulty Block Address

Data read as normal

0

Toggle

1

No Toggle

Toggle

1

0

Note: Unspecified data bits should be ignored.

Figure 5. Data Polling Flowchart

Figure 6. Data Toggle Flowchart

START

READ DQ6

READ DQ5 & DQ7

at VALID ADDRESS

READ

DQ5 & DQ6

DQ7

=

DATA

YES

DQ6

NO

=

NO

TOGGLE

YES

NO

DQ5

= 1

NO

DQ5

YES

= 1

YES

READ DQ7

at VALID ADDRESS

READ DQ6

TWICE

DQ7

=

DATA

YES

DQ6

=

NO

FAIL

TOGGLE

YES

FAIL

PASS

AI90194

AI90195B

18/49

M29W640DT, M29W640DB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Symbol

Parameter

Min

–50

–65

Max

125

150

Unit

°C

T

Temperature Under Bias

Storage Temperature

BIAS

T

°C

STG

(1)

(2)

T

°C

LEAD

Lead Temperature during Soldering

260

V +0.6

CC

(3,4)

V

–0.6

V

IO

Input or Output Voltage

V

Supply Voltage

4

CC

V

ID

Identification Voltage

13.5

(5)

Program Voltage

V

PP

®

Note: 1. Compliant with the ECOPACK 7191395 specification for Lead-free soldering processes.

2. Not exceeding 250°C for more than 30s, and peaking at 260°C.

3. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

4. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.

CC

5. V must not remain at 12V for more than a total of 80hrs.

PP

19/49

M29W640DT, M29W640DB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 9. Operating and AC Measurement Conditions

Parameter

M29W640D

Unit

Min

2.7

Max

3.6

85

V

Supply Voltage

V

°C

pF

ns

V

CC

Ambient Operating Temperature

–40

Load Capacitance (C )

30

10

L

Input Rise and Fall Times

0 to V

Input Pulse Voltages

CC

V

/2

Input and Output Timing Ref. Voltages

V

CC

Figure 7. AC Measurement I/O Waveform

Figure 8. AC Measurement Load Circuit

V

CC

PP

CC

V

CC

V

/2

CC

25kΩ

0V

DEVICE

UNDER

TEST

AI05557

25kΩ

C

L

0.1µF

C

includes JIG capacitance

L

AI05558

Table 10. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

Unit

C

V

IN

= 0V

6

pF

IN

C

V

OUT

12

OUT

Note: Sampled only, not 100% tested.

20/49

M29W640DT, M29W640DB

Table 11. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Max

±1

Unit

µA

I

LI

0V ≤ V ≤ V

IN

CC

I

0V ≤ V

≤ V

OUT CC

±1

µA

LO

E = V , G = V ,

IL

IH

I

Supply Current (Read)

10

100

20

mA

µA

mA

CC1

f = 6MHz

E = V ±0.2V,

CC

I

Supply Current (Standby)

CC2

RP = V ±0.2V

CC

V

/WP =

or V

IH

PP

Supply Current (Program/

Erase)

Program/Erase

Controller active

IL

I

CC3

V

/WP = V

PP

20

mA

V

PP

V

Input Low Voltage

Input High Voltage

–0.5

0.8

IL

V

0.7V

V

+0.3

V

IH

CC

Voltage for V_PP/WP Program

Acceleration

V

= 2.7V ±10%

11.5

12.5

V

PP

CC

Current for V_PP/WP Program

Acceleration

I

= 2.7V ±10%

= 1.8mA

15

mA

V

I

Output Low Voltage

Output High Voltage

Identification Voltage

0.45

V

OL

V

–0.4

CC

= –100µA

OH

V

11.5

1.8

12.5

2.3

ID

Program/Erase Lockout Supply

Voltage

(1)

V

LKO

Note: 1. Sampled only, not 100% tested.

21/49

M29W640DT, M29W640DB

Figure 9. Read Mode AC Waveforms

tAVAV

VALID

A0-A20/

A–1

tAVQV

tAXQX

tEHQX

E

tELQV

tELQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI05559

Table 12. Read AC Characteristics

Symbol

Alt

Parameter

Test Condition

M29W640D Unit

E = V ,

IL

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

90

ns

AVAV

RC

G = V

IL

E = V ,

IL

t

ACC

Max

AVQV

G = V

E = V

IL

(1)

t

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Min

Max

Min

0

ns

t

LZ

ELQX

t

90

0

ELQV

CE

(1)

t

OLZ

IL

GLQX

t

E = V

Max

35

30

GLQV

OE

(1)

t

G = V

t

HZ

DF

IL

EHQZ

t

E = V

GHQZ

t

EHQX

Chip Enable, Output Enable or Address

Transition to Output Transition

t

Min

0

5

ns

GHQX

OH

AXQX

t

ELBL

ELFL

Chip Enable to BYTE Low or High

Max

ELBH

ELFH

t

BYTE Low to Output Hi-Z

BYTE High to Output Valid

Max

30

40

ns

BLQZ

FLQZ

t

FHQV

BHQV

Note: 1. Sampled only, not 100% tested.

22/49

M29W640DT, M29W640DB

Figure 10. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/

VALID

A–1

tWLAX

tAVWL

tWHEH

tWHGL

E

tELWL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI05560

Table 13. Write AC Characteristics, Write Enable Controlled

Symbol

Alt

Parameter

Address Valid to Next Address Valid

M29W640D Unit

t

WC

Min

90

0

ns

AVAV

t

CS

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

ELWL

t

50

0

WLWH

WP

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

WHDX

t

0

WHEH

t

WPH

30

0

WHWL

t

AS

AVWL

t

50

0

WLAX

AH

t

GHWL

t

OEH

0

WHGL

(1)

t

Program/Erase Valid to RB Low

Max

Min

35

50

ns

µs

t

BUSY

WHRL

t

V

High to Chip Enable Low

CC

VCHEL

VCS

Note: 1. Sampled only, not 100% tested.

23/49

M29W640DT, M29W640DB

Figure 11. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/

VALID

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI05561

Table 14. Write AC Characteristics, Chip Enable Controlled

Symbol

Alt

Parameter

Address Valid to Next Address Valid

M29W640D Unit

t

WC

Min

90

0

ns

AVAV

t

WS

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

WLEL

t

50

0

ELEH

CP

DS

DH

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

EHDX

t

WH

0

EHWH

t

30

0

EHEL

CPH

t

AS

AVEL

t

50

0

ELAX

AH

t

GHEL

t

0

EHGL

OEH

(1)

t

Program/Erase Valid to RB Low

Max

Min

35

50

ns

µs

t

BUSY

EHRL

t

V

High to Write Enable Low

CC

VCHWL

VCS

Note: 1. Sampled only, not 100% tested.

24/49

M29W640DT, M29W640DB

Figure 12. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX

RP

tPHPHH

tPLYH

AI02931B

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Symbol

Alt

Parameter

M29W640D

Unit

(1)

t

PHWL

RP High to Write Enable Low, Chip Enable Low, Output

Enable Low

t

Min

50

0

ns

PHEL

RH

(1)

t

PHGL

(1)

t

RHWL

RB High to Write Enable Low, Chip Enable Low, Output

Enable Low

t

ns

t

RB

RHEL

RHGL

t

RP Pulse Width

Min

Max

Min

500

50

ns

µs

ns

PLPX

RP

t

READY

RP Low to Read Mode

PLYH

(1)

t

RP Rise Time to V

500

t

VIDR

ID

PHPHH

V

Rise and Fall Time

PP

Min

250

ns

t

VHVPP

Note: 1. Sampled only, not 100% tested.

Figure 13. Accelerated Program Timing Waveforms

V

PP

V

/WP

PP

V

or V

IH

IL

tVHVPP

AI05563

25/49

M29W640DT, M29W640DB

PACKAGE MECHANICAL

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Note: Drawing is not to scale.

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.100

20.200

18.500

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.0039

0.7953

0.7283

–

A

A1

A2

B

0.100

1.000

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0020

0.0374

0.0067

0.0039

C

CP

D

19.800

18.300

–

0.7795

0.7205

–

D1

e

0.500

0.0197

E

11.900

0.500

0

12.100

0.700

5

0.4685

0.0197

0

0.4764

0.0276

5

L

alfa

N

48

26/49

M29W640DT, M29W640DB

Figure 15. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline

D

D1

SD

FD

e

ddd

SE

E

E1

BALL "A1"

FE

e

b

A

A2

A1

BGA-Z33

Note: Drawing is not to scale.

Table 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.250

0.0098

0.900

0.0354

0.350

0.450

0.0138

0.0177

D

7.000

5.600

–

6.900

7.100

0.2756

0.2205

–

0.2717

0.2795

D1

ddd

E

–

0.100

–

0.0039

11.000

8.800

0.800

0.700

1.100

0.400

10.900

11.100

0.4331

0.3465

0.0315

0.0276

0.0433

0.0157

0.4291

0.4370

E1

e

–

FD

FE

SD

SE

27/49

M29W640DT, M29W640DB

PART NUMBERING

Table 18. Ordering Information Scheme

Example:

M29W640DB

90

N

1

T

Device Type

M29

Operating Voltage

W = V = 2.7 to 3.6V

CC

Device Function

640D = 64 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA63: 7x11mm, 0.80 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

Note: This product is also available with the Extended Block factory locked. For further details and ordering

information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to 1. For a list of available op-

tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact your

nearest ST Sales Office.

28/49

M29W640DT, M29W640DB

APPENDIX A. BLOCK ADDRESSES

Table 19. Top Boot Block Addresses, M29W640DT

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

0

64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

1

Protection Group

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

29/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Block

(x8)

(x16)

Group

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64/32

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Protection Group

30/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

64/32

400000h–40FFFFh

410000h–41FFFFh

420000h–42FFFFh

430000h–43FFFFh

440000h–44FFFFh

450000h–45FFFFh

460000h–46FFFFh

470000h–47FFFFh

480000h–48FFFFh

490000h–49FFFFh

4A0000h–4AFFFFh

4B0000h–4BFFFFh

4C0000h–4CFFFFh

4D0000h–4DFFFFh

4E0000h–4EFFFFh

4F0000h–4FFFFFh

500000h–50FFFFh

510000h–51FFFFh

520000h–52FFFFh

530000h–53FFFFh

540000h–54FFFFh

550000h–55FFFFh

560000h–56FFFFh

570000h–57FFFFh

580000h–58FFFFh

590000h–59FFFFh

5A0000h–5AFFFFh

5B0000h–5BFFFFh

5C0000h–5CFFFFh

5D0000h–5DFFFFh

5E0000h–5EFFFFh

5F0000h–5FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

Protection Group

31/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Block

(x8)

(x16)

Group

96

64/32

600000h–60FFFFh

610000h–61FFFFh

620000h–62FFFFh

630000h–63FFFFh

640000h–64FFFFh

650000h–65FFFFh

660000h–66FFFFh

670000h–67FFFFh

680000h–68FFFFh

690000h–69FFFFh

6A0000h–6AFFFFh

6B0000h–6BFFFFh

6C0000h–6CFFFFh

6D0000h–6DFFFFh

6E0000h–6EFFFFh

6F0000h–6FFFFFh

700000h–70FFFFh

710000h–71FFFFh

720000h–72FFFFh

730000h–73FFFFh

740000h–74FFFFh

750000h–75FFFFh

760000h–76FFFFh

770000h–77FFFFh

780000h–78FFFFh

790000h–79FFFFh

7A0000h–7AFFFFh

7B0000h–7BFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

97

Protection Group

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Protection Group

32/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

124

125

126

127

64/32

8/4

7C0000h–7CFFFFh

7D0000h–7DFFFFh

7E0000h–7EFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

(1)

7F0000h–7F1FFFh

7F2000h–7F3FFFh

7F4000h–7F5FFFh

7F6000h–7F7FFFh

7F8000h–7F9FFFh

3F8000h–3F8FFFh

(1)

128

129

130

131

132

133

134

8/4

3F9000h–3F9FFFh

(1)

3FA000h–3FAFFFh

Protection Group

(1)

3FB000h–3FBFFFh

(1)

3FC000h–3FCFFFh

(1)

7FA000h–7FBFFFh

7FC000h–7FDFFFh

3FD000h–3FDFFFh

(1)

3FE000h–3FEFFFh

(1)

7FE000h–7FFFFFh

3FF000h–3FFFFFh

Note: 1. Used as the Extended Block Addresses in Extended Block mode.

Table 20. Bottom Boot Block Addresses, M29W640DB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

(1)

0

1

2

3

4

5

6

7

8/4

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

000000h–000FFFh

(1)

001000h–001FFFh

(1)

002000h–002FFFh

(1)

003000h–003FFFh

(1)

004000h–004FFFh

Protection Group

(1)

00A000h-00BFFFh

005000h–005FFFh

(1)

00C000h-00DFFFh

006000h–006FFFh

(1)

00E000h-00FFFFh

007000h–007FFFh

8

64/32

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

9

10

11

12

13

14

Protection Group

33/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Block

(x8)

(x16)

Group

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

64/32

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

Protection Group

34/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

64/32

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h-40FFFFh

410000h-41FFFFh

420000h-42FFFFh

430000h-43FFFFh

440000h-44FFFFh

450000h-45FFFFh

460000h-46FFFFh

470000h-47FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

Protection Group

35/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Block

(x8)

(x16)

Group

79

80

64/32

480000h-48FFFFh

490000h-49FFFFh

4A0000h-4AFFFFh

4B0000h-4BFFFFh

4C0000h-4CFFFFh

4D0000h-4DFFFFh

4E0000h-4EFFFFh

4F0000h-4FFFFFh

500000h-50FFFFh

510000h-51FFFFh

520000h-52FFFFh

530000h-53FFFFh

540000h-54FFFFh

550000h-55FFFFh

560000h-56FFFFh

570000h-57FFFFh

580000h-58FFFFh

590000h-59FFFFh

5A0000h-5AFFFFh

5B0000h-5BFFFFh

5C0000h-5CFFFFh

5D0000h-5DFFFFh

5E0000h-5EFFFFh

5F0000h-5FFFFFh

600000h-60FFFFh

610000h-61FFFFh

620000h-62FFFFh

630000h-63FFFFh

640000h-64FFFFh

650000h-65FFFFh

660000h-66FFFFh

670000h-67FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

Protection Group

81

82

83

84

Protection Group

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

36/49

M29W640DT, M29W640DB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

64/32

680000h-68FFFFh

690000h-69FFFFh

6A0000h-6AFFFFh

6B0000h-6BFFFFh

6C0000h-6CFFFFh

6D0000h-6DFFFFh

6E0000h-6EFFFFh

6F0000h-6FFFFFh

700000h-70FFFFh

710000h-71FFFFh

720000h-72FFFFh

730000h-73FFFFh

740000h-74FFFFh

750000h-75FFFFh

760000h-76FFFFh

770000h-77FFFFh

780000h-78FFFFh

790000h-79FFFFh

7A0000h-7AFFFFh

7B0000h-7BFFFFh

7C0000h-7CFFFFh

7D0000h-7DFFFFh

7E0000h-7EFFFFh

7F0000h-7FFFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

Protection Group

Note: 1. Used as the Extended Block Addresses in Extended Block mode.

37/49

M29W640DT, M29W640DB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

is read from the memory. Table 21. to Table 26.

show the addresses used to retrieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 26., Security Code Area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST.

Table 21. Query Structure Overview

Address

Sub-section Name

Description

x16

10h

1Bh

27h

x8

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific Extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

80h

61h

C2h

Security Code Area

64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Table 22. CFI Query Identification String

Address

Data

Description

Value

x16

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

x8

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h

0059h

0002h

0000h

0040h

0000h

“Q”

"R"

"Y"

Query Unique ASCII String "QRY"

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

AMD

Compatible

Address for Primary Algorithm extended Query table (see Table 25.)

P = 40h

NA

Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

NA

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

38/49

M29W640DT, M29W640DB

Table 23. CFI Query System Interface Information

Address

Data

Description

Value

x16

x8

V

Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

CC

1Bh

36h

0027h

0036h

00B5h

00C5h

2.7V

3.6V

Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

CC

1Ch

1Dh

1Eh

38h

3Ah

3Ch

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

PP

11.5V

12.5V

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in volts

PP

bit 3 to 0BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0004h

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

16µs

NA

Typical timeout per single byte/word program = 2 µs

n

Typical timeout for minimum size write buffer program = 2 µs

n

1s

Typical timeout per individual Block Erase = 2 ms

n

NA

Typical timeout for full Chip Erase = 2 ms

n

256 µs

NA

Maximum timeout for byte/word program = 2 times typical

n

Maximum timeout for write buffer program = 2 times typical

n

8s

Maximum timeout per individual Block Erase = 2 times typical

n

NA

Maximum timeout for Chip Erase = 2 times typical

Table 24. Device Geometry Definition

Address

Data

Description

Value

x16

x8

n

27h

4Eh

0017h

8 MByte

Device Size = 2 in number of bytes

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface Code description

2Ah

2Bh

54h

56h

0000h

n

NA

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions. It specifies the number of

2Ch

58h

0002h

regions containing contiguous Erase Blocks of the same size.

2Dh

2Eh

5Ah

5Ch

0007h

0000h

Region 1 Information

Number of Erase Blocks of identical size = 0007h+1

8

2Fh

30h

5Eh

60h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8Kbyte

127

31h

32h

62h

64h

007Eh

0000h

Region 2 Information

Number of Erase Blocks of identical size= 007Eh+1

33h

34h

66h

68h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64Kbyte

39/49

M29W640DT, M29W640DB

Address

Data

Description

Value

x16

x8

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Region 3 Information

Number of Erase Blocks of identical size=007Fh+1

Region 3 Information

0

Block size in Region 3 = 0000h * 256 byte

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Region 4 Information

Number of Erase Blocks of Identical size=007Fh+1

Region 4 Information

0

Block size in Region 4 = 0000h * 256 byte

Note: For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase Block Region 2 from address

008000h to 3FFFFFh.

For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase Block Region 2 from address

3F8000h to 3FFFFFh.

Table 25. Primary Algorithm-Specific Extended Query Table

Address

Data

Description

Value

x16

40h

41h

42h

43h

44h

45h

x8

80h

82h

84h

86h

88h

8Ah

0050h

0052h

0049h

0031h

0033h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

“1”

"3"

Yes

Address Sensitive Unlock (bits 1 to 0)

00h = required, 01h = not required

Silicon Revision Number (bits 7 to 2)

46h

47h

48h

49h

8Ch

8Eh

90h

92h

0002h

0004h

0001h

0004h

Erase Suspend

00h = not supported, 01h = Read only, 02 = Read and Write

2

4

Block Protection

00h = not supported, x = number of blocks per protection group

Temporary Block Unprotect

00h = not supported, 01h = supported

Yes

04

Block Protect /Unprotect

04 = M29W640D

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Simultaneous Operations, 00h = not supported

Burst Mode, 00h = not supported, 01h = supported

No

Page Mode, 00h = not supported, 01h = 4 page word, 02h = 8 page

word

4Dh

4Eh

4Fh

9Ah

9Ch

9Eh

00B5h

00C5h

V

Supply Minimum Program/Erase voltage

11.5V

12.5V

–

PP

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

V

Supply Maximum Program/Erase voltage

PP

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Top/Bottom Boot Block Flag

02h = Bottom Boot device

03h = Top Boot device

0002h

0003h

40/49

M29W640DT, M29W640DB

Address

Data

Description

Value

x16

x8

50h

A0h

0000h

Program Suspend

00h = Not Supported

01h = Supported

_

Table 26. Security Code Area

Address

Data

Description

x16

61h

62h

63h

64h

x8

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

41/49

M29W640DT, M29W640DB

APPENDIX C. EXTENDED MEMORY BLOCK

The M29W640D has an extra block, the Extended

Block, that can be accessed using a dedicated

command.

This Extended Block is 32 KWords in x16 mode

and 64 KBytes in x8 mode. It is used as a security

block (to provide a permanent security identifica-

tion number) or to store additional information.

Factory Locked Extended Block

In devices where the Extended Block is factory

locked, the Security Identification Number is writ-

ten to the Extended Block address space (see Ta-

ble 27., Extended Block Address and Data) in the

factory. The DQ7 bit is set to ‘1’ and the Extended

Block cannot be unprotected.

The Extended Block is either Factory Locked or

Customer Lockable, its status is indicated by bit

DQ7. This bit is permanently set to either ‘1’ or ‘0’

at the factory and cannot be changed. When set to

‘1’, it indicates that the device is factory locked and

the Extended Block is protected. When set to ‘0’, it

indicates that the device is customer lockable and

the Extended Block is unprotected. Bit DQ7 being

permanently locked to either ‘1’ or ‘0’ is another

security feature which ensures that a customer

lockable device cannot be used instead of a facto-

ry locked one.

Bit DQ7 is the most significant bit in the Extended

Block Verify Code and a specific procedure must

be followed to read it. See “Extended Memory

Block Verify Code” in Table 2., Bus Operations,

BYTE = V_ILand Table 3., Bus Operations, BYTE =

V_IH, for details of how to read bit DQ7.

The Extended Block can only be accessed when

the device is in Extended Block mode. For details

of how the Extended Block mode is entered and

exited, refer to the Enter Extended Block Com-

mand and Exit Extended Block Command para-

graphs, and to Table 4., Commands, 16-bit mode,

BYTE = V_IHand Table 5., Commands, 8-bit mode,

BYTE = V_IL.

Customer Lockable Extended Block

A device where the Extended Block is customer

lockable is delivered with the DQ7 bit set to ‘0’ and

the Extended Block unprotected. It is up to the

customer to program and protect the Extended

Block but care must be taken because the protec-

tion of the Extended Block is not reversible.

There are two ways of protecting the Extended

Block:

■

Issue the Enter Extended Block command to

place the device in Extended Block mode,

then use the In-System Technique with RP

either at V_IHor at V_ID(refer to APPENDIX D.,

In-System Technique and to the

corresponding flowcharts, Figures 18 and 19,

for a detailed explanation of the technique).

■

Issue the Enter Extended Block command to

place the device in Extended Block mode,

then use the Programmer Technique (refer to

APPENDIX D., Programmer Technique and to

the corresponding flowcharts, Figures 16 and

17, for a detailed explanation of the

technique).

Once the Extended Block is programmed and pro-

tected, the Exit Extended Block command must be

issued to exit the Extended Block mode and return

the device to Read mode.

Table 27. Extended Block Address and Data

(1)

Data

Address

Device

x8

x16

Factory Locked

Customer Lockable

Security Identification

Number

7F0000h-7F000Fh

7F0010h-7FFFFFh

000000h-00000Fh

000010h-00FFFFh

3F8000h-3F8007h

3F8008h-3FFFFFh

000000h-000007h

000008h-007FFFh

Determined by

Customer

M29W640DT

M29W640DB

Unavailable

Security Identification

Number

Determined by

Customer

Unavailable

Note: 1. See Tables 19 and 20, Top and Bottom Boot Block Addresses.

42/49

M29W640DT, M29W640DB

APPENDIX D. BLOCK PROTECTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the memo-

ry. The blocks are protected in groups, refer to

APPENDIX A., Table 19. and Table 20. for details

of the Protection Groups. Once protected, Pro-

gram and Erase operations within the protected

group fail to change the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In-System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is described in the Signal De-

scriptions section.

specified, it is followed as closely as possible. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP⁽¹⁾. This can be achieved without violating

the maximum ratings of the components on the mi-

croprocessor bus, therefore this technique is suit-

able for use after the memory has been fitted to

the system.

To protect a group of blocks follow the flowchart in

Figure 18., In-System Equipment Group Protect

Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all the

groups can be unprotected at the same time. To

unprotect the chip follow Figure 19., In-System

Equipment Chip Unprotect Flowchart.

Programmer Technique

The Programmer technique uses high (V_ID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a group of blocks follow the flowchart in

Figure 16., Programmer Equipment Group Protect

Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all

groups can be unprotected at the same time. To

unprotect the chip follow Figure 17., Programmer

Equipment Chip Unprotect Flowchart. Table

28., Programmer Technique Bus Operations,

BYTE = V_IHor V_IL, gives a summary of each oper-

ation.

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do

not allow the microprocessor to service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Note: 1. RP can be either at V or at V when using the In-Sys-

IH

ID

tem Technique to protect the Extended Block.

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

Table 28. Programmer Technique Bus Operations, BYTE = V_IHor V_IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A21

Block (Group)

A9 = V , A12-A21 Block Address

ID

V

Pulse

X

IL

ID

IL

(1)

Others = X

Protect

A9 = V , A12 = V , A15 = V

ID

IH

V

ID

Chip Unprotect

ID

IL

Others = X

A0 = V , A1 = V , A6 = V , A9 = V ,

IL

IH

IL

ID

Block (Group)

Protection Verify

Pass = XX01h

Retry = XX00h

V

A12-A21 Block Address

Others = X

IL

IH

A0 = V , A1 = V , A6 = V , A9 = V ,

IL

IH

ID

Block (Group)

Unprotection Verify

Retry = XX01h

Pass = XX00h

V

A12-A21 Block Address

Others = X

Note: 1. Block Protection Groups are shown in APPENDIX A., Tables 19 and 20.

43/49

M29W640DT, M29W640DB

Figure 16. Programmer Equipment Group Protect Flowchart

START

ADDRESS = GROUP ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = V

,

IH

A0, A6 = V

A1 = V

,

IL

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

NO

YES

++n

= 25

NO

A9 = V

E, G = V

IH

YES

PASS

A9 = V

IH

E, G = V

IH

AI05574

FAIL

Note: Block Protection Groups are shown in APPENDIX D., Table 19. and Table 20..

44/49

M29W640DT, M29W640DB

Figure 17. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1, A6 = V

IL

IH

E = V

IL

Wait 4µs

G = V

IL

INCREMENT

CURRENT GROUP

Wait 60ns

Read DATA

NO

YES

DATA

=

00h

LAST

GROUP

NO

++n

= 1000

YES

A9 = V

IH

A9 = V

IH

E, G = V

IH

FAIL

PASS

AI05575

Note: Block Protection Groups are shown in APPENDIX D., Table 19. and Table 20..

45/49

M29W640DT, M29W640DB

Figure 18. In-System Equipment Group Protect Flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 100µs

WRITE 40h

IL

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

Wait 4µs

READ DATA

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

DATA

NO

=

01h

YES

++n

= 25

NO

RP = V

IH

YES

ISSUE READ/RESET

COMMAND

RP = V

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI05576

Note: 1. Block Protection Groups are shown in APPENDIX D., Table 19. and Table 20..

2. RP can be either at V or at V when using the In-System Technique to protect the Extended Block.

IH

ID

46/49

M29W640DT, M29W640DB

Figure 19. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 4µs

INCREMENT

CURRENT GROUP

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

DATA

NO

YES

=

00h

++n

= 1000

NO

LAST

GROUP

YES

RP = V

IH

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PASS

FAIL

AI05577

Note: Block Protection Groups are shown in APPENDIX D., Table 19. and Table 20..

47/49

M29W640DT, M29W640DB

REVISION HISTORY

Table 29. Document Revision History

Date

Version

Revision Details

14-Dec-2001

-01

Document released

Description of Ready/Busy signal clarified (and Figure 12. modified)

Clarified allowable commands during Block Erase

Clarified the mode the device returns to in the CFI Read Query command section

tPLYH (time to reset device) respecified. Correction to table of Commands.

19-Apr-2002

24-Apr-2002

-02

-03

Values for addresses 23h and 25h corrected in CFI Query System Interface Information

table in Appendix B

When in Extended Block mode, the block at the boot block address can be used as OTP.

Value of electronic signature changed. Data Toggle Flow chart corrected. SO44 package

removed. Double Word Program Time (typ) changed to 20s. Revision numbering

modified: a minor revision will be indicated by incrementing the digit after the dot, and a

major revision, by incrementing the digit before the dot (revision version 03 equals 3.0).

05-Sep-2002

08-Jan-2003

3.1

3.2

Values corrected for typical times for Double Word Program (Byte or Word) and Chip

Program (Quadruple Byte, Double Word) in the Program, Erase Times and Program,

Erase Endurance Cycles table.

Document promoted from Product Preview to Preliminary Data.

Data Retention and Erase Suspend Latency Time parameters added to Table

6., Program, Erase Times and Program, Erase Endurance Cycles, and Typical after 100k

W/E Cycles column removed.

I

(Identification) current removed from Table 11., DC Characteristics. Data modified at

ID

addresses 2Eh, 31h, 32h in Table 24.

Extended Memory Block Verify Codes modified in Tables 2 and 3, “Bus Operations, BYTE

= V ” and “Bus Operations, BYTE = V ”, respectively. Block 75 address space corrected

04-Apr-2003

3.3

IL

IH

for x8 mode in Table 19., Top Boot Block Addresses, M29W640DT, and Block 71

address space corrected for x8 mode in Table 20., Bottom Boot Block Addresses,

M29W640DB.

APPENDIX C., EXTENDED MEMORY BLOCK, added. V pin connection to ground

SS

clarified.

Lead-free package options E and F added to Table 18., Ordering Information Scheme.

Status of Ready/Busy signal for Erase Suspend Operation modified in Table 7, Status

Register Bits.

Double Word Program Command modified in COMMAND INTERFACE section.

TLEAD parameter added in Table 8., Absolute Maximum Ratings.

Note modified and addresses 31h to 3Ch added in Table 24., Device Geometry

Definition.

2-Oct-2003

3.4

Addresses 43h and 4Eh modified; addresses 4Fh and 50h added in Table 25., Primary

Algorithm-Specific Extended Query Table.

10-Nov-2003

19-Dec-2003

3.5

3.6

70ns access time option removed.

V

and I test conditions updated in Table 11., DC Characteristics.

PP

Block Protect/Unprotect code updated in APPENDIX B., Table 25..

Customer Lockable Extended Block mechanism modified in APPENDIX C., EXTENDED

MEMORY BLOCK.

APPENDIX D., BLOCK PROTECTION updated: Note 1 added in the In-System

Technique section and Note 2 added below Figure 18., In-System Equipment Group

Protect Flowchart.

Document status updated to Full Datasheet.

10-Dec-2004

5.0

Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in

Table 7., Status Register Bits.

48/49

M29W640DT, M29W640DB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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www.st.com

49/49


型号：	M29W640DB70ZA1E
厂家：	ST
描述：	64 Mbit 8Mb x8 or 4Mb x16, Boot Block 3V Supply Flash Memory 64兆位的8Mb ×8或4Mb的X16 ，引导块3V电源快闪记忆体闪存存储内存集成电路
文件：	总49页 (文件大小：943K)
中文：	中文翻译
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M29W640DB70ZA1E [STMICROELECTRONICS]

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