M29W640FT60ZA6E_技术文档

M29W640FT

M29W640FB

64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block)

3V Supply Flash Memory

Figure 1. Packages

Features summary

Supply Voltage

– V_CC= 2.7V to 3.6V for Program, Erase,

Read

– V_PP=12 V for Fast Program (optional)

Asynchronous Random/Page Read

– Page Width: 4 Words

TSOP48 (N)

12 x 20mm

– Page Access: 25ns

– Random Access: 60ns, 70ns

Programming Time

FBGA

– 10 µs per Byte/Word typical

– 4 Words/8 Bytes Program

135 memory blocks

TFBGA48 (ZA)

6x8mm

– 1 Boot Block and 7 Parameter Blocks,

8 KBytes each (Top or Bottom Location)

– 127 Main Blocks, 64 KBytes each

Program/Erase Controller

Electronic Signature

– Manufacturer Code: 0020h

– Embedded Byte/Word Program algorithms

Program/Erase Suspend and Resume

Table 1.

Device Codes

– Read from any Block during Program

Root Part Number

Device Code

Suspend

– Read and Program another Block during

M29W640FT

M29W640FB

22EDh

22FDh

Erase Suspend

Unlock Bypass Program command

– Faster Production/Batch Programming

ECOPACK^®packages

V_PP/WP pin for Fast Program and Write Protect

Temporary Block Unprotection mode

Common Flash Interface

– 64-bit Security Code

Extended Memory Block

– Extra block used as security block or to

store additional information

Low power consumption

– Standby and Automatic Standby

100,000 Program/Erase cycles per block

Rev3

1/72

December 2005

www.st.com

1

M29W640FT, M29W640FB

Contents

1

2

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V_PP/Write Protect (V_PP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.11 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.12 V_CCSupply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.13 V_SSGround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

3.2

3.3

3.4

3.5

3.6

Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.1 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.2 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4

Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1

Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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M29W640FT, M29W640FB

4.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.6 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.7 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.8 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.9 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2

Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.1 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.3 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.4 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.5 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.6 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.7 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.8 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3

Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.1 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.2 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.3 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . . . . 27

5

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1

5.2

5.3

5.4

5.5

Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6

7

8

9

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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M29W640FT, M29W640FB

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

C.1

C.2

Factory Locked Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

D.1

D.2

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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M29W640FT, M29W640FB

List of tables

Table 1.

Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1.

Table 2.

Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hardware Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Operations, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bus Operations, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Commands, 16-bit mode, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Commands, 8-bit mode, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 29

Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Reset/Block Temporary Unprotect AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 44

TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data. . . . . . 45

Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Top Boot Block Addresses, M29W640FT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Bottom Boot Block Addresses, M29W640FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Extended Block Address and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Programmer Technique Bus Operations, BYTE = V_IHor V_{IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66}

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

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M29W640FT, M29W640FB

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . 44

Figure 15. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Outline . . . . . . . . . . . . . 45

Figure 16. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 18. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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M29W640FT, M29W640FB

1 Summary description

1

Summary description

The M29W640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,

erased and reprogrammed. These operations can be performed using a single low voltage (2.7

to 3.6V) supply. On power-up the memory defaults to its Read mode.

The memory is divided into blocks that can be erased independently so it is possible to

preserve valid data while old data is erased. Blocks can be protected in units of 256 KByte

(generally groups of four 64 KByte blocks), to prevent accidental Program or Erase commands

from modifying the memory. Program and Erase commands are written to the Command

Interface of the memory. An on-chip Program/Erase Controller simplifies the process of

programming or erasing the memory by taking care of all of the special operations that are

required to update the memory contents. The end of a program or erase operation can be

detected and any error conditions identified. The command set required to control the memory

is consistent with JEDEC standards.

The device features an asymmetrical blocked architecture. The device has an array of 135

blocks:

8 Parameters Blocks of 8 KBytes each (or 4 KWords each)

127 Main Blocks of 64 KBytes each (or 32 KWords each)

M29W640FT has the Parameter Blocks at the top of the memory address space while the

M29W640FB locates the Parameter Blocks starting from the bottom.

The M29W640F has an extra block, the Extended Block, of 128 Words in x16 mode or of 256

Byte in x8 mode that can be accessed using a dedicated command. The Extended Block can

be protected and so is useful for storing security information. However the protection is not

reversible, once protected the protection cannot be undone.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.

They allow simple connection to most microprocessors, often without additional logic.

The V_PP/WP signal is used to enable faster programming of the device, enabling multiple word/

byte programming. If this signal is held at V_SS, the boot block, and its adjacent parameter block,

are protected from program and erase operations.

The device supports Asynchronous Random Read and Page Read from all blocks of the

memory array.

The memories are offered in TSOP48 (12x 20mm) and TFBGA48 (6x8mm, 0.8mm pitch)

packages.

In order to meet environmental requirements, ST offers the M29W640FT and the M29W640FB

in ECOPACK^®packages. ECOPACK packages are Lead-free. The category of second Level

Interconnect is marked on the package and on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:

www.st.com.

The memory is delivered with all the bits erased (set to 1).

7/72

1 Summary description

M29W640FT, M29W640FB

Figure 1. Logic Diagram

V

/WP

CC PP

22

15

A0-A21

DQ0-DQ14

W

E

DQ15A–1

BYTE

RB

M29W640FT

M29W640FB

G

RP

V

SS

AI11250

Table 1.

Signal Names

Address Inputs

A0-A21

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

DQ15A–1 (or DQ15)

Data Input/Output or Address Input (or Data Input/Output)

Chip Enable

E

G

Output Enable

W

Write Enable

RP

RB

BYTE

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

V

CC

V

/WP

Supply Voltage for Fast Program (optional) or Write Protect

PP

Ground

SS

NC

Not Connected Internally

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M29W640FT, M29W640FB

Figure 2. TSOP Connections

1 Summary description

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

V

SS

DQ15A–1

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A19

A20

W

M29W640FT

M29W640FB

DQ12

DQ4

RP

12

13

37

36

V

CC

A21

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

/WP

RB

A18

A17

A7

PP

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI11251

9/72

1 Summary description

M29W640FT, M29W640FB

Figure 3. TFBGA48 Connections (Top view through package)

1

2

3

4

5

6

RB

W

A

B

A3

A4

A7

A17

A6

A9

A8

A13

A12

V

/WP

RP

PP

A2

A1

A0

E

A18

A21

A19

DQ5

A10

A14

A15

A16

BYTE

C

D

A5

A20

A11

DQ2

DQ7

DQ14

DQ13

DQ6

DQ0

DQ8

DQ9

DQ1

E

F

DQ10

DQ11

DQ3

DQ12

DQ15

A–1

G

V

G

H

CC

V

DQ4

V

SS

AI11554

10/72

M29W640FT, M29W640FB

2 Signal descriptions

2

Signal descriptions

See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals

connected to this device.

2.1

2.2

2.3

Address Inputs (A0-A21)

The Address Inputs select the cells in the memory array to access during Bus Read operations.

During Bus Write operations they control the commands sent to the Command Interface of the

Program/Erase Controller.

Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.

During Bus Write operations they represent the commands sent to the Command Interface of

the Program/Erase Controller.

Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation

when BYTE is High, V_IH. When BYTE is Low, V_IL, these pins are not used and are high

impedance. During Bus Write operations the Command Register does not use these bits.

When reading the Status Register these bits should be ignored.

2.4

Data Input/Output or Address Input (DQ15A–1)

When BYTE is High, V_IH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, V_IL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the

addressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when BYTE is High and references to the Address

Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

2.5

2.6

Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be

performed. When Chip Enable is High, V_IH, all other pins are ignored.

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

11/72

2 Signal descriptions

M29W640FT, M29W640FB

2.7

2.8

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

V /Write Protect (V /WP)

PP

The V_PP/Write Protect pin provides two functions. The V_PPfunction allows the memory to use

an external high voltage power supply to reduce the time required for Unlock Bypass Program

operations. The Write Protect function provides a hardware method of protecting the two

outermost boot blocks. The V_PP/Write Protect pin must not be left floating or unconnected.

When V_PP/Write Protect is Low, V_IL, the memory protects the two outermost boot blocks;

Program and Erase operations in this block are ignored while V_PP/Write Protect is Low, even

when RP is at V_ID.

When V_PP/Write Protect is High, V_IH, the memory reverts to the previous protection status of

the two outermost boot blocks. Program and Erase operations can now modify the data in the

two outermost boot blocks unless the block is protected using Block Protection.

Applying V_PPHto the V_PP/WP pin will temporarily unprotect any block previously protected

(including the two outermost parameter blocks) using a High Voltage Block Protection

technique (In-System or Programmer technique). See Table 2: Hardware Protection for details.

When V_PP/Write Protect is raised to V_PPthe memory automatically enters the Unlock Bypass

mode. When V_PP/Write Protect returns to V_IHor V_ILnormal operation resumes. During Unlock

Bypass Program operations the memory draws I_PPfrom the pin to supply the programming

circuits. See the description of the Unlock Bypass command in the Command Interface section.

The transitions from V_IHto V_PPand from V_PPto V_IHmust be slower than t_VHVPP, see Figure 13:

Accelerated Program Timing Waveforms.

Never raise V_PP/Write Protect to V_PPfrom any mode except Read mode, otherwise the

memory may be left in an indeterminate state.

A 0.1µF capacitor should be connected between the V_PP/Write Protect pin and the V_SSGround

pin to decouple the current surges from the power supply. The PCB track widths must be

sufficient to carry the currents required during Unlock Bypass Program, I_PP.

Table 2.

V

Hardware Protection

/WP

RP

Function

PP

2 outermost parameter blocks protected from

Program/Erase operations

V

IH

V

IL

All blocks temporarily unprotected except the 2

outermost blocks

V

ID

V

or V

All blocks temporarily unprotected

IH

ID

V

or V

IH ID

PPH

12/72

M29W640FT, M29W640FB

2 Signal descriptions

2.9

Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

Note that if V_PP/WP is at V_IL, then the two outermost boot blocks will remain protected even if

RP is at V_ID.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V_IL, for at

least t_PLPX. After Reset/Block Temporary Unprotect goes High, V_IH, the memory will be ready

for Bus Read and Bus Write operations after t_PHELor t_RHEL, whichever occurs last. See the

Ready/Busy Output section, Table 16: Reset/Block Temporary Unprotect AC Characteristics

and Figure 12: Reset/Block Temporary Unprotect AC Waveforms, for more details.

Holding RP at V_IDwill temporarily unprotect the protected Blocks in the memory. Program and

Erase operations on all blocks will be possible. The transition from V_IHto V_IDmust be slower

than t_PHPHH

.

2.10 Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is

performing a Program or Erase operation. During Program or Erase operations Ready/Busy is

Low, V_OL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase

Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy

becomes high-impedance. See Table 16: Reset/Block Temporary Unprotect AC Characteristics

and Figure 12: Reset/Block Temporary Unprotect AC Waveforms, for more details.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.11 Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of

the memory. When Byte/Word Organization Select is Low, V_IL, the memory is in x8 mode, when

it is High, V_IH, the memory is in x16 mode.

2.12 V Supply Voltage (2.7V to 3.6V)

CC

V_CCprovides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the V_CCSupply Voltage is less than the Lockout

Voltage, V_LKO. This prevents Bus Write operations from accidentally damaging the data during

power up, power down and power surges. If the Program/Erase Controller is programming or

erasing during this time then the operation aborts and the memory contents being altered will

be invalid.

A 0.1µF capacitor should be connected between the V_CCSupply Voltage pin and the V_SS

Ground pin to decouple the current surges from the power supply. The PCB track widths must

be sufficient to carry the currents required during Program and Erase operations, I_CC3

.

13/72

2 Signal descriptions

M29W640FT, M29W640FB

2.13 V Ground

SS

V_SSis the reference for all voltage measurements. The device features two V_SSpins which

must be both connected to the system ground.

14/72

M29W640FT, M29W640FB

3 Bus operations

3

Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus Write,

Output Disable, Standby and Automatic Standby. See Table 3: Bus Operations, BYTE = VIL

and Table 4: Bus Operations, BYTE = VIH, for a summary. Typically glitches of less than 5ns on

Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

3.1

Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

Interface. A valid Bus Read operation involves setting the desired address on the Address

Inputs, applying a Low signal, V_IL, to Chip Enable and Output Enable and keeping Write Enable

High, V_IH. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode AC

Waveforms, and Table 13: Read AC Characteristics, for details of when the output becomes

valid.

3.2

Bus Write

Bus Write operations write to the Command Interface. To speed up the read operation the

memory array can be read in Page mode where data is internally read and stored in a page

buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.

A valid Bus Write operation begins by setting the desired address on the Address Inputs. The

Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or

Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command

Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output

Enable must remain High, V_IH, during the whole Bus Write operation. See Figure 10: Write AC

Waveforms, Write Enable Controlled, Figure 11: Write AC Waveforms, Chip Enable Controlled,

and Table 14: Write AC Characteristics, Write Enable Controlled and Table 15: Write AC

Characteristics, Chip Enable Controlled, for details of the timing requirements.

3.3

3.4

Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V_IH.

Standby

When Chip Enable is High, V_IH, the memory enters Standby mode and the Data Inputs/Outputs

pins are placed in the high-impedance state. To reduce the Supply Current to the Standby

Supply Current, I_CC2, Chip Enable should be held within V_CC± 0.2V. For the Standby current

level see Table 12: DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply

Current, I_CC3, for Program or Erase operations until the operation completes.

15/72

3 Bus operations

M29W640FT, M29W640FB

3.5

Automatic Standby

If CMOS levels (V_CC± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more

the memory enters Automatic Standby where the internal Supply Current is reduced to the

Standby Supply Current, I_CC2. The Data Inputs/Outputs will still output data if a Bus Read

operation is in progress.

3.6

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply

and remove Block Protection. These bus operations are intended for use by programming

equipment and are not usually used in applications. They require V_IDto be applied to some

pins.

3.6.1 Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read to

identify the memory. These codes can be read by applying the signals listed in Table 3: Bus

Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH.

3.6.2 Block Protect and Chip Unprotect

Groups of blocks can be protected against accidental Program or Erase. The Protection

Groups are shown in Appendix A: Block addresses Table 20 and Table 21. The whole chip can

be unprotected to allow the data inside the blocks to be changed.

The V_PP/Write Protect pin can be used to protect the two outermost boot blocks. When V_PP

Write Protect is at V_ILthe two outermost boot blocks are protected and remain protected

/

regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status.

Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.

16/72

M29W640FT, M29W640FB

Table 3. Bus Operations, BYTE = V_IL

Operation

3 Bus operations

Data Inputs/Outputs

Address Inputs

DQ15A–1, A0-A21

E

G

W

DQ14-DQ8

Hi-Z

DQ7-DQ0

Data Output

Data Input

Hi-Z

V

IH

Bus Read

Bus Write

Output Disable

Standby

Cell Address

IL

IH

V

Command Address

Hi-Z

IL

X

Hi-Z

IH

V

X

Hi-Z

IH

A0-A3 = V , A6 = V ,

Read Manufacturer

Code

IL

V

Hi-Z

20h

IL

IH

A9 = V , Others V or V

IH

ID

IL

A0 = V , A1-A3= V ,

IH

IL

EDh (M29W640FT)

FDh (M29W640FB)

A6 = V , A9 = V ,

Read Device Code

IL

IH

IL

ID

Others V or V

IL

IH

A0 -A1 = V , A2-A3= V ,

80h (factory locked)

IH

IL

Read Extended

Memory Block Verify

Code

V

A6 = V , A9 = V ,

Hi-Z

00h (Customer

Lockable)

IL

IH

IL

ID

Others V or V

IL

IH

A0,A2,A3, A6= V ,

IL

A1= V , A9 = V ,

01h (protected)

Read Block

Protection Status

IH

ID

A12-A21 = Block Address,

Others V or V

00h (unprotected)

IL

IH

1. X = V or V

.

IH

IL

17/72

3 Bus operations

M29W640FT, M29W640FB

Table 4.

Bus Operations, BYTE = V_IH

Address Inputs

A0-A21

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

V

IH

Bus Read

Bus Write

Output Disable

Standby

Cell Address

Data Output

Data Input

Hi-Z

IL

IH

V

Command Address

IL

X

IH

V

X

Hi-Z

IH

A0-A3 = V , A6 = V ,

Read Manufacturer

Code

IL

V

0020h

IL

IH

A9 = V , Others V or V

IH

ID

IL

A0 = V , A1-A3= V , A6 = V ,

22EDh (M29W640FT)

22FDh (M29W640FB)

IH

IL

V

Read Device Code

A9 = V , Others V or V

IH

ID

IL

A0 -A1 = V , A2-A3= V ,

IH

IL

Read Extended

Memory Block Verify

Code

80h (factory locked)

V

A6 = V , A9 = V ,

IL

IH

IL

ID

00h (Customer Lockable)

Others V or V

IL

IH

A0,A2,A3, A6= V ,

IL

0001h (protected)

A1 = V , A9 = V ,

Read Block

Protection Status

IH

ID

V

A12-A21 = Block Address,

Others V or V

0000h (unprotected)

IL

IH

1. X = V or V

IL

.

IH

18/72

M29W640FT, M29W640FB

4 Command Interface

4

Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface. Commands

consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of

Bus Write operations will result in the memory returning to Read mode. The long command

sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-bit or

8-bit mode. See either Table 5, or Table 6, depending on the configuration that is being used,

for a summary of the commands.

4.1

Standard commands

4.1.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode. It also resets the errors in

the Status Register. Either one or three Bus Write operations can be used to issue the Read/

Reset command.

The Read/Reset command can be issued, between Bus Write cycles before the start of a

program or erase operation, to return the device to read mode. If the Read/Reset command is

issued during the timeout of a Block Erase operation then the memory will take up to 10µs to

abort. During the abort period no valid data can be read from the memory. The Read/Reset

command will not abort an Erase operation when issued while in Erase Suspend.

4.1.2 Auto Select command

The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block

Protection Status and the Extended Memory Block Verify Code. Three consecutive Bus Write

operations are required to issue the Auto Select command. Once the Auto Select command is

issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read

CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands

are ignored.

In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a Bus

Read operation with addresses and control signals set as shown in Table 3: Bus Operations,

BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’.

The Block Protection Status of each block can be read using a Bus Read operation with

addresses and control signals set as shown in Table 3: Bus Operations, BYTE = VIL and

Table 4: Bus Operations, BYTE = VIH, except for A9 that is ‘Don’t Care’. If the addressed block

is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output (in

8-bit mode).

The protection status of the Extended Memory block, or Extended Memory Block Verify code,

can be read using a Bus Read operation with addresses and control signals set as shown in

Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, except for A9

that is ‘Don’t Care’. If the Extended Block is "Factory Locked" then 80h is output on Data Input/

Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).

19/72

4 Command Interface

M29W640FT, M29W640FB

4.1.3 Read CFI Query command

The Read CFI Query Command is used to read data from the Common Flash Interface (CFI)

Memory Area. This command is valid when the device is in the Read Array mode, or when the

device is in Autoselected mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is

issued subsequent Bus Read operations read from the Common Flash Interface Memory Area.

The Read/Reset command must be issued to return the device to the previous mode (the Read

Array mode or Autoselected mode). A second Read/Reset command would be needed if the

device is to be put in the Read Array mode from Autoselected mode.

See Appendix B: Common Flash Interface (CFI), Tables 22, 23, 24, 25, 26 and 27 for details on

the information contained in the Common Flash Interface (CFI) memory area.

4.1.4 Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are

required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of

the blocks are protected the Chip Erase operation appears to start but will terminate within

about 100µs, leaving the data unchanged. No error condition is given when protected blocks

are ignored.

During the erase operation the memory will ignore all commands, including the Erase Suspend

command. It is not possible to issue any command to abort the operation. Typical chip erase

times are given in Table 7: Program, Erase Times and Program, Erase Endurance Cycles. All

Bus Read operations during the Chip Erase operation will output the Status Register on the

Data Inputs/Outputs. See the section on the Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode, unless

an error has occurred. When an error occurs the memory will continue to output the Status

Register. A Read/Reset command must be issued to reset the error condition and return to

Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All

previous data is lost.

4.1.5 Block Erase command

The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write

operations are required to select the first block in the list. Each additional block in the list can be

selected by repeating the sixth Bus Write operation using the address of the additional block.

The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus

Write operation. Once the Program/Erase Controller starts it is not possible to select any more

blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs

timer restarts when an additional block is selected. The Status Register can be read after the

sixth Bus Write operation. See the Status Register section for details on how to identify if the

Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are

erased. If all of the selected blocks are protected the Block Erase operation appears to start but

will terminate within about 100µs, leaving the data unchanged. No error condition is given when

protected blocks are ignored.

20/72

M29W640FT, M29W640FB

4 Command Interface

During the Block Erase operation the memory will ignore all commands except the Erase

Suspend command. Typical block erase times are given in Table 7: Program, Erase Times and

Program, Erase Endurance Cycles. All Bus Read operations during the Block Erase operation

will output the Status Register on the Data Inputs/Outputs. See the section on the Status

Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and return

to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All

previous data in the selected blocks is lost.

4.1.6 Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase operation

and return the memory to Read mode. The command requires one Bus Write operation.

The Program/Erase Controller will suspend within the Erase Suspend Latency time of the

Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the

memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend

command is issued during the period when the memory is waiting for an additional block

(before the Program/Erase Controller starts) then the Erase is suspended immediately and will

start immediately when the Erase Resume Command is issued. It is not possible to select any

further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations behave as normal on these blocks. If any attempt is

made to program in a protected block or in the suspended block then the Program command is

ignored and the data remains unchanged. The Status Register is not read and no error

condition is given. Reading from blocks that are being erased will output the Status Register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands

during an Erase Suspend. The Read/Reset command must be issued to return the device to

Read Array mode before the Resume command will be accepted.

4.1.7 Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller after an

Erase Suspend. The device must be in Read Array mode before the Resume command will be

accepted. An erase can be suspended and resumed more than once.

4.1.8 Program Suspend command

The Program Suspend command allows the system to interrupt a program operation so that

data can be read from any block. When the Program Suspend command is issued during a

program operation, the device suspends the program operation within the Program Suspend

Latency time (see Table 7: Program, Erase Times and Program, Erase Endurance Cycles for

value) and updates the Status Register bits.

After the program operation has been suspended, the system can read array data from any

address. However, data read from Program-Suspended addresses is not valid.

The Program Suspend command may also be issued during a program operation while an

erase is suspended. In this case, data may be read from any addresses not in Erase Suspend

21/72

4 Command Interface

M29W640FT, M29W640FB

or Program Suspend. If a read is needed from the Extended Block area (One-time Program

area), the user must use the proper command sequences to enter and exit this region.

The system may also issue the Auto Select command sequence when the device is in the

Program Suspend mode. The system can read as many Auto Select codes as required. When

the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is

ready for another valid operation. See Auto Select command sequence for more information.

4.1.9 Program Resume command

After the Program Resume command is issued, the device reverts to programming. The

controller can determine the status of the program operation using the DQ7 or DQ6 status bits,

just as in the standard program operation. See Write Operation Status for more information.

The system must write the Program Resume command, to exit the Program Suspend mode

and to continue the programming operation.

Further issuing of the Resume command is ignored. Another Program Suspend command can

be written after the device has resumed programming.

4.1.10 Program command

The Program command can be used to program a value to one address in the memory array at

a time. The command requires four Bus Write operations, the final write operation latches the

address and data, and starts the Program/Erase Controller.

Programming can be suspended and then resumed by issuing a Program Suspend command

and a Program Resume command, respectively (see Section 4.1.8: Program Suspend

command and Section 4.1.9: Program Resume command).

If the address falls in a protected block then the Program command is ignored, the data remains

unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue

any command to abort or pause the operation. Typical program times are given in Table 7:

Program, Erase Times and Program, Erase Endurance Cycles. Bus Read operations during

the program operation will output the Status Register on the Data Inputs/Outputs. See the

section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an

error has occurred. When an error occurs the memory will continue to output the Status

Register. A Read/Reset command must be issued to reset the error condition and return to

Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

22/72

M29W640FT, M29W640FB

4 Command Interface

4.2

Fast Program commands

There are four Fast Program commands available to improve the programming throughput, by

writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple Byte

Program commands are available for x8 operations, while the Double Quadruple Word Program

command are available for x16 operations.

Fast Program commands can be suspended and then resumed by issuing a Program Suspend

command and a Program Resume command, respectively (see Section 4.1.8: Program

Suspend command and Section 4.1.9: Program Resume command).

When V_PPHis applied to the V_PP/Write Protect pin the memory automatically enters the Fast

Program mode. The user can then choose to issue any of the Fast Program commands. Care

must be taken because applying a V_PPHto the V_PP/WP pin will temporarily unprotect any

protected block.

4.2.1 Double Byte Program command

The Double Byte Program command is used to write a page of two adjacent Bytes in parallel.

The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the

Double Byte Program command.

1. The first bus cycle sets up the Double Byte Program Command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4.2.2 Quadruple Byte Program command

The Quadruple Byte Program command is used to write a page of four adjacent Bytes in

parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are

necessary to issue the Quadruple Byte Program command.

1. The first bus cycle sets up the Quadruple Byte Program Command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and

starts the Program/Erase Controller.

23/72

4 Command Interface

M29W640FT, M29W640FB

4.2.3 Octuple Byte Program command

This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the

eight Bytes must differ only in A1, A0 and DQ15A-1.

Nine bus write cycles are necessary to issue the command:

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Byte to be written.

3. The third bus cycle latches the Address and the Data of the second Byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.

6. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.

7. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.

8. The eighth bus cycle latches the Address and the Data of the seventh Byte to be written.

9. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written and

starts the Program/Erase Controller.

4.2.4 Double Word Program command

The Double Word Program command is used to write a page of two adjacent Words in parallel.

The two Words must differ only for the address A0.

Three bus write cycles are necessary to issue the Double Word Program command.

The first bus cycle sets up the Quadruple Word Program Command.

The second bus cycle latches the Address and the Data of the first Word to be written.

The third bus cycle latches the Address and the Data of the second Word to be written and

starts the Program/Erase Controller.

After the program operation has completed the memory will return to the Read mode, unless an

error has occurred. When an error occurs Bus Read operations will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and return

to Read mode.

Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the

Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to

’1’.

Typical Program times are given in Table 7: Program, Erase Times and Program, Erase

Endurance Cycles.

24/72

M29W640FT, M29W640FB

4 Command Interface

4.2.5 Quadruple Word Program command

This is used to write a page of four adjacent Words (or 8 adjacent Bytes), in x16 mode,

simultaneously. The addresses of the four Words must differ only in A1 and A0.

Five bus write cycles are necessary to issue the command:

The first bus cycle sets up the command.

The second bus cycle latches the Address and the Data of the first Word to be written.

The third bus cycle latches the Address and the Data of the second Word to be written.

The fourth bus cycle latches the Address and the Data of the third Word to be written.

The fifth bus cycle latches the Address and the Data of the fourth Word to be written and

starts the Program/Erase Controller.

4.2.6 Unlock Bypass command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory faster than with the standard program commands. When the

cycle time to the device is long, considerable time saving can be made by using these

commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and the Unlock Bypass Reset command. The memory can be read

as if in Read mode.

When V_PPis applied to the V_PP/Write Protect pin the memory automatically enters the Unlock

Bypass mode and the Unlock Bypass Program command can be issued immediately.

4.2.7 Unlock Bypass Program command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory. When the cycle time to the device is long, considerable time

saving can be made by using these commands. Three Bus Write operations are required to

issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and the Unlock Bypass Reset command. The memory can be read

as if in Read mode.

The memory offers accelerated program operations through the V_PP/Write Protect pin. When

the system asserts V_PPon the V_PP/Write Protect pin, the memory automatically enters the

Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program

command sequence. The memory uses the higher voltage on the V_PP/Write Protect pin, to

accelerate the Unlock Bypass Program operation.

Never raise V_PP/Write Protect to V_PPfrom any mode except Read mode, otherwise the

memory may be left in an indeterminate state.

4.2.8 Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock

Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset

command. Read/Reset command does not exit from Unlock Bypass Mode.

25/72

4 Command Interface

M29W640FT, M29W640FB

4.3

Block Protection commands

4.3.1 Enter Extended Block command

The device has an extra 256 Byte block (Extended Block) that can only be accessed using the

Enter Extended Block command. Three Bus write cycles are required to issue the Extended

Block command. Once the command has been issued the device enters Extended Block mode

where all Bus Read or Write operations to the Boot Block addresses access the Extended

Block. The Extended Block (with the same address as the Boot Blocks) cannot be erased, and

can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot

Blocks are not accessible.

To exit from the Extended Block mode the Exit Extended Block command must be issued.

The Extended Block can be protected, however once protected the protection cannot be

undone.

4.3.2 Exit Extended Block command

The Exit Extended Block command is used to exit from the Extended Block mode and return

the device to Read mode. Four Bus Write operations are required to issue the command.

26/72

M29W640FT, M29W640FB

4 Command Interface

4.3.3 Block Protect and Chip Unprotect commands

Groups of blocks can be protected against accidental Program or Erase. The Protection

Groups are shown in Appendix A: Block addresses, Table 20: Top Boot Block Addresses,

M29W640FT and Table 21: Bottom Boot Block Addresses, M29W640FB. The whole chip can

be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.

Table 5.

Commands, 16-bit mode, BYTE = V_IH

Bus Write Operations

Command

1st

2nd

3rd

4th

5th

6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1

3

4

3

X

F0

AA

50

Read/Reset

555

2AA

55

X

F0

90

A0

Auto Select

555

Program

PA

PD

Double Word Program

PA0 PD0 PA1 PD1

PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

Quadruple Word

Program

5

3

2

555

X

56

AA

A0

Unlock Bypass

2AA

PA

55

555

20

Unlock Bypass

Program

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Program/Erase

Suspend

1

X

B0

30

Program/Erase

Resume

Read CFI Query

1

3

4

55

98

AA

Enter Extended Block

Exit Extended Block

555

2AA

55

555

88

90

X

00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15

are Don’t Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IL

IH

27/72

4 Command Interface

M29W640FT, M29W640FB

Table 6.

Commands, 8-bit mode, BYTE = V_IL

Bus Write Operations

5th

Command

1st

2nd

3rd

4th

6th

7th

8th

9th

Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data

1

3

4

X

F0

AA

Read/Reset

AAA

555

55

X

F0

90

A0

Auto Select

Program

AAA

PA

PD

Double Byte

Program

3

5

9

3

AAA

50

56

8B

AA

PA0 PD0 PA1 PD1 PA2 PD2

Quadruple

Byte Program

PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

Octuple Byte

Program

PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7

Unlock

Bypass

555

PA

55

AAA

20

Unlock

Bypass

2

X

A0

PD

Program

Unlock

Bypass Reset

2

6

X

90

AA

X

00

55

Chip Erase

Block Erase

AAA

555

AAA

80

AAA

AA

555

55

AAA

BA

10

30

6

+

AAA AA

Program/

Erase

1

X

B0

Suspend

Program/

Erase

Resume

1

3

4

X

30

98

Read CFI

Query

AA

Enter

Extended

Block

AAA

AA

555

55

AAA

88

90

Exit Extended

Block

X

00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15

are Don’t Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IL

IH

28/72

M29W640FT, M29W640FB

4 Command Interface

Table 7.

Program, Erase Times and Program, Erase Endurance Cycles

(1) (2)

(2)

Parameter

Min

Unit

Typ

80

Max

(3)

Chip Erase

s

400

(4)

Block Erase (64 KBytes)

0.8

6

(4)

Erase Suspend Latency Time

µs

s

50

(3)

Program (Byte or Word)

10

80

40

20

10

200

400

200

100

Double Byte

Double Word /Quadruple Byte Program

Quadruple Word / Octuple Byte Program

Chip Program (Byte by Byte)

Chip Program (Word by Word)

s

Chip Program (Double Word/Quadruple Byte Program)

Chip Program (Quadruple Word/Octuple Byte Program)

s

(3)

s

50

Program Suspend Latency Time

Program/Erase Cycles (per Block)

Data Retention

4

µs

100,000

20

cycles

years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.

CC

4. Maximum value measured at worst case conditions for both temperature and V

.

CC

29/72

5 Status Register

M29W640FT, M29W640FB

5

Status Register

Bus Read operations from any address always read the Status Register during Program and

Erase operations. It is also read during Erase Suspend when an address within a block being

erased is accessed.

The bits in the Status Register are summarized in Table 8: Status Register Bits.

5.1

Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Program operation the memory returns

to Read mode and Bus Read operations from the address just programmed output DQ7, not its

complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase operation the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within

a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/

Erase Controller has suspended the Erase operation.

Figure 4: Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid

Address is the address being programmed or an address within the block being erased.

5.2

Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully

completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on

DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address. After successful completion of the operation

the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block

being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

Figure 5: Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

30/72

M29W640FT, M29W640FB

5 Status Register

5.3

Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error

Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct

data to the memory. If the Error Bit is set a Read/Reset command must be issued before other

commands are issued. The Error bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do

so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of

the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’

to ’1’.

5.4

5.5

Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation

during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase

Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’

and additional blocks to be erased may be written to the Command Interface. The Erase Timer

Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase

operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc.,

with successive Bus Read operations from addresses within the blocks being erased. A

protected block is treated the same as a block not being erased. Once the operation completes

the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read operations from addresses within the blocks being erased. Bus Read

operations to addresses within blocks not being erased will output the memory cell data as if in

Read mode.

After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be

used to identify which block or blocks have caused the error. The Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within

blocks that have not erased correctly. The Alternative Toggle Bit does not change if the

addressed block has erased correctly.

31/72

5 Status Register

M29W640FT, M29W640FB

Table 8.

Status Register Bits

Operation

Address

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Program

Any Address

DQ7

Toggle

0

–

0

Program During Erase

Suspend

Any Address

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Any Address

DQ7

Toggle

1

0

–

1

0

1

–

Hi-Z

0

1

Toggle

Erasing Block

Toggle

Block Erase before

timeout

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

0

Toggle

Hi-Z

0

Block Erase

Erase Suspend

Erase Error

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

No Toggle

Hi-Z

0

Non-Erasing Block

Good Block Address

Faulty Block Address

Data read as normal

0

Toggle

1

No Toggle

Toggle

1

0

1. Unspecified data bits should be ignored.

Figure 4. Data Polling Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

=

DATA

YES

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

DQ7

=

DATA

YES

NO

FAIL

PASS

AI90194

32/72

M29W640FT, M29W640FB

5 Status Register

Figure 5. Data Toggle Flowchart

START

READ DQ6

READ

DQ5 & DQ6

DQ6

=

NO

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

DQ6

=

NO

TOGGLE

YES

FAIL

PASS

AI90195B

33/72

6 Maximum rating

M29W640FT, M29W640FB

6

Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause

permanent damage to the device. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. These are stress ratings only and operation of

the device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

Table 9.

Absolute Maximum Ratings

Symbol

Parameter

Min

–50

Max

125

150

Unit

°C

V

T

Temperature Under Bias

Storage Temperature

BIAS

T

–65

STG

(1)(2)

V

+0.6

–0.6

Input or Output Voltage

Supply Voltage

IO

CC

V

4

V

CC

V

Identification Voltage

13.5

V

ID

(3)

PP

Program Voltage

V

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.

CC

3.

V

must not remain at 12V for more than a total of 80hrs.

PP

34/72

M29W640FT, M29W640FB

7 DC and AC parameters

7

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that follow

are derived from tests performed under the Measurement Conditions summarized in the

relevant tables. Designers should check that the operating conditions in their circuit match the

measurement conditions when relying on the quoted parameters.

Table 10. Operating and AC Measurement Conditions

Parameter

M29W640FT, M29W640FB

Unit

Min

Max

V

Supply Voltage

2.7

3.6

85

V

°C

pF

ns

V

CC

Ambient Operating Temperature

–40

Load Capacitance (C )

30

L

Input Rise and Fall Times

Input Pulse Voltages

10

0 to V

CC

V

/2

Input and Output Timing Ref. Voltages

V

CC

Figure 6. AC Measurement I/O Waveform

V

CC

V

/2

CC

0V

AI05557

Figure 7. AC Measurement Load Circuit

V

CC

PP

CC

25k

DEVICE

UNDER

TEST

25k

C

L

0.1µF

C

includes JIG capacitance

L

AI05558

35/72

7 DC and AC parameters

M29W640FT, M29W640FB

Table 11. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

V

OUT

12

pF

OUT

1. Sampled only, not 100% tested.

Table 12. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Max

±1

Unit

I

0V V V

IN CC

µA

LI

I

0V V

V

CC

±1

LO

OUT

E = V , G = V

,

IH

IL

I

Supply Current (Read)

10

100

20

mA

µA

CC1

f = 6MHz

E = V ±0.2V,

CC

I

Supply Current (Standby)

CC2

RP = V ±0.2V

CC

V

/WP =

PP

mA

Supply Current (Program/

Erase)

Program/Erase

Controller active

V

or V

IH

IL

I

CC3

V

/WP = V

PP

20

mA

V

PP

V

Input Low Voltage

Input High Voltage

–0.5

0.8

IL

V

0.7V

V

+0.3

CC

V

IH

CC

Voltage for V /WP Program

Acceleration

PP

V

= 2.7V ±10%

11.5

12.5

V

PP

CC

Current for V /WP Program

PP

I

= 2.7V ±10%

15

mA

Acceleration

V

I

= 1.8mA

OL

Output Low Voltage

Output High Voltage

Identification Voltage

0.45

V

OL

V

= –100µA

V

–0.4

OH

CC

V

11.5

1.8

12.5

2.3

ID

Program/Erase Lockout

Supply Voltage

(1)

LKO

V

1. Sampled only, not 100% tested.

36/72

M29W640FT, M29W640FB

7 DC and AC parameters

Figure 8. Read Mode AC Waveforms

tAVAV

VALID

A0-A20/

A–1

tAVQV

tAXQX

E

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI05559

Figure 9. Page Read AC Waveforms

A2-A21

VALID ADDRESS

VALID

A0-A1

VALID

tAVQV

VALID

E

tELQV

tEHQX

tEHQZ

G

tGHQX

tGHQZ

tGLQV

tAVQV1

VALID

DATA

DQ0-DQ15

VALID DATA

AI11553

37/72

7 DC and AC parameters

M29W640FT, M29W640FB

Table 13. Read AC Characteristics

M29W640FT,

M29W640FB

Symbol

Alt

Parameter

Test Condition

Unit

60

70

E = V ,

IL

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

Max

60

70

ns

AVAV

RC

G = V

IL

E = V ,

IL

t

ACC

60

25

70

25

AVQV

G = V

IL

E = V ,

IL

t

PAGE

Address Valid to Output Valid (Page)

AVQV1

G = V

E = V

IL

(1)

t

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Min

Max

Min

0

ns

t

LZ

ELQX

t

60

0

70

0

ELQV

CE

(1)

t

OLZ

IL

GLQX

t

E = V

Max

25

GLQV

OE

(1)

t

G = V

t

HZ

DF

IL

EHQZ

(1)

t

E = V

Output Enable High to Output Hi-Z

Max

25

ns

t

GHQZ

t

EHQX

Chip Enable, Output Enable or Address

Transition to Output Transition

t

Min

0

ns

GHQX

OH

t

AXQX

t

ELBL

ELFL

Chip Enable to BYTE Low or High

Max

5

ns

t

ELFH

ELBH

t

BYTE Low to Output Hi-Z

BYTE High to Output Valid

Max

25

30

25

30

ns

BLQZ

FLQZ

t

FHQV

BHQV

1. Sampled only, not 100% tested.

38/72

M29W640FT, M29W640FB

7 DC and AC parameters

Figure 10. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/

VALID

A–1

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI05560

39/72

7 DC and AC parameters

M29W640FT, M29W640FB

Table 14. Write AC Characteristics, Write Enable Controlled

M29W640FT,

M29W640FB

Symbol

Alt

Parameter

Unit

60

0

70

0

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Min

ns

AVAV

t

CS

ELWL

t

WP

45

0

45

0

WLWH

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

WHDX

t

0

WHEH

t

WPH

30

0

30

0

WHWL

t

AVWL

AS

t

45

0

45

0

WLAX

AH

t

GHWL

t

OEH

0

WHGL

(1)

t

Program/Erase Valid to RB Low

Max

Min

30

50

30

50

ns

t

BUSY

WHRL

t

V

High to Chip Enable Low

CC

µs

VCHEL

VCS

1. Sampled only, not 100% tested.

40/72

M29W640FT, M29W640FB

7 DC and AC parameters

Figure 11. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/

VALID

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI05561

41/72

7 DC and AC parameters

M29W640FT, M29W640FB

Table 15. Write AC Characteristics, Chip Enable Controlled

M29W640FT, M29W640FB

Unit

Symbol

Alt

Parameter

60

0

70

0

t

WC

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

Max

Min

ns

µs

AVAV

t

WS

WLEL

t

45

0

45

0

ELEH

CP

DS

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

Program/Erase Valid to RB Low

EHDX

DH

t

WH

0

EHWH

t

30

0

30

0

EHEL

CPH

t

AVEL

AS

t

45

0

45

0

ELAX

AH

t

GHEL

t

0

EHGL

OEH

(1)

t

30

50

30

50

t

BUSY

EHRL

t

V

High to Write Enable Low

CC

VCHWL

VCS

1. Sampled only, not 100% tested.

42/72

M29W640FT, M29W640FB

7 DC and AC parameters

Figure 12. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX

RP

tPHPHH

tPLYH

AI02931B

Figure 13. Accelerated Program Timing Waveforms

V

PP

V

/WP

PP

V

or V

IH

IL

tVHVPP

AI05563

Table 16. Reset/Block Temporary Unprotect AC Characteristics

M29W640FT,

M29W640FB

Symbol

Alt

Parameter

Unit

(1)

t

PHWL

RP High to Write Enable Low, Chip Enable Low,

Output Enable Low

t

Min

50

0

ns

PHEL

RH

(1)

t

PHGL

(1)

t

RHWL

RB High to Write Enable Low, Chip Enable Low,

Output Enable Low

(1)

t

ns

t

RB

RHEL

RHGL

t

(1)

t

RP Pulse Width

Min

Max

Min

500

50

ns

µs

ns

PLPX

RP

t

READY

RP Low to Read Mode

PLYH

(1)

t

RP Rise Time to V

500

t

VIDR

ID

PHPHH

(1)

V

Rise and Fall Time

Min

250

ns

t

PP

VHVPP

1. Sampled only, not 100% tested.

43/72

8 Package mechanical

M29W640FT, M29W640FB

8

Package mechanical

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

L

DIE

C

CP

TSOP-G

1. Drawing is not to scale.

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

millimeters

inches

Symbol

Typ

Min

Max

1.200

Typ

Min

Max

0.0472

A

A1

A2

B

0.100

0.050

0.950

0.170

0.100

0.150

1.050

0.270

0.210

0.100

12.100

20.200

18.500

–

0.0039

0.0020

0.0059

0.0413

0.0106

0.0083

0.0039

0.4764

0.7953

0.7283

–

1.000

0.220

0.0394

0.0087

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

a

0

5

0

5

44/72

M29W640FT, M29W640FB

8 Package mechanical

Figure 15. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Outline

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z32

1. Drawing is not to scale.

Table 18. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

5.900

–

0.450

0.0138

0.2323

–

0.0177

D

6.000

4.000

6.100

0.2362

0.1575

0.2402

D1

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.000

1.200

0.400

7.900

8.100

0.3150

0.2205

0.0315

0.0394

0.0472

0.0157

0.3110

0.3189

E1

e

–

FD

FE

SD

SE

45/72

9 Part Numbering

M29W640FT, M29W640FB

9

Part Numbering

Table 19. Ordering Information Scheme

Example:

M29W640FB

70

N

6

F

Device Type

M29

Operating Voltage

W = V = 2.7 to 3.6V

CC

Device Function

640F = 64 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

60 = 60ns

70 = 70ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x8mm, 0.80 mm pitch

Temperature Range

6 = 40 to 85 °C

Option

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

Note: This product is also available with the Extended Block factory locked. For further details

and ordering information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to 1. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact your nearest ST Sales Office.

46/72

M29W640FT, M29W640FB

9 Part Numbering

Appendix A Block addresses

Table 20. Top Boot Block Addresses, M29W640FT

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

(1)

0

64/32

000000h–00FFFFh

000000h–007FFFh

1

64/32

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

Protection Group

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

47/72

9 Part Numbering

M29W640FT, M29W640FB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

64/32

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

Protection Group

48/72

M29W640FT, M29W640FB

9 Part Numbering

KBytes/

KWords

Protection Block

Block

(x8)

(x16)

Group

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

64/32

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3FFFFFh

400000h–40FFFFh

410000h–41FFFFh

420000h–42FFFFh

430000h–43FFFFh

440000h–44FFFFh

450000h–45FFFFh

460000h–46FFFFh

470000h–47FFFFh

480000h–48FFFFh

490000h–49FFFFh

4A0000h–4AFFFFh

4B0000h–4BFFFFh

4C0000h–4CFFFFh

4D0000h–4DFFFFh

4E0000h–4EFFFFh

4F0000h–4FFFFFh

500000h–50FFFFh

510000h–51FFFFh

520000h–52FFFFh

530000h–53FFFFh

540000h–54FFFFh

550000h–55FFFFh

560000h–56FFFFh

570000h–57FFFFh

580000h–58FFFFh

590000h–59FFFFh

5A0000h–5AFFFFh

5B0000h–5BFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

Protection Group

49/72

9 Part Numbering

M29W640FT, M29W640FB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

92

64/32

5C0000h–5CFFFFh

5D0000h–5DFFFFh

5E0000h–5EFFFFh

5F0000h–5FFFFFh

600000h–60FFFFh

610000h–61FFFFh

620000h–62FFFFh

630000h–63FFFFh

640000h–64FFFFh

650000h–65FFFFh

660000h–66FFFFh

670000h–67FFFFh

680000h–68FFFFh

690000h–69FFFFh

6A0000h–6AFFFFh

6B0000h–6BFFFFh

6C0000h–6CFFFFh

6D0000h–6DFFFFh

6E0000h–6EFFFFh

6F0000h–6FFFFFh

700000h–70FFFFh

710000h–71FFFFh

720000h–72FFFFh

730000h–73FFFFh

740000h–74FFFFh

750000h–75FFFFh

760000h–76FFFFh

770000h–77FFFFh

780000h–78FFFFh

790000h–79FFFFh

7A0000h–7AFFFFh

7B0000h–7BFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

93

Protection Group

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

50/72

M29W640FT, M29W640FB

9 Part Numbering

KBytes/

KWords

Protection Block

Block

(x8)

(x16)

Group

124

125

126

127

64/32

8/4

7C0000h–7CFFFFh

7D0000h–7DFFFFh

7E0000h–7EFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

7F0000h–7F1FFFh

7F2000h–7F3FFFh

7F4000h–7F5FFFh

7F6000h–7F7FFFh

7F8000h–7F9FFFh

7FA000h–7FBFFFh

7FC000h–7FDFFFh

7FE000h–7FFFFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

128

129

130

131

132

133

134

8/4

Protection Group

1. Used as the Extended Block Addresses in Extended Block mode.

51/72

9 Part Numbering

M29W640FT, M29W640FB

Table 21. Bottom Boot Block Addresses, M29W640FB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

(1)

0

1

2

3

4

5

6

7

8/4

000000h-001FFFh

000000h–000FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

Protection Group

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

8

64/32

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Protection Group

52/72

M29W640FT, M29W640FB

9 Part Numbering

KBytes/

Block

Protection Block

Group

(x8)

(x16)

KWords

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

64/32

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

Protection Group

53/72

9 Part Numbering

M29W640FT, M29W640FB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

64/32

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h-40FFFFh

410000h-41FFFFh

420000h-42FFFFh

430000h-43FFFFh

440000h-44FFFFh

450000h-45FFFFh

460000h-46FFFFh

470000h-47FFFFh

480000h-48FFFFh

490000h-49FFFFh

4A0000h-4AFFFFh

4B0000h-4BFFFFh

4C0000h-4CFFFFh

4D0000h-4DFFFFh

4E0000h-4EFFFFh

4F0000h-4FFFFFh

500000h-50FFFFh

510000h-51FFFFh

520000h-52FFFFh

530000h-53FFFFh

540000h-54FFFFh

550000h-55FFFFh

560000h-56FFFFh

570000h-57FFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

Protection Group

54/72

M29W640FT, M29W640FB

9 Part Numbering

KBytes/

Block

Protection Block

Group

(x8)

(x16)

KWords

95

64/32

580000h-58FFFFh

590000h-59FFFFh

5A0000h-5AFFFFh

5B0000h-5BFFFFh

5C0000h-5CFFFFh

5D0000h-5DFFFFh

5E0000h-5EFFFFh

5F0000h-5FFFFFh

600000h-60FFFFh

610000h-61FFFFh

620000h-62FFFFh

630000h-63FFFFh

640000h-64FFFFh

650000h-65FFFFh

660000h-66FFFFh

670000h-67FFFFh

680000h-68FFFFh

690000h-69FFFFh

6A0000h-6AFFFFh

6B0000h-6BFFFFh

6C0000h-6CFFFFh

6D0000h-6DFFFFh

6E0000h-6EFFFFh

6F0000h-6FFFFFh

700000h-70FFFFh

710000h-71FFFFh

720000h-72FFFFh

730000h-73FFFFh

740000h-74FFFFh

750000h-75FFFFh

760000h-76FFFFh

770000h-77FFFFh

2C0000h–2C7FFFh

96

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

Protection Group

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

55/72

9 Part Numbering

M29W640FT, M29W640FB

KBytes/

KWords

Protection Block

Group

Block

(x8)

(x16)

127

128

129

130

131

132

133

134

64/32

780000h-78FFFFh

790000h-79FFFFh

7A0000h-7AFFFFh

7B0000h-7BFFFFh

7C0000h-7CFFFFh

7D0000h-7DFFFFh

7E0000h-7EFFFFh

7F0000h-7FFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

Protection Group

1. Used as the Extended Block Addresses in Extended Block mode.

56/72

M29W640FT, M29W640FB

9 Part Numbering

Appendix B Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be

read from the Flash memory device. It allows a system software to query the device to

determine various electrical and timing parameters, density information and functions

supported by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data

structure is read from the memory. Tables 22, 23, 24, 25, 26, and 27, show the addresses used

to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number is

written (see Table 27: Security Code Area). This area can be accessed only in Read mode by

the final user. It is impossible to change the security number after it has been written by ST.

Table 22. Query Structure Overview

Address

Sub-section Name

Description

x16

x8

10h

1Bh

27h

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific Extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

61h

80h

C2h

Security Code Area

64 bit unique device number

1. Query data are always presented on the lowest order data outputs.

57/72

9 Part Numbering

M29W640FT, M29W640FB

Table 23. CFI Query Identification String

Address

Data

Description

Value

x16

x8

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

“Q”

"R"

"Y"

0052h Query Unique ASCII String "QRY"

0059h

0002h

AMD

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

Compatible

0000h

0040h

Address for Primary Algorithm extended Query table (see Table 26)

P = 40h

NA

0000h

Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported

0000h

Address for Alternate Algorithm extended Query table

0000h

NA

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 24. CFI Query System Interface Information

Address

Data

0027h

0036h

00B5h

00C5h

Description

Value

2.7V

x16

x8

V

Logic Supply Minimum Program/Erase voltage

CC

1Bh

36h

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

V

Logic Supply Maximum Program/Erase voltage

CC

1Ch

1Dh

1Eh

38h

3Ah

3Ch

3.6V

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

PP

11.5V

12.5V

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

V

[Programming] Supply Maximum Program/Erase voltage

PP

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

3Eh

40h

42h

44h

46h

48h

0004h

0000h

000Ah

0000h

0004h

0000h

16µs

NA

Typical timeout per single byte/word program = 2 µs

n

Typical timeout for minimum size write buffer program = 2 µs

n

1s

Typical timeout per individual Block Erase = 2 ms

n

NA

Typical timeout for full Chip Erase = 2 ms

n

256 µs

NA

Maximum timeout for byte/word program = 2 times typical

n

Maximum timeout for write buffer program = 2 times typical

58/72

M29W640FT, M29W640FB

9 Part Numbering

Address

Data

Description

Value

x16

25h

26h

x8

n

4Ah

4Ch

0003h

0000h

8s

Maximum timeout per individual Block Erase = 2 times typical

n

NA

Maximum timeout for Chip Erase = 2 times typical

59/72

9 Part Numbering

M29W640FT, M29W640FB

Table 25. Device Geometry Definition

Address

Data

Description

Value

x16

x8

n

27h

4Eh

0017h

8 MByte

Device Size = 2 in number of bytes

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface Code description

2Ah

2Bh

54h

56h

0004h

0000h

n

16 Bytes

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions. It specifies the number of

regions containing contiguous Erase Blocks of the same size.

2Ch

58h

0002h

2Dh

2Eh

5Ah

5Ch

0007h

0000h

Region 1 Information

8

Number of Erase Blocks of identical size = 0007h+1

2Fh

30h

5Eh

60h

0020h

0000h

Region 1 Information

8Kbyte

127

Block size in Region 1 = 0020h * 256 byte

31h

32h

62h

64h

007Eh

0000h

Region 2 Information

Number of Erase Blocks of identical size= 007Eh+1

33h

34h

66h

68h

0000h

0001h

Region 2 Information

64Kbyte

Block size in Region 2 = 0100h * 256 byte

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Region 3 Information

Number of Erase Blocks of identical size=007Fh+1

Region 3 Information

0

Block size in Region 3 = 0000h * 256 byte

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Region 4 Information

Number of Erase Blocks of Identical size=007Fh+1

Region 4 Information

0

Block size in Region 4 = 0000h * 256 byte

1. For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase Block Region 2

from address 008000h to 3FFFFFh.

For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase Block Region 2 from

address 3F8000h to 3FFFFFh.

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M29W640FT, M29W640FB

9 Part Numbering

Table 26. Primary Algorithm-Specific Extended Query Table

Address

Data

Description

Value

x16

x8

40h

41h

42h

43h

44h

80h

82h

84h

86h

88h

0050h

"P"

0052h Primary Algorithm extended Query table unique ASCII string “PRI”

0049h

"R"

"I"

0031h Major version number, ASCII

0033h Minor version number, ASCII

“1”

"3"

Address Sensitive Unlock (bits 1 to 0)

0000h 00h = required, 01h = not required

Silicon Revision Number (bits 7 to 2)

45h

8Ah

Yes

Erase Suspend

46h

47h

48h

49h

8Ch

8Eh

90h

92h

0002h

2

4

00h = not supported, 01h = Read only, 02 = Read and Write

Block Protection

0004h

00h = not supported, x = number of blocks per protection group

Temporary Block Unprotect

0001h

Yes

04

00h = not supported, 01h = supported

Block Protect /Unprotect

0004h

04 = M29W640F

4Ah

4Bh

94h

96h

0000h Simultaneous Operations, 00h = not supported

0000h Burst Mode: 00h = not supported, 01h = supported

No

Page Mode: 00h = not supported, 01h = 4 page word, 02h = 8

page word

4Ch

98h

0001h

Yes

V

Supply Minimum Program/Erase voltage

PP

4Dh

9Ah

00B5h

00C5h

11.5V

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

V

Supply Maximum Program/Erase voltage

PP

4Eh

4Fh

50h

9Ch

9Eh

A0h

12.5V

–

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Top/Bottom Boot Block Flag

0002h 02h = Bottom Boot device

0003h 03h = Top Boot device

Program Suspend

0001h 00h = Not Supported

01h = Supported

Supported

61/72

9 Part Numbering

M29W640FT, M29W640FB

Table 27. Security Code Area

Address

Data

Description

x16

x8

61h

62h

63h

64h

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

62/72

M29W640FT, M29W640FB

9 Part Numbering

Appendix C Extended Memory Block

The M29W640F has an extra block, the Extended Block, that can be accessed using a

dedicated command.

This Extended Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a

security block to provide a permanent security identification number) or to store additional

information.

The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit

DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed. When

set to ‘1’, it indicates that the device is factory locked and the Extended Block is protected.

When set to ‘0’, it indicates that the device is customer lockable and the Extended Block is

unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature

which ensures that a customer lockable device cannot be used instead of a factory locked one.

Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure

must be followed to read it. See “Extended Memory Block Verify Code” in Table 3: Bus

Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH, for details of how to read bit

DQ7.

The Extended Block can only be accessed when the device is in Extended Block mode. For

details of how the Extended Block mode is entered and exited, refer to the Section 4.3.1: Enter

Extended Block command and Section 4.3.2: Exit Extended Block command, and to Table 5

and Table 6: Commands, 8-bit mode, BYTE = VIL.

C.1 Factory Locked Extended Block

In devices where the Extended Block is factory locked, the Security Identification Number is

written to the Extended Block address space (see Table 28: Extended Block Address and Data)

in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.

C.2 Customer Lockable Extended Block

A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to ‘0’

and the Extended Block unprotected. It is up to the customer to program and protect the

Extended Block but care must be taken because the protection of the Extended Block is not

reversible.

There are two ways of protecting the Extended Block:

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the In-System Technique with RP either at V_IHor at V_ID(refer to Appendix D,

Section D.2: In-System Technique and to the corresponding flowcharts, Figure 18 and

Figure 19, for a detailed explanation of the technique).

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the Programmer Technique (refer to Appendix D, Section D.1: Programmer

Technique and to the corresponding flowcharts, Figure 16 and Figure 17, for a detailed

explanation of the technique).

Once the Extended Block is programmed and protected, the Exit Extended Block command

must be issued to exit the Extended Block mode and return the device to Read mode.

63/72

9 Part Numbering

M29W640FT, M29W640FB

Table 28. Extended Block Address and Data

Address

Data

x8

x16

Factory Locked

Customer Lockable

000000h-00020Fh

000021h-0000FFh

000000h-00000Fh

000010h-00007Fh

Security Identification Number

Unavailable

Determined by Customer

64/72

M29W640FT, M29W640FB

9 Part Numbering

Appendix D Block Protection

Block protection can be used to prevent any operation from modifying the data stored in the

memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Table 20

and Table 21 for details of the Protection Groups. Once protected, Program and Erase

operations within the protected group fail to change the data.

There are three techniques that can be used to control Block Protection, these are the

Programmer technique, the In-System technique and Temporary Unprotection. Temporary

Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described

in the Signal Descriptions section.

D.1 Programmer Technique

The Programmer technique uses high (V_ID) voltage levels on some of the bus pins. These

cannot be achieved using a standard microprocessor bus, therefore the technique is

recommended only for use in Programming Equipment.

To protect a group of blocks follow the flowchart in Figure 16: Programmer Equipment Group

Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all groups can be unprotected at the same time. To unprotect the chip follow Figure 17:

Programmer Equipment Chip Unprotect Flowchart. Table 29: Programmer Technique Bus

Operations, BYTE = VIH or VIL, gives a summary of each operation.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do not abort the procedure before reaching the

end. Chip Unprotect can take several seconds and a user message should be provided to show

that the operation is progressing.

D.2 In-System Technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary

Unprotect pin, RP⁽¹⁾. This can be achieved without violating the maximum ratings of the

components on the microprocessor bus, therefore this technique is suitable for use after the

memory has been fitted to the system.

To protect a group of blocks follow the flowchart in Figure 18: In-System Equipment Group

Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 19:

In-System Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do not allow the microprocessor to service

interrupts that will upset the timing and do not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a user message should be provided to show that

the operation is progressing.

Note:

RP can be either at V_IHor at V_IDwhen using the In-System Technique to protect the Extended

Block.

65/72

9 Part Numbering

M29W640FT, M29W640FB

Table 29. Programmer Technique Bus Operations, BYTE = V_IHor V_IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A21

A9 = V , A12-A21 = Block Address

Block (Group)

ID

V

Pulse

X

IL

ID

IL

(1)

Protect

Others = X

A9 = V , A12 = V , A15 = V

ID

IH

V

Chip Unprotect

ID

Others = X

A0, A2, A3 = V , A1 = V , A6 = V ,

IL

IH

IL

Pass = XX01h

Retry = XX00h

Block (Group)

Protection Verify

V

A9 = V , A12-A21 = Block Address

ID

IL

IH

Others = X

A0, A2, A3 = V , A1 = V , A6 = V ,

IH

IL

IH

Retry = XX01h

Pass = XX00h

Block (Group)

Unprotection Verify

V

A9 = V , A12-A21 = Block Address

IH

ID

Others = X

1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.

66/72

M29W640FT, M29W640FB

9 Part Numbering

Figure 16. Programmer Equipment Group Protect Flowchart

START

ADDRESS = GROUP ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = V

,

IH

A0, A2, A3 = V , A1 =V

,

IH

IL

A6 =V A9 = VID, Others = X

IL,

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

NO

YES

++n

NO

A9 = V

E, G = V

= 25

IH

YES

A9 = V

PASS

IH

E, G = V

IH

AI11555

FAIL

1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.

67/72

9 Part Numbering

M29W640FT, M29W640FB

Figure 17. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = V , A1 =V

,

IL IH

A6 =V A9 = VID, Others = X

IL,

E = V

IL

Wait 4µs

G = V

IL

INCREMENT

CURRENT GROUP

Wait 60ns

Read DATA

NO

YES

DATA

=

00h

LAST

GROUP

NO

++n

= 1000

YES

A9 = V

E, G = V

IH

E, G = V

IH

FAIL

PASS

AI11556

1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.

68/72

M29W640FT, M29W640FB

9 Part Numbering

Figure 18. In-System Equipment Group Protect Flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V , A1 = V

IL

IH

WRITE 60h

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V , A1 = V

IL

Wait 100µs

WRITE 40h

IH

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V , A1 = V

IL

IH

Wait 4µs

READ DATA

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = V , A1 = V

IL

IH

DATA

NO

=

01h

YES

++n

= 25

NO

RP = V

IH

YES

RP = V

ISSUE READ/RESET

COMMAND

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI11563

2. Block Protection Groups are shown in Appendix A, Tables 20 and 21.

3. RP can be either at V or at V when using the In-System Technique to protect the Extended Block.

IH

ID

69/72

9 Part Numbering

M29W640FT, M29W640FB

Figure 19. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0, A2, A3, A6 = V , A1 = V

IL

IH

WRITE 60h

ANY ADDRESS WITH

A0, A2, A3 = V , A1, A6 = V

IL

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = V , A1, A6 = V

IL

IH

Wait 4µs

INCREMENT

CURRENT GROUP

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = V , A1, A6 = V

IL

IH

NO DATA

YES

=

00h

++n

= 1000

NO

LAST

GROUP

YES

RP = V

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PASS

FAIL

AI11564

1. Block Protection Groups are shown in Appendix A, Tables 20 and 21.

70/72

M29W640FT, M29W640FB

10 Revision History

Table 30. Document Revision History

Date

Version

Revision Details

01-Mar-2005

0.1

First Issue.

Asynchronous Page mode added.

70ns speed class added.

17-May-2005

0.2

Device codes modified.

TFBGA63 replaced by TFBGA48 6x8 package. ECOPACK text updated

Page size changed to 4 Word.

90ns speed class removed.

Quadruple Word/Octuple Byte Program command added.

07-Oct-2005

1.0

Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH: A0-

A21 addresses for reading the Device Code, the Manufacturer Code, the Extended

Memory Block Verify Code, and the Block Protection Status, have been updated.

Appendix D: Block Protection: Table 29: Programmer Technique Bus Operations, BYTE

= VIH or VIL: A0-A21 addresses updated for Block Protection/Unprotection Verify using

the Programmer technique.

Datasheet status changed to “Full Datasheet”.

60ns speed class added.

Program Suspend and Resume added.

02-Dec-2005

15-Dec-2005

2

3

Section 2.8: VPP/Write Protect (VPP/WP) and Section 4.2: Fast Program commands.

Section 4: Command Interface restructured.

Table 28: Extended Block Address and Data updated.

Double Byte Program commands added in Section 4: Command Interface.

Table 3: Bus Operations, BYTE = VIL and Table 4: Bus Operations, BYTE = VIH.: A6

changed from V to V for Read Block Protection Status operation.

IH

IL

71/72

M29W640FT, M29W640FB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

72/72


型号：	M29W640FT60ZA6E
厂家：	ST
描述：	64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block) 3V Supply Flash Memory 64兆位（8MB X8或X16 4Mb的，页，引导块） 3V供应闪存闪存存储内存集成电路
文件：	总72页 (文件大小：476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29W640FT60ZA6E [STMICROELECTRONICS]

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