M29W800AB100N1T_技术文档

M29W800AT

M29W800AB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

Low Voltage Single Supply Flash Memory

■ 2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 80ns

44

■ PROGRAMMING TIME: 10µs typical

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte or Word-by-Word

– Status Register bits and Ready/Busy Output

■ SECURITY PROTECTION MEMORY AREA

■ INSTRUCTION ADDRESS CODING: 3 digits

■ MEMORY BLOCKS

1

TSOP48 (N)

12 x 20mm

SO44 (M)

FBGA

– Boot Block (Top or Bottom location)

– Parameter and Main blocks

LFBGA48 (ZA)

8 x 6 solder balls

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ MULTI BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

Figure 1. Logic Diagram

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ LOW POWER CONSUMPTION

V

CC

– Stand-by and Automatic Stand-by

■ 100,000 PROGRAM/ERASE CYCLES per

19

15

BLOCK

A0-A18

DQ0-DQ14

■ 20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

W

E

DQ15A–1

BYTE

RB

■ ELECTRONIC SIGNATURE

M29W800AT

M29W800AB

– Manufacturer Code: 20h

G

– Top Device Code, M29W800AT: D7h

– Bottom Device Code, M29W800AB: 5Bh

RP

V

SS

AI02599

March 2000

1/33

M29W800AT, M29W800AB

Figure 2. TSOP Connections

Figure 3. SO Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

RB

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

E

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RP

BYTE

2

W

V

SS

3

A8

DQ15A–1

DQ7

4

A9

5

A10

A11

A12

A13

A14

A15

A16

BYTE

DQ14

DQ6

6

7

A8

DQ13

DQ5

8

NC

W

9

DQ12

DQ4

10

11

12

13

14

15

16

17

18

19

20

21

22

M29W800

M29W800B

T

RP

NC

RB

A18

A17

A7

12

13

37

36

V

M29W800T

M29W800B

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

SS

DQ15A–1

SS

G

DQ0

DQ8

DQ7

DQ14

DQ6

DQ1

DQ9

DQ13

DQ5

A6

DQ2

A5

DQ10

DQ3

DQ12

DQ4

A4

A3

V

E

SS

DQ11

V

CC

A2

AI02181

A1

24

25

A0

AI02179

Table 1. Signal Names

DESCRIPTION

The M29W800A isa non-volatile memory that may

be erased electrically at the block or chip level and

programmed in-system on a Byte-by-Byte or

Word-by-Word basis using only a single 2.7V to

A0-A18

DQ0-DQ7

DQ8-DQ14

DQ15A–1

E

Address Inputs

Data Input/Outputs, Command Inputs

Data Input/Outputs

3.6V V

supply. For Program and Erase opera-

CC

tions the necessary high voltages are generated

internally. The device can also be programmed in

standard programmers.

Data Input/Output or Address Input

Chip Enable

The array matrix organisation allows each block to

be erased and reprogrammed without affecting

other blocks. Blocks can be protected against pro-

graming and erase on programming equipment,

and temporarily unprotected to make changes in

the application. Each block can be programmed

and erased over 100,000 cycles.

G

Output Enable

W

Write Enable

RP

Reset/Block Temporary Unprotect

Ready/Busy Output

RB

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection

status, Programming, Block and Chip Erase,

Erase Suspend and Resume are written to the de-

vice in cycles of commands to a Command Inter-

face using standard microprocessor write timings.

BYTE

Byte/Word Organization

Supply Voltage

V

CC

V

Ground

SS

NC

DU

Not Connected Internally

Don’t Use as Internally Connected

The device is offered in TSOP48 (12 x 20mm),

SO44 and LFBGA48 0.8 mm ball pitch packages.

2/33

M29W800AT, M29W800AB

Figure 4. LFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

DQ15

A–1

F

E

D

C

B

A

A13

A9

W

A12

A8

A14

A10

DU

A18

A6

A15

A11

DU

A5

A16

DQ7

DQ5

DQ2

DQ0

A0

BYTE

DQ14

DQ12

DQ10

DQ8

E

V

SS

DQ13

DQ6

DQ4

DQ3

DQ1

RP

DU

A17

A4

V

CC

RB

A7

A3

DQ11

DQ9

G

A2

A1

V

SS

AI00656

Organisation

Memory Blocks

The M29W800A is organised as 1M x8 or 512K

x16 bits selectable by the BYTE signal. When

BYTE is Low the Byte-wide x8 organisation is se-

lected and the address lines are DQ15A–1 and

A0-A18. The Data Input/Output signal DQ15A–1

acts as address line A–1 which selects the lower

or upper Byte of the memory word for output on

DQ0-DQ7, DQ8-DQ14 remain at High impedance.

When BYTE is High the memory uses the address

inputs A0-A18 and the Data Input/Outputs DQ0-

DQ15. Memory control is provided by Chip Enable

E, Output Enable G and Write Enable W inputs.

The devices feature asymmetrically blocked archi-

tecture providing system memory integration. Both

M29W800AT and M29W800AB devices have an

array of 19 blocks, one Boot Block of 16 KBytes or

8 KWords, two Parameter Blocks of 8 KBytes or 4

KWords, one Main Block of 32 KBytes or 16

KWords and fifteen Main Blocks of 64 KBytes or

32 KWords. The M29W800AT has the Boot Block

at the top of the memory address space and the

M29W800AB locates the Boot Block starting at the

bottom. The memory maps are showed in Figure

5.

A Reset/Block Temporary Unprotection RP tri-lev-

el input provides a hardware reset when pulled

Each block can be erased separately, any combi-

nation of blocks can be specified for multi-block

erase or the entire chip may be erased. The Erase

operations are managed automatically by the P/

E.C. The block erase operation can be suspended

in order to read from or program to any block not

being erased, and then resumed.

Low, and when held High (at V ) temporarily un-

ID

protects blocks previously protected allowing them

to be programed and erased. Erase and Program

operations are controlled by an internal Program/

Erase Controller (P/E.C.). Status Register data

output on DQ7 provides a Data Polling signal, and

DQ6 and DQ2 provide Toggle signals to indicate

the state of the P/E.C operations. A Ready/Busy

RB output indicates the completion of the internal

algorithms.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment. All previously protected blocks can be

temporarily unprotected in the application.

3/33

M29W800AT, M29W800AB

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(3)

T

–40 to 85

–50 to 125

–65 to 150

–0.6 to 5

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

T

BIAS

T

STG

(2)

Input or Output Voltage

Supply Voltage

V

IO

V

–0.6 to 5

V

CC

(A9, E, G, RP)

(2)

A9, E, G, RP Voltage

–0.6 to 13.5

V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions forextended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

3. Depends on range.

Bus Operations

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase op-

erations. The Status Register Data Polling,

Toggle, Error bits and the RB output may be read

at any time, during programming or erase, to mon-

itor the progress of the operation.

The following operations can be performed using

the appropriate bus cycles: Read (Array, Electron-

ic Signature, Block Protection Status), Write com-

mand, Output Disable, Stan-by, Reset, Block

Protection, Unprotection, Protection Verify, Unpro-

tection Verify and Block Temporary Unprotection.

See Tables 5 and 6.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

Command Interface which is common to all in-

structions (see Table 9).

Command Interface

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.). For added

data protection, program or erase execution starts

after 4 or 6 cycles. The first, second, fourth and

fifth cycles are used to input Coded cycles to the

C.I. This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The ’Com-

mand’ itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quence will reset the device to Read Array mode.

The third cycle inputs the instruction set-up com-

mand. Subsequent cycles output the addressed

data, Electronic Signature or Block Protection Sta-

tus for Read operations. In order to give additional

data protection, the instructions for Program and

Block or Chip Erase require further command in-

puts. For a Program instruction, the fourth com-

mand cycle inputs the address and data to be

programmed. For an Erase instruction (Block or

Chip), the fourth and fifth cycles input a further

Coded sequence before the Erase confirm com-

mand on the sixth cycle. Erasure of a memory

block may be suspended, in order to read data

from another block or to program data in another

block, and then resumed. When power is first ap-

Instructions

Seven instructions are defined to perform Read

Array, Auto Select (to read the Electronic Signa-

ture or Block Protection Status), Program, Block

Erase, Chip Erase, Erase Suspend and Erase Re-

sume.

plied or if V falls below V

, the command in-

CC

LKO

terface is reset to Read Array.

4/33

M29W800AT, M29W800AB

Table 3. Top Boot Block Addresses,

M29W800AT

Table 4. Bottom Boot Block Addresses,

M29W800AB

Size

(Kbytes)

Address Range Address Range

(x8) (x16)

Size

(Kbytes)

Address Range Address Range

(x8) (x16)

#

18

17

16

15

14

13

12

11

10

9

16

8

FC000h-FFFFFh 7E000h-7FFFFh

FA000h-FBFFFh 7D000h-7DFFFh

F8000h-F9FFFh 7C000h-7CFFFh

F0000h-F7FFFh 78000h-7BFFFh

E0000h-EFFFFh 70000h-77FFFh

D0000h-DFFFFh 68000h-6FFFFh

C0000h-CFFFFh 60000h-67FFFh

B0000h-BFFFFh 58000h-5FFFFh

A0000h-AFFFFh 50000h-57FFFh

90000h-9FFFFh 48000h-4FFFFh

80000h-8FFFFh 40000h-47FFFh

70000h-7FFFFh 38000h-3FFFFh

60000h-6FFFFh 30000h-37FFFh

50000h-5FFFFh 28000h-2FFFFh

40000h-4FFFFh 20000h-27FFFh

30000h-3FFFFh 18000h-1FFFFh

20000h-2FFFFh 10000h-17FFFh

10000h-1FFFFh 08000h-0FFFFh

00000h-0FFFFh 00000h-07FFFh

18

17

16

15

14

13

12

11

10

9

64

32

8

F0000h-FFFFFh 78000h-7FFFFh

E0000h-EFFFFh 70000h-77FFFh

D0000h-DFFFFh 68000h-6FFFFh

C0000h-CFFFFh 60000h-67FFFh

B0000h-BFFFFh 58000h-5FFFFh

A0000h-AFFFFh 50000h-57FFFh

90000h-9FFFFh 48000h-4FFFFh

80000h-8FFFFh 40000h-47FFFh

70000h-7FFFFh 38000h-3FFFFh

60000h-6FFFFh 30000h-37FFFh

50000h-5FFFFh 28000h-2FFFFh

40000h-4FFFFh 20000h-27FFFh

30000h-3FFFFh 18000h-1FFFFh

20000h-2FFFFh 10000h-17FFFh

10000h-1FFFFh 08000h-0FFFFh

08000h-0FFFFh 04000h-07FFFh

06000h-07FFFh 03000h-03FFFh

04000h-05FFFh 02000h-02FFFh

00000h-03FFFh 00000h-01FFFh

8

32

64

8

7

6

5

4

3

2

1

8

0

16

5/33

M29W800AT, M29W800AB

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Write Enable (W). This input controls writing to

the Command Register and Address and Data

latches.

Address Inputs (A0-A18). The address inputs

for thememory array are latched during a write op-

eration on the falling edge at Chip Enable E or

Write Enable W. In Word-wide organisation the

address lines are A0-A18, in Byte-wide organisa-

tion DQ15A–1 acts as an additional LSB address

Byte/Word Organization Select (BYTE). The BYTE

input selects the output configuration for the de-

vice: Byte-wide (x8) mode or Word-wide (x16)

mode. When BYTE is Low, the Byte-wide mode is

selected and the data is read and programmed on

DQ0-DQ7. In this mode, DQ8-DQ14 are at high

impedance and DQ15A–1 is the LSB address.

When BYTE is High, the Word-wide mode is se-

lected and the data is read and programmed on

DQ0-DQ15.

line. When A9 is raised to V , either a Read Elec-

ID

tronic Signature Manufacturer or Device Code,

Block Protection Status or a Write Block Protection

or BlockUnprotection is enabled depending on the

combination of levels on A0, A1, A6, A12 and A15.

Ready/Busy Output (RB). Ready/Busy is an

open-drain output and gives the internal state of

the P/E.C. of the device. When RB is Low, the de-

vice is Busy with a Program or Erase operation

and it will not accept any additional program or

erase instructions except the Erase Suspend in-

struction. When RB is High, the device is ready for

any Read, Program or Erase operation. The RB

will also be High when the memory is put in Erase

Suspend or Stan-by modes.

Data Input/Outputs (DQ0-DQ7). These Inputs/

Outputs are used in the Byte-wide and Word-wide

organisations. Theinput is data to be programmed

in the memory array or a command to be written to

the C.I. Both are latched on the rising edge of Chip

Enable E or Write Enable W. The output is data

from the Memory Array, the Electronic Signature

Manufacturer or Device codes, the Block Protec-

tion Status or the Status register Data Polling bit

DQ7, the Toggle Bits DQ6 and DQ2, the Error bit

DQ5 or the Erase Timer bit DQ3. Outputs are valid

when Chip Enable E and Output Enable G are ac-

tive. The output is high impedance when the chip

is deselected or the outputs are disabled and

when RP is at a Low level.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and pro-

tected block(s) temporary unprotection functions.

Reset of the memory is achieved by pulling RP to

V

IL

for at least t

. When the reset pulse is giv-

PLPX

Data Input/Outputs (DQ8-DQ14 and DQ15A–

1). These Inputs/Outputs are additionally used in

the Word-wide organisation. When BYTE is High

DQ8-DQ14 and DQ15A–1 act as the MSB of the

Data Input or Output, functioning as described for

DQ0-DQ7 above, and DQ8-DQ15 are ’don’t care’

for command inputs or status outputs. When

BYTE is Low, DQ0-DQ14 are high impedance,

DQ15A–1 is the Address A–1 input.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E High deselects the

memory and reduces the power consumption to

the stan-by level. E can also be used to control

writing to the command register and to the memo-

ry array, while W remains at a low level. The Chip

en, if the memory is in Read or Stan-by modes, it

will be available for new operations in t after

PHEL

the rising edge of RP. If the memory is in Erase,

Erase Suspend or Program modes the reset will

take t

during which the RB signal will be held

PLYH

at V . The end of the memory reset will be indicat-

IL

ed by the rising edge of RB. A hardware reset dur-

ing an Erase or Program operation will corrupt the

data being programmed or the sector(s) being

erased. See Tables 15, 16, and Figure 11.

Temporary block unprotection is made by holding

RP at V . In this condition previously protected

ID

blocks can be programmed or erased. The transi-

tion of RP from V to V must slower than t

IH

ID

PH-

. See Tables 17, 18, and Figure 11. When RP

PHH

is returned from V to V all blocks temporarily

ID

IH

Enable must be forced to V during the Block Un-

unprotected will be again protected.

ID

protection operation.

V

CC

Supply Voltage. The power supply for all

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When G is High the outputs are High im-

operations (Read, Program and Erase).

V

SS

Ground. V is the reference for all voltage

SS

measurements.

pedance. G must be forced to V level during

ID

Block Protection and Unprotection operations.

6/33

M29W800AT, M29W800AB

DEVICE OPERATIONS

See Tables 5, 6 and 7.

The Electronic Signature can also be read, without

raising A9 to V , by giving the memory the In-

ID

struction AS. If the Byte-wide configuration is se-

lected the codes are output on DQ0-DQ7 with

DQ8-DQ14 at High impedance; if the Word-wide

configuration is selected the codes are output on

DQ0-DQ7 with DQ8-DQ15 at 00h.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register or the Block Protection

Status. Both Chip Enable E and Output Enable G

must below in order to read theoutput of the mem-

ory. A new operation is initiated either on the fol-

lowing edge of Chip Enable E or on any address

Block Protection. Each block can be separately

protected against Program or Erase on program-

ming equipment. Block protection provides addi-

tional data security, as it disables all program or

erase operations. This mode is activated when

transition with E at V .

IL

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch input

data to be programmed. A write operation is initi-

ated when Chip Enable E is Low and Write Enable

W is Low with Output Enable G High. Addresses

are latchedon the falling edgeof W or E whichever

occurs last. Commands and Input Data are

latched on the rising edge of W or E whichever oc-

curs first.

both A9 and G are raised to V and an address in

ID

the block is applied on A12-A18. Block protection

is initiated on the edge of W falling to V . Then af-

IL

ter a delay of 100µs, the edge of W rising to V

IH

ends the protection operations. Block protection

verify is achieved by bringing G, E, A0 and A6 to

V and A1 to V , while W is at V and A9 at V .

IL

IH

ID

Under these conditions, reading the data output

will yield 01h if the block defined by the inputs on

A12-A18 is protected. Any attempt to program or

erase a protected block will be ignored by the de-

vice.

Block Temporary Unprotection. Any previously

protected block can be temporarily unprotected in

order to change stored data. The temporary un-

Output Disable. The data outputs are high im-

pedance when the Output Enable G is High with

Write Enable W High.

Stan-by. The memory is in stan-by when Chip

Enable E is High and the P/E.C. is idle. The power

consumption is reduced to the stan-by level and

the outputs are high impedance, independent of

the Output Enable G or Write Enable W inputs.

protection mode is activated by bringing RP to V .

ID

During the temporary unprotection mode the pre-

viously protected blocks are unprotected. A block

can be selected and data can be modified by exe-

cuting the Erase or Program instruction with the

RP signal held at V . When RP is returned to V ,

Automatic Stan-by. After 150ns of bus inactivity

(no address transition, CE = V ) and when CMOS

IL

levels are driving the addresses, the chip automat-

ically enters a pseudo-stan-by mode where con-

sumption is reduced to the CMOS stan-by value,

ID

IH

all the previously protected blocks are again pro-

while outputs still drive the bus (if G = V ).

IL

tected.

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory. The manufacturer’s code for STMicro-

electronics is 20h, the device code is D7h for the

M29W800AT (Top Boot) and 5Bh for the

M29W800AB (Bottom Boot). These codes allow

programming equipment or applications to auto-

matically match their interface to the characteris-

tics of the M29W800A. The Electronic Signature is

output by a Read operation when the voltage ap-

Block Unprotection. All protected blocks can be

unprotected on programming equipment to allow

updating of bit contents. All blocks must first be

protected before the unprotection operation. Block

unprotection is activated when A9, G and E are at

V

and A12, A15 at V . Unprotection is initiated

ID

IH

by the edge of W falling to V . After a delay of

IL

10ms, the unprotection operation will end. Unpro-

tection verify is achieved by bringing G and E to

V while A0 is at V , A6 and A1 are at V and A9

plied to A9 is at V and address inputs A1 is Low.

IL

IH

ID

remains at V . In these conditions, reading the

The manufacturer code is output when the Ad-

dress input A0 is Low and the device code when

this input is High. Other Address inputs are ig-

nored. The codes are output on DQ0-DQ7.

ID

output data will yield 00h if the block defined by the

inputs A12-A18 has been successfully unprotect-

ed. Each block must be separately verified by giv-

ing its address in order to ensure that it has been

unprotected.

7/33

M29W800AT, M29W800AB

Table 5. User Bus Operations

(1)

DQ0-

DQ7

DQ8-

DQ14

DQ15

A–1

Operation

Read Word

Read Byte

Write Word

Write Byte

E

G

W

RP BYTE A0 A1 A6 A9 A12 A15

Data

Output

Data

Output

Data

Output

V

IH

A0 A1 A6 A9 A12 A15

IL

IH

Data

Output

Address

Input

V

Hi-Z

IL

Data

Input

Data

Input

Data

Input

V

IH

IL

IH

Data

Input

Address

Input

V

IL

Hi-Z

IL

IH

V

Output Disable

Stan-by

Reset

X

Hi-Z

IH

X

IH

V

X

IL

Block

V

Pulse

V

X

IL

ID

IL

IH

ID

(2,4)

Protection

Blocks

V

IH

ID

IH

(4)

Unprotection

Block

Protection

Protect

V

X

A12 A15

X

IL

IH

ID

IL

IH

IL

ID

(2,4)

(3)

Verify

Status

Block

Unprotection

Block

Protect

V

IH

(2,4)

(3)

Verify

Status

Block

Temporary

Unprotection

X

Note: 1. X = V or V

.

IH

IL

2. Block Address must be given an A12-A18 bits.

3. See Table 7.

4. Operation performed on programming equipment.

Table 6. Read Electronic Signature (following AS instruction or with A9 = V )

ID

Other

DQ0- DQ8- DQ15

Org.

Code

Device

E

G

W

BYTE A0

A1

Addresses DQ7 DQ14

A–1

Manufact.

Code

V

Don’t Care

20h

00h

0

IL

IH

IL

Word-

wide

V

M29W800AT

M29W800AB

Don’t Care

D7h

5Bh

00h

0

IL

IH

IL

Device

Code

V

IL

Table 7. Read Block Protection with AS Instruction

Other

Addresses

Code

E

G

W

A0

A1

A12-A18

DQ0-DQ7

V

Protected Block

Block Address

Don’t Care

01h

00h

IL

IH

IL

IH

V

Unprotected Block

IL

IH

8/33

M29W800AT, M29W800AB

INSTRUCTIONS AND COMMANDS

monitor DQ7 in the Erase Suspend mode an ad-

dress within a block being erased must be provid-

ed. For a Read Operation in Erase Suspend

mode, DQ7 will output ’1’ if the read is attempted

on a block being erased and the data value on oth-

er blocks. During Program operation in Erase Sus-

pend Mode, DQ7 will have the same behavior as

in the normal program execution outside of the

suspend mode.

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either G,

or E when G is low. The operation is completed

when two successive reads yield the same output

data. The next read will output the bit last pro-

grammed or a ’1’ after erasing. The toggle bit DQ6

is valid only during P/E.C. operations, that is after

the fourth W pulse for programming or after the

sixth W pulse for Erase. If the blocks selected for

erasure are protected, DQ6 will toggle for about

100µs and then return back to Read. DQ6 will be

set to ’1’ if a Read operation is attempted on an

Erase Suspend block. When erase is suspended

DQ6 will toggle during programming operations in

a block different to the block in Erase Suspend. Ei-

ther E or G toggling will cause DQ6 to toggle. See

Figure 14 for Toggle Bit flowchart and Figure 15

for Toggle Bit waveforms.

The Command Interface latches commands writ-

ten to the memory. Instructions are made up from

one or more commands to perform Read Memory

Array, Read Electronic Signature, Read Block Pro-

tection, Program, Block Erase, Chip Erase, Erase

Suspend and Erase Resume. Commands are

made of address and data sequences. The in-

structions require from 1 to 6 cycles, the first or first

three of which are always write operations used to

initiate the instruction. They are followed by either

further write cycles to confirm the first command or

execute the command immediately. Command se-

quencing must be followed exactly. Any invalid

combination of commands will reset the device to

Read Array. The increased number of cycles has

been chosen to assure maximum data security. In-

structions are initialised by two initial Coded cycles

which unlock the Command Interface. In addition,

for Erase, instruction confirmation is again preced-

ed by the two Coded cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mand execution will automatically output these

five Status Register bits. The P/E.C. automatically

sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other

bits (DQ0, DQ1 and DQ4) are reserved for future

use and should be masked. See Tables 10 and 11.

Table 8. Commands

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programming or

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocks selectedfor erasure are protected, DQ7 will

be set to ’0’ for about 100µs, and then return to the

previous addressed memory data value. See Fig-

ure 13 for the Data Polling flowchart and Figure 12

for the Data Polling waveforms. DQ7 will also flag

the Erase Suspend mode by switching from ’0’ to

’1’ at the start of the Erase Suspend. In order to

Hex Code

Command

00h

Invalid/Reserved

10h

Chip Erase Confirm

Reserved

20h

30h

Block Erase Resume/Confirm

Set-up Erase

80h

Read Electronic Signature/

Block Protection Status

90h

A0h

B0h

F0h

Program

Erase Suspend

Read Array/Reset

9/33

M29W800AT, M29W800AB

(1)

Table 9. Instructions

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc.

4th Cyc.

5th Cyc. 6th Cyc.

7th Cyc.

(3,7)

X

Read Memory Array until a new write cycle is initiated.

Addr.

Data

1+

F0h

Read/Reset

Memory Array

Read Memory Array until a new write cycle is

initiated.

(2,4)

RD

Byte

AAAh

555h

AAAh

Addr.

Data

3+

4

Word

555h

AAh

2AAh

55h

555h

F0h

Byte

AAAh

555h

AAh

555h

2AAh

55h

AAAh

555h

90h

(3,7)

Read Electronic Signature or Block Protection

Status until a new write cycle is initiated. See Note

5 and 6.

Addr.

Data

(4)

Auto Select

Program

Word

AS

Byte

AAAh

555h

2AAh

AAAh

555h

Program

Address

Addr.

Data

Word

Read Data Polling or Toggle Bit until

PG

Program completes.

Program

AAh

55h

A0h

Data

Byte

AAAh

555h

AAh

AAAh

555h

AAh

X

555h

2AAh

55h

AAAh

555h

80h

AAAh

555h

AAh

555h

2AAh

55h

Additional

Block

Address

(3,7)

Addr.

Data

(8)

Block

BE

CE

Block Erase

Chip Erase

6

Word

30h

AAAh

555h

10h

30h

Byte

555h

2AAh

55h

AAAh

555h

80h

AAAh

555h

AAh

555h

2AAh

55h

Addr.

Data

Word

Note 9

(3,7)

Addr.

Data

Erase

Suspend

Read until Toggle stops, then read all the data needed from any Block(s)

not being erased then Resume Erase.

(10)

1

ES

B0h

X

Addr.

Data

Erase

Resume

Read Data Polling or Toggle Bits until Erase completes or Erase is

suspended another time.

ER

30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting anynew

PLYH

operation (see Tables 15, 16 and Figure 11).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. Signature Address bits A0, A1, at V will output Manufacturer code (20h). Address bits A0 at V and A1, at V willoutput Device

IL

IH

IL

code.

6. Block Protection Address: A0, at V , A1 at V and A15-A18 within the Block will output the Block Protection status.

IL

IH

7. For Coded cycles address inputs A11-A18 are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be

verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit

until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

10/33

M29W800AT, M29W800AB

Table 10. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase block

in Erase Suspend

’1’

’0’

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits DQ5 for program or Erase

Success.

Erase On-going

Data

Polling

7

Program Complete or data of

non erase block during Erase

Suspend

DQ

Program On-going

’-1-0-1-0-1-0-1-’ Erase or Program On-going

Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C. operations are

completed or Erase Suspend is

DQ

Program Complete

6

Toggle Bit

Erase Complete or Erase

’-1-1-1-1-1-1-1-’ Suspend on currently

addressed block

acknowledged.

’1’

’0’

Program or Erase Error

This bit is set to ‘1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started. Only

possible command entry is Erase Suspend

(ES).

’1’

’0’

Erase Timeout Period Expired

Erase Timeout Period On-going

Erase

Time Bit

3

An additional block to be erased in parallel

can be entered to the P/E.C.

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

’-1-0-1-0-1-0-1-’

Erase Error due to the currently

addressed block

(when DQ5 = ‘1’).

Indicates the erase status and allows to

identify the erased block

2

1

Toggle Bit

Program on-going, Erase on-

going on another block or

Erase Complete

1

Erase Suspend read on non

Erase Suspend block

DQ

Reserved

0

Note:

Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

11/33

M29W800AT, M29W800AB

Table 11. Polling and Toggle Bits

During the second cycle the Coded cycles consist

of writing the data 55h at address 555h inthe Byte-

wide configuration and at address 2AAh in the

Word-wide configuration. In the Byte-wide config-

uration the address lines A–1 to A10 are valid, in

Word-wide A0 to A11are valid, other address lines

are ’don’t care’. The Coded cycles happen on first

and second cycles of the command write or on the

fourth and fifth cycles.

Mode

DQ7

0

DQ6

DQ2

Program

Erase

Toggle

1

Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

Instructions

Erase Suspend Read

(outside Erase Suspend

block)

See Table 9.

DQ7

DQ6

DQ2

N/A

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded cycles. Subsequent read opera-

tions will read the memory array addressed and

output the data read. A wait state of 10µs is nec-

essary after Read/Reset prior to any valid read if

the memory was in an Erase mode when the RD

instruction is given. The Read/Reset command is

not accepted during Erase and erase Suspend.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address AAAh in

the Byte-wide configuration or address 555h in the

Word-wide configuration for command set-up. A

subsequent read will output the manufacturer

code and the device code or the block protection

status depending on the levels of A0 and A1. The

manufacturer code, 20h, is output when the ad-

dresses lines A0 and A1 are Low, the device code,

EEh for Top Boot, EFh for Bottom Boot is output

when A0 is High with A1 Low.

Erase Suspend Program

Toggle

Note: 1. Toggle if the address is within a block being erased.

’1’ if the address is within a block not being erased.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. It can also be used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to ’1’ during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to ’1’ dur-

ing program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to ’1’, DQ2 will toggle if the faulty block

is addressed.

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

the memory block. In case of an error in block

erase or program, the block in which the error oc-

curred or to which the programmed data belongs,

must be discarded. The DQ5 failure condition will

also appear if a user tries to program a ’1’ to a lo-

cation that is previously programmed to ’0’. Other

Blocks may still be used. The error bit resets after

a Read/Reset (RD) instruction. In case of success

of Program or Erase, the error bit will be set to ’0’.

The AS instruction also allows access to the block

protection status. After giving the AS instruction,

A0 is set to V with A1 at V , while A12-A18 de-

fine the address of the block to be verified. A read

in these conditions will output a 01h if the block is

protected and a 00h if the block is not protected.

IL

IH

Program (PG) Instruction. This instruction uses

four write cycles. Both for Byte-wide configuration

and for Word-wide configuration. The Program

command A0h is written to address AAAh in the

Byte-wide configuration or to address 555h in the

Word-wide configuration on the third cycle after

two Coded cycles. A fourth write operation latches

the Address on the falling edge of W or E and the

Data to be written on the rising edge and starts the

P/E.C. Read operations output the Status Register

bits after the programming has started. Memory

programming is made only by writing ’0’ in place of

’1’. Status bits DQ6 and DQ7 determine if pro-

gramming is on-going and DQ5 allows verification

of any possible error. Programming at an address

not in blocks being erased is also possible during

erase suspend. In this case, DQ2 will toggle at the

address being programmed.

Erase Timer Bit (DQ3). This bit is set to ’0’ by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50µs to 90µs, DQ3 returns

to ’1’.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address AAAh in the

Byte-wide configuration and at address 555h in

the Word-wide configuration during the first cycle.

12/33

M29W800AT, M29W800AB

Table 12. AC Measurement Conditions

Figure 6. AC Testing Load Circuit

Input Rise and Fall Times

≤10ns

0.8V

Input Pulse Voltages

0 to 3V

1.5V

Input and Output Timing Ref. Voltages

1N914

Figure 5. AC Testing Input Output Waveform

3.3kΩ

DEVICE

UNDER

TEST

OUT

= 30pF or 100pF

3V

C

L

1.5V

0V

AI01417

C

includes JIG capacitance

L

AI01968

(1)

Table 13. Capacitance (T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: Sampled only, not 100% tested.

Table 14. DC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C; V = 2.7V to 3.6V)

A

CC

Symbol

Parameter

Test Condition

Min

Max

Unit

Typ.

I

0V ≤ V ≤ V

Input Leakage Current

±1

µA

mA

µA

LI

IN

CC

I

0V ≤ V ≤ V

OUT CC

Output Leakage Current

LO

I

E = V , G = V , f = 6MHz

IL IH

Supply Current (Read by Word)

Supply Current (Stan-by)

3

10

CC1

I

E = V , G = V , f = 6MHz

IL IL

4.5

30

10

CC2

I

E = V ±0.2V

100

CC3

CC

Supply Current

(Program or Erase)

Byte program, Block or

Chip Erase in progress

(1)

20

mA

I

CC4

V

Input Low Voltage

–0.5

0.8

V

IL

V

0.7 V

V

+ 0.3

CC

Input High Voltage

IH

CC

I

= 1.8mA

OL

Output Low Voltage

0.45

V

OL

V

I

= –100µA

V

–0.4V

CC

Output High Voltage CMOS

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

V

OH

V

11.5

12.5

100

V

ID

I

A9 = V

30

µA

ID

Supply Voltage (Erase and

Program lock-out)

(1)

2.0

2.3

V

LKO

Note: 1. Sampled only, not 100% tested.

13/33

M29W800AT, M29W800AB

Table 15. Read AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

80

90

Test

Condition

Symbol

Alt

Parameter

Unit

V

= 3.0V to 3.6V

CL = 30pF

V

= 3.0V to 3.6V

CL = 30pF

CC

Min

Max

Min

90

Max

E = V

G = V

Address Validto Next

Address Valid

IL,

t

80

ns

AVAV

RC

IL

E = V

G = V

Address Validto Output

Valid

IL,

t

ACC

80

90

ns

AVQV

AXQX

BHQV

IL

E = V

Address Transition to

Output Transition

IL,

t

0

OH

G = V

IL

BYTE Switching High to

Output Valid

t

50

ns

FHQV

BYTE Switching Low to

Output High Z

t

FLQZ

BLQZ

Chip Enable High to Output

Transition

t

G = V

IL

EHQX

OH

Chip Enable High to Output

Hi-Z

(1)

t

G = V

IL

30

5

30

5

t

HZ

EHQZ

t

ELFH

t

ELFL

Chip Enable to BYTE

Switching Low or High

ELBH

ELBL

Chip Enable Low to Output

Valid

(2)

(1)

t

G = V

IL

80

90

t

CE

ELQV

Chip Enable Low to Output

Transition

t

G = V

0

LZ

IL

ELQX

Output Enable High to

Output Transition

t

E = V

GHQX

OH

IL

Output Enable High to

Output Hi-Z

(1)

t

30

35

30

35

t

DF

OE

GHQZ

Output Enable Low to

Output Valid

(2)

(1)

t

GLQV

Output Enable Low to

Output Transition

t

0

t

OLZ

GLQX

RP High to Chip Enable

Low

t

RH

50

PHEL

t

RRB

(1, 3)

RP Low to Read Mode

10

µs

t

PLYH

t

READY

t

RP Pulse Width

500

ns

PLPX

RP

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

14/33

M29W800AT, M29W800AB

Table 16. Read AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

100

120

Test

Condition

Symbol

Alt

Parameter

Unit

V

= 2.7V to 3.6V

CL = 30pF

V

= 2.7V to 3.6V

CL = 30pF

CC

Min

Max

Min

120

Max

E = V

G = V

Address Validto Next

Address Valid

IL,

t

100

ns

AVAV

RC

IL

E = V

G = V

Address Validto Output

Valid

IL,

t

ACC

100

120

ns

AVQV

AXQX

BHQV

IL

E = V

Address Transition to

Output Transition

IL,

t

0

OH

G = V

IL

BYTE Switching High to

Output Valid

t

50

60

ns

FHQV

BYTE Switching Low to

Output High Z

t

FLQZ

BLQZ

Chip Enable High to Output

Transition

t

G = V

IL

EHQX

OH

Chip Enable High to Output

Hi-Z

(1)

t

G = V

IL

30

5

30

5

t

HZ

EHQZ

t

ELFH

t

ELFL

Chip Enable to BYTE

Switching Low or High

ELBH

ELBL

Chip Enable Low to Output

Valid

(2)

(1)

t

G = V

IL

100

120

t

CE

ELQV

Chip Enable Low to Output

Transition

t

G = V

0

LZ

IL

ELQX

Output Enable High to

Output Transition

t

E = V

GHQX

OH

IL

Output Enable High to

Output Hi-Z

(1)

t

30

40

30

50

t

DF

OE

GHQZ

Output Enable Low to

Output Valid

(2)

(1)

t

GLQV

Output Enable Low to

Output Transition

t

0

t

OLZ

GLQX

RP High to Chip Enable

Low

t

RH

50

PHEL

t

RRB

(1, 3)

RP Low to Read Mode

10

µs

t

PLYH

t

READY

t

RP Pulse Width

500

ns

PLPX

RP

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

15/33

M29W800AT, M29W800AB

Figure 7. Read Mode AC Waveforms

16/33

M29W800AT, M29W800AB

Table 17. Write AC Characteristics, W Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

80

90

Symbol

Alt

Parameter

Unit

V

= 3.0V to 3.6V

CL = 30pF

V

= 3.0V to 3.6V

CL = 30pF

CC

Min

80

0

Max

Min

90

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Write Enable Low

Input Valid to Write Enable High

ns

AVAV

t

0

45

0

AVWL

AS

DS

CS

t

35

0

DVWH

t

Chip Enable Low to Write Enable Low

Output Enable High to Write Enable Low

ELWL

t

0

GHWL

(1, 2)

(1)

t

RP Rise Time to V

500

4

500

ns

t

VIDR

ID

PHPHH

t

RP High to Write Enable Low

RP Pulse Width

4

µs

t

RSP

PHWL

t

500

50

0

500

50

0

ns

µs

ns

PLPX

RP

t

V

High to Chip Enable Low

CC

VCHEL

VCS

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

WHDX

DH

CH

t

0

WHEH

t

0

WHGL

(1)

OEH

t

Program Erase Valid to RB Delay

90

ns

t

BUSY

WHRL

t

Write Enable High to Write Enable Low

Write Enable Low to Address Transition

Write Enable Low to Write Enable High

30

45

35

30

45

35

ns

WHWL

WPH

t

WLAX

AH

t

WP

WLWH

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address AAAh

in the Byte-wide configuration or address 555h in

the Word-wide configuration on third cycle after

the two Coded cycles. The Block Erase Confirm

command 30h is similarly written on the sixth cycle

after another two Coded cycles. During the input of

the second command an address within the block

to be erased is given and latched into the memory.

Additional block Erase Confirm commands and

block addresses can be written subsequently to

erase other blocks in parallel, without further Cod-

ed cycles. The erase will start after the erase tim-

eout period (see Erase Timer Bit DQ3 description).

Thus, additional Erase Confirm commands for oth-

er blocks must be given within this delay. The input

of a new Erase Confirm command will restart the

timeout period. The status of the internal timer can

be monitored through the level of DQ3, if DQ3 is ’0’

the Block Erase Command has been given and

the timeout is running, if DQ3 is ’1’, the timeout has

expired and the P/E.C. is erasing the Block(s). If

the second command given is not an erase con-

firm or if the Coded cycles are wrong, the instruc-

tion aborts, and the device is reset to Read Array.

It is not necessary to program the block with 00h

as the P/E.C. will do this automatically before to

erasing to FFh. Read operations after the sixth ris-

ing edge of W or E output the status register status

bits.

17/33

M29W800AT, M29W800AB

Table 18. Write AC Characteristics, W Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

100

120

Symbol

Alt

Parameter

Unit

V

= 2.7V to 3.6V

CL = 30pF

V

= 2.7V to 3.6V

CL = 30pF

CC

Min

100

0

Max

Min

120

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Write Enable Low

Input Valid to Write Enable High

ns

AVAV

t

0

50

0

AVWL

AS

DS

CS

t

45

0

DVWH

t

Chip Enable Low to Write Enable Low

Output Enable High to Write Enable Low

ELWL

t

0

GHWL

(1, 2)

(1)

t

RP Rise Time to V

500

4

500

ns

t

VIDR

ID

PHPHH

t

RP High to Write Enable Low

RP Pulse Width

4

µs

t

RSP

PHWL

t

500

50

0

500

50

0

ns

µs

ns

PLPX

RP

t

V

High to Chip Enable Low

CC

VCHEL

VCS

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

WHDX

DH

CH

t

0

WHEH

t

0

WHGL

(1)

OEH

t

Program Erase Valid to RB Delay

90

ns

t

BUSY

WHRL

t

Write Enable High to Write Enable Low

Write Enable Low to Address Transition

Write Enable Low to Write Enable High

30

45

35

30

50

ns

WHWL

WPH

t

WLAX

AH

t

WP

WLWH

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

During the execution of the erase by the P/E.C.,

the memory accepts only the Erase Suspend ES

and Read/Reset RD instructions. Data Polling bit

DQ7 returns ’0’ while the erasure is in progress

and ’1’ when it has completed. The Toggle bit DQ2

and DQ6 toggle during the erase operation. They

stop when erase is completed. After completion

the Status Register bit DQ5 returns ’1’ if there has

been an erase failure. In such a situation, the Tog-

gle bit DQ2 can be used to determine which block

is not correctly erased. In the case of erase failure,

a Read/Reset RD instruction is necessary in order

to reset the P/E.C.

wide configuration on the third cycle after the two

Coded cycles. The Chip Erase Confirm command

10h is similarly written on the sixth cycle after an-

other two Coded cycles. If the second command

given is not an erase confirm or if the Coded cy-

cles are wrong, the instruction aborts and the de-

vice is reset to Read Array. It is not necessary to

program the array with 00h first as the P/E.C. will

automatically do this before erasing it to FFh.

Read operations after the sixth rising edge of W or

E output the Status Register bits. During the exe-

cution of the erase by the P/E.C., Data Polling bit

DQ7 returns ’0’, then ’1’ on completion. The Toggle

bits DQ2 and DQ6 toggle during erase operation

and stop when erase is completed. After comple-

tion the Status Register bit DQ5 returns ’1’if there

has been an Erase Failure.

Chip Erase (CE) Instruction. This

instruction

uses six write cycles. The Erase Set-up command

80h is written to address AAAh in the Byte-wide

configuration or the address 555h in the Word-

18/33

M29W800AT, M29W800AB

Figure 8. Write AC Waveforms, W Controlled

tAVAV

VALID

A0-A18/

A–1

tWLAX

tAVWL

tWHEH

tWHGL

E

tELWL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI02183

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

Erase Suspend (ES) Instruction. The

Block

suspended, a Read from blocks being erased will

output DQ2 toggling and DQ6 at ’1’. A Read from

a block not being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. It will result in both DQ2 and DQ6 toggling

when the data is being programmed. A Read/Re-

set command will definitively abort erasure and re-

sult in invalid data in the blocks being erased.

Erase Resume (ER) Instruction. If an Erase

Suspend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

Erase operation may be suspended by this in-

struction which consists of writing the command

B0h without any specific address. No Coded cy-

cles are required. It permits reading of data from

another block and programming in another block

while an erase operation is in progress.Erase sus-

pend is accepted only during the Block Erase in-

struction execution. Writing this command during

Erase timeout will, in addition to suspending the

erase, terminate the timeout. The Toggle bit DQ6

stops toggling when the P/E.C. is suspended. The

Toggle bits will stop toggling between 0.1µs and

15µs after the Erase Suspend (ES) command has

been written. The device will then automatically be

set to Read Memory Array mode. When erase is

19/33

M29W800AT, M29W800AB

Table 19. Write AC Characteristics, E Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

80

90

Symbol

Alt

Parameter

Unit

V

= 3.0V to 3.6V

CL = 30pF

V

= 3.0V to 3.6V

CL = 30pF

CC

Min

80

0

Max

Min

90

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Chip Enable Low

Input Valid to Chip Enable High

ns

AVAV

t

0

45

0

AVEL

AS

DS

t

35

0

DVEH

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

EHDX

DH

t

30

0

30

0

EHEL

CPH

OEH

t

EHGL

(1)

t

Program Erase Valid to RB Delay

80

90

ns

t

BUSY

EHRL

t

Chip Enable High to Write Enable High

Chip Enable Low to Address Transition

Chip Enable Low to Chip Enable High

Output Enable High Chip Enable Low

0

45

35

0

45

35

0

EHWH

WH

t

ELAX

ELEH

AH

t

CP

GHEL

(1, 2)

(1)

t

RP Rise TIme to V

500

t

VIDR

ID

PHPHH

t

RP High to Write Enable Low

RP Pulse Width

4

µs

t

RSP

PHWL

t

500

50

0

500

50

0

ns

µs

ns

PLPX

RP

t

V

High to Write Enable Low

CC

VCHWL

VCS

t

Write Enable Low to Chip Enable Low

WLEL

WS

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

POWER SUPPLY

Power Up

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

The memory Command Interface is reset on pow-

er up to Read Array. The device does not accept

commands on the first rising edge of W, if both W

have the V rail decoupled with a 0.1µF capacitor

CC

close to the V

widths should be sufficient to carry the V

gram and erase currents required.

and V pins. The PCB trace

CC

SS

pro-

CC

and E are at V with G at V during power-up.

IL

IH

Any write cycle initiation is blocked when V

is

CC

below V

.

LKO

20/33

M29W800AT, M29W800AB

Table 20. Write AC Characteristics, E Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

100

120

Symbol

Alt

Parameter

Unit

V

= 2.7V to 3.6V

CL = 30pF

V

= 2.7V to 3.6V

CL = 30pF

CC

Min

100

0

Max

Min

120

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Chip Enable Low

Input Valid to Chip Enable High

ns

AVAV

t

0

50

0

AVEL

AS

DS

t

45

0

DVEH

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

EHDX

DH

t

30

0

30

0

EHEL

CPH

OEH

t

EHGL

(1)

t

Program Erase Valid to RB Delay

90

ns

t

BUSY

EHRL

t

Chip Enable High to Write Enable High

Chip Enable Low to Address Transition

Chip Enable Low to Chip Enable High

Output Enable High Chip Enable Low

0

45

35

0

50

0

EHWH

WH

t

ELAX

ELEH

AH

t

CP

GHEL

(1,2)

(1)

t

RP Rise TIme to V

500

t

VIDR

ID

PHPHH

t

RP High to Write Enable Low

RP Pulse Width

4

µs

t

RSP

PHWL

t

500

50

0

500

50

0

ns

µs

ns

PLPX

RP

t

V

High to Write Enable Low

CC

VCHWL

VCS

t

Write Enable Low to Chip Enable Low

WLEL

WS

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

21/33

M29W800AT, M29W800AB

Figure 9. Write AC Waveforms, E Controlled

tAVAV

VALID

A0-A18/

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tDVEH

VALID

tEHDX

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI02184

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

Figure 10. Read and Write AC Characteristics, RP Related

E

tPHEL

W

tPHWL

RB

tPLPX

RP

tPHPHH

tPLYH

AI02091

22/33

M29W800AT, M29W800AB

(1)

CC

Table 21. Data Polling and Toggle Bit AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

80

90

Symbol

Parameter

Unit

V

= 3.0V to 3.6V

CL = 30pF

V

= 3.0V to 3.6V

CL = 30pF

CC

Min

10

Max

Min

Max

Chip Enable High to DQ7 Valid

(Program, E Controlled)

2400

10

2400

µs

t

EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

60

1.0

60

sec

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Chip Erase)

Q7 Valid to Output Valid (Data Polling)

10

2400

60

10

2400

60

µs

sec

ns

t

EHQV

1.0

t

35

Q7VQV

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

60

10

2400

60

ms

t

WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

sec

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Chip Erase)

10

2400

60

10

2400

60

µs

t

WHQV

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

(1)

Table 22. Data Polling and Toggle Bit AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W800AT / M29W800AB

100 120

Symbol

Parameter

Unit

V

= 2.7V to 3.6V

CL = 30pF

V

= 2.7V to 3.6V

CL = 30pF

CC

Min

10

Max

Min

Max

Chip Enable High to DQ7 Valid

(Program, E Controlled)

2400

10

2400

µs

t

EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

60

1.0

60

sec

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Chip Erase)

Q7 Valid to Output Valid (Data Polling)

10

2400

60

10

2400

60

µs

sec

ns

t

EHQV

1.0

t

40

50

Q7VQV

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

60

10

2400

60

ms

t

WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

sec

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Chip Erase)

10

2400

60

10

2400

60

µs

t

WHQV

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

23/33

M29W800AT, M29W800AB

Figure 11. Data Polling DQ7 AC Waveforms

24/33

M29W800AT, M29W800AB

Figure 12. Data Polling Flowchart

Figure 13. Data Toggle Flowchart

START

READ

DQ2, DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

NO

DQ2, DQ6

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ7

READ DQ2, DQ6

DQ7

=

DATA

YES

NO

DQ2, DQ6

=

TOGGLE

NO

YES

FAIL

PASS

FAIL

PASS

AI01369

AI01873

Table 23. Program, Erase Times and Program, Erase Endurance Cycles

(T = 0 to 70°C; V = 2.7V to 3.6V)

A

CC

M29W800AT / M29W800AB

Parameter

Unit

(1)

Typical after

100k W/E Cycles

Min

Typ

Max

Chip Erase (Preprogrammed, V = 2.7V)

10

15

1.5

10

15

sec

CC

Chip Erase (V = 2.7V)

CC

Main Block Erase (V

= 2.7V)

15

CC

(1)

10

Chip Program (Byte)

(1)

5

sec

µs

Chip Program (Word)

Byte/Word Program

10

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Excluded the time required to execute bus cycles sequence for program operation.

25/33

M29W800AT, M29W800AB

Figure 14. Data Toggle DQ6, DQ2 AC Waveforms

26/33

M29W800AT, M29W800AB

SECURITY PROTECTION MEMORY AREA

Read Security Data (RDS) Instruction. This RDS

uses a single write cycle instruction: the command

B8h is written to the address AAh. This sets the

memory to the Read Security mode. Any succes-

sive read attempt will output the addressed Secu-

rity byte until a new write cycle is initiated.

The M29W800A features a security protection

memory area. It consists of amemory block of 256

bytes or128 words which is programmedin the ST

factory to store a unique code that uniquely identi-

fies the part.

This memory block can be read by using the Read

Security Data instruction (RDS) as shown in Table

24.

Table 24. Security Block Instruction

Unlock Cycle

1st Cyc.

AAh

Mne.

Instr.

Cyc.

2nd Cyc.

(1)

Read

Security

Data

Addr.

Data

RDS

1

Read OTP Data until a new write cycle is initiated.

(2)

B8h

Note: 1. Address bits A10-A19 are don’t care for coded address inputs.

2. Data bits DQ8-DQ15 are don’t care for coded address inputs.

Figure 15. Security Block Address Table

BYTE Organisation (x8)

TOP BOOT BLOCK

BOTTOM BOOT BLOCK

000FFh

0E0FFh

0E000h

Security

Memory Block

Security

Memory Block

00000h

WORD Organisation (x16)

TOP BOOT BLOCK

BOTTOM BOOT BLOCK

0007Fh

00000h

0E01Fh

0E000h

Security

Memory Block

Security

Memory Block

AI02746

27/33

M29W800AT, M29W800AB

Table 25. Ordering Information Scheme

Example:

M29W800AT

80

N

1

T

Device Type

M29

Operating Voltage

W = 2.7 to 3.6V

Device Function

800A = 8 Mbit (1Mb x8 or 512Kb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

80 = 80 ns

90 = 90 ns

100 = 100 ns

120 = 120 ns

Package

N = TSOP48: 12 x 20 mm

M = SO44

ZA = LFBGA48: 0.8 mm pitch

Temperature Range

1 = 0 to 70 °C

5 = –20 to 85°C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

28/33

M29W800AT, M29W800AB

Table 26. Revision History

Date

Description

November 1998

February 1999

March 1999

First issue

Removed TSOP48 Package Reverse Pinout

Program, Erase Times and Erase Endurance Cycles change

New document template

Document type: from Preliminary Data to Data Sheet

Program, Erase Times and Endurance Cycles change (Table23)

LFBGA Package Mechanical Data change (Table 29)

LFBGA Package Outline drawing change (Figure 18)

02/09/00

03/06/00

Program Erase Times change (Table 23)

29/33

M29W800AT, M29W800AB

Table 27. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

mm

inches

Symbol

Typ

Min

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

–

Typ

Min

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.4764

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.4685

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0276

5°

α

N

48

CP

0.10

0.0039

Figure 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Drawing is not to scale.

A1

α

L

30/33

M29W800AT, M29W800AB

Table 28. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

mm

Min

2.42

0.22

2.25

inches

Min

Symbol

Typ

Max

2.62

0.23

2.35

0.50

0.25

28.30

13.40

–

Typ

Max

0.1031

0.0091

0.0925

0.0197

0.0098

1.1142

0.5276

–

A

A1

A2

B

0.0953

0.0087

0.0886

C

0.10

28.10

13.20

–

0.0039

1.1063

0.5197

–

D

E

e

1.27

0.0500

H

15.90

–

16.10

–

0.6260

–

0.6339

–

L

0.80

0.0315

α

3°

–

3°

–

N

44

CP

0.10

0.0039

Figure 17. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2

A

C

B

CP

e

D

N

1

E

H

A1

α

L

SO-b

Drawing is not to scale.

31/33

M29W800AT, M29W800AB

Table 29. LFBGA48 - 8 x 6 balls, 0.8 mm pitch, Package Mechanical Data

mm

inch

Min

Symbol

Typ

Min

Max

1.350

0.350

1.000

0.550

9.200

–

Typ

Max

A

A1

A2

b

0.0531

0.300

0.200

0.750

0.300

8.800

–

0.0118

0.0079

0.0295

0.0118

0.3465

–

0.0138

0.0394

0.0217

D

9.000

5.600

0.3543

0.2205

0.3622

D1

ddd

e

–

0.150

–

0.0059

0.800

6.000

4.000

1.700

1.000

0.400

–

0.0315

0.2362

0.1575

0.0669

0.0394

0.0157

–

E

5.800

6.200

–

0.2283

0.2441

E1

FD

FE

SD

SE

–

Figure 18. LFBGA48 - 8 x 6 balls, 0.8 mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

E

E1

BALL ”A1”

ddd

e

b

A2

A

A1

BGA-Z00

Drawing is not to scale.

32/33

M29W800AT, M29W800AB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

33/33


型号：	M29W800AB100N1T
厂家：	ST
描述：	8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory 8兆位1Mb的X8或X16 512KB ，引导块低电压单电源闪存闪存存储内存集成电路光电二极管
文件：	总33页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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