M29W800DT70ZE6E [STMICROELECTRONICS]
512KX16 FLASH 3V PROM, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-48;
| 型号： | M29W800DT70ZE6E |
| 厂家： | 
ST |
| 描述： | 512KX16 FLASH 3V PROM, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-48 可编程只读存储器 内存集成电路 闪存 |
| 文件： | 总49页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29W800DT
M29W800DB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
3V Supply Flash Memory
Features
■ Supply voltage
– V = 2.7V to 3.6V for Program, Erase and
CC
Read
■ Access times: 45, 70, 90ns
■ Programming time
– 10µs per Byte/Word typical
SO44 (M)
■ 19 memory blocks
– 1 Boot block (Top or Bottom location)
– 2 Parameter and 16 main blocks
■ Program/Erase controller
– Embedded Byte/Word Program algorithms
■ Erase Suspend and Resume modes
TSOP48 (N)
12 x 20 mm
– Read and Program another Block during
Erase Suspend
■ Unlock bypass program command
FBGA
– Faster production/batch programming
■ Temporary block unprotection mode
TFBGA48 (ZE)
6 x 8 mm
■ Common flash interface
– 64-bit Security Code
■ Low power consumption
– Standby and Automatic Standby
■ 100,000 Program/Erase cycles per block
■ Electronic signature
– Manufacturer Code: 0020h
– Top Device Code M29W800DT: 22D7h
– Bottom Device Code M29W800DB: 225Bh
March 2006
Rev 8
1/49
www.st.com
1
Contents
M29W800DT, M29W800DB
Contents
1
2
3
4
5
6
7
8
9
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Appendix A Block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
C.1
C.2
Programmer Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2/49
M29W800DT, M29W800DB
List of tables
List of tables
Table 1.
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2.
Table 3.
Bus Operations, BYTE = V
Bus Operations, BYTE = V
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 4.
Table 5.
Commands, 16-bit mode, BYTE = V
Commands, 8-bit mode, BYTE = V
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 6.
Table 7.
Table 8.
Table 9.
Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 20
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Device Capacitance
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset/Block Temporary Unprotect AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . 32
TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 33
TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data . . . 34
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Top Boot Block Addresses, M29W800DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bottom Boot Block Addresses, M29W800DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Programmer Technique Bus Operations, BYTE = V or V
IH
IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
List of figures
M29W800DT, M29W800DB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . . 32
Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . 33
Figure 17. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline . . . . . 34
Figure 18. Programmer Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 20. In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4/49
M29W800DT, M29W800DB
Summary description
1
Summary description
The M29W800D is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Figure 5: Block Addresses (x8)
and Figure 6: Block Addresses (x16). The first or last 64 Kbytes have been divided into four
additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start
the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage
and the remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in SO44, TSOP48 (12 x 20mm) and TFBGA48 6 x 8mm (0.8mm
pitch) packages. The memory is supplied with all the bits erased (set to ’1’).
Figure 1.
Logic Diagram
V
CC
19
15
A0-A18
DQ0-DQ14
DQ15A–1
W
E
M29W800DT
M29W800DB
G
RB
RP
BYTE
V
SS
AI05470B
5/49
Summary description
Table 1.
M29W800DT, M29W800DB
Signal Names
Signal
Description
A0-A18
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output (not available on SO44 package)
Byte/Word Organization Select
Supply Voltage
BYTE
VCC
VSS
Ground
NC
Not Connected Internally
Figure 2.
SO Connections
RP
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
W
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
2
NC
3
A8
4
A9
5
A10
A11
A12
A13
A14
A15
A16
BYTE
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M29W800DT
M29W800DB
V
V
SS
DQ15A–1
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
DQ2
DQ10
DQ3
DQ12
DQ4
DQ11
V
CC
AI05462b
6/49
M29W800DT, M29W800DB
Summary description
Figure 3.
TSOP Connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ14
DQ6
A8
DQ13
DQ5
NC
NC
W
DQ12
DQ4
RP
NC
NC
RB
A18
A17
A7
12
13
37
36
V
M29W800DT
M29W800DB
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
A6
A5
A4
A3
V
E
SS
A2
A1
24
25
A0
AI05461
7/49
Summary description
Figure 4.
M29W800DT, M29W800DB
TFBGA Connections (Top view through package)
1
2
3
4
5
6
A9
A8
A
B
C
D
E
F
A3
A4
A7
RB
NC
W
A13
A12
RP
A17
A2
A1
A6
A5
A18
NC
NC
NC
A10
A11
A14
A15
A0
DQ0
DQ2
DQ5
DQ7
A16
DQ12
DQ14
DQ13
DQ6
E
DQ8
DQ9
DQ1
DQ10
DQ11
DQ3
BYTE
DQ15
A–1
G
H
G
V
CC
V
DQ4
V
SS
SS
AI00656
8/49
M29W800DT, M29W800DB
Summary description
Figure 5.
Block Addresses (x8)
M29W800DT
Top Boot Block Addresses (x8)
M29W800DB
Bottom Boot Block Addresses (x8)
FFFFFh
FFFFFh
16 KByte
8 KByte
8 KByte
32 KByte
64 KByte
64 KByte
64 KByte
FC000h
FBFFFh
F0000h
EFFFFh
FA000h
F9FFFh
E0000h
Total of 15
64 KByte Blocks
F8000h
F7FFFh
F0000h
EFFFFh
1FFFFh
64 KByte
32 KByte
8 KByte
8 KByte
16 KByte
E0000h
10000h
0FFFFh
08000h
07FFFh
Total of 15
64 KByte Blocks
06000h
05FFFh
1FFFFh
64 KByte
64 KByte
10000h
0FFFFh
04000h
03FFFh
00000h
00000h
AI05463
Note:
Also see Appendix A: Block address table, Table 20 and Table 21 for a full listing of the
Block Addresses.
9/49
Summary description
M29W800DT, M29W800DB
Figure 6.
Block Addresses (x16)
M29W800DT
Top Boot Block Addresses (x16)
M29W800DB
Bottom Boot Block Addresses (x16)
7FFFFh
7FFFFh
8 KWord
4 KWord
4 KWord
16 KWord
32 KWord
32 KWord
32 KWord
7E000h
7DFFFh
78000h
77FFFh
7D000h
7CFFFh
70000h
Total of 15
32 KWord Blocks
7C000h
7BFFFh
78000h
77FFFh
0FFFFh
32 KWord
16 KWord
4 KWord
4 KWord
8 KWord
70000h
08000h
07FFFh
04000h
03FFFh
Total of 15
32 KWord Blocks
03000h
02FFFh
0FFFFh
32 KWord
32 KWord
08000h
07FFFh
02000h
01FFFh
00000h
00000h
AI05464
Note:
Also see Appendix A: Block address table, Table 20 and Table 21 for a full listing of the
Block Addresses.
10/49
M29W800DT, M29W800DB
Signal descriptions
2
Signal descriptions
See Figure 1: Logic Diagram and Table 1: Signal Names for a brief overview of the signals
connected to this device.
Address Inputs (A0-A18)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation. During Bus Write operations they represent the commands sent to the Command
Interface of the internal state machine.
Data Inputs/Outputs (DQ8-DQ14)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read
operation when BYTE is High, V . When BYTE is Low, V , these pins are not used and are
IH
IL
high impedance. During Bus Write operations the Command Register does not use these
bits. When reading the Status Register these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, V , this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
IH
When BYTE is Low, V , this pin behaves as an address pin; DQ15A–1 Low will select the
IL
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE is High
and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V , all other pins are ignored.
IH
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V , for at
IL
least t
. After Reset/Block Temporary Unprotect goes High, V , the memory will be
PLPX
IH
ready for Bus Read and Bus Write operations after t
or t
, whichever occurs last.
RHEL
PHEL
See the Ready/Busy Output section, Table 15: Reset/Block Temporary Unprotect AC
11/49
Signal descriptions
M29W800DT, M29W800DB
Characteristics and Figure 14: Reset/Block Temporary Unprotect AC Waveforms, for more
details.
Holding RP at V will temporarily unprotect the protected Blocks in the memory. Program
ID
and Erase operations on all blocks will be possible. The transition from V to V must be
IH
ID
slower than t
.
PHPHH
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, V . Ready/Busy is high-impedance during Read mode, Auto Select mode and
OL
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC
Characteristics and Figure 14: Reset/Block Temporary Unprotect AC Waveforms.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus
modes of the memory. When Byte/Word Organization Select is Low, V , the memory is in 8-
IL
bit mode, when it is High, V , the memory is in 16-bit mode.
IH
VCC Supply Voltage
The V Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
CC
The Command Interface is disabled when the V Supply Voltage is less than the Lockout
CC
Voltage, V
. This prevents Bus Write operations from accidentally damaging the data
LKO
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the V Supply Voltage pin and the V
CC
SS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, I
.
CC3
VSS Ground
The V Ground is the reference for all voltage measurements.
SS
12/49
M29W800DT, M29W800DB
Bus operations
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 2 and Table 3, Bus
Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V , to Chip Enable and Output Enable and keeping Write
IL
Enable High, V . The Data Inputs/Outputs will output the value, see Figure 11: Read Mode
IH
AC Waveforms, and Figure 12: Read AC Characteristics for details of when the output
becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V ,
IH
during the whole Bus Write operation. See Figure 12 and Figure 13, Write AC Waveforms,
and Table 13 and Table 14, Write AC Characteristics, for details of the timing requirements.
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V .
IH
Standby
When Chip Enable is High, V , the memory enters Standby mode and the Data
IH
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
, Chip Enable should be held within V ± 0.2V. For the
CC2
CC
Standby current level see Table 11: DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
, for Program or Erase operations until the operation completes.
CC3
Automatic Standby
If CMOS levels (V ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or
CC
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, I
. The Data Inputs/Outputs will still output data if a Bus
CC2
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V to be
ID
applied to some pins.
13/49
Bus operations
M29W800DT, M29W800DB
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2
and Table 3, Bus Operations.
Block Protection and Blocks Unprotection
Each block can be separately protected against accidental Program or Erase. Protected
blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. Block Protect and Chip Unprotect
operations are described in Appendix C: Block protection.
(1)
Table 2.
Bus Operations, BYTE = V
IL
Data Inputs/Outputs
Address Inputs
Operation
E
G
W
DQ15A–1, A0-A18
DQ14-DQ8
DQ7-DQ0
Bus Read
Bus Write
Output Disable
Standby
VIL
VIL
X
VIL
VIH
VIH
X
VIH Cell Address
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Output
Data Input
Hi-Z
VIL Command Address
VIH
X
X
X
VIH
Hi-Z
Read
Manufacturer
Code
A0 = VIL, A1 = VIL, A9 =
VID, Others VIL or VIH
VIL
VIL
VIL
VIH
VIH
Hi-Z
Hi-Z
20h
D7h (M29W800DT)
5Bh (M29W800DB)
A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or VIH
Read Device Code VIL
1. X = VIL or VIH
.
(1)
Bus Operations, BYTE = V
IH
Table 3.
Address Inputs
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
A0-A18
Bus Read
Bus Write
Output Disable
Standby
VIL
VIL
X
VIL
VIH
VIH
X
VIH
VIL
VIH
X
Cell Address
Data Output
Data Input
Hi-Z
Command Address
X
X
VIH
Hi-Z
Read Manufacturer
Code
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
VIL
VIL
VIL
VIL
VIH
VIH
0020h
22D7h (M29W800DT)
225Bh (M29W800DB)
A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or VIH
Read Device Code
1. X = VIL or VIH
.
14/49
M29W800DT, M29W800DB
Command interface
4
Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.
Read/Reset Command
The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.
Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.
Auto Select Command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset
commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits may be set to either V or V . The
IL
IL
IL
IH
Manufacturer Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read operation with A0 = V and A1 = V . The
IH
IL
other address bits may be set to either V or V . The Device Code for the M29W800DT is
IL
IH
22D7h and for the M29W800DB is 225Bh.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= V , A1 = V , and A12-A18 specifying the address of the block. The other address bits
IL
IH
may be set to either V or V . If the addressed block is protected then 01h is output on
IL
IH
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
Program Command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 6 Bus Read operations during the program operation will output the Status Register
on the Data Inputs/Outputs. See the section on the Status Register for more details.
15/49
Command interface
M29W800DT, M29W800DB
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
Unlock Bypass Command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
Unlock Bypass Program Command
The Unlock Bypass Program command can be used to program one address in memory at
a time. The command requires two Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. A protected block cannot be
programmed; the operation cannot be aborted and the Status Register is read. Errors must
be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.
See the Program command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
Chip Erase Command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table 6 All Bus
Read operations during the Chip Erase operation will output the Status Register on the Data
Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
16/49
M29W800DT, M29W800DB
Command interface
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
Block Erase Command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register for details on how
to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 6 All Bus Read operations
during the Block Erase operation will output the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
Erase Suspend Command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to
Table 6 for value) of the Erase Suspend Command being issued. Once the Program/Erase
Controller has stopped the memory will be set to Read mode and the Erase will be
suspended. If the Erase Suspend command is issued during the period when the memory is
waiting for an additional block (before the Program/Erase Controller starts) then the Erase is
suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
17/49
Command interface
M29W800DT, M29W800DB
Erase Resume Command
The Erase Resume command must be used to restart the Program/Erase Controller from
Erase Suspend. An erase can be suspended and resumed more than once.
Read CFI Query Command
The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Auto Select mode.
One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (Read
Array mode or Auto Select mode). A second Read/Reset command would be needed if the
device is to be put in the Read Array mode from Auto Select mode.
See Appendix B: Common Flash Interface (CFI), Table 22, Table 23, Table 24, Table 25,
Table 26 and Table 27 for details on the information contained in the Common Flash
Interface (CFI) memory area.
Block Protect and Chip Unprotect Commands
Each block can be separately protected against accidental Program or Erase. The whole
chip can be unprotected to allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are described in Appendix C: Block protection
18/49
M29W800DT, M29W800DB
Command interface
(1)
Table 4.
Commands, 16-bit mode, BYTE = V
IH
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
2
2
6
X
F0
AA
AA
AA
AA
A0
90
Read/Reset
555
555
555
555
X
2AA
2AA
2AA
2AA
PA
55
55
55
55
PD
00
55
55
X
F0
90
A0
20
Auto Select
555
555
555
Program
PA
PD
Unlock Bypass
Unlock Bypass Program
Unlock Bypass Reset
Chip Erase
X
X
555
AA
AA
B0
30
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
Read CFI Query
1
1
1
X
X
55
98
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal format.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH
.
19/49
Command interface
M29W800DT, M29W800DB
(1)
Table 5.
Commands, 8-bit mode, BYTE = V
IL
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
AAA
AAA
AAA
AAA
555
555
555
555
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
AAA
AAA
AAA
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
98
X
00
55
55
AAA
555
555
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
BA
10
30
Block Erase
6+ AAA
Erase Suspend
Erase Resume
Read CFI Query
1
1
1
X
X
AA
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH
.
Table 6.
Program, Erase Times and Program, Erase Endurance Cycles
Parameter
Min.
Typ. (1), (2)
Max. (2)
Unit
Chip Erase
12
0.8
15
10
12
6
60 (3)
6 (4)
s
s
Block Erase (64 Kbytes)
Erase Suspend Latency Time
Program (Byte or Word)
25 (3)
200 (3)
60 (3)
30 (4)
µs
µs
Chip Program (Byte by Byte)
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
Data Retention
s
s
100,000
20
cycles
years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC
.
20/49
M29W800DT, M29W800DB
Status register
5
Status register
Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.
The bits in the Status Register are summarized in Table 7: Status Register Bits.
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 7: Data Polling Flowchart gives an example of how to use the Data Polling Bit. A Valid
Address is the address being programmed or an address within the block being erased.
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is
signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 1µs.
Figure 8: Data Toggle Flowchart gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
21/49
Status register
M29W800DT, M29W800DB
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.
22/49
M29W800DT, M29W800DB
Status register
(1)
Table 7.
Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
–
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
1. Unspecified data bits should be ignored.
Figure 7.
Data Polling Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
= 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI03598
23/49
Status register
M29W800DT, M29W800DB
Figure 8.
Data Toggle Flowchart
START
READ DQ6
READ
DQ5 & DQ6
DQ6
=
NO
TOGGLE
YES
NO
DQ5
= 1
YES
READ DQ6
TWICE
DQ6
=
NO
TOGGLE
YES
FAIL
PASS
AI01370C
24/49
M29W800DT, M29W800DB
Maximum rating
6
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8.
Symbol
Absolute maximum ratings
Parameter
Min
Max
Unit
TBIAS
TSTG
VIO
Temperature Under Bias
Storage Temperature
Input or Output Voltage (1) (2)
Supply Voltage
–50
–65
125
150
°C
°C
V
–0.6
–0.6
–0.6
VCC +0.6
4
VCC
VID
V
Identification Voltage
13.5
V
1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
25/49
DC and AC parameters
M29W800DT, M29W800DB
7
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 9: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 9.
Operating and AC Measurement Conditions
M29W800D
Parameter
45
70
90
Unit
Min
Max
Min
Max
Min
Max
V
CC Supply Voltage
3.0
–40
0
3.6
85
70
2.7
–40
0
3.6
85
70
2.7
–40
0
3.6
85
70
V
Ambient Operating Temperature (Range 6)
Ambient Operating Temperature (Range 1)
Load Capacitance (CL)
°C
30
30
100
pF
ns
V
Input Rise and Fall Times
10
10
10
Input Pulse Voltages
0 to VCC
VCC/2
0 to VCC
VCC/2
0 to VCC
VCC/2
Input and Output Timing Ref. Voltages
V
Figure 9.
AC Measurement I/O Waveform
V
CC
0V
V
/2
CC
AI04498
26/49
M29W800DT, M29W800DB
DC and AC parameters
Figure 10. AC Measurement Load Circuit
V
V
CC
CC
25kΩ
DEVICE
UNDER
TEST
25kΩ
0.1µF
C
L
AI04499
C
includes JIG capacitance
L
(1)
Table 10. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
6
pF
pF
COUT
VOUT = 0V
12
1. Sampled only, not 100% tested.
Table 11. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
Output Leakage Current
0V ≤ VIN ≤ VCC
±1
±1
µA
µA
ILO
0V ≤ VOUT ≤ VCC
E = VIL, G = VIH,
f = 6MHz
ICC1
Supply Current (Read)
10
mA
µA
E = VCC ±0.2V,
RP = VCC ±0.2V
ICC2
Supply Current (Standby)
100
Supply Current
(Program/Erase)
Program/Erase
Controller active
(1)
ICC3
20
mA
VIL
VIH
VOL
VOH
VID
IID
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Identification Voltage
Identification Current
–0.5
0.8
V
V
0.7VCC
VCC +0.3
0.45
IOL = 1.8mA
V
IOH = –100µA
VCC –0.4
11.5
V
12.5
100
V
A9 = VID
µA
Program/Erase Lockout Supply
Voltage
VLKO
1.8
2.3
V
1. Sampled only, not 100% tested.
27/49
DC and AC parameters
M29W800DT, M29W800DB
Figure 11. Read Mode AC Waveforms
tAVAV
VALID
A0-A18/
A–1
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
VALID
DQ0-DQ7/
DQ8-DQ15
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05448
Table 12. Read AC Characteristics
M29W800D
Symbol
Alt
Parameter
Test Condition
Unit
45
70
90
E = VIL,
Min
tAVAV
tAVQV
tRC
Address Valid to Next Address Valid
45
70
90
ns
ns
G = VIL
E = VIL,
Max
tACC Address Valid to Output Valid
45
70
90
G = VIL
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
G = VIL Min
G = VIL Max
0
0
0
ns
ns
ns
ns
ns
ns
tELQV
tCE
45
0
70
0
90
0
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
E = VIL
Min
tGLQV
tOE
tHZ
tDF
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
E = VIL Max
G = VIL Max
E = VIL Max
25
20
20
30
25
25
35
30
30
(1)
tEHQZ
(1)
tGHQZ
tEHQX
tGHQX
Chip Enable, Output Enable or Address
Transition to Output Transition
tOH
Min
0
5
0
5
0
5
ns
ns
tAXQX
tELBL
tELBH
tBLQZ
tBHQV
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
tFLQZ BYTE Low to Output Hi-Z
tFHQV BYTE High to Output Valid
Max
Max
25
30
25
30
30
40
ns
ns
1. Sampled only, not 100% tested.
28/49
M29W800DT, M29W800DB
DC and AC parameters
Figure 12. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A18/
VALID
A–1
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI05449
Table 13. Write AC Characteristics, Write Enable Controlled
M29W800D
70
Symbol
Alt
Parameter
Unit
45
90
tAVAV
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tWHGL
tWC
tCS
tWP
tDS
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
45
0
70
0
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
30
25
0
45
45
0
50
50
0
tDH
tCH
tWPH
tAS
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
0
0
0
30
0
30
0
30
0
tAH
40
0
45
0
50
0
tOEH
tBUSY
tVCS
0
0
0
(1)
tWHRL
30
50
30
50
35
50
tVCHEL
VCC High to Chip Enable Low
1. Sampled only, not 100% tested.
29/49
DC and AC parameters
M29W800DT, M29W800DB
Figure 13. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A18/
VALID
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI05450
Table 14. Write AC Characteristics, Chip Enable Controlled
M29W800D
Symbol
Alt
Parameter
Unit
45
70
90
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tELAX
tGHEL
tEHGL
tWC
tWS
tCP
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
45
0
70
0
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
30
25
0
45
45
0
50
50
0
tDS
tDH
tWH
tCPH
tAS
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
Program/Erase Valid to RB Low
0
0
0
30
0
30
0
30
0
tAH
40
0
45
0
50
0
tOEH
tBUSY
tVCS
0
0
0
(1)
tEHRL
30
50
30
50
35
50
tVCHWL
VCC High to Write Enable Low
1. Sampled only, not 100% tested.
30/49
M29W800DT, M29W800DB
DC and AC parameters
Figure 14. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI06870
Table 15. Reset/Block Temporary Unprotect AC Characteristics
M29W800D
Symbol
Alt
Parameter
Unit
ns
45
70
90
(1)
tPHWL
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
tPHEL
tRH
Min
Min
50
50
50
(1)
tPHGL
(1)
tRHWL
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
(1)
tRHEL
tRB
0
0
0
ns
(1)
tRHGL
tPLPX
tRP
RP Pulse Width
Min
Max
Min
500
10
500
10
500
10
ns
µs
ns
(1)
tPLYH
tREADY RP Low to Read Mode
tVIDR RP Rise Time to VID
(1)
tPHPHH
500
500
500
1. Sampled only, not 100% tested.
31/49
Package mechanical data
M29W800DT, M29W800DB
8
Package mechanical data
Figure 15. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Note:
Drawing is not to scale.
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
2.80
0.1102
0.10
2.20
0.35
0.10
0.0039
0.0866
0.0138
0.0039
2.30
0.40
0.15
2.40
0.50
0.20
0.08
28.40
13.50
16.25
–
0.0906
0.0157
0.0059
0.0945
0.0197
0.0079
0.0030
1.1181
0.5315
0.6398
–
C
CP
D
28.20
13.30
16.00
1.27
28.00
13.20
15.75
–
1.1102
0.5236
0.6299
0.0500
0.0315
1.1024
0.5197
0.6201
–
E
EH
e
L
0.80
a
8°
8°
N
44
44
32/49
M29W800DT, M29W800DB
Package mechanical data
Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
Note:
Drawing is not to scale.
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3°
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3°
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
a
0°
5°
0°
5°
33/49
Package mechanical data
M29W800DT, M29W800DB
Figure 17. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z32
Note:
Drawing is not to scale.
Table 18. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
0.900
0.0354
0.350
5.900
–
0.450
0.0138
0.2323
–
0.0177
D
6.000
4.000
6.100
0.2362
0.1575
0.2402
D1
ddd
E
–
–
0.100
0.0039
8.000
5.600
0.800
1.000
1.200
0.400
0.400
7.900
8.100
0.3150
0.2205
0.0315
0.0394
0.0472
0.0157
0.0157
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
34/49
M29W800DT, M29W800DB
Part numbering
9
Part numbering
Table 19. Ordering Information Scheme
Example:
M29W800DB
90 N
6
T
Device Type
M29
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
800D = 8 Mbit (x8/x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45ns
70 = 70 ns
90 = 90 ns
Package
M = SO44
N = TSOP48: 12 x 20 mm
ZE = TFBGA48: 6x8mm, 0.80mm pitch
Temperature Range
6 = –40 to 85 °C
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
35/49
Block address table
M29W800DT, M29W800DB
Appendix A
Block address table
Table 20. Top Boot Block Addresses, M29W800DT
#
Size (Kbytes)
Address Range (x8)
Address Range (x16)
18
17
16
15
14
13
12
11
10
9
16
8
FC000h-FFFFFh
FA000h-FBFFFh
F8000h-F9FFFh
F0000h-F7FFFh
E0000h-EFFFFh
D0000h-DFFFFh
C0000h-CFFFFh
B0000h-BFFFFh
A0000h-AFFFFh
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
7E000h-7FFFFh
7D000h-7DFFFh
7C000h-7CFFFh
78000h-7BFFFh
70000h-77FFFh
68000h-6FFFFh
60000h-67FFFh
58000h-5FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
8
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
7
6
5
4
3
2
1
0
36/49
M29W800DT, M29W800DB
Block address table
Table 21. Bottom Boot Block Addresses, M29W800DB
#
Size (Kbytes)
Address Range (x8)
Address Range (x16)
18
17
16
15
14
13
12
11
10
9
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
8
F0000h-FFFFFh
E0000h-EFFFFh
D0000h-DFFFFh
C0000h-CFFFFh
B0000h-BFFFFh
A0000h-AFFFFh
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
78000h-7FFFFh
70000h-77FFFh
68000h-6FFFFh
60000h-67FFFh
58000h-5FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
8
7
6
5
4
3
2
1
8
0
16
37/49
Common Flash Interface (CFI)
M29W800DT, M29W800DB
Appendix B
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data
structure is read from the memory. Table 22, Table 23, Table 24, Table 25, Table 26 and
Table 27 show the addresses used to retrieve the data.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Table 27: Security Code Area). This area can be accessed only in Read
mode by the final user. It is impossible to change the security number after it has been
written by ST. Issue a Read command to return to Read mode.
(1)
Table 22. Query Structure Overview
Address
Sub-section Name
Description
x16
x8
10h
1Bh
27h
20h
36h
4Eh
CFI Query Identification String
System Interface Information
Device Geometry Definition
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Primary Algorithm-specific Extended Additional information specific to the
40h
61h
80h
Query table
Primary Algorithm (optional)
C2h Security Code Area
64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
38/49
M29W800DT, M29W800DB
Common Flash Interface (CFI)
(1)
Table 23. CFI Query Identification String
Address
Data
Description
Value
x16
x8
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
"Q"
"R"
"Y"
0052h Query Unique ASCII String "QRY"
0059h
0002h
AMD
Primary Algorithm Command Set and Control Interface ID
code 16 bit ID code defining a specific algorithm
Compatible
0000h
0040h
Address for Primary Algorithm extended Query table (see
Table 26)
P = 40h
NA
0000h
0000h
Alternate Vendor Command Set and Control Interface ID
Code second vendor - specified algorithm supported
0000h
0000h
0000h
Address for Alternate Algorithm extended Query table
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Table 24. CFI Query System Interface Information
Address
Data
0027h
0036h
Description
Value
2.7V
3.6V
x16
x8
V
CC Logic Supply Minimum Program/Erase voltage
1Bh
36h
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
VCC Logic Supply Maximum Program/Erase voltage
1Ch
38h
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h VPP [Programming] Supply Minimum Program/Erase voltage
0000h PP [Programming] Supply Maximum Program/Erase voltage
0004h Typical timeout per single byte/word program = 2n µs
0000h Typical timeout for minimum size write buffer program = 2n µs
000Ah Typical timeout per individual block erase = 2n ms
0000h Typical timeout for full chip erase = 2n ms (1)
NA
NA
V
16µs
NA
1s
0004h Maximum timeout for byte/word program = 2n times typical
0000h Maximum timeout for write buffer program = 2n times typical
0003h Maximum timeout per individual block erase = 2n times typical
0000h Maximum timeout for chip erase = 2n times typical (1)
256µs
NA
8s
1. Not supported in the CFI.
39/49
Common Flash Interface (CFI)
M29W800DT, M29W800DB
Table 25.
Address
Device Geometry Definition
Data
Description
Value
x16
x8
27h
4Eh
0014h Device Size = 2n in number of bytes
1 MByte
28h
29h
50h
52h
0002h
x8, x16
Async.
Flash Device Interface Code description
0000h
2Ah
2Bh
54h
56h
0000h
0000h
Maximum number of bytes in multi-byte program or page =
NA
4
2n
Number of Erase Block Regions within the device.
2Ch
58h
0004h
It specifies the number of regions within the device
containing contiguous Erase Blocks of the same size.
2Dh
2Eh
5Ah
5Ch
0000h Region 1 Information
1
16 Kbyte
2
0000h Number of identical size erase block = 0000h+1
2Fh
30h
5Eh
60h
0040h Region 1 Information
0000h Block size in Region 1 = 0040h * 256 byte
31h
32h
62h
64h
0001h Region 2 Information
0000h Number of identical size erase block = 0001h+1
33h
34h
66h
68h
0020h Region 2 Information
8 Kbyte
1
0000h Block size in Region 2 = 0020h * 256 byte
35h
36h
6Ah
6Ch
0000h Region 3 Information
0000h Number of identical size erase block = 0000h+1
37h
38h
6Eh
70h
0080h Region 3 Information
32 Kbyte
15
0000h Block size in Region 3 = 0080h * 256 byte
39h
3Ah
72h
74h
000Eh Region 4 Information
0000h Number of identical-size erase block = 000Eh+1
3Bh
3Ch
76h
78h
0000h Region 4 Information
64 Kbyte
0001h Block size in Region 4 = 0100h * 256 byte
40/49
M29W800DT, M29W800DB
Common Flash Interface (CFI)
Table 26. Primary Algorithm-Specific Extended Query Table
Address
Data
Description
Value
x16
x8
40h
41h
42h
43h
44h
80h
82h
84h
86h
88h
0050h
0052h
0049h
"P"
"R"
"I"
Primary Algorithm extended Query table unique ASCII
string “PRI”
0031h Major version number, ASCII
0030h Minor version number, ASCII
"1"
"0"
Address Sensitive Unlock (bits 1 to 0)
0000h 00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
45h
8Ah
Yes
Erase Suspend
46h
47h
48h
49h
8Ch
8Eh
90h
92h
0002h
2
1
00 = not supported, 01 = Read only, 02 = Read and Write
Block Protection
0001h
00 = not supported, x = number of sectors in per group
Temporary Block Unprotect
0001h
Yes
4
00 = not supported, 01 = supported
Block Protect /Unprotect
0004h
04 = M29W400B
4Ah
4Bh
94h
96h
0000h Simultaneous Operations, 00 = not supported
0000h Burst Mode, 00 = not supported, 01 = supported
No
No
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8
page word
4Ch
98h
0000h
No
Table 27. Security Code Area
Address
Data
Description
x16
x8
61h
62h
63h
64h
C3h, C2h
C5h, C4h
C7h, C6h
C9h, C8h
XXXX
XXXX
XXXX
XXXX
64 bit: unique device number
41/49
Block protection
M29W800DT, M29W800DB
Appendix C
Block protection
Block protection can be used to prevent any operation from modifying the data stored in the
Flash. Each Block can be protected individually. Once protected, Program and Erase
operations on the block fail to change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is
described in the Signal Descriptions section.
Unlike the Command Interface of the Program/Erase Controller, the techniques for
protecting and unprotecting blocks change between different Flash memory suppliers. For
example, the techniques for AMD parts will not work on STMicroelectronics parts. Care
should be taken when changing drivers for one part to work on another.
C.1
Programmer Technique
The Programmer technique uses high (V ) voltage levels on some of the bus pins. These
ID
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.
To protect a block follow the flowchart in Figure 18: Programmer Equipment Block Protect
Flowchart, To unprotect the whole chip it is necessary to protect all of the blocks first, then
all blocks can be unprotected at the same time. To unprotect the chip follow Figure 19:
Programmer Equipment Chip Unprotect Flowchart. Table 28: Programmer Technique Bus
Operations, BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
C.2
In-System Technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP. This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
Flash has been fitted to the system.
To protect a block follow the flowchart in Figure 20: In-System Equipment Block Protect
Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then
all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 21:
In-System Equipment Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
42/49
M29W800DT, M29W800DB
Block protection
Table 28. Programmer Technique Bus Operations, BYTE = V or V
IH
IL
Address Inputs
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
A0-A18
A9 = VID, A12-A18 Block Address
Others = X
Block Protect
VIL
VID VIL Pulse
X
X
A9 = VID, A12 = VIH, A15 = VIH
Others = X
Chip Unprotect
VID VID VIL Pulse
A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A18 Block Address
Pass = XX01h
Retry = XX00h
Block Protection
Verify
VIL
VIL
VIH
Others = X
A0 = VIL, A1 = VIH, A6 = VIH,
A9 = VID, A12-A18 Block Address
Retry = XX01h
Pass = XX00h
Block Unprotection
Verify
VIL
VIL
VIH
Others = X
43/49
Block protection
M29W800DT, M29W800DB
Figure 18. Programmer Equipment Block Protect Flowchart
START
ADDRESS = BLOCK ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
,
IH
A0, A6 = V
A1 = V
,
IL
IH
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
E, G = V
IH
IH
YES
PASS
A9 = V
IH
E, G = V
IH
AI03469
FAIL
44/49
M29W800DT, M29W800DB
Block protection
Figure 19. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
(1)
A6, A12, A15 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1, A6 = V
IL
IH
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT BLOCK
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
BLOCK
NO
NO
++n
= 1000
YES
YES
A9 = V
IH
A9 = V
IH
E, G = V
E, G = V
IH
IH
FAIL
PASS
AI03470
45/49
Block protection
M29W800DT, M29W800DB
Figure 20. In-System Equipment Block Protect Flowchart
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
Wait 100µs
WRITE 40h
IL
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
DATA
NO
=
01h
YES
++n
= 25
NO
RP = V
IH
YES
ISSUE READ/RESET
COMMAND
RP = V
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI03471
46/49
M29W800DT, M29W800DB
Block protection
Figure 21. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 4µs
INCREMENT
CURRENT BLOCK
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
DATA
NO
YES
=
00h
++n
= 1000
NO
NO
LAST
BLOCK
YES
RP = V
YES
RP = V
IH
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI03472
47/49
Revision history
M29W800DT, M29W800DB
Revision history
Table 29. Document revision history
Date
Version
Revision Details
August 2001
1.0
First Issue
Block Protection Appendix added, SO44 drawing and package
mechanical data updated, CFI Table 26, address 39h/72h data clarified,
Read/Reset operation during Erase Suspend clarified
03-Dec-2001
2.0
Description of Ready/Busy signal clarified (and Figure 14 modified)
Clarified allowable commands during block erase
01-Mar-2002
11-Apr-2002
3.0
4.0
Clarified the mode the device returns to in the CFI Read Query command
section
Temperature range 1 added
Document promoted from Preliminary Data to full Data Sheet
Erase Suspend Latency Time (typical and maximum) and Data Retention
parameters added to Table Table 6: Program, Erase Times and Program,
Erase Endurance Cycles, and Typical after 100k W/E Cycles column
removed. Minimum voltage corrected for 70ns Speed Class in Table 9:
Operating and AC Measurement Conditions.
31-Mar-2003
13-Feb-2004
4.1
5.0
Logic Diagram and Data Toggle Flowchart corrected.
Lead-free package options E and F added to Table 19: Ordering
Information Scheme.
TSOP48 package Outline and Mechanical Data updated.
TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch added.
Table 9: Operating and AC Measurement Conditions updated for 70ns
speed option.
23-Apr-2004
16-Sep-2004
6.0
7.0
Figure 2: SO Connections updated.
45ns speed class added.
Removed TFBGA48 (ZA) (6 x 9 mm) package. Converted to new ST
Corporate template.
21-Mar-2006
8.0
48/49
M29W800DT, M29W800DB
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,
AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS,
NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
49/49
相关型号：
M29W800DT70ZE6F
512KX16 FLASH 3V PROM, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-48
STMICROELECTR
M29W800DT90M1F
512KX16 FLASH 3V PROM, 90ns, PDSO44, 0.525 INCH, LEAD FREE, PLASTIC, SO-44
STMICROELECTR
M29W800DT90M6E
512KX16 FLASH 3V PROM, 90ns, PDSO44, 0.525 INCH, LEAD FREE, PLASTIC, SO-44
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明