M34C02-WMM1G [STMICROELECTRONICS]
256X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 2 X 3 MM, LEAD FREE, VFDFPN-8;
| 型号： | M34C02-WMM1G |
| 厂家： | 
ST |
| 描述： | 256X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 2 X 3 MM, LEAD FREE, VFDFPN-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M34C02
2 Kbit Serial I²C Bus EEPROM
For DIMM Serial Presence Detect
FEATURES SUMMARY
■ Software Data Protection for lower 128 bytes
Figure 1. Packages
2
■ Two Wire I C Serial Interface
■ 100kHz and 400kHz Transfer Rates
■ Single Supply Voltage:
– 2.5 to 5.5V up to 400kHz for M34C02-W
– 2.2 to 5.5V up to 400kHz for M34C02-L
– 1.8 to 5.5V up to 100kHz for M34C02-R
– 1.7 to 3.6V up to 100kHz for M34C02-F
■ BYTE and PAGE WRITE (up to 16 bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
8
1
PDIP8 (BN)
■ Automatic Address Incrementing
8
■ Enhanced ESD/Latch-Up Protection
■ More than 1 Million Erase/Write Cycles
■ More than 40 Year Data Retention
1
SO8 (MN)
150 mil width
VFDFPN8 (MM)
2x3mm² (MLP)
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
July 2003
1/26
M34C02
SUMMARY DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
the memory become permanently write protected.
Care must be taken when using this sequence as
its effect cannot be reversed. In addition, the
device allows the entire memory area to be write
protected, using the WC input (for example by
Device Select Code and RW bit (as described in
Table 2), terminated by an acknowledge bit.
When writing data to the memory, the memory
th
inserts an acknowledge bit during the 9 bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Figure 3. DIP, SO, TSSOP and VFDFPN
Connections (Top View)
M34C02
tieing this input to V ).
These I C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 256x8 bits.
E0
E1
E2
1
2
3
4
8
V
CC
WC
CC
2
7
6
5
SCL
SDA
V
SS
AI01932C
Figure 2. Logic Diagram
V
Note: 1. See the pages after page 19 for package dimensions,
and how to identify pin-1.
CC
3
Table 1. Signal Names
E0-E2
SDA
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
M34C02
SCL
WC
SCL
WC
V
V
CC
V
SS
SS
AI01931
2
I C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The device
carries a built-in 4-bit Device Type Identifier code
Power On Reset: V Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
Write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
2
(1010) in accordance with the I C bus definition to
access the memory area and a second Device
Type Identifier Code (0110) to access the
Protection Register. These codes are used
together with three chip enable inputs (E2, E1, E0)
so that up to eight 2 Kbit devices may be attached
to the I²C bus and selected individually.
is held active until V
has reached the POR
CC
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
drops from the operating
CC
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command.
2
The device behaves as a slave device in the I C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
A stable and valid V
(as defined in Tables 6 to
CC
9) must be applied before applying any logic
signal.
2/26
M34C02
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
nected from Serial Clock (SCL) to V . (Figure 4
CC
inputs must be tied to V or V to establish the
CC
SS
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Device Select Code.
Write Control (WC)
This input signal is provided for protecting the con-
tents of the whole memory from inadvertent write
operations. Write Control (WC) is used to enable
(when driven Low) or disable (when driven High)
write instructions to the entire memory area or to
the Protection Register.
When Write Control (WC) is tied Low or left
unconnected, the write protection of the first half of
the memory is determined by the status of the
Protection Register.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V . (Fig-
CC
2
Figure 4. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/26
M34C02
2
Figure 5. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
1
2
RW
Device Type Identifier
Chip Enable Address
b6
0
b5
1
b4
b3
b2
E1
b1
b0
b7
Memory Area Select
1
0
0
E2
E2
E0
E0
RW
RW
Code (two arrays)
Protection Register
Select Code
0
1
1
E1
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
4/26
M34C02
DEVICE OPERATION
2
The device supports the I C protocol. This is sum-
marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The memory device is always a
slave in all communication.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b; to address the
Protection Register, it is 0110b.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Up to eight memory devices can be connected on
a single I C bus. Each one is given a unique 3-bit
2
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the
device only responds if the Chip Enable Address
is the same as the value on the Chip Enable (E0,
E1, E2) inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
Acknowledge Bit (ACK)
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
th
on Serial Data (SDA) during the 9 bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
(SDA) after sending eight bits of data. During the
th
9
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Table 3. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 16
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
5/26
M34C02
Figure 6. Setting the Write Protection Register (WC = 0)
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
BUS ACTIVITY
ACK
ACK
ACK
VALUE
VALUE
(DON'T CARE) (DON'T CARE)
AI01935B
Setting the Software Write-Protection
The write protection feature is activated by writing
once to the Protection Register. The Protection
Register is accessed with the device select code
set to 0110b (as shown in Table 2), and the E2, E1
and E0 bits set according to the states being
applied on the E2, E1 and E0 signals. As for any
other write command, Write Control (WC) needs to
be held Low. Address and data bytes must be sent
with this command, but their values are all ignored,
and are treated as Don’t Care. Once the
Protection Register has been written, the write
protection of the first 128 bytes of the memory is
enabled, and it is not possible to unprotect these
128 bytes, even if the device is powered off and
on, and regardless the state of Write Control (WC).
The M34C02 has a hardware write-protection
feature, using the Write Control (WC) signal. This
signal can be driven High or Low, and must be
held constant for the whole instruction sequence.
When Write Control (WC) is held Low, the whole
memory array (addresses 00h to FFh) is write
protected. When Write Control (WC) is held High,
the write protection of the memory array is
dependent on whether software write-protection
has been set.
Software write-protection allows the bottom half of
the memory area (addresses 00h to 7Fh) to be
permanently write protected irrespective of
subsequent states of the Write Control (WC)
signal.
When the Protection Register has been written,
the M34C02 no longer responds to the device type
identifier 0110b in either read or write mode.
Figure 7. Result of Setting the Write Protection
FFh
Standard
FFh
Standard
Array
Array
Memory
80h
80h
7Fh
Area
7Fh
Write
Protected
Array
Standard
Array
00h
00h
Default EEPROM memory area
state before write access
to the Protect Register
State of the EEPROM memory
area after write access
to the Protect Register
AI01936C
6/26
M34C02
Figure 8. Write Mode Sequences in a Non Write-Protected Area
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
ACK
BYTE ADDR
ACK
PAGE WRITE
DEV SEL
ACK
DATA IN 1
DATA IN 2
R/W
ACK
DATA IN N
AI01941
Write Operations
replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown
in Figure 8.
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
8, and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10 bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
th
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is hardware write-protected, the device replies
to the data byte with NoAck, and the locations are
not modified. After each byte is transferred, the in-
ternal byte address counter (the 4 least significant
address bits only) is incremented. The transfer is
terminated by the bus master generating a Stop
condition.
Byte Write
After the Device Select Code and the address
byte, the bus master sends one data byte. If the
addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and
the location is not modified. If, instead, the ad-
dressed location is not Write-protected, the device
7/26
M34C02
Figure 9. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
Minimizing System Delays by Polling On ACK
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
The maximum Write time (t ) is shown in Tables
w
16 and 17, but the typical time is shorter. To make
use of this, a polling sequence can be used by the
bus master.
The sequence, as shown in Figure 9, is:
– Initial condition: a Write cycle is in progress.
8/26
M34C02
Figure 10. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
st
rd
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.
Read Operations
and outputs the contents of the addressed byte.
The bus master must not acknowledge the byte,
and terminates the transfer with a Stop condition.
Read operations are performed independently of
whether hardware or software protection has been
set.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read.
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 10, without acknowledging the
byte.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 10) but without sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
RW bit set to 1. The device acknowledges this,
9/26
M34C02
Sequential Read
recommended that the first step is to use the test
equipment to write the module information (such
as its access speed, its size, its organization) to
the first half of the memory, starting from the first
memory location. When the data has been
validated, the test equipment can send a Write
command to the Protection Register, using the
device select code ’01100000b’ followed by an
address and data byte (made up of Don’t Care
values) as shown in Figure 6. The first 128 bytes
of the memory area are then write-protected, and
the M34C02 will no longer respond to the specific
device select code ’0110000xb’. It is not possible
to reverse this sequence.
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 10.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Table 4. DRAM DIMM Connections
Acknowledge in Read Mode
DIMM Position
E2
E1
E0
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9 bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
V
V
V
0
1
2
3
4
5
6
7
SS
SS
SS
SS
CC
CC
CC
CC
SS
SS
CC
CC
SS
SS
CC
CC
SS
CC
SS
CC
SS
CC
SS
CC
th
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
USE WITHIN A DRAM DIMM
In the application, the M34C02 is soldered directly
in the printed circuit module. The 3 Chip Enable
inputs (pins 1, 2 and 3) are wired at V
or V
CC
SS
through the DIMM socket (see Table 4). The pull-
2
up resistors needed for normal behavior of the I C
2
bus are connected on the I C bus of the mother-
board (as shown in Figure 11).
The Write Control (WC) of the M34C02 can be left
unconnected. However, connecting it to V
recommended, to maintain full read and write
access.
Programming the M34C02
When the M34C02 is delivered, full read and write
access is given to the whole memory array. It is
is
SS
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
10/26
M34C02
Figure 11. Serial Presence Detect Block Diagram
R = 4.7kΩ
DIMM Position 7
E2
E1
E0 SCL SDA
V
CC
DIMM Position 6
DIMM Position 5
DIMM Position 4
DIMM Position 3
DIMM Position 2
DIMM Position 1
DIMM Position 0
E2
E1
E0 SCL SDA
V
V
SS
CC
E2
E1
E0 SCL SDA
V
V
V
CC
CC
SS
E2
E1
E0 SCL SDA
V
V
SS
CC
E2
E1
E1
E0 SCL SDA
V
V
CC
SS
E2
E0 SCL SDA
V
V
V
SS
SS
CC
E2
E1
E0 SCL SDA
V
V
CC
SS
E2
E1
E0 SCL SDA
V
SS
SCL line
SDA line
From the motherboard
2
I C master controller
AI01937
Note: 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices.
2. Common clock and common data are shared across all the devices.
3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 kΩ) because these lines are open drain when used as
outputs.
11/26
M34C02
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 5. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
TSTG
Storage Temperature
–65
150
°C
PDIP: 10 seconds
SO: 20 seconds (max)
260
235
235
Lead Temperature during
Soldering
1
TLEAD
°C
1
TSSOP: 20 seconds (max)
VIO
VCC
VESD
Input or Output range
Supply Voltage
–0.6
–0.3
6.5
6.5
V
V
V
2
–4000
4000
Electrostatic Discharge Voltage (Human Body model)
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
12/26
M34C02
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 6. Operating Conditions (M34C02-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 7. Operating Conditions (M34C02-L)
Symbol
Parameter
Min.
2.2
Max.
5.5
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Table 8. Operating Conditions (M34C02-R)
Symbol
Parameter
Min.
1.8
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
Table 9. Operating Conditions (M34C02-F)
Symbol
Parameter
Min.
1.7
0
Max.
3.6
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
70
°C
13/26
M34C02
Table 10. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
Input Levels
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Levels
V
CC
Figure 12. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
Table 11. Input Parameters
1,2
Symbol
CIN
Test Condition
Min.
Max.
8
Unit
pF
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
CIN
6
pF
ZWCL
ZWCH
VIN < 0.5 V
5
20
kΩ
kΩ
VIN > 0.7VCC
WC Input Impedance
500
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
500
ns
Note: 1. T = 25 °C, f = 400 kHz
A
2. Sampled only, not 100% tested.
14/26
M34C02
Table 12. DC Characteristics (M34C02-W)
Test Condition
(in addition to those in Table 6)
Symbol
Parameter
Max.
Unit
Min.
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
2
µA
mA
mA
µA
V
CC =5V, f =400kHz (rise/fall time < 30ns)
c
ICC
Supply Current
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
1
c
VIN = VSS or VCC , VCC = 5V
1
ICC1
Stand-by Supply Current
V
IN = VSS or VCC , VCC = 2.5V
0.5
µA
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.3
–0.3
0.3VCC
0.5
V
V
V
VIL
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
IOL = 3mA, VCC = 5V
0.4
0.4
V
V
VOL
Output Low Voltage
I
OL = 2.1mA, VCC = 2.5V
Table 13. DC Characteristics (M34C02-L)
Test Condition
(in addition to those in Table 7)
Symbol
Parameter
Max.
Unit
Min.
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
2
µA
mA
mA
mA
µA
V
CC =5V, f =400kHz (rise/fall time < 30ns)
c
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
ICC
Supply Current
1
c
VCC =2.2V, f =400kHz (rise/fall time < 30ns)
1
c
VIN = VSS or VCC , VCC = 5 V
1
ICC1
Stand-by Supply Current
V
IN = VSS or VCC , 2.2V ≤ VCC < 2.5V
0.5
µA
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.3
–0.3
0.3VCC
0.5
V
V
V
VIL
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
IOL = 3mA, VCC = 5V
0.4
0.4
V
V
VOL
Output Low Voltage
I
OL = 2.1mA, 2.2V ≤ VCC < 2.5V
15/26
M34C02
Table 14. DC Characteristics (M34C02-R)
Test Condition
(in addition to those in Table 8)
Symbol
Parameter
Max.
Unit
Min.
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
1
µA
mA
µA
µA
V
V
CC =1.8V, f =100kHz (rise/fall time < 30ns)
c
VIN = VSS or VCC , VCC = 5V
1
ICC1
Stand-by Supply Current
V
IN = VSS or VCC , 1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
0.5
– 0.3
– 0.3
–0.3
0.3 VCC
Input Low Voltage
(E2, E1, E0, SCL, SDA)
VIL
VIH
VOL
1.8V ≤ VCC < 2.5V
V
V
0.25 VCC
0.5
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
0.7VCC
VCC+1
V
IOL = 3mA, VCC = 5V
0.4
0.4
V
V
V
IOL = 2.1mA, 2.2V ≤ VCC < 2.5V
Output Low Voltage
IOL = 0.15mA, VCC = 1.8V
0.2
Table 15. DC Characteristics (M34C02-F)
Test Condition
(in addition to those in Table 9)
1
1
Symbol
Parameter
Unit
Min.
Max.
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
VOUT = VSS or VCC, SDA in Hi-Z
Output Leakage Current
Supply Current
± 2
1
µA
mA
µA
µA
V
V
CC =1.7V, f =100kHz (rise/fall time < 30ns)
c
VIN = VSS or VCC , VCC = 3.6V
1
ICC1
Stand-by Supply Current
V
IN = VSS or VCC , 1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 3.6V
0.5
– 0.3
– 0.3
–0.3
0.3 VCC
Input Low Voltage
(E2, E1, E0, SCL, SDA)
VIL
1.7V ≤ VCC < 2.5V
V
V
0.25 VCC
0.5
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
V
IOL = 2.1mA, 2.2V ≤ VCC ≤ 3.6V
0.4
0.2
V
V
VOL
Output Low Voltage
IOL = 0.15mA, VCC = 1.7V
Note: 1. Preliminary Data.
16/26
M34C02
Table 16. AC Characteristics (M34C02-W, M34C02-L)
Test conditions specified in Table 10 and Table 6 or 7
Symbol
fC
Alt.
fSCL
Parameter
Unit
kHz
ns
Min.
Max.
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
Start Condition Set Up Time
Start Condition Hold Time
600
600
ns
ns
ns
ns
ms
tCHDX
tDLCL
tCHDH
tDHDL
tW
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
tWR
10
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Table 17. AC Characteristics (M34C02-R, M34C02-F)
Test conditions specified in Table 10 and Table 8 or 9
Symbol
fC
Alt.
fSCL
Parameter
Unit
kHz
ns
Min.
Max.
Clock Frequency
100
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
4000
4700
20
ns
2
300
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
250
0
ns
ns
200
200
4700
4000
4000
4700
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
3500
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
ns
tCHDX
tDLCL
tCHDH
tDHDL
tW
Start Condition Hold Time
ns
Stop Condition Set Up Time
ns
Time between Stop Condition and Next Start Condition
Write Time
ns
tWR
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
17/26
M34C02
Figure 13. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
18/26
M34C02
PACKAGE MECHANICAL
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Notes: 1. Drawing is not to scale.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
19/26
M34C02
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
20/26
M34C02
VFDFPN8 – 8 lead Very thin Fine pitch Dual Flat Package No lead 2x3mm², Package Outline
D2
Top View
L
8
7
6
5
E
E2
1
2
3
4
D
A
b
e
A3
A1
VFDFPN-02
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V . It must not be allowed to be connected to
SS
any other voltage or signal line on the PCB, for example during the soldering process.
VFDFPN8 – 8 lead Very thin Fine pitch Dual Flat Package No lead 2x3mm², Package Mechanical
Data
mm
Min.
0.80
0.00
inches
Min.
Symbol
Typ.
0.90
0.02
0.05
0.25
2.00
1.65
3.00
1.80
0.50
0.40
Max.
1.00
0.05
Typ.
Max.
0.039
0.002
A
A1
A3
b
0.035
0.001
0.002
0.010
0.079
0.065
0.118
0.071
0.020
0.016
0.031
0.000
0.20
-
0.32
-
0.008
0.013
D
-
-
0.069
-
D2
E
1.50
-
1.75
-
0.059
-
E2
e
1.65
-
1.90
-
0.065
-
0.075
-
L
0.30
0.50
0.012
0.020
21/26
M34C02
TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Notes: 1. Drawing is not to scale.
TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
22/26
M34C02
TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Notes: 1. Drawing is not to scale.
TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.100
0.150
0.950
0.400
0.230
3.100
5.150
3.100
–
Typ.
Max.
0.0433
0.0059
0.0374
0.0157
0.0091
0.1220
0.2028
0.1220
–
A
A1
A2
b
0.050
0.750
0.250
0.130
2.900
4.650
2.900
–
0.0020
0.0295
0.0098
0.0051
0.1142
0.1831
0.1142
–
0.850
0.0335
c
D
3.000
4.900
3.000
0.650
0.1181
0.1929
0.1181
0.0256
E
E1
e
CP
L
0.100
0.700
0.0039
0.0276
0.550
0.950
0.400
0°
0.0217
0.0374
0.0157
0°
L1
α
6°
6°
23/26
M34C02
PART NUMBERING
Table 18. Ordering Information Scheme
2
Example :
M34C02
–
W MN
6
T
P
Device Type
2
M34 = ASSP I C serial access EEPROM
Device Function
02 = 2 Kbit (256 x 8)
Operating Voltage
W = V = 2.5 to 5.5V (400kHz)
CC
L = V = 2.2 to 5.5V (400kHz)
CC
R = V = 1.8 to 5.5V (100kHz)
CC
F = V = 1.7 to 3.6V (100kHz)
CC
Package
1
BN = PDIP8
MN = SO8 (150 mil width)
MM = VFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
DS = TSSOP8 (3x3mm² body size, MSOP8)
Temperature Range
6 = –40 to 85 °C
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
2
Plating Technology
blank = Standard SnPb plating
P = Pb-free plating
G = Green pack
Note: 1. Package available only on request.
2. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your near-
est ST Sales Office.
24/26
M34C02
REVISION HISTORY
Table 19. Revision History
Date
Rev.
Description of Revision
Adjustments to the formatting. 0 to 70°C temperature range removed from DC and AC tables.
No change to description of device, or parameters
27-Dec-1999
2.0
07-Dec-2000
13-Mar-2001
18-Jul-2002
22-May-2002
21-Jul-2003
2.1
2.2
2.3
2.4
3.0
New definition of lead soldering temperature absolute rating for certain packages
-R voltage range added
TSSOP8 (3x3mm² body size) package (MSOP8) added
VFDFPN8 package (MLP8) added
Document reformatted. -F voltage range added.
25/26
M34C02
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2003 STMicroelectronics - All Rights Reserved
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www.st.com
26/26
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