M34D64WBN5_技术文档

M34D64

M34D32

64/32 Kbit Serial I²C Bus EEPROM

With Hardware Write Control on Top Quarter of Memory

PRELIMINARY DATA

2

■ Compatible with I C Extended Addressing

2

■ Two Wire I C Serial Interface

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M34Dxx

– 2.5V to 5.5V for M34Dxx-W

– 1.8V to 3.6V for M34Dxx-R

8

1

■ Hardware Write Control of the top quarter of

PSDIP8 (BN)

memory

0.25 mm frame

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Programming Cycle

8

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

1

SO8 (MN)

150 mil width

DESCRIPTION

These electrically erasable programmable

memory (EEPROM) devices are fabricated with

STMicroelectronics’ High Endurance, CMOS

technology. This guarantees an endurance

typically well above one million Erase/Write

cycles, with a data retention of 40 years. The

memories are organized as 8192x8 bits (M34D64)

and 4096x8 bits (M34D32), and operate down to

Figure 1. Logic Diagram

V

CC

Table 1. Signal Names

3

E0-E2

SDA

E0, E1, E2

SDA

Chip Enable Inputs

M34D64

M34D32

Serial Data/Address Input/

Output

SCL

WC

SCL

WC

Serial Clock

Write Control

Supply Voltage

Ground

V

CC

SS

V

SS

AI02850

May 2000

1/15

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M34D64, M34D32

Figure 2A. DIP Connections

2.5 V (for the -W version of each device), and

down to 1.8 V (for the -R version of each device).

The M34D64 and M34D32 are available in Plastic

Dual-in-Line and Plastic Small Outline packages.

M34D64

M34D32

These memory devices are compatible with the

2

I C extended memory standard. This is a two wire

serial interface that uses a bi-directional data bus

and serial clock. The memory carries a built-in 4-

bit unique Device Type Identifier code (1010) in

E0

E1

E2

1

2

3

4

8

V

CC

WC

7

6

2

SCL

SDA

accordance with the I C bus definition.

The memory behaves as a slave device in the I C

2

V

5

SS

AI02851

protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are

initiated by a START condition, generated by the

bus master. The START condition is followed by a

Device Select Code and RW bit (as described in

Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory

th

inserts an acknowledge bit during the 9 bit time,

Figure 2B. SO Connections

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a STOP condition after an Ack for WRITE, and

after a NoAck for READ.

M34D64

M34D32

Power On Reset: V

Lock-Out Write Protect

CC

E0

E1

E2

1

2

3

4

8

V

CC

WC

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is included. The internal reset

7

6

SCL

SDA

V

5

is held active until the V

voltage has reached

SS

CC

AI02852

the POR threshold value, and all operations are

disabled – the device will not respond to any

command. In the same way, when V drops from

CC

the operating voltage, below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable and

1

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

T_A

Ambient Operating Temperature

-40 to 125

-65 to 150

T_STG

Storage Temperature

°C

PSDIP8: 10 sec

SO8: 40 sec

260

215

T_LEAD

Lead Temperature during Soldering

°C

V_IO

V_CC

Input or Output range

Supply Voltage

-0.6 to 6.5

-0.3 to 6.5

4000

V

2

V_ESD

Electrostatic Discharge Voltage (Human Body model)

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

3. EIAJ IC-121 (Condition C) (200 pF, 0 Ω)

2/15

M34D64, M34D32

2

Figure 3. Maximum R Value versus Bus Capacitance (C

) for an I C Bus

L

BUS

V

CC

20

16

12

R

L

SDA

MASTER

C

BUS

8

SCL

fc = 100kHz

4

fc = 400kHz

C

BUS

0

10

100

(pF)

1000

C

BUS

AI01665

valid V

logic signal.

must be applied before applying any

(WC=V ) or disable (WC=V ) write instructions to

IL IH

the top quarter of the memory area. When

unconnected, the WC input is internally read as

CC

SIGNAL DESCRIPTION

Serial Clock (SCL)

The SCL input pin is used to strobe all data in and

out of the memory. In applications where this line

is used by slaves to synchronize the bus to a

slower clock, the master must have an open drain

output, and a pull-up resistor must be connected

V , and write operations are allowed.

IL

DEVICE OPERATION

2

The memory device supports the I C protocol.

This is summarized in Figure 5, and is compared

with other serial bus protocols in Application Note

AN1001. Any device that sends data on to the bus

is defined to be a transmitter, and any device that

from the SCL line to V . (Figure 3 indicates how

CC

the value of the pull-up resistor can be calculated).

In most applications, though, this method of

synchronization is not employed, and so the pull-

up resistor is not necessary, provided that the

master has a push-pull (rather than open drain)

output.

Figure 4. Memory Map of Write Control Areas

1FFh

Write Controlled

Area

Serial Data (SDA)

The SDA pin is bi-directional, and is used to

transfer data in or out of the memory. It is an open

drain output that may be wire-OR’ed with other

open drain or open collector signals on the bus. A

pull up resistor must be connected from the SDA

180h

bus to V . (Figure 3 indicates how the value of

the pull-up resistor can be calculated).

Chip Enable (E2, E1, E0)

These chip enable inputs are used to set the value

that is to be looked for on the three least significant

bits (b3, b2, b1) of the 7-bit device select code.

CC

100h

FFh

Write Controlled

Area

C0h

80h

40h

00h

80h

These inputs must be tied to V

establish the device select code.

or V

to

CC

SS

Write Control (WC)

The hardware Write Control pin (WC) is useful for

protecting the top quarter of the memory (as

shown in Figure 4) from inadvertent erase or write.

The Write Control signal is used to enable

000h

M34D32

M34D64

AI03114

3/15

M34D64, M34D32

2

Figure 5. I C Bus Protocol

SCL

SDA

START

SDA

STOP

CONDITION

INPUT CHANGE

CONDITION

1

2

3

7

8

9

SCL

SDA

ACK

MSB

START

CONDITION

1

2

3

7

8

9

SCL

SDA

MSB

ACK

STOP

CONDITION

AI00792

state.

A

STOP

condition

terminates

reads the data to be a receiver. The device that

controls the data transfer is known as the master,

and the other as the slave. A data transfer can only

be initiated by the master, which will also provide

the serial clock for synchronization. The memory

communication between the memory device and

the bus master. A STOP condition at the end of a

Read command, after (and only after) a NoAck,

forces the memory device into its standby state. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

device is always

communication.

a

slave device in all

Acknowledge Bit (ACK)

Start Condition

An acknowledge signal is used to indicate a

successful byte transfer. The bus transmitter,

whether it be master or slave, releases the SDA

START is identified by a high to low transition of

the SDA line while the clock, SCL, is stable in the

high state. A START condition must precede any

data transfer command. The memory device

th

bus after sending eight bits of data. During the 9

clock pulse period, the receiver pulls the SDA bus

low to acknowledge the receipt of the eight data

bits.

continuously

monitors

(except

during

a

programming cycle) the SDA and SCL lines for a

START condition, and will not respond unless one

is given.

Data Input

Stop Condition

STOP is identified by a low to high transition of the

SDA line while the clock SCL is stable in the high

During data input, the memory device samples the

SDA bus signal on the rising edge of the clock,

SCL. For correct device operation, the SDA signal

must be stable during the clock low-to-high

4/15

M34D64, M34D32

1

Table 3. Device Select Code

Device Type Identifier

Chip Enable

RW

b7

b6

0

b5

1

b4

0

b3

E2

b2

E1

b1

E0

b0

Device Select Code

1

RW

Note: 1. The most significant bit, b7, is sent first.

transition, and the data must change only when

the SCL line is low.

Memory Addressing

Table 4. Most Significant Byte

b15

b14

b13 b12

b11 b10 b9

b8

b0

Note: 1. b15 to b13 are Don’t Care on the M34D64 series.

To start communication between the bus master

and the slave memory, the master must initiate a

START condition. Following this, the master sends

the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the

7-bit Device Select Code, and the 1-bit Read/Write

Designator (RW). The Device Select Code is

further subdivided into: a 4-bit Device Type

Identifier, and a 3-bit Chip Enable “Address” (E2,

E1, E0).

b15 to b12 are Don’t Care on the M34D32 series.

Table 5. Least Significant Byte

b7

b6

b5

b4

b3

b2

b1

later. A communication between the master and

the slave is ended with a STOP condition.

Each data byte in the memory has a 16-bit (two

byte wide) address. The Most Significant Byte

(Table 4) is sent first, followed by the Least

significant Byte (Table 5). Bits b15 to b0 form the

address of the byte in memory. Bits b15 to b13 are

treated as a Don’t Care bit on the M34D64

memory. Bits b15 to b12 are treated as Don’t Care

bits on the M34D32 memory.

To address the memory array, the 4-bit Device

Type Identifier is 1010b.

If all three chip enable inputs are connected, up to

eight memory devices can be connected on a

2

single I C bus. Each one is given a unique 3-bit

code on its Chip Enable inputs. When the Device

Select Code is received on the SDA bus, the

memory only responds if the Chip Select Code is

the same as the pattern applied to its Chip Enable

pins.

Write Operations

Following a START condition the master sends a

Device Select Code with the RW bit set to ’0’, as

shown in Table 6. The memory acknowledges this,

and waits for two address bytes. The memory

responds to each address byte with an

acknowledge bit, and then waits for the data byte.

Writing to the memory may be inhibited if the WC

input pin is taken high. Any write command with

WC=1 (during a period of time from the START

condition until the end of the two address bytes)

will not modify the contents of the top quarter of

the memory.

th

The 8 bit is the RW bit. This is set to ‘1’ for read

and ‘0’ for write operations. If a match occurs on

the Device Select Code, the corresponding

memory gives an acknowledgment on the SDA

th

bus during the 9 bit time. If the memory does not

match the Device Select Code, it deselects itself

from the bus, and goes into stand-by mode.

There are two modes both for read and write.

These are summarized in Table 6 and described

Table 6. Operating Modes

1

Mode

RW bit

Bytes

Initial Sequence

WC

X

Current Address Read

1

0

1

0

1

START, Device Select, RW = ‘1’

X

START, Device Select, RW = ‘0’, Address

reSTART, Device Select, RW = ‘1’

Similar to Current or Random Address Read

START, Device Select, RW = ‘0’

Random Address Read

1

X

Sequential Read

Byte Write

X

≥ 1

1

V_IL

Page Write

≤ 32

START, Device Select, RW = ‘0’

Note: 1. X = V_IHor V_IL.

5/15

M34D64, M34D32

Figure 6. Write Mode Sequences

ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

R/W

ACK

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

R/W

ACK

PAGE WRITE

(cont'd)

DATA IN N

AI02853

Byte Write

contents of the addressed memory location are

not modified. After each byte is transferred, the

internal byte address counter (the 5 least

significant bits only) is incremented. The transfer is

terminated by the master generating a STOP

condition.

In the Byte Write mode, after the Device Select

Code and the address bytes, the master sends

one data byte. If the addressed location is write

protected by the WC pin, the location is not

modified. The master terminates the transfer by

generating a STOP condition.

When the master generates a STOP condition

th

immediately after the Ack bit (in the “10 bit” time

Page Write

slot), either at the end of a byte write or a page

write, the internal memory write cycle is triggered.

A STOP condition at any other time does not

trigger the internal write cycle.

During the internal write cycle, the SDA input is

disabled internally, and the device does not

respond to any requests.

The Page Write mode allows up to 32 bytes to be

written in a single write cycle, provided that they

are all located in the same “row” in the memory:

that is the most significant memory address bits

(b12-b5 for the M34D64 and b11-b5 for the

M34D32) are the same. If more bytes are sent

than will fit up to the end of the row, a condition

known as ‘roll-over’ occurs. Data starts to become

overwritten (in a way not formally specified in this

data sheet).

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory

disconnects itself from the bus, and copies the

data from its internal latches to the memory cells.

The master sends from one up to 32 bytes of data,

each of which is acknowledged by the memory if

the WC pin is low. If the WC pin is high, the

The maximum write time (t ) is shown in Table 9,

w

but the typical time is shorter. To make use of this,

6/15

M34D64, M34D32

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

NO

First byte of instruction

with RW = 0 already

decoded by M24xxx

YES

Addressing the

Memory

NO

YES

Send

Byte Address

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

AI01847

an Ack polling sequence can be used by the

master.

The sequence, as shown in Figure 7, is:

– Initial condition: a Write is in progress.

– Step 1: the master issues a START condition

followed by a Device Select Code (the first byte

of the new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no Ack will be returned and the

master goes back to Step 1. If the memory has

terminated the internal write cycle, it responds

with an Ack, indicating that the memory is ready

to receive the second part of the next instruction

(the first byte of this instruction having been sent

during Step 1).

Read Operations

Read operations are performed independently of

the state of the WC pin.

Random Address Read

A dummy write is performed to load the address

into the address counter, as shown in Figure 8.

Then, without sending a STOP condition, the

master sends another START condition, and

repeats the Device Select Code, with the RW bit

set to ‘1’. The memory acknowledges this, and

outputs the contents of the addressed byte. The

master must not acknowledge the byte output, and

terminates the transfer with a STOP condition.

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read mode, following a START

condition, the master sends a Device Select Code

with the RW bit set to 1. The memory

acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. The master

terminates the transfer with a STOP condition, as

7/15

M34D64, M34D32

Figure 8. Read Mode Sequences

ACK

NO ACK

DATA OUT

CURRENT

ADDRESS

READ

DEV SEL

R/W

ACK

NO ACK

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

BYTE ADDR

DEV SEL *

R/W

ACK

NO ACK

SEQUENTIAL

CURRENT

READ

DEV SEL

DATA OUT 1

DATA OUT N

R/W

ACK

SEQUENTIAL

RANDOM

READ

DEV SEL *

BYTE ADDR

DEV SEL * DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

AI01105C

st

th

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.

shown in Figure 8, without acknowledging the byte

output.

Sequential Read

After the last memory address, the address

counter ‘rolls-over’ and the memory continues to

output data from the start of the memory block.

Acknowledge in Read Mode

In all read modes, the memory waits, after each

byte read, for an acknowledgment during the 9

bit time. If the master does not pull the SDA line

low during this time, the memory terminates the

data transfer and switches to its standby state.

This mode can be initiated with either a Current

Address Read or a Random Address Read. The

master does acknowledge the data byte output in

this case, and the memory continues to output the

next byte in sequence. To terminate the stream of

bytes, the master must not acknowledge the last

byte output, and must generate a STOP condition.

th

The output data comes from consecutive

addresses, with the internal address counter

automatically incremented after each byte output.

8/15

M34D64, M34D32

Table 7. DC Characteristics

(T = 0 to 70 °C or –40 to 85 °C; V = 4.5 to 5.5 V or 2.5 to 5.5 V)

A

CC

1

(T = 0 to 70 °C or –20 to 85 °C; V = 1.8 to 3.6 V )

A

Symbol

Parameter

Test Condition

0 V ≤ V_IN≤ V_CC

Min.

Max.

Unit

Input Leakage Current

(SCL, SDA)

I_LI

± 2

µA

I_LO

Output Leakage Current

0 V ≤ V_OUT≤ V_CC,SDA in Hi-Z

± 2

2

µA

mA

V

_CC=5V, f =400kHz (rise/fall time < 30ns)

c

V

_CC=2.5V, f =400kHz (rise/fall time < 30ns)

-W series:

-R series:

1

I_CC

Supply Current

c

1

V

_CC=1.8V, f =100kHz (rise/fall time < 30ns)

mA

µA

c

0.8

I_CC1

I_CC2

I_CC3

Supply Current (Stand-by)

V_IN= V_SSor V_CC, V_CC= 5 V

V_IN= V_SSor V_CC, V_CC= 2.5 V

V_IN= V_SSor V_CC, V_CC= 1.8 V

10

2

1

Input Low Voltage

(E0-E2, SCL, SDA)

V_IL

V_IH

–0.3

0.3 V_CC

V_CC+1

V

Input High Voltage

(E0-E2, SCL, SDA)

0.7V_CC

V_ILW

V_IHW

Input Low Voltage (WC)

Input High Voltage (WC)

–0.3

0.5

V_CC+1

0.4

V

0.7V_CC

I

_OL= 3 mA, V_CC= 5 V

_OL= 2.1 mA, V_CC= 2.5 V

_OL= 0.15 mA, V_CC= 1.8 V

Output Low

-W series:

-R series:

I

0.4

V_OL

Voltage

1

I

0.2

Note: 1. This is preliminary data.

1

Table 8. Input Parameters (T = 25 °C, f = 400 kHz)

A

Symbol

C_IN

Parameter

Test Condition

Min.

Max.

8

Unit

Input Capacitance (SDA)

Input Capacitance (other pins)

WC Input Impedance

pF

kΩ

C_IN

6

Z_WCL

Z_WCH

t_NS

V_IN< V_ILW

V_IN> V_IHW

50

300

WC Input Impedance

500

Pulse width ignored

(Input Filter on SCL and SDA)

Single glitch

50

ns

Note: 1. Sampled only, not 100% tested.

9/15

M34D64, M34D32

Table 9. AC Characteristics

M34D64 / M34D32

V

=2.5 to 5.5 V

CC

=1.8 to 3.6 V

V

=4.5 to 5.5 V

V

CC

T =0 to 70°C or

Symbol

Alt.

Parameter

T =0 to 70°C or T =0 to 70°C or

A

Unit

A

4

–40 to 85°C

–20 to 85°C

Min

Max

300

Min

Max

300

Min

Max

1000

300

t_CH1CH2

t_CL1CL2

t_R

t_F

t_R

t_F

Clock Rise Time

ns

µs

Clock Fall Time

SDA Rise Time

SDA Fall Time

2

20

1000

t_DH1DH2

2

300

t_DL1DL2

1

t_SU:STAClock High to Input Transition

t_HIGHClock Pulse Width High

600

0

600

0

4700

4000

0

t_CHDX

t_CHCL

t_DLCL

t_CLDX

t_CLCH

t_HD:STAInput Low to Clock Low (START)

t_HD:DATClock Low to Input Transition

t_LOW

t_SU:DAT

t_SU:STO

t_BUF

Clock Pulse Width Low

1.3

4.7

Input Transition to Clock

Transition

t_DXCX

t_CHDH

t_DHDL

100

600

1.3

100

600

1.3

250

4000

4.7

ns

µs

ns

Clock High to Input High (STOP)

Input High to Input Low (Bus

Free)

3

t_AA

Clock Low to Data Out Valid

200

900

200

900

200

3500

t_CLQV

Data Out Hold Time After Clock

Low

t_CLQX

t_DH

f_C

f_SCL

t_WR

Clock Frequency

Write Time

400

10

400

10

100

10

kHz

ms

t_W

Note: 1. For a reSTART condition, or following a write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

4. This is preliminary data.

Figure 9. AC Testing Input Output Waveforms

Table 10. AC Measurement Conditions

0.8V

Input Rise and Fall Times

Input Pulse Voltages

≤ 50 ns

CC

0.7V

0.3V

CC

0.2V to 0.8V

CC

0.2V

CC

Input and Output Timing

Reference Voltages

0.3V to 0.7V

CC

AI00825

10/15

M34D64, M34D32

Figure 10. AC Waveforms

tCHCL

tDLCL

tCLCH

SCL

tDXCX

tCHDH

SDA IN

tCHDX

tCLDX

SDA

tDHDL

START

CONDITION

SDA

STOP &

BUS FREE

INPUT CHANGE

SCL

tCLQV

tCLQX

DATA VALID

SDA OUT

DATA OUTPUT

SCL

tW

SDA IN

tCHDH

tCHDX

STOP

WRITE CYCLE

START

CONDITION

AI00795B

11/15

M34D64, M34D32

Table 11. Ordering Information Scheme

Example:

M34D64

–

W

MN

1

T

Memory Capacity

Option

64

32

64 Kbit (8K x 8)

32 Kbit (4K x 8)

T

Tape and Reel Packing

Operating Voltage

blank 4.5 V to 5.5 V

W

2.5 V to 5.5 V

1.8 V to 3.6 V

2

R

Package

Temperature Range

1

BN

PSDIP8 (0.25 mm frame)

SO8 (150 mil width)

0 °C to 70 °C

1

6

5

MN

–40 °C to 85 °C

–20 °C to 85 °C

Note: 1. Temperature range available only on request.

2. The -R version (V range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1.

CC

ORDERING INFORMATION

Devices are shipped from the factory with the

memory content set at all 1s (FFh).

The notation used for the device number is as

shown in Table 11. For a list of available options

(speed, package, etc.) or for further information on

any aspect of this device, please contact your

nearest ST Sales Office.

12/15

M34D64, M34D32

Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm

inches

Symb.

Typ.

Min.

3.90

0.49

3.30

0.36

1.15

0.20

9.20

–

Max.

5.90

–

Typ.

Min.

0.154

0.019

0.130

0.014

0.045

0.008

0.362

–

Max.

0.232

–

A

A1

A2

B

5.30

0.56

1.65

0.36

9.90

–

0.209

0.022

0.065

0.014

0.390

–

B1

C

D

E

7.62

2.54

0.300

0.100

E1

e1

eA

eB

L

6.00

–

6.70

–

0.236

–

0.264

–

7.80

–

0.307

–

10.00

3.80

0.394

0.150

3.00

8

0.118

8

N

Figure 11. PSDIP8 (BN)

A2

A

L

A1

e1

B

C

eA

eB

B1

D

N

1

E1

E

PSDIP-a

Note: 1. Drawing is not to scale.

13/15

M34D64, M34D32

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm

inches

Min.

0.053

0.004

0.013

0.007

0.189

0.150

–

Symb.

Typ.

Min.

1.35

0.10

0.33

0.19

4.80

3.80

–

Max.

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ.

Max.

0.069

0.010

0.020

0.010

0.197

0.157

–

A

A1

B

C

D

E

e

1.27

0.050

H

h

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

L

α

N

CP

8

0.10

0.004

Figure 12. SO8 narrow (MN)

h x 45˚

C

A

B

CP

e

D

N

1

E

H

A1

α

L

SO-a

Note: 1. Drawing is not to scale.

14/15

M34D64, M34D32

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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15/15


型号：	M34D64WBN5
厂家：	ST
描述：	IC,SERIAL EEPROM,8KX8,CMOS,DIP,8PIN,PLASTIC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器双倍数据速率光电二极管内存集成电路
文件：	总15页 (文件大小：119K)
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M34D64WBN5 [STMICROELECTRONICS]

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