M36DR432AD_技术文档

M36DR432AD

M36DR432BD

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory

and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

■ Multiple Memory Product

Figure 1. Package

– 1 bank of 32 Mbit (2Mb x16) Flash Memory

– 1 bank of 4 Mbit (256Kb x16) SRAM

■ SUPPLY VOLTAGE

– V

= V

=1.65V to 2.2V

DDF

PPF

DDS

= 12V for Fast Program (optional)

FBGA

■ ACCESS TIMES: 85ns, 100ns, 120ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

Stacked LFBGA66 (ZA)

12 x8mm

– Manufacturer Code: 0020h

– Top Device Code, M36DR432AD: 00A0h

– Bottom Device Code, M36DR432BD: 00A1h

FLASH MEMORY

■ MEMORY BLOCKS

– Dual Bank Memory Array: 4 Mbit, 28 Mbit

– Parameter Blocks (Top or Bottom location)

■ PROGRAMMING TIME

■ ERASE SUSPEND and RESUME MODES

– 10µs by Word typical

■ 100,000 PROGRAM/ERASE CYCLES per

– Double Word Program Option

■ ASYNCHRONOUS PAGE MODE READ

– Page Width: 4 Words

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

– Page Access: 35ns

SRAM

– Random Access: 85ns, 100ns, 120ns

■ DUAL BANK OPERATIONS

■ 4 Mbit (256Kb x16)

■ LOW V

DATA RETENTION: 1.0V

DDS

– Read within one Bank while Program or

Erase within the other

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

– No delay between Read and Write operations

■ BLOCK LOCKING

– All blocks locked at Power up

– Any combination of blocks can be locked

– WPF for Block Lock-Down

■ COMMON FLASH INTERFACE (CFI)

– 64 bit Unique Device Identifier

– 64 bit User Programmable OTP Cells

February 2003

1/52

M36DR432AD, M36DR432BD

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Reset/Power-Down (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VDDF Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

Programming Voltage (11.4V to 12.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PPF

SSF

SRAM Chip Enable (ES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

VDDS Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . 13

Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Flash Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Flash Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/52

M36DR432AD, M36DR432BD

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Exit Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Quadruple Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bank Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Flash Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19

Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3/52

M36DR432AD, M36DR432BD

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. Absolute Maximum Ratings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 26

Table 14. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Flash DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17. SRAM DC Characteristics (T = –40 to 85°C; V

= V

= 1.65V to 2.2V) . . . . . . . . 28

DDS

A

DDF

Figure 8. Flash Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 9. Flash Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12. Flash Reset/Power-Down AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21. Flash Reset/Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Flash Data Polling DQ7 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 22. Flash Data Polling and Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15. Flash Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16. Flash Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V . . . . . . 38

IL

Figure 18. SRAM Read AC Waveforms, ES or GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23. SRAM Read AC Characteristics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 40

Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High . . . . . . . . . . . . . . . . . . . . . . 40

Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . . 41

Figure 23. SRAM Write AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 24. SRAM Low V

Data Retention AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . 42

Data Retention Characteristics (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . 43

DDS

Table 25. SRAM Low V

DDS

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline44

Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . . . 44

4/52

M36DR432AD, M36DR432BD

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47

APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 32. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 33. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 34. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 35. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 51

5/52

M36DR432AD, M36DR432BD

SUMMARY DESCRIPTION

The M36DR432AD/BD is a low-voltage Multiple

Memory Product which combines two memory de-

vices: a 32 Mbit (2Mbit x16) non-volatile Flash

memory and a 4 Mbit SRAM.

The memory is available in a Stacked LFBGA66

12x8mm - 8x8 active ball array, 0.8mm pitch pack-

age and supplied with all the bits erased (set to

‘1’).

Table 1. Signal Names

A0-A17

Address Inputs

A18-A20

DQ0-DQ15

Address Inputs for Flash Chip only

Data Input/Outputs, Command Inputs

Flash Power Supply

V

DDF

Flash Optional Supply Voltage for Fast

Program & Erase

V

PPF

Figure 2. Logic Diagram

V

Flash Ground

V

SSF

DDS

SSS

DDF PPF DDS

SRAM Power Supply

SRAM Ground

21

16

A0-A20

DQ0-DQ15

NC

Not Connected Internally

WF

EF

Flash control functions

EF

Chip Enable

GF

Output Enable

RPF

WPF

WF

RPF

WPF

Write Enable

M36DR432AD

M36DR432BD

Reset/Power-Down

Write Protect input

E1S

E2S

GS

SRAM control functions

E1S

E2S

GS

Chip Enable

WS

UBS

LBS

Chip Enable

Output Enable

Write Enable

WS

UBS

LBS

Upper Byte Enable

Lower Byte Enable

V

SSS

SSF

AI07309b

6/52

M36DR432AD, M36DR432BD

Figure 3. TFBGA Connections (Top view through package)

7/52

M36DR432AD, M36DR432BD

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

When Output Enable, GF, is at V the outputs are

High impedance.

Flash Write Enable (WF). The Write Enable

controls the Bus Write operation of the Flash

memory’s Command Interface.

IH

Address Inputs (A0-A17). Addresses A0-A17

are common inputs for the Flash and the SRAM

components. The Address Inputs select the cells

in the memory array to access during Bus Read

operations. During Bus Write operations they con-

trol the commands sent to the Command Interface

of the internal state machine. During a write oper-

ation, the address inputs for the Flash memory are

latched on the falling edge of the Flash Chip En-

able (EF) or Write Enable (WF), whichever occurs

last, whereas for the SRAM array they are latched

on the falling edge of the SRAM Chip Enable lines

(E1S or E2S) or Write Enable (WS). In the rest of

the datasheet, only the Active Low SRAM Chip

Enable line will be discussed. It will be referred to

as ES.

Address Inputs (A18-A20). Addresses A18-A20

are inputs for the Flash component only. They are

latched during a write operation on the falling edge

of Flash Chip Enable (EF) or Write Enable (WF),

whichever occurs last.

Data Input/Output (DQ0-DQ15). The Data I/O

output the data stored at the selected address dur-

ing a Bus Read operation or input a command or

the data to be programmed during a Write Bus op-

eration.

Flash Write Protect (WPF). Write Protect is an

input that gives an additional hardware protection

for each Flash block. When Write Protect is at V ,

IL

the locked-down blocks cannot be locked or un-

locked. When Write Protect is at V , the Lock-

IH

Down is disabled and the Locked-Down blocks

can be locked or unlocked. Refer to Table 8, Read

Protection Register.

Flash Reset/Power-Down (RPF). The Reset/

Power-Down input provides hardware reset of the

Flash memory, and/or Power-Down functions, de-

pending on the Flash Configuration Register sta-

tus. Reset or Power-Down of the memory is

achieved by pulling RPF to V for at least t

.

IL

PLPH

The Reset/Power-Down function is set in the Con-

figuration Register (see Set Configuration Regis-

ter Command). If it is set to ‘0’ the Reset function

is enabled, if it is set to ‘1’ the Power-Down func-

tion is enabled. After a Reset or Power-Up the

power save function is disabled and all blocks are

locked.

The memory Command Interface is reset on Pow-

er Up to Read Array. Either Chip Enable or Write

Enable must be tied to V during Power Up to al-

IH

The input is data to be programmed in the Flash or

SRAM memory array or a command to be written

to the C.I. of the Flash memory. Both are latched

on the rising edge of Flash Write Enable (WF) and,

SRAM Chip Enable lines (ES) or Write Enable

(WS). The output is data from the Flash memory

array or SRAM array, the Electronic Signature

Manufacturer or Device codes, the Block Protec-

tion status, the Configuration Register status or

the Status Register Data (Polling bit DQ7, Toggle

bits DQ6 and DQ2, Error bit DQ5 or Erase Timer

bit DQ3) depending on the address. Outputs are

valid when Flash Chip Enable (EF) and Output En-

able (GF) or SRAM Chip Enable lines (ES) and

Output Enable (GS) are active.

low maximum security and the possibility to write a

command on the first rising edge of Write Enable.

After a Reset, when the device is in Read, Erase

Suspend Read or Standby, valid data will be out-

put t

after the rising edge of RPF. If the de-

PHQ7V1

vice is in Erase or Program, the operation will be

aborted and the reset recovery will take a maxi-

mum of t

set/Power-Down t

. The memory will recover from Re-

PLQ7V

after the rising edge of

PHQ7V2

RPF. See Tables 18 and 19, and Figure 12.

V

Supply Voltage (1.65V to 2.2V). V

pro-

DDF

vides the power supply to the internal core and I/O

pins of the memory device. It is the main power

supply for all operations (read, program and

erase).

The output is high impedance when both the Flash

chip and the SRAM chip are deselected or the out-

V

PPF

Programming Voltage (11.4V to 12.6V).

puts are disabled and when Reset (RPF) is at V .

V

provides a high voltage power supply for fast

IL

PPF

factory programming. V

Double Word and Quadruple Word Program com-

mands.

is required to use the

PPF

Flash Chip Enable (EF). The Chip Enable input

activates the Flash memory control logic, input

buffers, decoders and sense amplifiers. When

Chip Enable is at V the memory is deselected

V

Ground. V

ground is the reference for

SSF

IH

SSF

and the power consumption is reduced to the

standby level.

the core supply. It must be connected to the sys-

tem ground.

Flash Output Enable (GF). gates the outputs

through the data buffers during a read operation.

SRAM Chip Enable (ES). The Chip Enable in-

puts for SRAM activate the memory control logic,

input buffers and decoders. ES at V deselects

IH

8/52

M36DR432AD, M36DR432BD

the memory and reduces the power consumption

to the standby level. ES can also be used to con-

trol writing to the SRAM memory array, while WS

SRAM Upper Byte Enable (UBS). Enables the

upper bytes for SRAM (DQ8-DQ15). UBS is active

Low.

remains at V . It is not allowed to set EF at V and

IL

SRAM Lower Byte Enable (LBS). Enables the

lower bytes for SRAM (DQ0-DQ7). LBS is active

Low.

ES at V at the same time.

IL

SRAM Write Enable (WS). The Write Enable in-

put controls writing to the SRAM memory array.

WS is active Low.

V

Supply Voltage (1.65V to 2.2V). V

is the

DDS

SRAM power supply for all operations.

Note: Each device in a system should have

and V decoupled with a 0.1µF capaci-

SRAM Output Enable (GS). The Output Enable

gates the outputs through the data buffers during

a read operation of the SRAM chip. GS is active

Low.

V

DDF

PPF

tor close to the pin. See Figure 7, AC Measure-

ment Load Circuit. The PCB trace widths

should be sufficient to carry the required V

program and erase currents.

PPF

9/52

M36DR432AD, M36DR432BD

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate

power supplies and grounds and are distinguished

by three chip enable inputs: EF for the Flash mem-

ory and ES (E1S and E2S, respectively) for the

SRAM.

Figure 4. Functional Block Diagram

V

PPF

DDF

EF

GF

WF

Flash Memory

32 Mbit (2Mb x 16)

RPF

WPF

A18-A20

A0-A17

V

SSF

V

DQ0-DQ15

DDS

E1S

E2S

GS

SRAM

4 Mbit (256Kb x 16)

WS

UBS

LBS

V

SSS

AI07310b

10/52

M36DR432AD, M36DR432BD

Table 2. Main Operation Modes

(1)

Operation Mode

Read

EF

GF

WF

RPF

WPF

ES

GS WS

DQ15-DQ0

Data Output

Data Input

Hi-Z

UBS, LBS

V

IL

V

IH

V

IH

SRAM must be disabled

Any SRAM mode is allowed

IL

IH

V

IL

V

IL

V

IH

V

IH

Page Read

Write

IH

V

IL

V

IH

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

Standby

X

Reset/

Power-Down

V

IL

V

IH

X

Any SRAM mode is allowed

Hi-Z

V

IH

V

IH

V

IH

Output Disable

Read

IL

IH

Data out

Word Read

V

IL

V

IL

V

IH

V

Flash must be disabled

IL

Data in Word

Write

V

IL

V

IL

V

Write

IH

V

X

Hi-Z

IH

Standby/Power

Down

Any Flash mode is allowable

V

IH

X

V

X

IH

Data Retention

Output Disable

Any Flash mode is allowable

V

IH

X

V

IH

X

IL

IH

Note: 1. X = Don’t care (V or V ).

IL

IH

2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.

11/52

M36DR432AD, M36DR432BD

FLASH MEMORY COMPONENT

The Flash Memory is a 32 Mbit (2Mbit x16) non-

volatile Flash memory that may be erased electri-

cally at block level and programmed in-system on

Program and Erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

a Word-by-Word basis using a 1.65V to 2.2V V

DDF

supply for the circuitry and a 1.65V to 2.2V V

DDQF

supply for the Input/Output pins (in the stacked de-

vice, V and V are tied internally). An op-

DDF

DDQF

tional 12V V

power supply is provided to speed

PPF

up customer programming.

The Flash device features an asymmetrical block

architecture with an array of 71 blocks divided into

two banks, Banks A and B, providing Dual Bank

operations. While programming or erasing in Bank

A, read operations are possible in Bank B or vice

versa. Only one bank at a time is allowed to be in

program or erase mode. The bank architecture is

summarized in Table 3, and the Block Addresses

are shown in Appendix A. The Parameter Blocks

are located at the top of the memory address

space for the M36DR432AD and, at the bottom for

the M36DR432BD.

Each block can be erased separately. Erase can

be suspended, in order to perform either read or

program in any other block, and then resumed.

Each block can be programmed and erased over

100,000 cycles.

The Flash memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have two

levels of protection. They can be individually

locked and locked-down preventing any acciden-

tal programming or erasure. All blocks are locked

at Power Up and Reset.

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system’s design. The Protection Register is di-

vided into two 64 bit segments. The first segment

contains a unique device number written by ST,

while the second one is one-time-programmable

by the user. The user programmable segment can

be permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 5, shows the Flash Security Block

and Protection Register Memory Map.

Table 3. Flash Bank Architecture

Bank Size

Parameter Blocks

Main Blocks

Bank A

Bank B

4 Mbits

8 blocks of 4 KWords

-

7 blocks of 32 KWords

56 blocks of 32 KWords

28 Mbits

12/52

M36DR432AD, M36DR432BD

Figure 5. Flash Security Block and Protection Register Memory Map

PROTECTION REGISTER

User Programmable OTP

88h

SECURITY BLOCK

Parameter Block # 0

85h

84h

Unique device number

81h

80h

Protection Register Lock

2

1

0

AI06185

Flash Bus Operations

Flash Output Disable. The data outputs are high

impedance when the Output Enable GF is at V

IH

The following operations can be performed using

the appropriate bus cycles: Flash Read Array

(Random and Page Modes), Flash Write, Flash

Output Disable, Flash Standby and Flash Reset/

Power-Down, see Table 2, Main Operation

Modes.

Flash Read. Flash Read operations are used to

output the contents of the Memory Array, the Elec-

tronic Signature, the Status Register, the CFI, the

Block Protection Status or the Configuration Reg-

ister status. Read operation of the Flash memory

array is performed in asynchronous page mode,

that provides fast access time. Data is internally

read and stored in a page buffer. The page has a

size of 4 words and is addressed by A0-A1 ad-

dress inputs. Read operations of the Electronic

Signature, the Status Register, the CFI, the Block

Protection Status, the Configuration Register sta-

tus and the Security Code are performed as single

asynchronous read cycles (Random Read). Both

Flash Chip Enable EF and Flash Output Enable

with Write Enable WF at V .

IH

Flash Standby. The memory is in standby when

Chip Enable EF is at V and the P/E.C. is idle.

IH

The power consumption is reduced to the standby

level and the outputs are high impedance, inde-

pendent of the Output Enable GF or Write Enable

WF inputs.

Automatic Flash Standby. In Read mode, after

150ns of bus inactivity and when CMOS levels are

driving the addresses, the chip automatically en-

ters a pseudo-standby mode where consumption

is reduced to the CMOS standby value, while out-

puts still drive the bus.

Flash Power-Down. The memory is in Power-

Down when the Configuration Register is set for/

Power-Down and RPF is at V . The power con-

IL

sumption is reduced to the Power-Down level, and

Outputs are high impedance, independent of the

Chip Enable EF, Output Enable GF or Write En-

able WF inputs.

Dual Bank Operations. The Dual Bank allows

data to be read from one bank of memory while a

program or erase operation is in progress in the

other bank of the memory. Read and Write cycles

can be initiated for simultaneous operations in dif-

ferent banks without any delay. Status Register

during Program or Erase must be monitored using

an address within the bank being modified.

GF must be at V in order to read the output of the

IL

memory.

Flash Write. Write operations are used to give

commands to the memory or to latch Input Data to

be programmed. A write operation is initiated

when Chip Enable EF and Write Enable WF are at

V

with Output Enable GF at V . Addresses are

IL

IH

latched on the falling edge of WF or EF whichever

occurs last. Commands and Input Data are

latched on the rising edge of WF or EF whichever

occurs first. Noise pulses of less than 5ns typical

on EF, WF and GF signals do not start a write cy-

cle.

Flash Command Interface

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

13/52

M36DR432AD, M36DR432BD

dles all timings and verifies the correct execution

of the Program and Erase commands. Two bus

write cycles are required to unlock the Command

Interface. They are followed by a setup or confirm

cycle. The increased number of write cycles is to

ensure maximum data security.

address bits are ignored. Address input A10 de-

fines the status of the Reset/Power-Down func-

tions. If it is set to ‘0’ the Reset function is enabled,

if it is set to ‘1’ the Power-Down function is en-

abled. At Power Up the Configuration Register bit

is set to ‘0’.

The Program/Erase Controller provides a Status

Register whose output may be read at any time to

monitor the progress or the result of the operation.

The Command Interface is reset to Read mode

when power is first applied or exiting from Reset.

Command sequences must be followed exactly.

Any invalid combination of commands will reset

the device to Read mode

Flash Read/Reset Command. The Read/Reset

command returns the device to Read mode. One

Bus Write cycle is required to issue the Read/Re-

set command and return the device to Read mode.

Subsequent Read operations will read the ad-

dressed location and output the data. The write cy-

cle can be preceded by the unlock cycles but it is

not mandatory.

The Set Configuration Register command is used

to write a new value to the Configuration Register.

The command uses the two unlock cycles followed

by one write cycle to setup the command and a

further write cycle to write the data and confirm the

command.

Program Command. The Program command

uses the two unlock cycles followed by a write cy-

cle to setup the command and a further write cycle

to latch the Address and Data and start the Pro-

gram Erase Controller. Read operations within the

same bank output the Status Register after pro-

gramming has started.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole bank from ’0’ to ’1’. If the Program

command is used to try to set a bit from ‘0’ to ‘1’

Status Register Error bit DQ5 will be set to ‘1’, only

Flash Read CFI Query Command. The

Read

CFI Query command is used to read data from the

Common Flash Interface (CFI) and the Electronic

Signature (Manufacturer or the Device Code, see

Table 5). The Read CFI Query Command consists

of one Bus Write cycle. Once the command is is-

sued the device enters Read CFI mode. Subse-

quent Bus Read operations read the Common

Flash Interface or Electronic Signature. Once the

device has entered Read CFI mode, only the

Read/Reset command should be used and no oth-

er. Issuing the Read/Reset command returns the

device to Read mode.

if V

is in the range of 11.4V to 12.6V.

PPF

Double Word Program Command. This feature

is offered to improve the programming throughput

by writing a page of two adjacent words in parallel.

The V

supply voltage is required to be from

PPF

11.4V to 12.6V for the Double Word Program com-

mand.

The command uses the two unlock cycles followed

by a write cycle to setup the command. A further

two cycles are required to latch the address and

data of the two Words and start the Program Erase

Controller.

The addresses must be the same except for the

A0. The Double Word Program command can be

executed in Bypass mode to skip the two unlock

cycles.

See Appendix B, Common Flash Interface, Tables

33, 34, and 35 for details on the information con-

tained in the Common Flash Interface memory ar-

ea.

Auto Select Command. The Auto Select com-

mand uses the two unlock cycles followed by one

write cycle to any bank address to setup the com-

mand. Subsequent reads at any address will out-

put the Block Protection status, Protection

Register and Protection Register Lock or the Con-

figuration Register status depending on the levels

of A0 and A1 (see Tables 6, 7 and 8). Once the

Auto Select command has been issued only the

Read/Reset command should be used and no oth-

er. Issuing the Read/Reset command returns the

device to Read mode.

Set Configuration Register Command. The

Flash component contains a Configuration Regis-

ter, see Table 7, Configuration Register.

It is used to define the status of the Reset/Power-

Down functions. The value for the Configuration

Register is always presented on A0-A15, the other

Note that the Double Word Program command

cannot change a bit set at ’0’ back to ’1’. One of the

Erase Commands must be used to set all the bits

in a block or in the whole bank from ’0’ to ’1’. If the

Double Word Program command is used to try to

set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5

will be set to ‘1’.

Quadruple Word Program Command. The

Quadruple Word Program command improves the

programming throughput by writing a page of four

adjacent words in parallel. The four words must

differ only for the addresses A0 and A1. The V

PPF

supply voltage is required to be from 11.4V to

12.6V for the Quadruple Word Program com-

mand.

14/52

M36DR432AD, M36DR432BD

The command uses the two unlock cycles followed

by a write cycle to setup the command. A further

four cycles are required to latch the address and

data of the four Words and start the Program

Erase Controller.

The Quadruple Word Program command can be

executed in Bypass mode to skip the two unlock

cycles.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Block Lock

command and latches the block address.

The lock status can be monitored for each block

using the Auto Select command. Table 10 shows

the Lock Status after issuing a Block Lock com-

mand.

Note that the Quadruple Word Program command

cannot change a bit set to ’0’ back to ’1’. One of the

Erase Commands must be used to set all the bits

in a block or in the whole bank from ’0’ to ’1’. If the

Quadruple Word Program command is used to try

to set a bit from ‘0’ to ‘1’ Status Register Error bit

DQ5 will be set to ‘1’.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation.

Block Unlock Command. The Blocks Unlock

command is used to unlock a block, allowing the

block to be programmed or erased.

Three Bus Write cycles are required to issue the

Blocks Unlock command.

Enter Bypass Mode Command. The

Bypass

mode is used to reduce the overall programming

time when large memory arrays need to be pro-

grammed.

The Enter Bypass Mode command uses the two

unlock cycles followed by one write cycle to set up

the command. Once in Bypass mode, it is impera-

tive that only the following commands be issued:

Exit Bypass, Program, Double Word Program or

Quadruple Word Program.

Exit Bypass Mode Command. The Exit Bypass

Mode command uses two write cycles to setup

and confirm the command. The unlock cycles are

not required. After the Exit Bypass Mode com-

mand, the device resets to Read mode.

Program in Bypass Mode Command. The

Program in Bypass Mode command can be is-

sued when the device is in Bypass mode (issue a

Enter Bypass Mode command). It uses the same

sequence of cycles as the Program command with

the exception of the unlock cycles.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Block UnLock

command and latches the block address.

The lock status can be monitored for each block

using the Auto Select command. Table 10 shows

the lock status after issuing a Block Unlock com-

mand. Refer to the section, Block Locking, for a

detailed explanation.

Block Lock-Down Command. A locked or un-

locked block can be locked-down by issuing the

Block Lock-Down command. A locked-down block

cannot be programmed or erased, or have its pro-

tection status changed when WPF is Low, V .

IL

When WPF is High, V the Lock-Down function is

IH,

disabled and the locked blocks can be individually

unlocked by the Block Unlock command.

Three Bus Write cycles are required to issue the

Block Lock-Down command.

■ The first two bus cycles unlock the Command

Double Word Program in Bypass Mode Com-

mand. The Double Word Program in Bypass

Mode command can be issued when the device is

in Bypass mode (issue a Enter Bypass Mode com-

mand). It uses the same sequence of cycles as the

Double Word Program command with the excep-

tion of the unlock cycles.

Quadruple Word Program in Bypass Mode

Command. The Quadruple Word Program in By-

pass Mode command can be issued when the de-

vice is in Bypass mode (issue a Enter Bypass

Mode command). It uses the same sequence of

cycles as the Quadruple Word Program command

with the exception of the unlock cycles.

Interface.

■ The third bus cycle sets up the Block Lock-

Down command and latches the block address.

The lock status can be monitored for each block

using the Auto Select command. Locked-Down

blocks revert to the locked (and not locked-down)

state when the device is reset on power-down. Ta-

ble 10 shows the Lock Status after issuing a Block

Lock-Down command. Refer to the section, Block

Locking, for a detailed explanation.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all the

bits within the selected block to ’1’. All previous

data in the block is lost. If the block is protected

then the Erase operation will abort, the data in the

block will not be changed and the device will return

to Read Array mode. It is not necessary to pre-pro-

Block Lock Command. The Block Lock com-

mand is used to lock a block and prevent Program

or Erase operations from changing the data in it.

All blocks are locked at power-up or reset.

Three Bus Write cycles are required to issue the

Block Lock command.

15/52

M36DR432AD, M36DR432BD

gram the block as the Program/Erase Controller

does it automatically before erasing.

On successful completion of the Bank Erase com-

mand, the device returns to Read Array mode.

Six Bus Write cycles are required to issue the

command.

■ The first two write cycles unlock the Command

Erase Suspend Command. The Erase Suspend

command is used to pause a Block Erase opera-

tion. In a Dual Bank memory it can be used to read

data within the bank where an Erase operation is

in progress. It is also possible to program data in

blocks not being erased.

Interface.

■ The third write cycles sets up the command

■ the fourth and fifth write cycles repeat the unlock

One bus write cycle is required to issue the Erase

Suspend command. The Program/Erase Control-

ler suspends the Erase operation within 20µs of

the Erase Suspend command being issued and

bits 7, 6 and/ or 2 of the Status Register are set to

‘1’. The device is then automatically set to Read

mode. The command can be addressed to any

bank.

sequence

■ the sixth write cycle latches the block address

and confirms the command.

Additional Block Erase confirm cycles can be is-

sued to erase other blocks without further unlock

cycles. All blocks must belong to the same bank; if

a new block belonging to the other bank is given,

the operation is aborted.

The additional Block Erase confirm cycles must be

given within the DQ3 erase timeout period. Each

time a new confirm cycle is issued the timeout pe-

riod restarts. The status of the internal timer can

be monitored through the level of DQ3, see Status

Register section for more details.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read.

After the command has been issued the Flash

Read/Reset command will be accepted during the

DQ3 timeout period, after that only the Erase Sus-

pend command will be accepted.

During Erase Suspend the memory will accept the

Erase Resume, Program, Read CFI Query, Auto

Select, Block Lock, Block Unlock and Block Lock-

Down commands.

Erase Resume Command. The Erase Resume

command can be used to restart the Program/

Erase Controller after an Erase Suspend com-

mand has paused it. One Bus Write cycle is re-

quired to issue the command. The command must

be issued to an address within the bank being

erased. The unlock cycles are not required.

Protection Register Program Command. The

Protection Register Program command is used to

Program the Protection Register (One-Time-Pro-

grammable (OTP) segment and Protection Regis-

ter Lock). The OTP segment is programmed 16

bits at a time. When shipped all bits in the segment

are set to ‘1’. The user can only program the bits

to ‘0’.

On successful completion of the Block Erase com-

mand, the device returns to Read Array mode.

Bank Erase Command. The Bank Erase com-

mand can be used to erase a bank. It sets all the

bits within the selected bank to ’1’. All previous

data in the bank is lost. The Bank Erase command

will ignore any protected blocks within the bank. If

all blocks in the bank are protected then the Bank

Erase operation will abort and the data in the bank

will not be changed. It is not necessary to pre-pro-

gram the bank as the Program/Erase Controller

does it automatically before erasing.

Four write cycles are required to issue the Protec-

tion Register Program command.

■ The first two bus cycles unlock the Command

Interface.

■ The third bus cycle sets up the Protection

Register Program command.

■ The fourth latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

As for the Block Erase command six Bus Write cy-

cles are required to issue the command.

■ The first two write cycles unlock the Command

Read operations output the Status Register con-

tent after the programming has started.

Interface.

■ The third write cycles sets up the command

The OTP segment can be protected by program-

ming bit 1 of the Protection Register Lock. The

segment can be protected by programming bit 1 of

the Protection Register Lock. Bit 1 of the Protec-

tion Register Lock also protects bit 2 of the Protec-

tion Register Lock. Programming bit 2 of the

Protection Register Lock will result in a permanent

protection of Parameter Block #0 (see Figure 5,

Flash Security Block and Protection Register

Memory Map). Attempting to program a previously

■ the fourth and fifth write cycles repeat the unlock

sequence

■ the sixth write cycle latches the block address

and confirms the command.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read.

16/52

M36DR432AD, M36DR432BD

protected Protection Register will result in a Status

Register error. The protection of the Protection

Register and/or the Security Block is not revers-

ible.

Table 4. Flash Commands

Bus Operations

3rd 4th

1st

2nd

5th

6th

7th

Commands

Add Data Add Data Add Data Add Data Add Data Add Data Add Data

1+

X

F0h

Read Memory Array until a new write cycle is initiated.

Read/Reset

CFI Query

3+ 555h AAh 2AAh 55h 555h F0h Read Memory Array until a new write cycle is initiated.

1+ 55h 98h

Read CFI and Electronic Signature until a Read/Reset command is issued.

Read Protection Register, Block Protection or

Auto Select

3+ 555h AAh 2AAh 55h 555h 90h

Configuration Register Status until a Read/Reset

command is issued.

Set Configuration

Register

4 555h AAh 2AAh 55h 555h 60h CRD 03h

4 555h AAh 2AAh 55h 555h A0h PA PD

Read Data Polling or Toggle Bit until

Program completes.

Program

Double Word

Program

5 555h AAh 2AAh 55h 555h 40h PA1 PD1 PA2 PD2

5 555h AAh 2AAh 55h 555h 50h PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4

3 555h AAh 2AAh 55h 555h 20h

Quadruple Word

Program

Enter Bypass

Mode

Exit Bypass

Mode

2

X

90h

A0h

X

00h

PD

Program in

Bypass Mode

PA

Read Data Polling or Toggle Bit until Program completes.

Double Word

Program in

Bypass Mode

3

X

40h PA1 PD1 PA2 PD2

Quadruple Word

Program in

50h PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4

Bypass Mode

Block Lock

4 555h AAh 2AAh 55h 555h 60h

BA

01h

D0h

2Fh

Block Unlock

Block Lock-Down 4 555h AAh 2AAh 55h 555h 60h

Block Erase

Bank Erase

6+ 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h

6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h

BA

30h

10h

Read until Toggle stops, then read all the data needed from any Blocks not being

erased then Resume Erase.

Erase Suspend

Erase Resume

1

X

B0h

30h

Read Data Polling or Toggle Bits until Erase completes or Erase is suspended

another time

BA

Protection

Register Program

4 555h AAh 2AAh 55h

PA

C0h

PA

PD

Note: X = Don’t Care, BA = Block Address, PA = Program address, PD = Program Data, CRD = Configuration Register Data. For Coded

cycles address inputs A12-A20 are don’t care.

17/52

M36DR432AD, M36DR432BD

Table 5. Read Electronic Signature

Code

Device

EF

GF

WF

A0

A1

A7-A2 A8-A20 DQ15-DQ0

V

Manufacturer Code

0

X

0020h

00A0h

00A1h

IL

IH

IL

V

IL

V

IH

V

IL

M36DR432AD

M36DR432BD

IL

IH

Device Code

V

IL

V

IH

V

IL

IH

Note: X = Don’t care.

Table 6. Flash Read Block Protection

Other

Addresses

Block Status

EF GF WF A0 A1

A20-A12

A7-A2

DQ0 DQ1 DQ15-DQ2

V

Locked Block

Block Address

0

X

1

0

0000h

IL

IH

IL

IH

Unlocked Block

IH

IL

IH

Locked-Down

Block

V

IH

V

IL

V

IH

Block Address

0

X

1

0000h

IL

Note: X = Don’t care.

Table 7. Configuration Register

DQ9-DQ0

DQ15-DQ11

RPF Function

Reset

EF

GF

WF

A0

A1 A7-A2 Other Addresses

DQ10

V

IL

V

IL

V

0

X

0

1

Don’t Care

IH

V

IL

V

IL

V

Reset/Power-Down

Note: X = Don’t care.

IH

18/52

M36DR432AD, M36DR432BD

Table 8. Read Protection Register

Word

EF GF WF

A20-A8

A7-0

DQ15-8

DQ7-3

DQ2

DQ1

DQ0

Security

prot.data

OTP

prot.data

V

IL

V

IL

V

IH

Lock

X

80h

XXh

00000b

0

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

X

81h

82h

83h

84h

85h

86h

87h

88h

ID data

OTP data OTP data OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

Note: X= Don’t care.

Table 9. Program, Erase Times and Program, Erase Endurance Cycles

M36DR432AD, M36DR432BD

Parameter

Unit

Typical after

100k W/E Cycles

Min

Max

Typ

Parameter Block (4 KWord) Erase (Preprogrammed)

Main Block (32 KWord) Erase (Preprogrammed)

Bank Erase (Preprogrammed, Bank A)

2.5

4

0.3

0.8

3

1

3

s

6

Bank Erase (Preprogrammed, Bank B)

20

30

25

(1)

Chip Program

(1)

8

s

Chip Program (Double Word, V

= 12V)

PPF

(2)

100

10

8

µs

Word Program

Double Word Program (V

= 12V)

µs

PPF

Quadruple Word Program (V

= 12V)

8

PPF

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Excludes the time needed to execute the sequence for program command.

2. Same timing value if V

= 12V

PPF

Flash Block Locking

The protection status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 10, de-

fines all of the possible protection states (WPF,

DQ1, DQ0).

The Flash memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has two levels of protection.

Reading a Block’s Lock Status

■ Lock/Unlock - this first level allows software-

The lock status of every block can be read in the

Auto Select mode of the device. Subsequent

reads at the address specified in Table 6, will out-

put the protection status of that block. The lock

status is represented by DQ0 and DQ1. DQ0 indi-

cates the Block Lock/Unlock status and is set by

the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

19/52

M36DR432AD, M36DR432BD

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

The following sections explain the operation of the

locking system.

The Lock-Down function is dependent on the WPF

input pin. When WPF=0 (V ), the blocks in the

IL

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

WPF=1 (V ) the Lock-Down function is disabled

IH

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be re-locked

(1,1,1) and unlocked (1,1,0) as desired while WPF

remains High. When WPF is Low, blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WPF was High. Device reset or power-down

resets all blocks, including those in Lock-Down, to

the Locked state.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will reset the

device to Read Array mode. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their protection status can-

not be changed using software commands alone.

A Locked or Unlocked block can be Locked-Down

by issuing the Lock-Down command. Locked-

Down blocks revert to the Locked state when the

device is reset or powered-down.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

20/52

M36DR432AD, M36DR432BD

Table 10. Flash Lock Status

Current

(1)

Next Protection Status

(WPF, DQ1, DQ0)

(1)

Protection Status

(WPF, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Current State

After

WPF transition

Allowed

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Auto Select command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.

3. A WPF transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

Flash Status Register

provided. DQ7 will output ’1’ if the read is attempt-

ed on a block being erased and the data value on

other blocks. During a program operation in Erase

Suspend, DQ7 will have the same behavior as in

the normal program.

Toggle Bit (DQ6). When Program or Erase oper-

ations are in progress, successive attempts to

read DQ6 will output complementary data. DQ6

will toggle following the toggling of either GF or EF.

The operation is completed when two successive

reads give the same output data. The next read

will output the bit last programmed or a ’1’ after

erasing.

The Status Register provides information on the

current or previous Program or Erase operations.

Bus Read operations from any address within the

bank, always read the Status Register during Pro-

gram and Erase operations.

The various bits convey information about the sta-

tus and any errors of the operation.

The bits in the Status Register are summarized in

Table 12, Status Register Bits. Refer to Tables 11

and 12 in conjunction with the following text de-

scriptions.

Data Polling Bit (DQ7). When Program opera-

tions are in progress, the Data Polling bit outputs

the complement of the bit being programmed on

DQ7. For a Double Word Program operation, it is

the complement of DQ7 for the last Word written to

the Command Interface.

During an Erase operation, it outputs a ’0’. After

completion of the operation, DQ7 will output the bit

last programmed or a ’1’ after erasing.

Data Polling is valid and only effective during P/

E.C. operation, that is after the fourth WF pulse for

programming or after the sixth WF pulse for erase.

It must be performed at the address being pro-

grammed or at an address within the block being

erased. See Figure 22 for the Data Polling flow-

chart and Figure 13 for the Data Polling wave-

forms.

DQ7 will also flag an Erase Suspend by switching

from ’0’ to ’1’ at the start of the Erase Suspend. In

order to monitor DQ7 in the Erase Suspend mode

an address within a block being erased must be

The Toggle Bit DQ6 is valid only during P/E.C. op-

erations, that is after the fourth WF pulse for pro-

gramming or after the sixth WF pulse for Erase.

DQ6 will be set to ’1’ if a read operation is attempt-

ed on an Erase Suspend block. When erase is

suspended DQ6 will toggle during programming

operations in a block different from the block in

Erase Suspend.

See Figure 16 for Toggle Bit flowchart and Figure

14 for Toggle Bit waveforms.

Toggle Bit (DQ2). Toggle Bit DQ2, together with

DQ6, can be used to determine the device status

during erase operations.

During Erase Suspend a read from a block being

erased will cause DQ2 to toggle. A read from a

block not being erased will output data. DQ2 will

be set to '1' during program operation and to ‘0’ in

erase operation. If a read operation is addressed

to a block where an erase error has occurred, DQ2

will toggle.

21/52

M36DR432AD, M36DR432BD

Error Bit (DQ5). The Error Bit can be used to

identify if an error occurs during a program or

erase operation.

DQ0, DQ1 and DQ4 are reserved for future use

and should be masked.

The Error Bit is set to ‘1’ when a program or erase

operation has failed. When it is set to ‘0’ the pro-

gram or erase operation was successful.

If any Program command is used to try to set a bit

from ‘0’ to ‘1’ Status Register Error bit DQ5 will be

Table 11. Polling and Toggle Bits

Mode

DQ7

0

DQ6

DQ2

1

Program

Erase

Toggle

set to ‘1’, only if V is in the range of 11.4V to

PP

N/A

12.6V.

Erase Suspend Read

(in Erase Suspend

block)

The Error Bit is reset by a Read/Reset command.

1

Toggle

Erase Timer Bit (DQ3). The Erase Timer bit is

used to indicate the timeout period for an erase

operation.

When the last block Erase command has been en-

tered to the Command Interface and it is waiting

for the erase operation to start, the Erase Timer Bit

is set to ‘0’. When the erase timeout period is fin-

ished, DQ3 returns to ‘1’, (80µs to 120µs).

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

1

Erase Suspend Program

Toggle

22/52

M36DR432AD, M36DR432BD

Table 12. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase complete or erase block

in Erase Suspend.

’1’

’0’

Indicates the P/E.C. status, check

during Program or Erase, and on

completion before checking bits DQ5

for Program or Erase success.

Erase in progress

Data

Polling

7

Program complete or data of

non erase block during Erase

Suspend.

DQ

(2)

DQ

’-1-0-1-0-1-0-1-’

DQ

Program in progress

Erase or Program in progress

Program complete

Successive reads output

complementary data on DQ6 while

Programming or Erase operations are

in progress. DQ6 remains at constant

level when P/E.C. operations are

completed or Erase Suspend is

acknowledged.

6

Toggle Bit

Erase complete or Erase

Suspend on currently addressed

block

’-1-1-1-1-1-1-1-’

’1’

’0’

Program or Erase Error

This bit is set to ’1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase in progress

Reserved

P/E.C. Erase operation has started.

Only possible command entry is Erase

Suspend

’1’

’0’

Erase Timeout Period Expired

Erase Time

Bit

3

An additional block to be erased in

parallel can be entered to the P/E.C

provided that it belongs to the same

bank

Erase Timeout Period in

progress

Erase Suspend read in the

Erase Suspended Block.

Erase Error due to the currently

addressed block (when DQ5 =

’1’).

’-1-0-1-0-1-0-1-’

Indicates the erase status and allows

to identify the erased block.

2

Toggle Bit

Program in progress or Erase

complete.

1

Erase Suspend read on non

Erase Suspend block.

DQ

1

0

Reserved

Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations.

2. In case of double word program DQ7 refers to the last word input.

23/52

M36DR432AD, M36DR432BD

SRAM COMPONENT

The SRAM is a 4 Mbit (256Kb x16) low-power con-

among ES going to V and WS going to V .

IL IL

sumption memory array with low V

tion.

data reten-

Therefore, address setup time is referenced to

Write Enable and Chip Enable as t and t

DDS

AVWL

AVEL

respectively, and is determined by the latter occur-

ring edge. The Write cycle can be terminated by

the rising edge of ES or the rising edge of WS,

whichever occurs first.

SRAM Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write Ar-

ray, Output Disable, Power Down (see Table 2).

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable (WS) is at V with

Output Enable (GS) at V , Chip Enable ES and

UBS, LBS combinations are asserted.

Valid data will be available at the output pins within

If the Output is enabled (ES=V and GS=V ),

IL

then WS will return the outputs to high impedance

within t of its falling edge. Care must be taken

WLQZ

IH

to avoid bus contention in this type of operation.

Data input must be valid for t before the ris-

IL

DVWH

ing edge of Write Enable, or for t

before the

DVEH

rising edge of ES, whichever occurs first, and re-

t

after the last stable address, provided that

main valid for t and t (see Table 24, Fig-

AVQV

WHDX

EHAX

GS is Low and ES is Low. If Chip Enable or Output

Enable access times are not met, data access will

be measured from the limiting parameter (t

ure 20, 22, 24).

Standby/Power-Down. The SRAM chip has a

Chip Enable power-down feature which invokes

an automatic standby mode (see Table 23, Figure

19) whenever either Chip Enable is de-asserted

or

ELQV

t

) rather than the address. Data out may be

GLQV

indeterminate at t

and t

AVQV

, but data lines

(see Table 23, Figures

ELQX

GLQX

will always be valid at t

17 and 18).

Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever

the WS and ES pins are at V . Either the Chip En-

able input (ES) or the Write Enable input (WS)

must be de-asserted during address transitions for

subsequent write cycles. Write begins with the

concurrence of Chip Enable being active and WS

(ES=V ).

IH

Data Retention. The SRAM data retention per-

formances as V

go down to V are described

DDS

DR

in Table 25 and Figure 24. In ES controlled data

retention mode, minimum standby current mode is

IL

entered when ES ≥ V

– 0.2V.

DDS

Output Disable. The data outputs are high im-

pedance when the Output Enable (GS) is at V

IH

with Write Enable (WS) at V .

IH

at V . A Write begins at the latest transition

IL

24/52

M36DR432AD, M36DR432BD

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

(1)

Table 13. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

(3)

T

A

–40 to 85

–40 to 125

Ambient Operating Temperature

T

BIAS

Temperature Under Bias

Storage Temperature

°C

T

–55 to 150

°C

STG

(2)

(3)

Input or Output Voltage

Supply Voltage

V

–0.5 to V

+0.5

IO

DD

V

–0.5 to 2.7

–0.5 to 2.4

–0.5 to 13

DDF

V

SRAM Chip Supply Voltage

Program Voltage

DDS

V

PPF

Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns.

2. Depends on range.

3. V = V

= V

.

DD

DDS

DDF

25/52

M36DR432AD, M36DR432BD

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 14, Operating

and AC Measurement Conditions. Designers

should check that the operating conditions in their

circuit match the operating conditions when rely-

ing on the quoted parameters.

Table 14. Operating and AC Measurement Conditions

SRAM

Flash

70

85

100, 120

Parameter

Units

Min

-

Max

Min

1.8

-

Max

Min

Max

2.2

-

V

Supply Voltage

-

2.2

-

1.65

-

V

DDF

DDS

PPF

1.65

2.2

11.4

– 40

12.6

85

11.4

– 40

12.6

85

V

Ambient Operating Temperature

– 40

30

85

5

°C

pF

ns

V

Load Capacitance (C )

30

L

Input Rise and Fall Times

2

4

(1)

0 to V

DD

Input Pulse Voltages

(1)

V

DD

/2

V

DD

/2

V

DD

/2

V

Input and Output Timing Ref. Voltages

Note: 1. V = V

= V

DDF

DD

DDS

Figure 6. AC Measurement I/O Waveform

Figure 7. AC Measurement Load Circuit

VDD

V

DD

V

DD

V

/2

DD

25kΩ

0V

DEVICE

UNDER

TEST

AI90206

Note: V means V

= V

DDS

DD

DDF

25kΩ

0.1µF

C

L

= 50pF

AI90207

C

includes JIG capacitance

L

Note: V means V

= V

DDS

DD

DDF

Table 15. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

12

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

15

pF

Note: Sampled only, not 100% tested.

26/52

M36DR432AD, M36DR432BD

Table 16. Flash DC Characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V ≤ V ≤ V

Input Leakage Current

Output Leakage Current

LI

IN

DD

I

LO

0V ≤ V

≤ V

OUT DD

±5

µA

EF = V , GF = V , f =

Supply Current

(Read Mode)

IL

IH

I

3

6

mA

CC1

6MHz

Supply Current

(Power-Down)

I

RPF = V ± 0.2V

2

10

50

20

µA

CC2

SS

I

EF = V ± 0.2V

Supply Current (Standby)

10

CC3

DD

Supply Current

(Program or Erase)

Word Program, Block Erase

in progress

(1)

mA

I

CC4

Program/Erase in progress

in one Bank, Read in the

other Bank

Supply Current

(Dual Bank)

(1)

13

2

26

5

mA

I

CC5

V

Supply Current

PPF

I

V

= 12V ± 0.6V

PPF1

PPF2

PPF

(Program or Erase)

V

≤ V

0.2

5

µA

V

PPF

DD

V

Supply Current

PPF

I

(Standby or Read)

V

= 12V ± 0.6V

100

400

0.4

PPF

V

Input Low Voltage

Input High Voltage

Output Low Voltage

–0.5

IL

V

– 0.4

V

+ 0.4

DD

V

IH

DD

V

I

OL

= 100µA

0.1

V

OL

Output High Voltage

CMOS

V

OH

I

= –100µA

V

DD

–0.1

V

OH

V

+ 0.4

–0.4

11.4

V

DD

V

Supply Voltage

PPF

(2,3)

V

PPF

(Program or Erase)

Double Word Program

12.6

Note: 1. Sampled only, not 100% tested.

2. V may be connected to 12V power supply for a total of less than 100 hrs.

PPF

3. For standard program/erase operation V

is don’t care.

PPF

27/52

M36DR432AD, M36DR432BD

Table 17. SRAM DC Characteristics

(T = –40 to 85°C; V

= V

= 1.65V to 2.2V)

A

DDF

DDS

Symbol

Parameter

Test Condition

≤ V

output disabled

Min

-1

Typ

+1

Max

+1

Unit

µA

Output Leakage

Current

I

0V ≤ V

OUT

OZ

DDS,

I

IX

0V ≤ V ≤ V

IN DDS

Input Load Current

-1

±1

+1

µA

ES ≥ V

– 0.2V, V ≥ V

or V ≤ 0.2V, f=0

IN

– 0.2V

DDS

IN

DDS

V

Standby

Current

DD

I

1

10

7

µA

DDS

V

DDS

= 2.2V

I

= 0 mA, f = f

= 1/t , CMOS levels

= 2.2V

OUT

MAX

RC

4

1

mA

V

DDS

I

Supply Current

DD

I

= 0 mA, f = 0Hz

OUT

5

CMOS levels

V

= 1.65V

= 2.2V

Input Low Voltage

Input High Voltage

–0.5

1.4

0.4

V

IL

DDS

V

DDS

V

+0.2V

DDS

IH

= 1.65V

= 0.1µA

DDS

V

OL

Output Low Voltage

Output High Voltage

0.2

V

I

OL

V

= 1.65V

= –0.1µA

DDS

V

OH

1.4

I

OH

Note: 1. I

and I

DDWS

DDR.

are specified with device deselected. If device is read while in erase suspend, current draw is sum of I

DDES

and I

If the device is read while in program suspend, current draw is the sum of I

DDWS

and I .

DDR

2. V = V or V

IH

IN

IL

28/52

M36DR432AD, M36DR432BD

Figure 8. Flash Random Read AC Waveforms

29/52

M36DR432AD, M36DR432BD

Figure 9. Flash Page Read AC Waveforms

30/52

M36DR432AD, M36DR432BD

Table 18. Flash Read AC Characteristics

M36DR432AD, M36DR432BD

Symbol

Alt

Parameter

Test Condition

85

100

Max

120

Unit

Min Max Min

Min

Max

Address Valid to Next

Address Valid

(3)

100

85

t

EF = V , GF = V

120

ns

AVAV

RC

IL

Address Valid to

Output Valid (Random)

(3)

t

EF = V , GF = V

100

35

120

45

AVQV

ACC

IL

85

Address Valid to

Output Valid (Page)

(3)

t

EF = V , GF = V

AVQV1

PAGE

IL

30

Chip Enable Low to

Output Transition

(1)

t

GF = V

0

t

LZ

IL

ELQX

Chip Enable Low to

Output Valid

(2)

(3)

t

GF = V

100

25

120

35

t

CE

IL

85

25

20

ELQV

Output Enable Low to

Output Transition

(1)

t

EF = V

t

OLZ

IL

GLQX

Output Enable Low to

Output Valid

(2)

t

EF = V

t

OE

IL

GLQV

Chip Enable High to

Output Transition

t

GF = V

EHQX

OH

IL

Chip Enable High to

Output Hi-Z

(1)

t

GF = V

25

35

t

HZ

IL

EHQZ

Output Enable High to

Output Transition

t

EF = V

GHQX

OH

IL

Output Enable High to

Output Hi-Z

(1)

t

EF = V

25

35

t

DF

IL

GHQZ

Address Transition to

Output Transition

t

EF = V , GF = V

AXQX

OH

IL

Note: 1. Sampled only, not 100% tested.

2. GF may be delayed by up to t

3. To be characterized.

- t

after the falling edge of EF without increasing t

.

ELQV

ELQV GLQV

31/52

M36DR432AD, M36DR432BD

Figure 10. Flash Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20

VALID

tWLAX

tAVWL

tWHEH

EF

tELWL

tWHGL

GF

WF

tGHWL

tWLWH

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ15

V

DDF

tVDHEL

AI07314

Note: Addresses are latched on the falling edge of WF, Data is latched on the rising edge of WF.

Table 19. Flash Write AC Characteristics, Write Enable Controlled

M36DR432AD, M36DR432BD

100 120

Symbol

Alt

Parameter

85

Unit

Min

Max

Min

100

0

Max

Min

120

0

Max

(1)

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

ns

AVAV

85

t

CS

0

ELWL

(1)

t

50

WLWH

WP

50

(1)

t

Input Valid to Write Enable High

50

0

50

0

ns

µs

ns

DVWH

DS

DH

CH

40

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

0

WHDX

t

0

WHEH

t

WPH

30

0

30

0

30

0

WHWL

t

AVWL

AS

t

50

0

50

0

50

0

WLAX

AH

t

GHWL

t

V

DD

High to Chip Enable Low

50

30

50

30

50

30

VDHEL

VCS

t

Write Enable High to Output Enable Low

WHGL

OEH

RPF Low to Reset Complete During

Program/Erase

t

15

µs

PLQ7V

Note: 1. To be characterized.

32/52

M36DR432AD, M36DR432BD

Figure 11. Flash Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20

VALID

tELAX

tAVEL

tEHWH

tEHGL

WF

GF

EF

tWLEL

tGHEL

tELEH

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ15

V

DDF

tVDHWL

AI07315

Note: Addresses are latched on the falling edge of EF, Data is latched on the rising edge of EF.

Table 20. Flash Write AC Characteristics, Chip Enable Controlled

M36DR432AD, M36DR432BD

85 100 120

Symbol

Alt

Parameter

Unit

Min

Max

Min

100

0

Max

Min

120

0

Max

(1)

t

WC

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

ns

AVAV

85

t

WS

0

WLEL

(1)

t

50

ELEH

CP

50

(1)

t

Input Valid to Chip Enable High

50

0

50

0

ns

µs

ns

DVEH

DS

40

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

0

EHDX

DH

t

WH

0

EHWH

t

30

0

30

0

30

0

EHEL

CPH

t

AVEL

AS

t

AH

50

0

50

0

50

0

ELAX

t

GHEL

t

V

DD

High to Write Enable Low

50

30

50

30

50

30

VDHWL

VCS

t

Chip Enable High to Output Enable Low

EHGL

OEH

RPF Low to Reset Complete During

Program/Erase

t

15

µs

PLQ7V

Note: 1. To be characterized

33/52

M36DR432AD, M36DR432BD

Figure 12. Flash Reset/Power-Down AC Waveform

READ

PROGRAM / ERASE

WF

DQ7

RPF

DQ7

VALID

tPLPH

tPHQ7V

tPLQ7V

AI07316

Table 21. Flash Reset/Power-Down AC Characteristics

M36DR432AD, M36DR432BD

85 100 120

Max

Symbol Alt

Parameter

Test Condition

Unit

Min

Max

Min

Max

RPF High to Data Valid

(Read Mode)

t

150

50

150

ns

PHQ7V1

RPF High to Data Valid

(Reset/Power-Down

enabled)

t

50

µs

PHQ7V2

During Program

During Erase

10

20

10

20

10

20

µs

ns

RPF Low to Reset

Complete

t

PLQ7V

t

RP

RPF Pulse Width

50

PLPH

34/52

M36DR432AD, M36DR432BD

Figure 13. Flash Data Polling DQ7 AC Waveforms

35/52

M36DR432AD, M36DR432BD

Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms

36/52

M36DR432AD, M36DR432BD

Table 22. Flash Data Polling and Toggle Bits AC Characteristics

M36DR432AD,

M36DR432BD

Symbol

Parameter

Unit

Min

8

Max

100

4

Write Enable High to DQ7 Valid (Program, WF Controlled)

Write Enable High to DQ7 Valid (Block Erase, WF Controlled)

Chip Enable High to DQ7 Valid (Program, EF Controlled)

Chip Enable High to DQ7 Valid (Block Erase, EF Controlled)

Q7 Valid to Output Valid (Data Polling)

µs

s

t

WHQ7V

0.8

8

100

4

µs

s

t

EHQ7V

0.8

t

0

ns

µs

s

Q7VQV

Write Enable High to Output Valid (Program)

8

0.8

8

100

4

t

WHQV

Write Enable High to Output Valid (Block Erase)

Chip Enable High to Output Valid (Program)

100

4

µs

s

t

EHQV

Chip Enable High to Output Valid (Block Erase)

0.8

Note: All other timings are defined in Read AC Characteristics

Figure 15. Flash Data Polling Flowchart

Figure 16. Flash Data Toggle Flowchart

START

READ

DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

DQ6

NO

=

DQ7

=

DATA

YES

TOGGLES

YES

NO

DQ5

= 1

NO

DQ5

= 1

YES

READ DQ6

READ DQ7

DQ6

=

DQ7

=

DATA

NO

YES

TOGGLES

NO

YES

FAIL

PASS

FAIL

PASS

AI06197

AI06198

37/52

M36DR432AD, M36DR432BD

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V

IL

tAVAV

A0-A17

VALID

tAVQV

tAXQX

DQ0-DQ15

DATA VALID

AI90217

Note: ES = Low, GS = Low, WS = High.

Figure 18. SRAM Read AC Waveforms, ES or GS Controlled

tAVAV

A0-A17

VALID

tAVQV

tELQV

tAXQX

tEHQZ

ES

tELQX

tBLQV

tBHQZ

UBS, LBS

tBLQX

tGLQV

tGHQZ

GS

tGLQX

DQ0-DQ15

DATA VALID

AI07311

Note: Write Enable (WS) = High.

38/52

M36DR432AD, M36DR432BD

Figure 19. SRAM Standby AC Waveforms

ES

tPU

tPD

I

DD

AI07320

Table 23. SRAM Read AC Characteristics)

SRAM

Symbol

Alt

Parameter

70

Unit

Min

Max

t

Read Cycle Time

70

ns

AVAV

RC

t

Address Valid to Output Valid

70

AVQV

AA

t

Address Transition to Output Transition

UBS, LBS Disable to Hi-Z Output

UBS, LBS Access Time

10

5

AXQX

OH

t

BHZ

25

45

BHQZ

t

BLQV

BA

t

BLZ

UBS, LBS Enable to Low-Z Output

Chip Enable High to Output Hi-Z

Chip Enable Low to Output Valid

Chip Enable Low to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

Chip Enable High to Power Down

BLQX

t

HZ

25

70

EHQZ

t

ELQV

ACE

t

5

ELQX

LZ

t

25

35

GHQZ

OHZ

t

GLQV

EO

t

OLZ

5

0

GLQX

(1)

70

t

PD

t

PU

(1)

Chip Enable Low to Power Up

ns

Note: 1. Sampled only. Not 100% tested.

39/52

M36DR432AD, M36DR432BD

Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low

tAVAV

A0-A17

VALID

tAVWH

tELWH

tAVEL

tWHAX

ES

tBLWH

UBS, LBS

WS

tAVWL

tWLQZ

tWLWH

tWHQX

tWHDX

tDVWH

INPUT VALID

DQ0-DQ15

AI07321

Note: Output Enable (GS) = Low.

Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High

tAVAV

A0-A17

VALID

tAVWH

tELWH

tAVEL

tWHAX

ES

tBLWH

UBS, LBS

tAVWL

tWLWH

WS

GS

tDVWH

INPUT VALID

tWHDX

DQ0-DQ15

AI07322

40/52

M36DR432AD, M36DR432BD

Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low

tAVAV

VALID

A0-A17

ES

tEHAX

tAVWH

tBLWH

UBS, LBS

tAVWL

tWLEH

WS

tWHQX

tWHDX

DQ0-DQ15

tWLQZ

tDVWH

INPUT VALID

AI07323

Figure 23. SRAM Write AC Waveforms, ES Controlled

tAVAV

A0-A17

ES

VALID

tELWH

tAVEL

tEHAX

tBLWH

tWLWH

UBS, LBS

WS

tDVWH

INPUT VALID

tWHDX

DQ0-DQ15

AI07324

Note: Output Enable (GS) = High.

41/52

M36DR432AD, M36DR432BD

Table 24. SRAM Write AC Characteristics

SRAM

70

Symbol

Alt

Parameter

Unit

Min

Max

t

Write Cycle Time

70

ns

AVAV

WC

(1)

t

Address Valid to Chip Enable Low

Address Valid to Write Enable High

Address Valid to Write Enable Low

UBS, LBS Valid to End of Write

Input Valid to Write Enable High

Chip Enable High to Address Transition

0

60

0

t

AVEL

AS

t

AVWH

AW

(1)

t

AVWL

AS

t

60

BLWH

BW

t

DW

30

0

DVWH

(2)

(3)

(2)

t

EHAX

WR

t

,

Chip Select to End of Write

60

ns

ELWH

CW

t

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Output Transition

Write Enable Low to Output Hi-Z

Write Enable Pulse Width

0

ns

t

WHAX

WHDX

WR

t

DH

t

10

WHQX

OW

t

25

WLQZ

WLWH

WHZ

(4)

t

50

t

WP

Note: 1. t is measured from the address valid to the beginning of write.

AS

2. t

3. t

is measured from the end or write to the address change. t

is measured from ES going Low end of write.

applied in case a write ends as ES or WS goes High.

WR

CW

4. A Write occurs during the overlap (t ) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low with asserting

WP

UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-

liest transition when ES goes High and WS goes High. The t

is measured from the beginning of write to the end of write.

WP

Figure 24. SRAM Low V

Data Retention AC Waveforms, ES Controlled

DDS

tCDR

DATA RETENTION MODE

tR

V

1.65 V

≥ 1.0 V

DDS

V

DR

ES

ES ≥ V

– 0.2V

DDS

AI07325

42/52

M36DR432AD, M36DR432BD

(1, 2)

Table 25. SRAM Low V

Data Retention Characteristics

DDS

Symbol

Parameter

Test Condition

Min

Typical

Max

10

Unit

µA

V

DDS

= 1.0V, ES ≥ V – 0.2V

DDS

I

Supply Current (Data Retention)

Supply Voltage (Data Retention)

0.5

DDDR

no input may exceed V

+ 2V

DDS

V

DR

ES ≥ V

– 0.2V

1

0

2.2

DDS

Chip Disable to Data Retention

Time

t

ES ≥ V

– 0.2V

ns

CDR

t

Operation Recovery Time

ns

R

RC

Note: 1. All other Inputs V ≤ V

– 0.2V or V ≤ 0.2V.

IL

IH

DDS

2. Sampled only. Not 100% tested.

43/52

M36DR432AD, M36DR432BD

PACKAGE MECHANICAL

Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline

D

D2

D1

SE

b

E

E1

BALL "A1"

e

ddd

FE

FD

SD

e

A

A2

A1

BGA-Z12

Note: Drawing is not to scale.

Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.400

0.0551

0.250

0.0098

1.100

0.0433

0.400

12.000

5.600

8.800

0.350

0.450

0.0157

0.4724

0.2205

0.3465

0.0138

0.0177

D

–

D1

D2

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.600

1.200

0.400

–

0.3150

0.2205

0.0315

0.0630

0.0472

0.0157

–

E1

e

FD

FE

SD

SE

44/52

M36DR432AD, M36DR432BD

PART NUMBERING

Table 27. Ordering Information Scheme

Example:

M36 D R 4 32A

D

10 ZA

6

T

Device Type

M36 = MMP (Flash + SRAM)

Architecture

D = Dual Bank, Page Mode

Operating Voltage

R = V

= V

= 1.65V to 2.2V

DDS

DDF

SRAM Chip Size & Organization

4 = 4 Mbit (256Kb x 16 bit)

Flash Specification Details

32A = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Configuration

32B = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Configuration

SRAM Specification Details

D = Asynchronous SRAM, 0.16µm, 70ns speed

Speed

85 = 85ns (to be characterized)

10 = 100ns

12 = 120ns

Package

ZA = LFBGA66: 0.8mm pitch

Temperature Range

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-

tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-

Microelectronics Sales Office nearest to you.

45/52

M36DR432AD, M36DR432BD

APPENDIX A. BLOCK ADDRESSES

Table 28. Bank A, Top Boot Block Addresses

M36DR432AD

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

Size

(KWord)

#

Address Range

14

13

12

11

10

9

4

1FF000h-1FFFFFh

1FE000h-1FEFFFh

1FD000h-1FDFFFh

1FC000h-1FCFFFh

1FB000h-1FBFFFh

1FA000h-1FAFFFh

1F9000h-1F9FFFh

1F8000h-1F8FFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

4

8

4

7

4

6

32

5

4

3

2

1

0

Table 29. Bank B, Top Boot Block Addresses

M36DR432AD

Size

(KWord)

#

Address Range

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

32

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

32

8

32

7

32

6

32

5

32

4

32

3

32

2

32

1

32

0

32

46/52

M36DR432AD, M36DR432BD

Table 30. Bank B, Bottom Boot Block

Addresses M36DR432BD

18

17

16

15

14

13

12

11

10

9

32

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

Size

#

Address Range

(KWord)

32

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

8

7

6

5

4

3

2

1

0

Table 31. Bank A, Bottom Boot Block

Addresses M36DR432BD

Size

(KWord)

#

Address Range

14

13

12

11

10

9

32

4

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

8

7

6

4

5

4

3

4

2

4

1

4

0

4

47/52

M36DR432AD, M36DR432BD

APPENDIX B. COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 32, 33,

34 and 35 show the address used to retrieve each

data. The Query data is always presented on the

lowest order data outputs (DQ0-DQ7), the other

outputs (DQ8-DQ15) are set to 0.

The CFI data structure contains also a security

area starting at address 81h. This area can be ac-

cessed only in read mode and it is impossible to

change after it has been written by ST. Issue a

Read command to return to Read mode.

When the Read CFI Query Command is issued

the device enters CFI Query mode and the data

Table 32. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Table 33. CFI Query Identification String

Offset

Data

Description

00h

0020h

Manufacturer Code

Device Code

Reserved

00A1h - bottom

00A0h - top

01h

02h-0Fh

10h

reserved

0051h

Query Unique ASCII String "QRY"

11h

0052h

12h

0059h

13h

0002h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

14h

0000h

15h

offset = P = 0040h

0000h

Address for Primary Algorithm extended Query table

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

18h

0000h

19h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

note: 0000h means none exists

1Ah

48/52

M36DR432AD, M36DR432BD

Table 34. CFI Query System Interface Information

Offset

Data

Description

V

DDF

V

DDF

V

PPF

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

0022h

0000h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

Note: This value must be 0000h if no V

pin is present

PPF

V

PPF

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

1Eh

00C0h

Note: This value must be 0000h if no V

pin is present

PPF

n

Typical timeout per single byte/word program (multi-byte program count = 1), 2 µs

(if supported; 0000h = not supported)

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0003h

000Ah

0000h

0003h

0004h

0002h

0000h

n

Typical timeout for maximum-size multi-byte program or page write, 2 µs

(if supported; 0000h = not supported)

n

Typical timeout per individual block erase, 2 ms

(if supported; 0000h = not supported)

n

Typical timeout for full chip erase, 2 ms

(if supported; 0000h = not supported)

n

Maximum timeout for byte/word program, 2 times typical (offset 1Fh)

(0000h = not supported)

n

Maximum timeout for multi-byte program or page write, 2 times typical (offset 20h)

(0000h = not supported)

n

Maximum timeout per individual block erase, 2 times typical (offset 21h)

(0000h = not supported)

n

Maximum timeout for chip erase, 2 times typical (offset 22h)

(0000h = not supported)

49/52

M36DR432AD, M36DR432BD

Table 35. Device Geometry Definition

Offset Word

Data

Description

Device Size = 2 in number of bytes

Mode

n

27h

28h

29h

2Ah

2Bh

2Ch

0016h

0001h

0000h

0002h

Flash Device Interface Code description: Asynchronous x16

Maximum number of bytes in multi-byte program or page = 2

n

Number of Erase Block Regions within device

bit 7 to 0 = x = number of Erase Block Regions

Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."

2. x specifies the number of regions within the device containing one or more

contiguous Erase Blocks of the same size. For example, a 128KB device

(1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is

considered to have 5 Erase Block Regions. Even though two regions both

contain 16KB blocks, the fact that they are not contiguous means they are

separate Erase Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

M36DR432AD M36DR432AD Erase Block Region Information

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

003Eh

0000h

0001h

0007h

0000h

0020h

0000h

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes

in size. The value z = 0 is used for 128 byte block size.

e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase

Block Region:

e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = "1 block")

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

M36DR432AD M36DR432AD

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

0007h

0000h

0020h

0000h

003Eh

0000h

0001h

50/52

M36DR432AD, M36DR432BD

REVISION HISTORY

Table 36. Document Revision History

Date

Version

1.0

Revision Details

15-Jan-2003

25-Feb-2003

First issue.

Bottom Device Code corrected on page 1.

Document promoted from Preliminary Data to full Datasheet status.

signal removed from datasheet. SRAM Input Rise and Fall Times added to,

1.1

2.0

V

DDQF

and V

parameters differentiated in Table 14, Operating and AC

28-Feb-2003

2.1

DDF

DDS

Measurement Conditions. V

added to the SIGNAL DESCRIPTIONS section.

DDS

51/52

M36DR432AD, M36DR432BD

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong -

India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

www.st.com

52/52


型号：	M36DR432AD
厂家：	ST
描述：	32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product 32兆位的2Mb X16 ，双行，页闪存和4兆位256Kb的SRAM X16 ，多重内存产品闪存静态存储器
文件：	总52页 (文件大小：782K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36DR432AD [STMICROELECTRONICS]

相关型号：

M36DR432AD10ZA6T

M36DR432AD12ZA6

M36DR432AD12ZA6T

M36DR432AD85ZA6

M36DR432AD85ZA6T

M36DR432ADZA

M36DR432AZA

M36DR432B

M36DR432B100ZA6

M36DR432B100ZA6C

M36DR432B100ZA6CT

M36DR432B100ZA6T