M36L0R7060B1ZAQF [STMICROELECTRONICS]
128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package; 128兆位（多银行，多层次，连拍），闪存和64兆位（突发）的PSRAM ， 1.8 V电源供电，多芯片封装
| 型号： | M36L0R7060B1ZAQF |
| 厂家： | 
ST |
| 描述： | 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package |
| 文件： | 总22页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36L0R7060T1
M36L0R7060B1
128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory
and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package
Features
■ Multichip package
– 1 die of 128 Mbit (8 Mb x16, Multiple Bank,
Multilevel, Burst) Flash memory
FBGA
– 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM
■ Supply voltage
– V
– V
= V
= V
= 1.7 to 1.95 V
DDQF
DDF
PPF
CCP
TFBGA88 (ZAQ)
8 x 10 mm
= 9 V for fast program
■ Electronic signature
– Manufacturer Code: 20h
– Top Device Code
M36L0R7060T1: 88C4h
■ Security
– Bottom Device Code
M36L0R7060B1: 88C5h
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ Package
■ Block locking
– ECOPACK®
– All blocks locked at power-up
Flash memory
– Any combination of blocks can be locked
with zero latency
■ Synchronous / Asynchronous Read
– WP for Block Lock-Down
– Synchronous Burst Read mode: 54 MHz,
66 MHz
F
– Absolute Write Protection with V
= V
SS
PPF
– Random Access: 70 ns, 85 ns
■ Synchronous Burst Read Suspend
■ Programming time
PSRAM
■ Access time: 70 ns
■ Asynchronous Page Read
– 2.5 µs typical word program time using
Buffer Enhanced Factory Program
command
– Page Size: 4, 8 or 16 words
– Subsequent read within page: 20 ns
■ Memory organization
■ Low power features
– Multiple Bank memory array: 8 Mbit banks
– Parameter Blocks (top or bottom location)
– Automatic Temperature-compensated Self-
Refresh (TCR)
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) mode
■ Common Flash Interface (CFI)
■ 100 000 program/erase cycles per block
■ Dual operations
■ Synchronous Burst Read/Write
– program/erase in one Bank while read in
others
– No delay between read and write
operations
May 2007
Rev 1
1/22
www.st.com
1
Contents
M36L0R7060T1, M36L0R7060B1
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 11
2.17
VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.18 VCCP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.19
2.20
V
DDQF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PPF Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
2.21 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
4
5
6
2/22
M36L0R7060T1, M36L0R7060B1
Contents
7
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36L0R7060T1, M36L0R7060B1
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7.
Table 8.
4/22
M36L0R7060T1, M36L0R7060B1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline. . . . . . . . . . . . . . 18
5/22
Description
M36L0R7060T1, M36L0R7060B1
1
Description
The M36L0R7060T1 and M36L0R7060B1 combine two memory devices in a multichip
package:
■
■
a 128-Mbit, Multiple Bank Flash memory, the M58LR128HT or M58LR128HB
a 64-Mbit PseudoSRAM, the M69KB096AM
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58LR128HTB and
M69KB096AM datasheets, where all specifications required to operate the Flash memory
and PSRAM components are fully detailed. These datasheets are available from your local
STMicroelectronics distributor.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA88 (8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch)
package. The memory is supplied with all the bits erased (set to ‘1’).
Figure 1.
Logic diagram
V
V
PPF
DDQF
V
V
DDF
CCP
23
16
DQ0-DQ15
A0-A22
E
F
G
F
WAIT
W
F
RP
F
WP
L
F
M36L0R7060T1
M36L0R7060B1
K
E
P
G
P
W
P
CR
P
UB
LB
P
P
V
SS
AI13200
6/22
M36L0R7060T1, M36L0R7060B1
Description
Table 1.
Signal names
Signal name
Function
Direction
A0-A22
DQ0-DQ15
L
Address inputs
Inputs
I/O
Common Data input/output
Latch Enable input for Flash memory and PSRAM
Burst Clock for Flash memory and PSRAM
Wait Data in Burst Mode for Flash memory and PSRAM
Flash memory power supply
Input
Input
Output
K
WAIT
VDDF
VDDQF
VPPF
VSS
Flash power supply for I/O buffers
Flash optional supply voltage for Fast Program & Erase
Ground
VCCP
NC
PSRAM power supply
Not connected internally
DU
Do not use as internally connected
Flash memory
EF
Chip Enable input
Output Enable Input
Write Enable input
Reset input
Input
Input
Input
Input
Input
GF
WF
RPF
WPF
PSRAM
EP
Write Protect input
Chip Enable input
Input
Input
Input
Input
Input
Input
GP
Output Enable input
WP
Write Enable input
CRP
UBP
Configuration Register Enable input
Upper Byte Enable input
Lower Byte Enable input
LBP
7/22
Description
M36L0R7060T1, M36L0R7060B1
Figure 2.
TFBGA connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
A4
A5
A3
A2
A1
A0
DU
A21
A22
A9
DU
DU
A11
A12
A13
A15
A16
NC
A18
A19
NC
NC
NC
V
V
NC
K
V
SS
SS
DDF
LB
P
NC
A17
A7
V
W
P
E
P
PPF
WP
L
A20
A8
A10
A14
WAIT
DQ7
DQ15
F
A6
UB
P
RP
W
F
F
G
H
J
DQ8
DQ0
DQ2
DQ1
DQ9
DU
DQ10
DQ3
DQ11
NC
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
NC
G
P
NC
NC
G
F
V
DDQF
E
F
K
L
DU
V
V
CR
CCP
DDQF
P
V
V
V
V
V
V
V
V
SS
SS
DDQF
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
AI12023
8/22
M36L0R7060T1, M36L0R7060B1
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connect-ed to this device.
2.1
Address inputs (A0-A22)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The
other lines (A22) is an input for the Flash memory component only.
The Address inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine. The Flash memory is accessed through the Chip
Enable signal (E ) and through the Write Enable signal (WF), while the PSRAM is accessed
F
through the Chip Enable signal (E ) and the Write Enable signal (W ).
P
P
2.2
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data inputs/outputs (DQ8-DQ15) carry the data
to or from the upper part of the selected address when Upper Byte Enable (UB ) is driven
P
Low. The lower Byte Data inputs/outputs (DQ0-DQ7) carry the data to or from the lower part
of the selected address when Lower Byte Enable (LB ) is driven Low. When both UB and
P
P
LB are disabled, the Data inputs/outputs are high impedance.
P
2.3
2.4
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the
Flash memory.
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash
memory.
9/22
Signal descriptions
M36L0R7060T1, M36L0R7060B1
2.5
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM
and to the M58LR128HTB datasheet for the Flash memory.
2.6
Flash Chip Enable (EF)
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component. When Chip Enable is Low, V , and Reset is
IL
High, V , the device is in active mode. When Chip Enable is at V the Flash memory is
IH
IH
deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
2.7
2.8
Flash Output Enable (GF)
The Output Enable pin controls the data outputs during Flash memory Bus Read
operations.
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V , Lock-Down is enabled and the protection status of the Locked-
IL
Down blocks cannot be changed. When Write Protect is at High, V , Lock-Down is disabled
IH
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M30L0R7000T1/B1 datasheet).
2.10
Flash Reset (RPF)
The Reset input provides a hardware reset of the Flash memory. When Reset is at V , the
IL
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
. Refer to the M58LR128HTB datasheet, for the
DD2
value of I
. After Reset all blocks are in the Locked state and the Configuration Register is
DD2
reset. When Reset is at V , the device is in normal operation. Exiting Reset mode the
IH
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied
to V
(refer to the M58LR128HTB datasheet).
RPH
10/22
M36L0R7060T1, M36L0R7060B1
Signal descriptions
2.11
PSRAM Chip Enable input (EP)
The Chip Enable input activates the PSRAM when driven Low (asserted). When de-
asserted (V ), the device is disabled, and goes automatically in low-power Standby mode
IH
or Deep Power-down mode, according to the RCR settings.
2.12
PSRAM Write Enable (WP)
Write Enable, W , controls the Bus Write operation of the PSRAM. When asserted (V ), the
P
IL
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
2.14
2.15
PSRAM Output Enable (GP)
When held Low, V , the Output Enable, G , enables the Bus Read operations of the
IL
P
memory.
PSRAM Upper Byte Enable (UBP)
The Upper Byte En-able, UB , gates the data on the Upper Byte Data inputs/outputs (DQ8-
P
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LB , gates the data on the Lower Byte Data inputs/outputs (DQ0-
P
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB and UB are disabled (High) during an operation, the device will disable the data
P
P
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as E remains Low.
P
2.16
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, V , bus read or write operations access either the value of
IH
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.17
2.18
VDDF supply voltage
V
provides the power supply to the internal core of the Flash memory. It is the main
DDF
power supply for all Flash memory operations (Read, Program and Erase).
VCCP supply voltage
V
provides the power supply to the internal core of the PSRAM device. It is the main
CCP
power supply for all PSRAM operations.
11/22
Signal descriptions
M36L0R7060T1, M36L0R7060B1
2.19
VDDQF supply voltage
V
provides the power supply for the Flash I/O pins. This allows all outputs to be
DDQF
powered independently of the Flash core power supplies, V
and V
.
DDF
CCP
2.20
VPPF Program supply voltage
V
is both a Flash control input and a Flash power supply pin. The two functions are
PPF
selected by the voltage range applied to the pin.
If V is kept in a low voltage range (0V to V
) V is seen as a control input. In this
PPF
PPF
DDQF
case a voltage lower than V
gives an absolute protection against Program or Erase,
PPLK
while V in the V
range enables these functions (see the M58LR128HTB datasheet for
PP
PP1
the relevant values). V
is only sampled at the beginning of a Program or Erase; a change
PPF
in its value after the operation has started does not have any effect and Program or Erase
operations continue.
If V
is in the range of V
it acts as a power supply pin. In this condition V
must be
PPF
PPH
PPF
stable until the Program/Erase algorithm is completed.
2.21
VSS ground
V
is the common ground reference for all voltage measurements in the Flash (core and
SS
I/O buffers) and PSRAM chips. It must be connected to the system ground.
Note:
Each Flash memory device in a system should have their supply voltage (V
) and the
DDF
program supply voltage V
decoupled with a 0.1 µF ceramic capacitor close to the pin
PPF
(high frequency, inherently low inductance capacitors should be as close as possible to the
package). See Figure 5: AC measurement load circuit. The PCB track widths should be
sufficient to carry the required V
program and erase currents.
PPF
12/22
M36L0R7060T1, M36L0R7060B1
Functional description
3
Functional description
The PSRAM and Flash memory components have separate power supplies but share the
same grounds. They are distinguished by two Chip Enable inputs: E for the Flash memory
F
and E for the PSRAM.
P
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is simultaneous read operations on one of the Flash
memory and the PSRAM components which would result in a data bus contention.
Therefore it is recommended to put the other devices in the high impedance state when
reading the selected device.
Figure 3.
Functional block diagram
A22
E
F
W
F
128 Mbit
Flash
RP
F
WP
Memory
F
G
F
WAIT
V
V
V
DDF
DDQF
PPF
K
L
V
V
SS
CCP
A0-A21
DQ0-DQ15
E
P
64 Mbit
PSRAM
G
P
W
P
CR
P
UB
LB
P
P
AI12024
13/22
Functional description
M36L0R7060T1, M36L0R7060B1
(1)
Table 2.
Main operating modes
A0-
A17
A20-
A21
(4)
Operation(2)(3) EF GF WF LF RPF WAITF
EP CRP GP WP LBP,UBP A19 A18
DQ15-DQ0
Flash Data
Out
(5)
Flash Read
Flash Write
VIL VIL VIH VIL
VIL VIH VIL VIL
VIH
VIH
(5)
PSRAM must be disabled.
Flash Data In
Flash Address
Latch
Flash Data
VIL
X
VIH VIL VIH
Out or Hi-Z(6)
Flash Output
Disable
VIL VIH VIH
X
VIH
Hi-Z
Hi-Z
Any PSRAM mode is allowed.
Flash Standby VIH
X
X
X
X
X
X
VIH
VIL
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Flash Reset
X
PSRAM data
out
PSRAM Read
VIL VIL VIL VIH
VIL
VIL
Valid
Valid
PSRAM data
in
PSRAM Write
VIL VIL
VIL VIH
VIH VIL
X
X
VIL
The Flash memory must be
disabled.
PSRAM
Program
Configuration
Register (CR
Controlled)(7)
00(RCR) BCR/
10(BCR) RCR
VIL
X
Hi-Z
(8)
Data
PSRAM
Standby
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Any Flash mode is allowed.
PSRAM Deep
Power-Down(9)
VIH
X
1. X = Don't care.
2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in
Standby and Deep Power-Down modes.
3. The PSRAM must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LR128HTB datasheet for
details.
5. LF can be tied to VIH if the valid address has been previously latched.
6. Depends on GF.
7. BCR and RCR only.
8. A18 and A19 are used to select the BCR, RCR or DIDR registers.
9. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep Power-
Down mode.
14/22
M36L0R7060T1, M36L0R7060B1
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Min
Max
TA
Ambient operating temperature
Temperature under bias
Storage temperature
–25
–25
–55
–0.2
85
85
°C
°C
°C
V
TBIAS
TSTG
VIO
125
2.45
Input or output voltage
VDDF, VDDQF
,
Core and input/output supply
voltages
–0.2
–0.2
2.45
V
VCCP
VPPF
IO
Flash program voltage
Output short circuit current
Time for VPPF at VPPFH
10
V
100
100
mA
tVPPFH
hours
15/22
DC and AC parameters
M36L0R7060T1, M36L0R7060B1
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and AC measurement conditions
Flash memory
Parameter
PSRAM
Unit
Min
Max
Min
Max
VDDF supply voltage
VCCP supply voltage
1.7
–
1.95
–
–
1.7
–
–
1.95
–
V
V
V
V
VDDQF supply voltage
1.7
8.5
1.95
9.5
VPPF supply voltage (Factory environment)
–
–
VPPF supply voltage (Application
environment)
–0.4
–25
VDDQF +0.4
85
–
–
V
Ambient operating temperature
Load capacitance (CL)
–25
85
°C
pF
kΩ
ns
V
30
16.7
30
Output circuit resistors (R1, R2)
Input rise and fall times
16.7
5
2
Input pulse voltages
0 to VDDQF
VDDQF/2
0 to VCCP/2
VCCP/2
Input and output timing ref. voltages
V
Figure 4.
AC measurement I/O waveform
V
DDQF
V
/2
DDQF
0V
AI06161b
16/22
M36L0R7060T1, M36L0R7060B1
DC and AC parameters
Figure 5.
AC measurement load circuit
V
DDQF
V
V
DDQF
DDF
R
1
DEVICE
UNDER
TEST
C
L
0.1µF
R
2
0.1µF
C
includes JIG capacitance
L
AI08364c
Table 5.
Symbol
Device capacitance
Parameter
Test Condition
Min
Max(1)
Unit
CIN
Input capacitance
VIN = 0 V
14
18
pF
pF
COUT
Output capacitance
VOUT = 0 V
1. Sampled only, not 100% tested.
Please refer to the M58LR128HTB and M69KB096AM datasheets for further DC and AC
characteristics values and illustrations.
17/22
Package mechanical
M36L0R7060T1, M36L0R7060B1
6
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6.
TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
1. Drawing is not to scale.
18/22
M36L0R7060T1, M36L0R7060B1
Package mechanical
Table 6.
Symbol
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,
package mechanical data
millimeters
inches
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
–
E1
E2
e
–
–
FD
FE
FE1
SD
SE
19/22
Part numbering
M36L0R7060T1, M36L0R7060B1
7
Part numbering
Table 7.
Ordering information scheme
Example:
M36 L 0 R 7 0 6 0 T 1 ZAQ E
Device Type
M36 = Multichip package (Multiple Flash + RAM)
Flash 1 Architecture
L = Multilevel, Multiple Bank, Burst mode
Flash 2 Architecture
0 = No Die
Operating Voltage
R = VDDF = VCCP = VDDQF = 1.7 to 1.95V
Flash 1 Density
7 = 128 Mbits
Flash 2 Density
0 = No Die
RAM 1 Density
6 = 64 Mbits
RAM 0 Density
0 = No Die
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
1 = 90 nm Flash technology Multilevel Design, 70 and 85 ns speed
0.11 µm PSRAM, 70 ns speed, burst mode
Package
ZAQ = Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch
Option
E = ECOPACK® Standard packing
F = ECOPACK® Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the STMicroelectronics Sales Office nearest to you.
20/22
M36L0R7060T1, M36L0R7060B1
Revision history
8
Revision history
Table 8.
Date
Document revision history
Revision
Changes
23-May-2006
31-Aug-2006
0.1
First release.
PSRAM changed to M69KM096AM. Blank and T removed below
Option in Table 7: Ordering information scheme.
0.2
1
Document status promoted from Target Specification to full Datasheet.
70 ns speed class and 66 MHz frequency added.
07-May-2007
21/22
M36L0R7060T1, M36L0R7060B1
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22/22
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