M36L0T7060B2ZAQ [STMICROELECTRONICS]
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88;
| 型号： | M36L0T7060B2ZAQ |
| 厂家： | 
ST |
| 描述： | SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36L0T7060T2
M36L0T7060B2
128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory
and 64 Mbit (4 Mb x16) PSRAM, multichip package
Preliminary Data
Features
■ Multichip package
– 1 die of 128 Mbit (8 Mb x16, Multiple Bank,
Multilevel, Burst) Flash Memory
FBGA
– 1 die of 32 Mbit (2 Mb x16) Pseudo SRAM
■ Supply voltage
– V
– V
– V
= 1.7 to 2.0 V
DDF
CCP
PPF
TFBGA88 (ZAQ)
8 × 10 mm
= V
= 2.7 to 3.5 V
DDQ
= 9 V for fast program
■ Electronic signature
■ Block locking
– Manufacturer Code: 20h
– All blocks locked at power-up
– Device Code (Top Flash Configuration)
M36L0T7060T2: 88C4h
– Device Code (Bottom Flash Configuration)
M36L0T7060B2: 88C5h
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with V = V
■ ECOPACK® packages available
PP
SS
■ Security
– 64 bit unique device number
Flash memory
■ Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 52 MHz
– Random Access: 85 ns
– 2112 bit user programmable OTP Cells
■ Common Flash Interface (CFI)
■ 100,000 program/erase cycles per block
■ Synchronous Burst Read Suspend
■ Programming time
PSRAM
– 2.5 µs typical Word program time using
Buffer Enhanced Factory Program
command
■ Access time: 65 ns
■ Low standby current: 90 µA (T ≤ 40°C)
A
■ Deep Power-Down current: 10 µA
■ Memory organization
■ Byte control: UB /LB
P
P
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■ Compatible with standard LPSRAM
■ Power-Down modes
■ Dual operations
– Deep Power-Down
– program/erase in one Bank while read in
others
– No delay between read and write
operations
April 2007
Rev 1
1/22
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents
M36L0T7060T2, M36L0T7060B2
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 PSRAM Chip Enable input (E1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.12 PSRAM Chip Enable input (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.17
VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.18 VCCP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.19
2.20
V
V
DDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PPF Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
4
5
6
2/22
M36L0T7060T2, M36L0T7060B2
Contents
7
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36L0T7060T2, M36L0T7060B2
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch, package data. . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4/22
M36L0T7060T2, M36L0T7060B2
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch,
bottom view outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5/22
Description
M36L0T7060T2, M36L0T7060B2
1
Description
The M36L0T7060T2 and M36L0T7060B2 combine two memory devices in a multichip
package:
●
a 128-Mbit, Multiple Bank, Multilevel, Burst, Flash memory, the M58LT128HT or
M58LT128HB
●
a 64-Mbit PseudoSRAM, the M69KW096B.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It should be read in conjunction with the M58LT128HTB and
M69KW096B datasheets, where all specifications required to operate the Flash memory
and PSRAM components are fully detailed. These datasheets are available from your local
STMicroelectronics distributor.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA88 (8 x 10 mm, 8x10 ball array, 0.8 mm pitch)
package. The devices are supplied with all the bits erased (set to ‘1’).
Figure 1.
Logic diagram
V
V
PPF
DDQ
V
V
DDF
CCP
23
16
DQ0-DQ15
A0-A22
E
G
F
F
F
WAIT
W
F
RP
F
WP
F
M36L0T7060T2
M36L0T7060B2
L
F
K
F
P
P
E1
G
W
P
E2
P
UB
LB
P
P
V
AI13216
SS
6/22
M36L0T7060T2, M36L0T7060B2
Description
Table 1.
Signal names
A0-A22(1)
Address Inputs
DQ0-DQ15
VDDF
VDDQ
VPPF
VSS
Common Data Input/Output
Power Supply for Flash Memory
Flash Memory Power Supply for I/O Buffers
Flash Optional Supply Voltage for Fast Program and Erase
Ground
VCCP
NC
PSRAM Power Supply
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash memory signals
LF
Latch Enable Input
EF
Chip Enable Input
Output Enable Input
Write Enable Input
Reset Input
GF
WF
RPF
WPF
Write Protect Input
Burst Clock
KF
WAITF
Wait Data in Burst Mode
PSRAM signals
E1P
GP
Chip Enable Input
Output Enable Input
Write Enable Input
WP
E2P
UBP
LBP
Power-down Input
Upper Byte Enable Input
Lower Byte Enable Input
1. A22 is not connected to the PSRAM component.
7/22
Description
M36L0T7060T2, M36L0T7060B2
TFBGA connections (top view through package)
Figure 2.
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
A4
A5
A3
A2
A1
A0
DU
A21
A22
A9
DU
DU
A11
A12
A13
A15
A16
NC
A18
A19
NC
NC
NC
V
V
NC
V
SS
SS
DDF
LB
P
NC
K
F
A17
A7
V
W
P
E
P
PPF
WP
L
F
A20
A8
A10
A14
WAIT
F
A6
UB
P
RP
W
F
F
G
H
J
DQ8
DQ0
DQ2
DQ1
DQ9
DU
DQ10
DQ3
DQ11
NC
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
NC
F
G
P
DQ7
NC
NC
G
F
DQ15
V
DDQ
E
F
K
L
DU
V
V
E2
P
CCP
DDQ
V
V
V
V
V
V
V
V
SS
SS
DDQ
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
AI08735b
8/22
M36L0T7060T2, M36L0T7060B2
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A22)
Addresses A0-A21 are common inputs for the Flash memory and the PSRAM components.
The other line (A22) is an input for the Flash memory component only.
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller in the Flash memory, and they select the cells to
be accessed in the PSRAM.
2.2
2.3
Data input/output (DQ0-DQ15)
In the Flash memory, the Data I/O outputs the data stored at the selected address during a
Bus Read operation or inputs a command or the data to be programmed during a Write Bus
operation.
In the PSRAM DQ0-DQ7 and/or DQ8-DQ15 carry the data to or from the upper and/or lower
part(s) of the selected address during a Write or Read operation, when Upper Byte Enable
(UB ) and/or Lower Byte Enable (LB ) is/are driven Low.
P
P
Flash Chip Enable (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V , and Reset is High, V , the device is in
IL
IH
active mode. When Chip Enable is at V the Flash memory is deselected, the outputs are
IH
high impedance and the power consumption is reduced to the standby level.
It is not allowed to set E at V E1 at V and E2 at V at the same time.
F
IL,
P
IL
P
IH
2.4
2.5
Flash Output Enable (GF)
The Output Enable input controls data output during Flash memory Bus Read operations.
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memories’ Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
9/22
Signal descriptions
M36L0T7060T2, M36L0T7060B2
2.6
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V , Lock-Down is enabled and the protection status of the Locked-
IL
Down blocks cannot be changed. When Write Protect is at High, V , Lock-Down is disabled
IH
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M58LT128HTB datasheet).
2.7
Flash Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
. Refer to M58LT128HTB datasheet for the value
DD2
of I
. After Reset all blocks are in the Locked state and the Configuration Register is
DD2
reset. When Reset is at V , the device is in normal operation. Exiting Reset mode the
IH
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
2.8
Flash Latch Enable (LF)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is Low, V , and it is inhibited when Latch Enable is High, V . Latch
IL
IH
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
2.9
Flash Clock (KF)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous
read operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V . Clock is don't care during Asynchronous
IL
Read and in write operations.
2.10
2.11
Flash Wait (WAITF)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data
on the output bus are valid. This output is high impedance when Flash Chip Enable is at V
IH
or Flash Reset is at V . It can be configured to be active during the wait cycle or one clock
IL
cycle in advance. The WAIT signal is not gated by Output Enable.
F
PSRAM Chip Enable input (E1P)
When asserted (Low), the Chip Enable, E1 , activates the memory state machine, address
P
buffers and decoders, allowing Read and Write operations to be performed. When de-
asserted (High), all other pins are ignored, and the device is put, automatically, in low-power
Standby mode.
It is not allowed to set E at V E1 at V and E2 at V at the same time.
F
IL,
P
IL
P
IH
10/22
M36L0T7060T2, M36L0T7060B2
Signal descriptions
2.12
PSRAM Chip Enable input (E2P)
The Chip Enable, E2 , puts the device in Deep Power-down mode when it is driven Low.
P
This is the lowest power mode.
2.13
2.14
PSRAM Write Enable (WP)
The Write Enable, W , controls the Bus Write operation of the memory.
P
PSRAM Output Enable (GP)
The Output Enable, G , provides a high speed tri-state control, allowing fast read/write
P
cycles to be achieved with the common I/O data bus.
2.15
2.16
2.17
2.18
2.19
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UB , gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
P
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LB , gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
P
DQ7) to or from the lower part of the selected address during a Write or Read operation.
VDDF supply voltage
V
provides the power supply to the internal cores of the Flash memory component. It is
DDF
the main power supply for all Flash operations (Read, Program and Erase).
VCCP supply voltage
The V
Supply Voltage supplies the power for all operations (Read or Write) and for
CCP
driving the refresh logic, even when the device is not being accessed.
VDDQ supply voltage
V
provides the power supply for the Flash memory I/O pins. This allows all Outputs to be
DDQ
powered independently of the Flash Memory core power supply, V
.
DDF
11/22
Signal descriptions
M36L0T7060T2, M36L0T7060B2
2.20
VPPF Program supply voltage
V
is both a Flash control input and a Flash power supply pin. The two functions are
PPF
selected by the voltage range applied to the pin.
If V is kept in a low voltage range (0V to V
) V is seen as a control input. In this
PPF
PPF
DDQ
case a voltage lower than V
gives an absolute protection against Program or Erase,
PPLKF
while V
> V
enables these functions (see the M58LT128HTB datasheet for the
PPF
PP1
relevant values). V
is only sampled at the beginning of a Program or Erase; a change in
PPF
its value after the operation has started does not have any effect and Program or Erase
operations continue.
If V
is in the range of V
it acts as a power supply pin. In this condition V
must be
PPF
PPH
PPF
stable until the Program/Erase algorithm is completed.
2.21
VSS ground
V
is the common ground reference for all voltage measurements in the Flash (core and
SS
I/O Buffers) and PSRAM chips.
Note:
The Flash memory device in a system should have their supply voltage (V
) and the
DDF
program supply voltage V
decoupled with a 0.1 µF ceramic capacitor close to the pin
PPF
(high frequency, inherently low inductance capacitors should be as close as possible to the
package). See Figure 5: AC measurement load circuit. The PCB track widths should be
sufficient to carry the required V
program and erase currents.
PPF
12/22
M36L0T7060T2, M36L0T7060B2
Functional description
3
Functional description
The PSRAM and Flash memory components have separate power supplies but share the
same grounds. They are distinguished by three Chip Enable inputs: E for the Flash
F
memory and E1 and E2 for the PSRAM.
P
P
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is simultaneous read operations in the Flash memory and
the PSRAM which would result in a data bus contention. Therefore it is recommended to put
the other device in the high impedance state when reading the selected device.
Figure 3.
Functional block diagram
V
V
V
PPF DDQ
DDF
A22
E
F
G
F
128 Mbit
Flash
Memory
DQ0-DQ15
A0-A21
W
F
RP
F
WAIT
F
WP
L
F
F
K
F
V
CCP
E1
P
G
P
W
64 Mbit
PSRAM
P
E2
P
UB
P
LB
P
V
SS
AI13217
13/22
Functional description
M36L0T7060T2, M36L0T7060B2
(1)
Table 2.
Operation
Operating modes
GF WF
DQ0-
DQ7
DQ8-
DQ15
(2)
EF
LF RPF WAITF
E2P E1P WP GP LBP, UBP A21
(3)
Flash Read
Flash Write
VIL VIL VIH VIL
VIL VIH VIL VIL
VIH
VIH
Data Out
(3)
Data In
PSRAM must be disabled
Flash Address
Latch
Data Out or
Hi-Z(4)
VIL
X
VIH VIL VIH
Flash Output
Disable
VIL VIH VIH
X
VIH
Hi-Z
Hi-Z
Any PSRAM mode is allowed
Flash Standby VIH
X
X
X
X
X
X
VIH
VIL
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Flash Reset
X
Deep Power-
Down(5)
VIL
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Standby
(Deselected)
VIH VIH
X
X
X
X
X
X
Hi-Z
Flash memory must be disabled
(6)
VIH
Hi-Z
Hi-Z
Output Disable
No Read
VIH VIH
VIH VIH
Hi-Z
Hi-Z
Hi-Z
Upper Byte
Read
Data
Output
VIH VIL
VIL VIH
VIH
VIL
Lower Byte
Read
Data
Output
Hi-Z
Data
Data
VIH VIL
Word Read
No Write
VIL VIL
VIH VIH
VIH VIL
Valid Output Output
Any Flash memory mode is allowed
Invalid Invalid
Upper Byte
Write
Data
Invalid
Input
(7)
VIL VIH
Lower Byte
Write
Data
VIL VIH
VIL VIL
Invalid
Input
Data
Input
Data
Input
Word Write
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LT128HTB datasheet for
details.
3. LF can be tied to VIH if the valid address has been previously latched.
4. Depends on GF.
5. Deep Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state.
6. A0 to A21 can be either VIH or VIL but must valid before the read or write operation.
7. GP can be VIL during the Write operation if the following conditions are satisfied:
a- Write pulse is initiated by E1P (E1P Controlled Write timing), or cycle time of the previous operation cycle is satisfied.
b- G stays VIL during the entire Write cycle.
14/22
M36L0T7060T2, M36L0T7060B2
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Min
Max
TA
Ambient Operating Temperature
Temperature Under Bias
–25
–25
–55
–0.5
–0.2
85
85
°C
°C
°C
V
TBIAS
TSTG
VIO
Storage Temperature
125
3.6
2.5
Input or Output Voltage
VDDF
Flash Memory Core Supply Voltage
V
PSRAM and Input/Output Supply
Voltages
VDDQ, VCCP
–0.2
3.6
V
VPPF
IO
Flash Program Voltage
Output Short Circuit Current
Time for VPPF at VPPFH
–0.2
–
10
V
100
100
mA
tVPPFH
hours
15/22
DC and AC parameters
M36L0T7060T2, M36L0T7060B2
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and AC measurement conditions
Flash memories
Parameter
PSRAM
Unit
Min
Max
Min
Max
VDDF Supply Voltage
VCCP Supply Voltage
1.7
–
2.0
–
–
2.7
–
–
3.5
–
V
V
V
V
VDDQ Supply Voltage
2.7
8.5
3.5
9.5
VPPF Supply Voltage (Factory environment)
–
–
VPPF Supply Voltage (Application
environment)
–0.4
–25
VDDQ +0.4
85
–
–
V
Ambient Operating Temperature
Load Capacitance (CL)
–30
85
°C
pF
kΩ
ns
V
30
22
50
22
Output Circuit Resistors (R1, R2)
Input Rise and Fall Times
5
5
Input Pulse Voltages
0 to VDDQ
VDDQ/2
0 to VDDQ
VDDQ/2
Input and Output Timing Ref. Voltages
V
Figure 4.
AC measurement I/O waveform
V
DDQ
V
/2
DDQ
0V
AI06161
16/22
M36L0T7060T2, M36L0T7060B2
DC and AC parameters
Figure 5.
AC measurement load circuit
VDDQ
VDDF
VDDQ
R1
DEVICE
UNDER
TEST
CL
0.1µF
R2
0.1µF
CL includes JIG capacitance
AI08364B
(1)
Table 5.
Symbol
Device capacitance
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
12
15
pF
pF
COUT
VOUT = 0V
1. Sampled only, not 100% tested.
Please refer to the M58LT128HTB and M69KW096B datasheets for further DC and AC
characteristic values and illustrations.
17/22
Package mechanical
M36L0T7060T2, M36L0T7060B2
6
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6.
Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch,
bottom view outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
1. Drawing is not to scale.
18/22
M36L0T7060T2, M36L0T7060B2
Package mechanical
Table 6.
Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch,
package data
millimeters
Min
inches
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
–
E1
E2
e
–
–
FD
FE
FE1
SD
SE
19/22
Part numbering
M36L0T7060T2, M36L0T7060B2
7
Part numbering
Table 7.
Ordering information scheme
Example:
M36 L
0
T
7
0 6
0
T
2
ZAQ F
Device Type
M36 = Multichip package (Flash + RAM)
Flash 1 Architecture
L = Multilevel, Multiple Bank, Burst mode
Flash 2 Architecture
0 = No Die
Operating Voltage
T = VDDF = 1.7 to 2.0 V; VDDQ = VCCP = 2.7 to 3.5 V
Flash 1 Density
7 = 128 Mbit
Flash 2 Density
0 = No Die
RAM 1 Density
6 = 64 Mbit
RAM 0 Density
0 = No Die
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
2 = 90 nm Flash technology and Multilevel design, 85 ns speed; 0.13 µm RAM, 65 ns
speed
Package
ZAQ = Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape and reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the STMicroelectronics Sales Office nearest to you.
20/22
M36L0T7060T2, M36L0T7060B2
Revision history
8
Revision history
Table 8.
Date
Document revision history
Revision
Changes
30-May-2006
0.1
Initial release.
Document status changed from Target Specification to Preliminary
Data.
20-Apr-2007
1
Updated VDDF, VCCP and VDDQ voltage ranges.
Section 2.7: Flash Reset (RPF) updated.
21/22
M36L0T7060T2, M36L0T7060B2
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22/22
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