M36LLR8860M1ZAQE [STMICROELECTRONICS]

SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88;
M36LLR8860M1ZAQE
型号: M36LLR8860M1ZAQE
厂家: ST    ST
描述:

SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88

静态存储器 内存集成电路
文件: 总18页 (文件大小:462K)
中文:  中文翻译
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M36LLR8860T1, M36LLR8860D1  
M36LLR8860M1, M36LLR8860B1  
2 x 256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory  
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package  
FEATURES SUMMARY  
MULTI-CHIP PACKAGE  
Figure 1. Package  
2 dice of 256 Mbit (16Mb x16, Multiple  
Bank, Multi-level, Burst) Flash Memory  
1 die of 64 Mbit (4Mb x16) Pseudo SRAM  
SUPPLY VOLTAGE  
FBGA  
V
1.95V  
= V  
= V  
= V  
= 1.7 to  
DDQF  
DDF1  
DDF2  
CCP  
V
= 9V for fast program (12V tolerant)  
PP  
ELECTRONIC SIGNATURE  
Manufacturer Code: 20h  
LFBGA88 (ZAQ)  
8 x 10mm  
Top Configuration (Top + Top)  
M36LLR8860T1: 880Dh + 880Dh  
Mixed Configuration (Bottom + Top)  
M36LLR8860D1: 880Eh + 880Dh  
Mixed Configuration (Top + Bottom)  
M36LLR8860M1: 880Dh + 880Eh  
DUAL OPEATIONS  
proram/erase in one Bank while read in  
others  
Bottom Configuration (Bottom + Bottom)  
M36LLR8860B1: 880Eh + 880Eh  
No delay between read and write  
operations  
PACKAGE  
SECURITY  
Compliant with Lead-Free Soldering  
Processes  
Lead-Free Versions  
64 bit unique device number  
2112 bit user programmable OTP Cells  
FLASH MEMORY  
BLOCK LOCKING  
SYNCHRONOUS / ASYNCHRONOUS READ  
All blocks locked at power-up  
Any combination of blocks can be locked  
with zero latency  
Synchronous Burst Rad mode: 54MHz  
Asynchronous PaRead mode  
Random Acess: 85ns  
WP for Block Lock-Down  
F
Absolute Write Protection with V  
= V  
SS  
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMING TIME  
PPF  
PSRAM  
ACCESS TIME: 70ns  
ASYNCHRONOUS PAGE READ  
0µs typical Word program time using  
Buffer Enhanced Factory Program  
command  
Page Size: 16 words  
Subsequent read within page: 20ns  
MEMORY ORGANIZATION  
Multiple Bank Memory Array: 16 Mbit  
Banks  
Parameter Blocks (Top or Bottom  
location)  
LOW POWER FEATURES  
Temperature Compensated Refresh  
(TCR)  
Partial Array Refresh (PAR)  
Deep Power-Down (DPD) Mode  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
SYNCHRONOUS BURST READ/WRITE  
July 2005  
1/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
TABLE OF CONTENTS  
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Flash Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
PSRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Flash Chip Enable Inputs (E , E ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
F1  
F2  
Flash Output Enable Inputs (G , G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
F1  
F2  
Flash Write Enable (W ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
F
Flash Write Protect (WP ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
F
Flash Reset (RP ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
F
PSRAM Chip Enable input (E ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
P
PSRAM Write Enable (W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
P
PSRAM Output Enable (G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
P
PSRAM Upper Byte Enable (UB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
P
PSRAM Lower Byte Enable (LB ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
P
PSRAM Configuration Register Enable (CR ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
P
V
V
V
V
V
/V  
Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
DDF1 DDF2  
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
CCP  
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
DDQF  
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
PPF  
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
SS  
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
2/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Table 6. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 7. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Table 8. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15  
Table 9. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15  
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
3/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
SUMMARY DESCRIPTION  
The  
M36LLR8860T1,  
M36LLR8860D1,  
Flash Memory Components  
M36LLR8860M1 and M36LLR8860B1 combine  
three memory devices in a Multi-Chip Package:  
The M36LLR8860T1,  
M36LLR8860D1,  
M36LLR8860M1 and M36LLR8860B1 contain two  
256 Mbit Flash memories, the M30L0R8000T0  
and/or the M30L0R8000B0.  
two 256-Mbit, Multiple Bank Flash memories  
a 64-Mbit PseudoSRAM.  
For detailed information on how to use the devic-  
es, refer to the M30L0R8000(T/B)0 datasheet  
which is available from your local STMicroelec-  
tronics distributor and should be read in conjunc-  
tion with the M36LLR8860x1 datasheet.  
What differs between the M36LLR8860T1,  
M36LLR8860D1 and M36LLR8860B1 is the con-  
figuration of the two Flash memories:  
in the M36LLR8860T1, the two Flash  
memories, Flash 1 and Flash 2, have a Top  
Configuration (Parameter Blocks located at  
the top of the address space).  
PSRAM Component  
The  
M36LLR8860T1,  
M36LLR8860D1,  
M36LLR8860M1 and M36LLR8860B1 contain a  
64 Mbit PSRAM, the M69KB096AA.  
For detailed information on how to use the device,  
see the M69KB096AA datasheet which is avail-  
able from your local STMicroelectronics distributor  
and should be read in conjunction with the  
M36LLR8860x1 datasheet.  
in the M36LLR8860D1, Flash 1 has a Bottom  
Configuration (Parameter Blocks at the  
bottom of the address space) and Flash 2 has  
a Top Configuration.  
In the M36LLR8860M1, Flash 1 has a Top  
Configuration and Flash 2 has a Bottom  
Configuration.  
In the M36LLR8860B1, both Flash 1 and  
Flash 2 have a Bottom Configuration.  
Recommended operating conditions do not allow  
more than one memory to be active at the same  
time.  
The memory is offered in a Stacked LFBGA88  
(8x10mm, 8x10 ball array, 0.8mm pitch) package.  
In addition to the standard version, the package is  
also available in Lead-free version, in compliance  
with JEDEC Std J-STD-020B, the ST ECOPACK  
7191395 Specification, and the RoHS (Restriction  
of Hazardous Substances) directive. All packages  
are compliant with Lead-free soldering processes.  
The memory is supplied with all the bits erased  
(set to ‘1’).  
4/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Figure 2. Logic Diagram  
Table 1. Signal Names  
(1)  
Address Inputs  
A0-A23  
V
V
PPF  
DDQF  
V
V
V
DDF1  
DDF2  
CCP  
DQ0-DQ15 Common Data Input/Output  
24  
Common Flash and PSRAM Latch  
Enable Input  
16  
L
A0-A23  
DQ0-DQ15  
K
Common Flash and PSRAM Burst Clock  
E
F1  
Wait Data in Burst Mode for both Flash  
memories and PSRAM  
G
WAIT  
F1  
E
F2  
V
Flash 1 Power Supply  
Flash 2 Power Supply  
DDF1  
G
F2  
WAIT  
V
DDF2  
W
F
M36LLR8860T1  
M36LLR8860D1  
M36LLR8860M1  
M36LLR8860B1  
RP  
Common Flash Power Supply for I/O  
Buffers  
F
V
DDQF  
WP  
F
Common Flash Optional Supply Voltage  
for Fast Program & Erase  
V
L
PPF  
K
V
Common, Ground  
SS  
E
P
V
PSRAM Power Supply  
CCP  
G
P
NC  
DU  
Not Connected Internally  
Do Not Use as Internally Connected  
W
P
CR  
P
UB  
LB  
P
Flash Memory Signals  
P
E
Flash 1 Chip Enable Input  
Flash 1 Output Enable Input  
Flash 2 Chip Enable Input  
Flash 2 Output Enable Input  
F1  
G
E
F1  
V
SS  
AI10502c  
F2  
G
F2  
Common Flash Memory Write Enable  
Input  
W
F
RP  
Common Flash Memory Reset input  
F
Common Flash Memory Write Protect  
Input  
WP  
F
PSRAM Signals  
E
Chip Enable Input  
P
G
Output Enable Input  
P
W
Write Enable Input  
P
CR  
UB  
Configuration Register Enable Input  
Upper Byte Enable Input  
Lower Byte Enable Input  
P
P
LB  
P
Note: 1. Address Inputs A22-A23 are for the Flash memory com-  
ponents only.  
5/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Figure 3. LFBGA Connections (Top view through package)  
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU  
A4  
A5  
A3  
A2  
A1  
A0  
DU  
A21  
A22  
A9  
DU  
DU  
A11  
A12  
A13  
A15  
A16  
A18  
A19  
A23  
NC  
V
V
V
V
SS  
SS  
DDF2  
DDF1  
LB  
P
NC  
K
A17  
A7  
V
W
P
E
P
PPF  
NC  
WP  
L
A20  
A8  
A10  
A14  
WAIT  
DQ7  
DQ15  
F
A6  
UB  
P
RP  
W
F
F
G
H
J
DQ8  
DQ0  
DQ2  
DQ1  
DQ9  
DU  
DQ10  
DQ3  
DQ11  
NC  
DQ5  
DQ12  
DQ4  
DQ13  
DQ14  
DQ6  
E
F2  
G
P
G
F2  
NC  
G
V
DDQF  
F1  
E
K
L
DU  
V
V
V
CR  
F1  
CCP  
DDF2  
DDQF  
P
V
V
V
V
V
V
V
V
SS  
SS  
DDQF  
DDF1  
SS  
SS  
SS  
SS  
DU  
DU  
M
DU  
DU  
AI10503b  
6/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
SIGNAL DESCRIPTIONS  
See Figure 2., Logic Diagram and Table 1., Signal  
Names, for a brief overview of the signals connect-  
ed to this device.  
Flash Chip Enable Inputs (E , E ). The  
F1 F2  
Flash Chip Enable inputs activate the control logic,  
input buffers, decoders and sense amplifiers of the  
Flash memory component selected (E is used to  
F1  
Address Inputs (A0-A23). Addresses A0-A21  
are common inputs for the Flash memory and  
PSRAM components. The other lines (A23-A22)  
are inputs for the Flash memory components only.  
The Address Inputs select the cells in the memory  
array to access during Bus Read operations. Dur-  
ing Bus Write operations they control the com-  
mands sent to the Command Interface of the  
internal state machine. The Flash memories are  
select Flash 1, E is used to select Flash 2).  
F2  
When Chip Enable is Low, V , and Reset is High,  
IL  
V , the device is in active mode. When Chip En-  
IH  
able is at V the corresponding Flash memory are  
IH  
deselected, the outputs are high impedance and  
the power consumption is reduced to the standby  
level.  
It is not allowed to have E at V , E at V and  
F1  
IL  
F2  
IL  
accessed through the Chip Enable signal (E ) and  
E at V at the same time. Only one memory com-  
F
P IL  
through the Write Enable signal (W ), while the  
ponent can be enabled at a time.  
Flash Output Enable Inputs (G , G ). The  
F
PSRAM is accessed through the Chip Enable sig-  
F1  
F2  
nal (E ) and the Write Enable signal (W ).  
P
P
Output Enable pins control the data outputs during  
Flash memory Bus Read operations.  
It is not allowed to have E Low, and E Low at the  
F
P
same time.  
Flash Write Enable (W ). The Write Enable  
F
Data Input/Output (DQ0-DQ15). The Data I/O  
output the data stored at the selected address dur-  
ing a Bus Read operation or input a command or  
the data to be programmed during a Bus Write op-  
eration.  
controls the Bus Write operation of the Flash  
memories’ Command Interface. The data and ad-  
dress inputs are latched on the rising edge of Chip  
Enable or Write Enable whichever occurs first.  
Flash Write Protect (WP ). Write Protect is an  
F
For the PSRAM component, the upper Byte Data  
Inputs/Outputs (DQ8-DQ15) carry the data to or  
from the upper part of the selected address when  
input that gives an additional hardware protection  
for each block. When Write Protect is Low, V ,  
IL  
Lock-Down is enabled and the protection status of  
the Locked-Down blocks cannot be changed.  
Upper Byte Enable (UB ) is driven Low. The lower  
P
Byte Data Inputs/Outputs (DQ0-DQ7) carry the  
data to or from the lower part of the selected ad-  
When Write Protect is at High, V , Lock-Down is  
IH  
disabled and the Locked-Down blocks can be  
locked or unlocked. (See the Lock Status Table in  
the M30L0R8000T0/B0 datasheet).  
dress when Lower Byte Enable (LB ) is driven  
P
Low. When both UB and LB are disabled, the  
P
P
Data Inputs/ Outputs are high impedance.  
Flash Reset (RP ). The Reset input provides a  
F
Latch Enable (L). The Latch Enable pin is com-  
mon to the Flash memory and PSRAM compo-  
nents.  
hardware reset of the Flash memories. When Re-  
set is at V , the memory is in Reset mode: the out-  
IL  
puts are high impedance and the current  
consumption is reduced to the Reset Supply Cur-  
For details of how the Latch Enable signal be-  
haves, please refer to the datasheets of the re-  
spective memory components: M69KB096AA for  
the PSRAM and M30L0R8000T/B0 for the Flash  
memories.  
Clock (K). The Clock input pin is common to the  
Flash memory and PSRAM components.  
For details of how the Clock signal behaves,  
please refer to the datasheets of the respective  
memory components: M69KB096AA for the  
PSRAM and M30L0R8000T/B0 for the Flash  
memories.  
Wait (WAIT). WAIT is an output pin common to  
the Flash memory and PSRAM components. How-  
ever the WAIT signal does not behave in the same  
way for the PSRAM and the Flash memories.  
For details of how it behaves, please refer to the  
M69KB096AA datasheet for the PSRAM and to  
the M30L0R8000T/B0 datasheet for the Flash  
memories.  
rent I  
. Refer to Table 6., Flash Memory DC  
DD2  
Characteristics - Currents, for the value of I  
. Af-  
DD2  
ter Reset all blocks are in the Locked state and the  
Configuration Register is reset. When Reset is at  
V , the device is in normal operation. Exiting Re-  
IH  
set mode the device enters Asynchronous Read  
mode, but a negative transition of Chip Enable or  
Latch Enable is required to ensure valid data out-  
puts.  
The Reset pin can be interfaced with 3V logic with-  
out any additional circuitry. It can be tied to V  
RPH  
(refer to Table 7., Flash Memory DC Characteris-  
tics - Voltages).  
PSRAM Chip Enable input (E ). The Chip En-  
P
able input activates the PSRAM when driven Low  
(asserted). When deasserted (V ), the device is  
IH  
disabled, and goes automatically in low-power  
Standby mode or Deep Power-down mode.  
PSRAM Write Enable (W ). Write Enable, W ,  
P
P
controls the Bus Write operation of the PSRAM.  
7/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
When asserted (V ), the device is in Write mode  
and Write operations can be performed either to  
the configuration registers or to the memory array.  
V
Supply Voltage. V  
DDQF  
provides the  
IL  
DDQF  
power supply for the Flash memory. This allows all  
Outputs to be powered independently of the Flash  
memory and SRAM core power supplies, V  
DDF  
PSRAM Output Enable (G ). Output  
G , provides a high speed tri-state control, allow-  
P
Enable,  
P
and V  
.
CCP  
ing fast read/write cycles to be achieved with the  
common I/O data bus.  
V
Program Supply Voltage. V  
is both a  
PPF  
PPF  
control input and a power supply pin for the Flash  
memories. The two functions are selected by the  
voltage range applied to the pin.  
PSRAM Upper Byte Enable (UB ). The Upper  
P
Byte En-able, UB , gates the data on the Upper  
P
Byte Data Inputs/Outputs (DQ8-DQ15) to or from  
the upper part of the selected address during a  
Write or Read operation.  
If V  
is kept in a low voltage range (0V to V  
is seen as a control input. In this case a volt-  
)
DDQF  
PPF  
V
PPF  
age lower than V  
against Program or Erase, while V  
gives an absolute protection  
PPLK  
> V  
en-  
PPF  
PP1  
PSRAM Lower Byte Enable (LB ). The Lower  
P
ables these functions (see Tables 6 and 7, DC  
Characteristics for the relevant values). V is  
only sampled at the beginning of a Program or  
Erase; a change in its value after the operation has  
started does not have any effect and Program or  
Erase operations continue.  
Byte Enable, LB , gates the data on the Lower  
P
PPF  
Byte Data Inputs/Outputs (DQ0-DQ7) to or from  
the lower part of the selected address during a  
Write or Read operation.  
If both LB and UB are disabled (High) during an  
P
P
operation, the device will disable the data bus from  
receiving or transmitting data. Although the device  
will seem to be deselected, it remains in an active  
If V  
is in the range of V  
it acts as a power  
PPH  
PPF  
supply pin. In this condition V  
until the Program/Erase algorithm is completed.  
must be stable  
PPF  
mode as long as E remains Low.  
P
V
Ground. V is the common ground refer-  
SS  
SS  
PSRAM Configuration Register Enable (CR ).  
P
ence for all voltage measurements in the Flash  
(core and I/O Buffers) and PSRAM chips. It must  
be connected to the system ground.  
Note: Each Flash memory device in a system  
should have their supply voltage (V  
When this signal is driven High, V , Write opera-  
IH  
tions load either the value of the Refresh Configu-  
ration Register (RCR) or the Bus configuration  
register (BCR).  
) and  
DDF  
V
V
/V  
Supply Voltages. V  
and  
DDF1 DDF2  
DDF1  
the program supply voltage V  
decoupled  
PPF  
provide the power supply to the internal  
DDF2  
with a 0.1µF ceramic capacitor close to the pin  
(high frequency, inherently low inductance ca-  
pacitors should be as close as possible to the  
package). See Figure 6., AC Measurement  
Load Circuit. The PCB track widths should be  
cores of Flash 1 and Flash 2, respectively. It is the  
main power supply for all Flash memory opera-  
tions (Read, Program and Erase).  
V
Supply Voltage. V  
provides the power  
CCP  
CCP  
supply to the internal core of the PSRAM device. It  
is the main power supply for all PSRAM opera-  
tions.  
sufficient to carry the required V  
and erase currents.  
program  
PPF  
8/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
FUNCTIONAL DESCRIPTION  
The PSRAM and Flash memory components have  
separate power supplies but share the same  
grounds. They are distinguished by three Chip En-  
most common example is simultaneous read oper-  
ations on one of the Flash memories and the  
PSRAM which would result in a data bus conten-  
tion. Therefore it is recommended to put the other  
devices in the high impedance state when reading  
the selected device.  
able inputs: E and E for Flash 1 and Flash 2,  
F1  
F2  
respectively, and E for the PSRAM.  
P
Recommended operating conditions do not allow  
more than one device to be active at a time. The  
Figure 4. Functional Block Diagram  
V
DDF1  
E
F1  
F1  
Flash 1  
G
256 Mbit  
Flash  
Memory  
A22-A23  
RP  
F
V
V
V
DDF2  
DDQF  
PPF  
WP  
F
W
F
A0-A21  
Flash 2  
E
F2  
F2  
DQ0-DQ15  
G
WAIT  
256 Mbit  
Flash  
L
Memory  
K
V
SS  
V
CCP  
E
P
64 Mbit  
PSRAM  
G
P
W
P
CR  
P
UB  
LB  
P
P
AI10504b  
9/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Table 2. Main Operating Modes  
(5)  
(5)  
(4)  
L
RP  
E
CR  
G
W
LB ,UB  
P P  
W
Operation  
Flash Read  
Flash Write  
DQ15-DQ0  
G
E
WAIT  
F
F
F
P
P
P
P
F
F
F
(2)  
V
V
V
IH  
V
IH  
Flash Data Out  
V
IL  
IL  
IL  
IL  
PSRAM must be disabled.  
(2)  
V
V
V
IL  
V
IH  
Flash Data In  
IH  
V
IL  
Only one Flash memory can be  
enabled at a time.  
Flash Data Out  
Flash Address  
Latch  
V
IL  
V
IH  
V
IL  
V
IH  
X
(3)  
or Hi-Z  
Flash Output  
Disable  
V
V
V
V
V
V
X
Hi-Z  
IL  
IH  
IH  
IH  
Any PSRAM mode is allowed.  
Both Flash memories must be  
disabled.  
Flash Standby  
Flash Reset  
X
X
X
X
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
IH  
IH  
V
X
X
X
IL  
PSRAM data  
out  
V
V
V
V
V
V
V
V
PSRAM Read  
PSRAM Write  
IL  
IL  
IL  
IL  
IH  
IL  
V
V
X
PSRAM data in  
IL  
IL  
IL  
IL  
Both Flash memories must be disabled  
PSRAM Write  
Configuration  
Register  
V
IL  
V
IH  
V
X
PSRAM data in  
IH  
PSRAM  
Standby  
V
V
X
X
X
X
Hi-Z  
Hi-Z  
IH  
IH  
IL  
Any Flash memory mode is allowed. Only  
one Flash memory can be enabled at a time  
PSRAM Deep  
Power-Down  
V
X
X
X
Note: 1. X = Don't care.  
2. L can be tied to V if the valid address has been previously latched.  
F
IH  
3. Depends on G .  
F
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000T0 datasheet for details.  
5. E is either E or E , and G is either G or G according to the Flash memory enabled. Only one Flash memory can be enabled  
F
F1  
F2  
F
F1  
F2  
at a time.  
10/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
MAXIMUM RATING  
Stressing the device above the rating listed in the  
Absolute Maximum Ratings table may cause per-  
manent damage to the device. These are stress  
ratings only and operation of the device at these or  
any other conditions above those indicated in the  
Operating sections of this specification is not im-  
plied. Exposure to Absolute Maximum Rating con-  
ditions for extended periods may affect device  
reliability. Refer also to the STMicroelectronics  
SURE Program and other relevant quality docu-  
ments.  
Table 3. Absolute Maximum Ratings  
Value  
Symbol  
Parameter  
Unit  
Min  
–25  
–25  
–65  
Max  
85  
T
Ambient Operating Temperature  
Temperature Under Bias  
°C  
°C  
°C  
°C  
V
A
T
85  
BIAS  
T
Storage Temperature  
125  
(1)  
STG  
T
Lead Temperature During Soldering  
Input or Output Voltage  
LEAD  
V
IO  
–0.5  
–0.2  
–0.2  
3.6  
V
V
, V  
DDF1  
,
DDF2  
Core and Input/Output Supply Voltages  
2.45  
V
, V  
DDQF CCP  
V
PPF  
Flash Program Voltage  
12.6  
100  
100  
V
I
O
Output Short Circuit Current  
mA  
t
Time for V at V  
PPF PPFH  
hours  
VPPFH  
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,  
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.  
11/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
DC AND AC PARAMETERS  
This section summarizes the operating measure-  
ment conditions, and the DC and AC characteris-  
tics of the device. The parameters in the DC and  
AC characteristics Tables that follow, are derived  
from tests performed under the Measurement  
Conditions summarized in Table 4., Operating and  
AC Measurement Conditions. Designers should  
check that the operating conditions in their circuit  
match the operating conditions when relying on  
the quoted parameters.  
Table 4. Operating and AC Measurement Conditions  
Flash Memories  
PSRAM  
Parameter  
Unit  
Min  
1.7  
Max  
1.95  
Min  
Max  
V
V
V
/V  
Supply Voltages  
V
V
V
V
DDF1 DDF2  
Supply Voltage  
1.7  
1.95  
CCP  
Supply Voltage  
1.7  
8.5  
1.95  
9.5  
DDQF  
V
V
Supply Voltage (Factory environment)  
Supply Voltage (Application environment)  
PPF  
PPF  
V
+0.4  
–0.4  
–25  
V
°C  
pF  
kΩ  
ns  
V
DDQF  
Ambient Operating Temperature  
85  
–25  
85  
Load Capacitance (C )  
30  
16.7  
30  
L
Output Circuit Resistors (R , R )  
16.7  
1
2
Input Rise and Fall Times  
Input Pulse Voltages  
5
0 to V  
0 to V  
DDQF  
DDQF  
V
DDQF  
/2  
V
/2  
DDQF  
Input and Output Timing Ref. Voltages  
V
Figure 5. AC Measurement I/O Waveform  
Figure 6. AC Measurement Load Circuit  
VDDQF  
V
DDQF  
VDDF  
VDDQF  
V
/2  
DDQF  
R1  
0V  
DEVICE  
UNDER  
TEST  
AI06161b  
CL  
0.1µF  
R2  
0.1µF  
CL includes JIG capacitance  
AI08364c  
Table 5. Device Capacitance  
Symbol  
Parameter  
Test Condition  
Min  
Max  
14  
Unit  
C
V
IN  
= 0V  
= 0V  
Input Capacitance  
Output Capacitance  
pF  
pF  
IN  
C
V
OUT  
18  
OUT  
Note: Sampled only, not 100% tested.  
12/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Table 6. Flash Memory DC Characteristics - Currents  
Symbol  
Parameter  
Input Leakage Current  
Output Leakage Current  
Test Condition  
0V V  
Typ  
Max  
±1  
Unit  
µA  
I
LI  
IN  
I
LO  
0V V V  
OUT DDQF  
±1  
µA  
Supply Current  
Asynchronous Read (f=5MHz)  
E = V , G = V  
13  
15  
mA  
IL  
IH  
4 Word  
8 Word  
16  
18  
23  
25  
18  
20  
25  
27  
mA  
mA  
mA  
mA  
I
DD1  
Supply Current  
Synchronous Read (f=54MHz)  
16 Word  
Continuous  
Supply Current  
(Reset)  
I
RP = V ± 0.2V  
50  
110  
µA  
DD2  
SS  
I
I
E = V ± 0.2V  
Supply Current (Standby)  
50  
50  
8
110  
110  
20  
µA  
µA  
DD3  
DD  
E = V , G = V  
Supply Current (Automatic Standby)  
DD4  
IL  
IH  
V
= V  
PPH  
mA  
mA  
mA  
mA  
PP  
Supply Current (Program)  
Supply Current (Erase)  
V
= V  
= V  
10  
8
25  
PP  
PP  
DD  
(1)  
I
DD5  
V
20  
PPH  
V
= V  
DD  
10  
25  
PP  
Program/Erase in one Bank,  
Asynchronous Read in another  
Bank  
23  
40  
mA  
Supply Current  
(Dual Operations)  
(1,2)  
(1)  
I
DD6  
Program/Erase in one Bank,  
Synchronous Read (Continuous  
f=54MHz) in another Bank  
35  
50  
52  
mA  
µA  
Supply Current Program/ Erase  
Suspended (Standby)  
E = V ± 0.2V  
110  
I
DD  
DD7  
V
= V  
PPH  
2
5
5
5
5
5
5
mA  
µA  
mA  
µA  
µA  
µA  
PP  
V
V
Supply Current (Program)  
Supply Current (Erase)  
PP  
V
= V  
= V  
0.2  
2
PP  
PP  
DD  
(1)  
I
PP1  
V
PPH  
PP  
V
= V  
0.2  
0.2  
0.2  
PP  
PP  
DD  
I
V
V
Supply Current (Read)  
V
V  
V  
PP2  
PP  
DD  
(1)  
Supply Current (Standby)  
V
PP  
I
PP  
DD  
PP3  
Note: 1. Sampled only, not 100% tested.  
2. V Dual Operation current is the sum of read and program or erase currents.  
DDF  
13/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Table 7. Flash Memory DC Characteristics - Voltages  
Symbol  
Parameter  
Input Low Voltage  
Test Condition  
Min  
Typ  
Max  
Unit  
V
V
IL  
0
0.4  
V
V
V
–0.4  
V
+ 0.4  
DDQF  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
V
IH  
DDQF  
V
I
= 100µA  
OL  
0.1  
V
OL  
V
OH  
I
= –100µA  
–0.1  
V
OH  
DDQF  
V
V
Program Voltage-Logic  
Program Voltage Factory  
Program, Erase  
Program, Erase  
1.3  
8.5  
1.8  
9.0  
3.3  
9.5  
0.4  
1
V
PP1  
PP  
V
PPH  
V
PP  
V
V
PPLK  
Program or Erase Lockout  
V Lock Voltage  
DD  
V
V
LKO  
V
V
RPH  
RP pin Extended High Voltage  
3.3  
V
Table 8. PSRAM DC Characteristics  
Symbo  
Uni  
t
Parameter  
l
Test Condition  
Min.  
Typ  
Max.  
25  
Operating Current: Asynchronous Random  
Read/Write  
(1)  
70ns  
mA  
I
CC1  
I
CC1P  
(1)  
Operating Current: Asynchronous Page Read  
70ns  
15  
mA  
80MHz  
66MHz  
80MHz  
66MHz  
80MHz  
66MHz  
35  
30  
18  
15  
35  
30  
mA  
mA  
mA  
mA  
mA  
mA  
V
=V or V ,  
E = V ,  
IL  
Operating Current:  
Initial Access, Burst Read/Write  
CC  
IH  
IL  
(1)  
I
CC2  
I
= 0mA  
OUT  
Operating Current:  
Continuous Burst Read  
(1)  
I
CC3R  
(1  
Operating Current:  
Continuous Burst Write  
I
CC3W  
)
V
CC  
= V  
E = V  
or 0V,  
CCQ  
(2)  
V
Standby Current  
120  
µA  
I
SB  
CC  
IH  
I
0V V V  
IN CC  
Input Leakage Current  
Output Leakage Current  
Deep-Power Down Current  
1
1
µA  
µA  
µA  
LI  
I
LO  
G = V or E = V  
IH IH  
I
V
= V or V  
IN IH IL  
10  
ZZ  
V
+
CCQ  
0.2  
V
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
1.4  
V
V
V
V
IH  
V
0.2  
0.4  
IL  
0.8V  
CC  
V
OH  
I
= 0.2mA  
OH  
Q
V
OL  
I
= 0.2mA  
0.2V  
CCQ  
OL  
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to  
drive the output capacitance expected in the actual system.  
2. I (Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temper-  
SB  
ature compensated refresh threshold at +85°C). In order to achieve low standby current, all inputs must be driven either to V  
CCQ  
or V  
.
SS  
3. The Operating Temperature is +25°C.  
14/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
PACKAGE MECHANICAL  
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline  
D
D1  
e
SE  
E
E2 E1  
b
e
BALL "A1"  
ddd  
FE1 FE  
FD  
A
SD  
A2  
A1  
BGA-Z45  
Note: Drawing is not to scale.  
Table 9. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data  
millimeters  
Min  
inches  
Min  
Symbol  
Typ  
Max  
Typ  
Max  
A
A1  
A2  
b
1.400  
0.0551  
0.200  
0.0079  
1.000  
0.350  
8.000  
5.600  
0.0394  
0.0138  
0.3150  
0.2205  
0.300  
7.900  
0.400  
0.0118  
0.3110  
0.0157  
D
8.100  
0.3189  
D1  
ddd  
E
0.100  
0.0039  
10.000  
7.200  
8.800  
0.800  
1.200  
1.400  
0.400  
0.400  
0.600  
9.900  
10.100  
0.3937  
0.2835  
0.3465  
0.0315  
0.0472  
0.0551  
0.0157  
0.0157  
0.0236  
0.3898  
0.3976  
E1  
E2  
e
FD  
FE  
SD  
SE  
FE1  
15/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
PART NUMBERING  
Table 10. Ordering Information Scheme  
Example:  
M36 L  
L
R 8  
8
6
0 T 1 ZAQ T  
Device Type  
M36 = Multiple Memory Product (Multiple Flash + RAM)  
Flash 1 Architecture  
L = Multilevel, Multiple Bank, Burst mode  
Flash 2 Architecture  
L = Multi-Level, Multiple Bank, Burst mode  
Operating Voltage  
R = V  
= V  
= V  
= 1.7 to 1.95V  
DDQF  
DDF  
CCP  
Flash 1 Density  
8 = 256 Mbits  
Flash 2 Density  
8 = 256 Mbits  
RAM 1 Density  
6 = 64 Mbits  
RAM 0 Density  
0 = No Die  
Parameter Blocks Location  
T = Top Boot Block Flash  
B = Bottom Boot Block Flash  
D = Mixed (Flash 1 Bottom, Flash 2 Top)  
M = Mixed (Flash 1 Top, Flash 2 Bottom)  
Product Version  
1 = 0.13µm Flash technology (2 Chip Enable inputs, one for each Flash memory), 85ns speed;  
0.11µm PSRAM, 70ns speed, burst mode  
Package  
ZAQ = Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch  
Option  
Blank = Standard Packing  
T = Tape & Reel Packing  
E = Lead-free and RoHS Standard packing  
F = Lead-free and RoHS Tape & Reel packing  
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-  
tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-  
Microelectronics Sales Office nearest to you.  
16/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
REVISION HISTORY  
Table 11. Document Revision History  
Date  
Version  
Revision Details  
14-Sep-2004  
0.1  
First Issue  
LFBGA88 Lead-Free packages are compliant with the ST ECOPACK specification.  
M69KR096A PSRAM replaced by the M69KB096A PSRAM. M30L0R8000T/B0  
specifications updated.  
26-Oct-2004  
0.2  
17-Nov-2004  
29-Apr-2004  
0.3  
0.4  
M36LLR8860M1 part number added.  
Part Number M69KB096A changed to M69KB096AA throughout document.  
V
changed to V  
throughout document Figure 2. Figure 3., Table 3., Table 6.,  
DDQ  
DDQF . ,  
07-July-2005  
0.5  
Table 7.and Table 8. modified.  
17/18  
M36LLR8860T1, M36LLR8860D1, M36LLR8860M1, M36LLR8860B1  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
ECOPACK is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2005 STMicroelectronics - All rights reserved  
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18/18  

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