M36W108B120ZN6_技术文档

M36W108T

M36W108B

8 Mbit (1Mb x8, Boot Block) Flash Memory and

1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product

NOT FOR NEW DESIGN

■ M36W108T and M36W108B are replaced

respectively by the M36W108AT and

M36W108AB

■ SUPPLY VOLTAGE

– V

= V

= 2.7V to 3.6V: for Program,

CCS

CCF

Erase and Read

BGA

LGA

■ ACCESS TIME: 100ns

■ LOW POWER CONSUMPTION

– Read: 40mA max. (SRAM chip)

– Stand-by: 30µA max. (SRAM chip)

– Read: 10mA max. (Flash chip)

– Stand-by: 100µA max. (Flash chip)

LBGA48 (ZM)

6 x 8 solder balls

LGA48 (ZN)

6 x 8 solder lands

FLASH MEMORY

■ 8 Mbit (1Mb x 8) BOOT BLOCK ERASE

Figure 1. Logic Diagram

■ PROGRAMMING TIME: 10µs typical

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte

V

CCF CCS

– Status Register bits and Ready/Busy Output

■ MEMORY BLOCKS

– Boot Block (Top or Bottom location)

– Parameter and Main Blocks

20

8

A0-A19

DQ0-DQ7

RB

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ ERASE SUSPEND and RESUME MODES

W

EF

– Read and Program another Block during

Erase Suspend

M36W108T

M36W108B

G

■ 100,000 PROGRAM/ERASE CYCLES per

RP

E1S

E2S

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code, M36W108T: D2h

– Device Code, M36W108B: DCh

V

SS

SRAM

AI02509

■ 1 Mbit (128Kb x 8)

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

■ LOW V

DATA RETENTION: 2V

CC

May 1999

1/35

This is information on a product still in production but not recommended for new designs.

M36W108T, M36W108B

Figure 2. LBGA and LGA Connections (Top View)

1

2

3

4

5

6

A10

DQ5

DQ2

A0

E1S

A

B

C

D

E

F

W

A14

A18

NC

EF

A11

A8

G

DQ7

DQ4

DQ0

A6

V

CCS

SS

A17

A5

DQ1

A1

V

NC

DQ3

NC

SS

NC

A3

A2

V

A19

A7

A4

CCF

DQ6

A12

G

H

NC

A13

NC

RP

RB

E2S

A9

A16

A15

AI02508

Table 1. Signal Names

DESCRIPTION

The M36W108 is multi-chip device containing an

8 Mbit boot block Flash memory and a 1 Mbit of

SRAM. The device is offered in the new Chip

Scale Package solutions: LBGA48 1.0 mm ball

pitch and LGA48 1.0 mm land pitch.

The two components, of the package’s overall 9

Mbit of memory, are distinguishable by use of the

three chip enable lines: EF for the Flash memory,

E1S and E2S for the SRAM.

The Flash memory component is identical with the

M29W008 device. It is a non-volatile memory that

may be erased electrically at the block or chip level

and programmed in-system on a Byte-by-Byte ba-

A0-A16

Address Inputs

A17-A19

Address Inputs for Flash Chip

Data Input/Outputs, Command Inputs

for Flash Chip

DQ0-DQ7

EF

Chip Enable for Flash Chip

Chip Enable for SRAM Chip

Output Enable

E1S, E2S

G

W

Write Enable

sis using only a single 2.7V to 3.6V V

supply.

CCF

RP

RB

Reset for Flash Chip

For Program and Erase operations the necessary

high voltages are generated internally. The device

can also be programmed in standard program-

mers. The array matrix organization allows each

block to be erased and reprogrammed without af-

fecting other blocks.

Ready/Busy Output for Flash Chip

Supply Voltage for Flash Chip

Supply Voltage for SRAM Chip

Ground

V

CCF

V

CCS

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature, Programming, Block

V

SS

2/35

M36W108T, M36W108B

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(3)

T

–40 to 85

–50 to 125

–65 to 150

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

T

BIAS

T

STG

(2)

–0.5 to V +0.5

Input or Output Voltage

V

CC

IO

V

Flash Chip Supply Voltage

SRAM Chip Supply Voltage

EF, RP Voltage

–0.6 to 5

–0.3 to 4.6

0.6 to 13.5

0.7

V

CCF

V

CCS

V

(EF, RP)

PD

Power Dissipation

W

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

and Chip Erase, Erase Suspend and Resume are

DQ7, the Toggle Bits DQ6 and DQ2, the Error bit

written to the device in cycles of commands to a

DQ5 or the Erase Timer bit DQ3. Outputs are valid

Command Interface using standard microproces-

when Flash Chip Enable (EF) or SRAM Chip En-

sor write timings.

able (E1S or E2S) and Output Enable (G) are ac-

The SRAM component is a low power SRAM that

features fully static operation requiring no external

clocks or timing strobes, with equal address ac-

cess and cycle times. It requires a single 2.7V to

tive. The output is high impedance when the both

the Flash chip and the SRAM chip are deselected

or the outputs are disabled and when Reset (RP)

is at a V .

IL

3.6V V

supply, and all inputs and outputs are

CCS

Flash Chip Enable (EF). The Chip Enable input

for Flash activates the memory control logic, input

TTL compatible.

buffers, decoders and sense amplifiers. EF at V

IH

SIGNAL DESCRIPTIONS

deselects the memory and reduces the power con-

sumption to the standby level. EF can also be

used to control writing to the command register

and to the Flash memory array, while W remains

See Figure 1 and Table 1.

Address Inputs (A0-A16). Addresses A0 to A16

are common inputs for the Flash chip and the

SRAM chip. The address inputs for the Flash

memory or the SRAM array are latched during a

write operation on the falling edge of Flash Chip

Enable (EF), SRAM Chip Enable (E1S or E2S) or

Write Enable (W).

at V . It is not allowed to set EF at V , E1S at V

IL

and E2S at V at the same time.

IH

SRAM Chip Enable (E1S, E2S). The Chip En-

able inputs for SRAM activate the memory control

logic, input buffers, decoders and sense amplifi-

ers. E1S at V or E2S at V deselects the mem-

Address Inputs (A17-A19). Address A17 to A19

are address inputs for the Flash chip. They are

latched during a write operation on the falling edge

of Flash Chip Enable (EF) or Write Enable (W).

Data Input/Outputs (DQ0-DQ7). The input is

data to be programmed in the Flash or SRAM

memory array or a command to be written to the

C.I. of the Flash chip. Both are latched on the ris-

ing edge of Flash Chip Enable (EF), SRAM Chip

Enable (E1S or E2S) or Write Enable (W). The

output is data from the Flash memory or SRAM ar-

ray, the Electronic Signature Manufacturer or De-

vice codes or the Status register Data Polling bit

IH

IL

ory and reduces the power consumption to the

standby level. E1S and E2S can also be used to

control writing to the SRAM memory array, while

W remains at V . It is not allowed to set EF at V ,

IL

E1S at V and E2S at V at the same time.

IL

IH

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When G is High the outputs are High im-

pedance.

Write Enable (W). The Write Enable input con-

trols writing to the Command Register of the Flash

chip and Address/Data latches.

3/35

M36W108T, M36W108B

(1)

Table 3. Main Operation Modes

Operation Mode

EF

E1S

E2S

G

W

RP

DQ0-DQ7

Data Output

Data Input

Hi-Z

V

IH

V

IH

X

IL

IH

Flash Chip Read

V

IL

V

IH

X

IL

V

IH

V

IL

V

IH

SRAM Chip Read

X

V

IH

V

IH

X

IL

IH

IL

Flash Chip Write

V

IL

V

IH

X

IL

V

IH

V

IL

V

IH

SRAM Chip Write

X

V

IH

V

IH

V

IH

V

IH

X

IH

Flash Chip Output Disable

V

X

Hi-Z

IL

V

IH

V

IL

V

IH

SRAM Chip Output Disable

Flash Chip Stand-by

Hi-Z

V

IH

X

V

IH

X

Hi-Z

V

IH

V

IL

X

Hi-Z

Flash Chip Reset

V

IL

X

Hi-Z

IL

V

IH

V

IL

X

Hi-Z

SRAM Chip Stand-by

V

IL

X

Hi-Z

IL

Note: 1. X = V or V

.

IH

IL

Reset Input (RP). The Reset input provides

hardware reset of the Flash chip. Reset of the

V

Supply Voltage. Flash memory power sup-

CCF

ply for all operations (Read, Program and Erase).

Flash memory is achieved by pulling RP to V for

IL

V

Supply Voltage. SRAM power supply for

CCS

at least t

. When the reset pulse is given, if the

PLPX

all operations (Read, Program).

V

measurements.

Flash memory is in Read or Standby modes, it will

Ground. V is the reference for all voltage

SS

be available for new operations in t

rising edge of RP.

after the

PHEL

If the Flash memory is in Erase or Program mode

the reset will take t during which the Ready/

POWER SUPPLY

PLYH

Power Up. The Flash memory Command Inter-

face is reset on power up to Read Array. Either

Flash Chip Enable (EF) or Write Enable (W) inputs

Busy (RB) signal will be held at V . The end of the

IL

Flash memory reset will be indicated by the rising

edge of RB. A hardware reset during an Erase or

Program operation will corrupt the data being pro-

grammed or the block(s) being erased. See Table

17 and Figure 9.

must be tied to V during Power Up to allow max-

IH

imum security and the possibility to write a com-

mand on the first rising edge of EF and W. Any

write cycle initiation is blocked when V

is below

CCF

Ready/Busy Output (RB). Ready/Busy is an

open-drain output of the Flash chip. It gives the in-

ternal state of the Program/Erase Controller (P/

E.C.) of the Flash device. When RB is Low, the

Flash device is busy with a Program or Erase op-

eration and it will not accept any additional pro-

gram or erase instructions except the Erase

Suspend instruction. When RB is High, the Flash

device is ready for any Read, Program or Erase

operation. The RB will also be High when the

Flash memory is put in Erase Suspend or Standby

modes.

V

.

LKO

Supply Rails. Normal precautions must be taken

for supply voltage decoupling; each device in a

system should have the V

pled with a 0.1µF capacitor close to the V

, V

rails decou-

CCF

CCS

,

CCF

V

and V pins. The PCB trace widths should

CCS

SS

be sufficient to carry the V

currents and the V

and V

erase current required.

program

CCS

CCF

4/35

M36W108T, M36W108B

Figure 3. Internal Functional Arrangement

V

SS

CCF

RP

EF

RB

8 Mbit

Flash Memory

(1Mb x 8)

A0-A19

DQ0-DQ7

W

G

V

CCS

SS

A0-A16

1 Mbit SRAM

(128 Kb x 8)

E1S

E2S

AI02444

5/35

M36W108T, M36W108B

FLASH MEMORY COMPONENT

Organization and Architecture

Organization. The Flash chip is organized as

1Mbit x 8. The memory uses the address inputs

A0-A19 and the Data Input/Outputs DQ0-DQ7.

Memory control is provided by Chip Enable (EF),

Output Enable (G) and Write Enable (W) inputs.

Erase and Program operations are controlled by

an internal Program/Erase Controller (P/E.C.).

Status Register data output on DQ7 provides a

Data Polling signal, while Status Register data out-

puts on DQ6 and DQ2 provide Toggle signals to

indicate the state of the P/E.C. operations. A

Ready/Busy (RB) output indicates the completion

of the internal algorithms.

Memory Blocks. The device features asymmetri-

cally blocked architecture providing system mem-

ory integration. Both Top and Bottom Boot Block

devices have an array of 19 blocks, one Boot

Block of 16K Bytes, two Parameter Blocks of 8K

Bytes, one Main Block of 32K Bytes and fifteen

Main Blocks of 64K Bytes. The Top Boot Block

version has the Boot Block at the top of the mem-

ory address space and the Bottom Boot Block ver-

sion locates the Boot Block starting at the bottom.

The memory maps and block address tables are

showed in Figures 4, 5 and Tables 4, 5. Each

block can be erased separately, any combination

of blocks can be specified for multi-block erase or

the entire chip may be erased. The Erase opera-

tions are managed automatically by the P/E.C.

The block erase operation can be suspended in

order to read from or program to any block not be-

ing erased, and then resumed.

Device Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write

command, Output Disable, Standby and Reset

(see Table 6).

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature or the Status Register. Both Chip Enable

(EF) and Output Enable (G) must be low, with

Write Enable (W) high, in order to read the output

of the memory.

Table 4. Top Boot Block, Flash Block Address

Table 5. Bottom Boot Block, Flash Block

Address

Size (KWord)

Address Range

FC000h-FFFFFh

FA000h-FBFFFh

F8000h-F9FFFh

F0000h-F7FFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

Size (KWord)

Address Range

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

16

8

64

32

8

32

64

8

16

6/35

M36W108T, M36W108B

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch input

data to be programmed. A write operation is initi-

ated when Chip Enable (EF) is Low and Write En-

Instructions and Commands

Seven instructions are defined (see Table 7) to

perform Read Array, Auto Select (to read the Elec-

tronic Signature), Program, Block Erase, Chip

Erase, Erase Suspend and Erase Resume. The

internal P/E.C. automatically handles all timing

and verification of the Program and Erase opera-

tions. The Status Register Data Polling, Toggle,

Error bits and the RB output may be read at any

time, during programming or erase, to monitor the

progress of the operation.

able (W) is at V with Output Enable (G) at V .

IL

IH

Addresses are latched on the falling edge of W or

EF whichever occurs last. Commands and Input

Data are latched on the rising edge of W or EF

whichever occurs first.

Output Disable. The data outputs are high im-

pedance when the Output Enable (G) is at V with

IH

Write Enable (W) at V .

Standby. The memory is in standby when Chip

IH

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.).

Enable (EF) is at V and the P/E.C. is idle. The

IH

power consumption is reduced to the standby level

and the outputs are high impedance, independent

of the Output Enable (G) or Write Enable (W) in-

puts.

Automatic Standby. After 150ns of bus inactivity

and when CMOS levels are driving the addresses,

the chip automatically enters a pseudo-standby

mode where consumption is reduced to the CMOS

standby value, while outputs still drive the bus.

The C.I. latches commands written to the memory.

Commands are made of address and data se-

quences. Two coded cycles unlock the Command

Interface. They are followed by an input command

or a confirmation command. The coded sequence

consists of writing the data AAh at the address

5555h during the first cycle and the data 55h at the

address 2AAAh during the second cycle.

(1)

Table 6. Flash User Bus Operations

Operation

Read Byte

EF

G

W

RP

A0

X

A1

X

A6

X

A9

X

A12

X

A15

X

DQ0-DQ7

Data Output

Data Input

Hi-Z

V

IH

V

IH

IL

IH

V

IH

Write Byte

Output Disable

Stand-by

IL

V

IH

IL

IH

V

IH

X

Hi-Z

IH

V

Reset

X

Hi-Z

IL

Note: 1. X = V or V

.

IH

IL

Table 7. Read Flash Electronic Signature

Other

Addresses

Code

Device

EF

G

W

A0

A1

DQ0-DQ7

V

Manufact. Code

Don’t care

20h

D2h

DCh

IL

IH

IL

V

IH

V

IL

M36W108T

M36W108B

IL

Device Code

V

IL

V

IH

V

IL

7/35

M36W108T, M36W108B

Table 8. Flash Commands

Command sequencing must be followed exactly.

Any invalid combination of commands will reset

the device to Read Array. The increased number

of cycles has been chosen to assure maximum

data security.

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded cycles. Subsequent read opera-

tions will read the memory array addressed and

Hex Code

00h

Command

Invalid/Reserved

Chip Erase Confirm

Reserved

10h

20h

30h

Block Erase Resume/Confirm

Set-up Erase

output the data read. A wait state of t

is nec-

PLYH

80h

essary after Read/Reset prior to any valid read if

the memory was in an Erase or Program mode

when the RD instruction is given (see Table 17

and Figure 9).

Read Electronic Signature/

Block Protection Status

90h

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address 5555h

for command set-up. A subsequent read will out-

put the Manufacturer Code or the Device Code

(Electronic Signature) depending on the levels of

A0 and A1 (see Table 7). The Electronic Signature

can be read from the memory allowing program-

ming equipment or applications to automatically

match their interface to the characteristics of the

Flash memory. The Manufacturer Code, 20h, is

output when the addresses lines A0 and A1 are at

A0h

B0h

F0h

Program

Erase Suspend

Read Array/Reset

Instructions are composed of up to six cycles. The

first two cycles input a Coded Sequence to the

Command Interface which is common to all in-

structions (see Table 9). The third cycle inputs the

instruction set-up command. Subsequent cycles

output the addressed data or Electronic Signature

for Read operations. In order to give additional

data protection, the instructions for Program and

Block or Chip Erase require further command in-

puts. For a Program instruction, the fourth com-

mand cycle inputs the address and data to be

programmed. For an Erase instruction (block or

chip), the fourth and fifth cycles input a further

Coded Sequence before the Erase confirm com-

mand on the sixth cycle. Erasure of a memory

block may be suspended, in order to read data

from another block or to program data in another

block, and then resumed.

V , the Device Code is output when A0 is at V

IL

IH

with A1 at V . Other address inputs are ignored.

IL

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address 5555h on the third cycle after

two Coded Cycles. A fourth write operation latch-

es the Address and the Data to be written and

starts the P/E.C. Read operations output the Sta-

tus Register bits after the programming has start-

ed. Memory programming is made only by writing

’0’ in place of ’1’. Status bits DQ6 and DQ7 deter-

mine if programming is on-going and DQ5 allows

verification of any possible error. Programming at

an address not in blocks being erased is also pos-

sible during erase suspend. In this case, DQ2 will

toggle at the address being programmed.

When power is first applied or if V

falls below

CCF

V

ray.

, the command interface is reset to Read Ar-

LKO

8/35

M36W108T, M36W108B

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 5555h

on third cycle after the two Coded cycles. The

Block Erase Confirm command 30h is similarly

written on the sixth cycle after another two Coded

Cycles. During the input of the second command

an address within the block to be erased is given

and latched into the memory.

ond command given is not an erase confirm or if

the Coded Sequence is wrong, the instruction

aborts and the device is reset to Read Array. It is

not necessary to program the array with 00h first

as the P/E.C. will automatically do this before

erasing it to FFh. Read operations after the sixth

rising edge of W or EF output the Status Register

bits. A complete state of the chip erase operation

is given by the Status Register bits (see DQ2,

DQ3, DQ5, DQ6 and DQ7 description).

Additional block Erase Confirm commands and

block addresses can be written subsequently to

erase other blocks in parallel, without further Cod-

ed cycles. The erase will start after the erase tim-

eout period (see Erase Timer Bit DQ3 description).

Thus, additional Erase Confirm commands for oth-

er blocks must be given within this delay. The input

of a new Erase Confirm command will restart the

timeout period. The status of the internal timer can

be monitored through the level of DQ3, if DQ3 is ’0’

the Block Erase Command has been given and

the timeout is running, if DQ3 is ’1’, the timeout has

expired and the P/E.C. is erasing the block(s). If

the second command given is not an erase con-

firm or if the Coded cycles are wrong, the instruc-

tion aborts, and the device is reset to Read Array.

It is not necessary to program the block with 00h

as the P/E.C. will do this automatically before to

erasing to FFh. Read operations after the sixth ris-

ing edge of W or EF output the Status Register

bits.

Erase Suspend (ES) Instruction. The

Block

Erase operation may be suspended by this in-

struction which consists of writing the command

B0h without any specific address. No Coded Cy-

cles are required. It permits reading of data from

another block and programming in another block

while an erase operation is in progress. Erase sus-

pend is accepted only during the Block Erase in-

struction execution. Writing this command during

the erase timeout period will, in addition to sus-

pending the erase, terminate the timeout. The

Toggle bit DQ6 stops toggling when the P/E.C. is

suspended. The Toggle bits will stop toggling be-

tween 0.1µs and 15µs after the Erase Suspend

(ES) command has been written. The device will

then automatically be set to Read Memory Array

mode. When erase is suspended, a Read from

blocks being erased will output DQ2 toggling and

DQ6 at '1'. A Read from a block not being erased

returns valid data. During suspension the memory

will respond only to the Erase Resume (ER) and

the Program (PG) instructions. A Program opera-

tion can be initiated during Erase Suspend in one

of the blocks not being erased. It will result in both

DQ2 and DQ6 toggling when the data is being pro-

grammed. A Read/Reset command will definitively

abort erasure and result in invalid data in the

blocks being erased.

During the execution of the erase by the P/E.C.,

the memory only accepts the Erase Suspend (ES)

and Read/Reset (RD) instructions. A Read/Reset

command will definitively abort erasure and result

in invalid data in blocks being erased. A complete

state of the block erase operation is given by the

Status Register bits (see DQ2, DQ3, DQ5, DQ6

and DQ7 description).

Erase Resume (ER) Instruction. If an Erase

Suspend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

Chip Erase (CE) Instruction. This

instruction

uses six write cycles. The Erase Set-up command

80h is written to address 5555h on the third cycle

after the two Coded Cycles. The Chip Erase Con-

firm command 10h is similarly written on the sixth

cycle after another two Coded Cycles. If the sec-

9/35

M36W108T, M36W108B

Table 9. Flash Instructions

(1)

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

(3,7)

X

Addr.

Data

1+

Read Memory Array until a new write cycle is initiated.

F0h

Read/Reset

Memory

Array

(2,4)

RD

5555h

AAh

2AAAh

55h

5555h

F0h

Addr.

Data

Read Memory Array until a new write cycle

is initiated.

3+

Read Electronic Signature or Block

Protection Status until a new write cycle is

initiated. See Note 5 and 6.

5555h

AAh

2AAAh

55h

5555h

90h

Addr.

Data

(4)

Auto Select

Program

AS

Program

Address

(3,7)

5555h

AAh

2AAAh

55h

5555h

A0h

Addr.

Data

Read Data Polling or Toggle Bit

until Program completes.

PG

4

6

Program

Data

Additional

Block

Address

5555h

2AAAh

5555h

2AAAh

Addr.

Data

(8)

Block

BE

CE

Block Erase

Chip Erase

AAh

5555h

AAh

X

55h

2AAAh

55h

80h

5555h

80h

AAh

5555h

AAh

55h

2AAAh

55h

30h

5555h

10h

30h

(3,7)

Addr.

Data

6

1

Note 9

Addr.

Data

Erase

Suspend

Read until Toggle stops, then read all the data needed from any

Block(s) not being erased then Resume Erase.

(10)

ES

B0h

X

Addr.

Data

Erase

Resume

Read Data Polling or Toggle Bits until Erase completes or Erase

is suspended another time.

ER

30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before

PLYH

starting any new operation (see Table 14 and Figure 7).

3. X = Don’t care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. Signature Address bits A0, A1, at V will output Manufacturer code (20h). Address bits A0 at V and A1, at V will output Device

IL

IH

IL

code.

6. Block Protection Address: A0, at V , A1 at V and A13-A19 within the Block will output the Block Protection status.

IL

IH

7. For Coded cycles address inputs A15-A19 are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be

verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, real Data Polling or Toggle bit

until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

10/35

M36W108T, M36W108B

(1)

Table 10. Flash Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase block

in Erase Suspend

‘1’

‘0’

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits DQ5 for Program or Erase

Success.

Erase On-going

Data

Polling

7

Program Complete or data of

non erase block during Erase

Suspend

DQ

‘-1-0-1-0-1-0-1-’

DQ

Program On-going

Erase or Program On-going

Program Complete

Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C. operations are

completed or Erase Suspend is

6

Toggle Bit

Erase Complete or Erase

Suspend on currently

addressed block

‘-1-1-1-1-1-1-1-’

acknowledged.

‘1’

‘0’

Program or Erase Error

This bit is set to ‘1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started. Only

‘1’

‘0’

Erase Timeout Period Expired possible command entry is Erase Suspend

Erase

Time Bit

(ES).

3

Erase Timeout Period

On-going

An additional block to be erased in parallel

can be entered to the P/E.C.

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

Erase Error due to the

currently addressed block

(when DQ5 = ‘1’)

‘-1-0-1-0-1-0-1-’

Indicates the erase status and allows to

identify the erased block.

2

Toggle Bit

Program on-going, Erase

on-going on another block or

Erase Complete

‘1’

Erase Suspend read on non

Erase Suspend block

DQ

1

0

Reserved

Note: 1. Logic level ‘1’ is High, ‘0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

11/35

M36W108T, M36W108B

(1)

Table 11. Flash Polling and Toggle Bits

er blocks. During Program operation in Erase Sus-

pend Mode, DQ7 will have the same behaviour as

in the normal program execution outside of the

suspend mode.

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either G,

Mode

DQ7

0

DQ6

DQ2

Program

Erase

Toggle

1

Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

or EF when G is at V . The operation is complet-

IL

ed when two successive reads yield the same out-

put data. The next read will output the bit last

programmed or a '1' after erasing. The toggle bit

DQ6 is valid only during P/E.C. operations, that is

after the fourth W pulse for programming or after

the sixth W pulse for Erase. If the blocks selected

for erasure are protected, DQ6 will toggle for about

100µs and then return back to Read. DQ6 will be

set to '1' if a Read operation is attempted on an

Erase Suspend block. When erase is suspended

DQ6 will toggle during programming operations in

a block different to the block in Erase Suspend. Ei-

ther EF or G toggling will cause DQ6 to toggle.

See Figure 11 for Toggle Bit flowchart and Figure

15 for Toggle Bit waveforms.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. It can also be used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to '1' during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to '1' dur-

ing program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to '1', DQ2 will toggle if the faulty block

is addressed.

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

N/A

Erase Suspend Program

Toggle

Note: 1. Toggle if the address is within a block being erased.

‘1’ if the address is within a block not being erased.

Status Register Bits

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mand execution will automatically output these

five Status Register bits. The P/E.C. automatically

sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other

bits (DQ0, DQ1 and DQ4) are reserved for future

use and should be masked (see Table 10 and Ta-

ble 11).

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programming or

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocks selected for erasure are protected, DQ7 will

be set to '0' for about 100µs, and then return to the

previous addressed memory data value. See Fig-

ure 9 for the Data Polling flowchart and Figure 11

for the Data Polling waveforms. DQ7 will also flag

the Erase Suspend mode by switching from '0' to

'1' at the start of the Erase Suspend. In order to

monitor DQ7 in the Erase Suspend mode an ad-

dress within a block being erased must be provid-

ed. For a Read Operation in Erase Suspend

mode, DQ7 will output '1' if the read is attempted

on a block being erased and the data value on oth-

Error Bit (DQ5). This bit is set to '1' by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

the memory block. In case of an error in block

erase or program, the block in which the error oc-

curred or to which the programmed data belongs,

must be discarded. The DQ5 failure condition will

also appear if a user tries to program a '1' to a lo-

cation that is previously programmed to '0'. Other

Blocks may still be used. The error bit resets after

a Read/Reset (RD) instruction. In case of success

of Program or Erase, the error bit will be set to '0'.

Erase Timer Bit (DQ3). This bit is set to '0' by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50µs to 90µs, DQ3 returns

to '1'.

12/35

M36W108T, M36W108B

Table 12. Flash Program/Erase Times and Endurance

(T = 0 to 70 °C; V = 2.7 V to 3.6 V)

A

CC

Flash Memory Chip

Typical after

Parameter

Unit

Max

Min

Typ

100k W/E Cycles

Chip Erase (Preprogrammed)

Chip Erase

5

3.3

sec

µs

12

2.4

2.3

2.7

3.3

8

Boot Block Erase

Parameter Block Erase

Main Block (32Kb) Erase

Main Block (64Kb) Erase

Chip Program (Byte)

Byte Program

15

8

10

Program/Erase Cycles (per Block)

100,000

cycles

13/35

M36W108T, M36W108B

SRAM COMPONENT

Device Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write Ar-

ray, Output Disable, Power Down (see Table 13).

occurring edge. The Write cycle can be terminated

by the rising edge of E1S, the rising edge of W or

the falling edge of E2S, whichever occurs first.

If the Output is enabled (E1S=V , E2S=V and

IL

IH

G=V ), then W will return the outputs to high im-

IL

pedance within t

of its falling edge. Care must

WLQZ

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable (W) is at V with

Output Enable (G) at V , and both Chip Enables

(E1S and E2S) are asserted.

Valid data will be available at the eight output pins

be taken to avoid bus contention in this type of op-

eration. Data input must be valid for t before

DVWH

IH

the rising edge of Write Enable, or for t

be-

DVE1H

IL

fore the rising edge of E1S or for t

before the

DVE2L

falling edge of E2S, whichever occurs first, and re-

main valid for t , t or t (see Table

WHDX E1HDX

E2LDX

within t

after the last stable address, provid-

AVQV

22, Figures 17, 18, 19).

Output Disable. The data outputs are high im-

pedance when the Output Enable (G) is at V with

ing G is Low, E1S is Low and E2S is High. If Chip

Enable or Output Enable access times are not

met, data access will be measured from the limit-

IH

Write Enable (W) at V .

IH

ing parameter (t

, t

, or t

) rather

E1LQV E2HQV

GLQV

Power-Down. The SRAM chip has a Chip Enable

power-down feature which invokes an automatic

standby mode (see Table 21, Figure 16) whenever

than the address. Data out may be indeterminate

at t

, t

and t

, but data lines will al-

(see Table 21, Figure 14,

E1LQX E2HQX

GLQX

ways be valid at t

Figure 15).

AVQV

either Chip Enable is de-asserted (E1S=V or

IH

E2S=V ).

IL

Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever

Data Retention

the W and E1S pins are at V , with E2S at V . Ei-

The SRAM data retention performances as V

CCS

IL

IH

ther the Chip Enable inputs (E1S and E2S) or the

Write Enable input (W) must be de-asserted dur-

ing address transitions for subsequent write cy-

cles. Write begins with the concurrence of both

go down to V are described in Table 23 and Fig-

DR

ures 22, 23. In E1S controlled data retention

mode, minimum standby current mode is entered

when E1S ≥ V

– 0.2V and E2S ≤ 0.2V or

CCS

Chip Enables being active with W at V . A Write

begins at the latest transition among E1S going to

E2S ≥ V

– 0.2V. In E2S controlled data reten-

IL

CCS

tion mode, minimum standby current mode is en-

V , E2S going to V and W going to V . There-

tered when E2S ≤ 0.2V.

IL

IH

IL

fore, address setup time is referenced to Write En-

able and both Chip Enables as t , t and

AVWL AVE1L

t

respectively, and is determined by the latter

AVE2H

(1)

Table 13. SRAM User Bus Operations

Operation

E1S

E2S

W

G

DQ0-DQ7

Data Output

Data Input

Hi-Z

Power

Active

V

IL

V

IL

Read

Write

IH

V

IL

V

IL

X

Active

IH

V

IL

V

IH

Output Disable

Active

IH

V

X

Hi-Z

Stand-by TTL

Stand-by TTL/CMOS

IH

Power Down

V

X

Hi-Z

IL

Note: 1. X = V or V

IL

.

IH

14/35

M36W108T, M36W108B

Table 14. DC Characteristics

(T = 0 to 70°C, –20 to 85°C, –40 to 85°C; V

= V

= 2.7V to 3.6V)

A

CCF

CCS

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

–1

Max

1

Unit

µA

I

0V ≤ V ≤ V

/ V

CCF CCS

LI

IN

I

0V ≤ V

≤ V

/ V

–1

1

µA

LO

OUT

CCF CCS

EF = V , G = V , f = 6MHz,

IL

IH

I

Flash Chip Supply Current (Read)

10

mA

CCF1

V ≤ V

≤ V

OUT

CCF

(1)

Flash Chip Supply Current (Write)

Program or Erase in progress

EF = V ± 0.2V

20

100

40

µA

mA

µA

V

I

CCF2

I

Flash Chip Supply Current (Stand-by)

CCF3

CCF

E1S = V , E2S = V , f= 10MHz

IL

IH

I

SRAM Chip Supply Current (Read)

CCS1

E1S = V , E2S = V , f= 1MHz

10

IL

IH

(1)

SRAM Chip Supply Current (Write)

SRAM Chip Supply Current (Stand-by)

Flash Chip Input Low Voltage

Flash Chip Input High Voltage

SRAM Chip Input Low Voltage

SRAM Chip Input High Voltage

Flash Chip Output Low Voltage

Flash Chip Output High Voltage

SRAM Chip Output Low Voltage

SRAM Chip Output High Voltage

20

I

CCS2

I

20

CCS3

V

–0.5

0.8

ILF

0.7 V

V

+ 0.3

CCF

V

IHF

ILS

CCF

V

–0.3

2.2

0.4

+ 0.3

CCS

V

IHS

V

I

= 1.8mA

= –100µA

= 2.1mA

= –1.0mA

0.45

V

OLF

OL

I

V

– 0.4

V

OHF

OH

CCF

V

I

OL

0.4

V

OLS

V

2.2

V

OHS

OH

Note: 1. Sampled only, not 100% tested.

(1)

Table 15. Capacitance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: 1. Sampled only, not 100% tested.

Table 16. AC Measurement Conditions

Input Rise and Fall Times

Figure 5. AC Testing Load Circuit

0.8V

≤ 10ns

0 to 3V

1.5V

Input Pulse Voltages

1N914

Input and Output Timing Ref. Voltages

3.3kΩ

Figure 4. AC Testing Input/Output Waveforms

DEVICE

UNDER

TEST

OUT

= 30pF or 100pF

3V

C

L

1.5V

0V

AI01417

C

includes JIG capacitance

L

AI01968

15/35

M36W108T, M36W108B

Table 17. Flash Read AC Characteristics

(T = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V

A

= 2.7V to 3.6V)

CCF

Flash Memory Chip

100 120

C = 30pF C = 100pF

Symbol

Alt

Parameter

Test Condition

Unit

L

Min

Max

Min

Max

t

EF = V , G = V

Address Valid to Next Address Valid

Address Valid to Output Valid

100

120

ns

AVAV

RC

IL

t

EF = V , G = V

100

120

AVQV

ACC

IL

(1)

t

G = V

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

0

ns

t

LZ

IL

ELQX

(2)

t

G = V

100

120

t

CE

IL

ELQV

Output Enabled Low to Output

Transition

(1)

t

EF = V

ns

t

OLZ

IL

GLQX

(2)

t

EF = V

Output Enable Low to Output Valid

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

40

30

50

30

ns

OE

IL

GLQV

t

G = V

EHQX

OH

IL

(1)

t

HZ

G = V

t

IL

EHQZ

Output Enable High to Output

Transition

t

EF = V

ns

GHQX

OH

IL

(1)

t

DF

EF = V

Output Enable High to Output Hi-Z

30

10

30

10

ns

t

IL

GHQZ

t

EF = V , G = V

Address Transition to Output Transition

AXQX

OH

IL

t

RRB

PLYH

(1,3)

RP Low to Read Mode

µs

t

READY

t

RP High to Chip Enable Low

RP Pulse Width

50

500

0

50

500

0

ns

PHEL

PLPX

RH

t

RP

(4)

Chip Enabled Recovery Time

t

CCR

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of EF without increasing t

.

ELQV

ELQV GLQV

3. To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program Mode.

4. See Flash-SRAM Switching Waveforms.

16/35

M36W108T, M36W108B

Figure 6. Flash Read Mode AC Waveforms

17/35

M36W108T, M36W108B

Table 18. Flash Write AC Characteristics, Write Enable Controlled

(T = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V

A

= 2.7V to 3.6V)

CCF

Flash Memory Chip

100 120

C = 30pF C = 100pF

Symbol

Alt

Parameter

Unit

L

Min

Max

Min

Max

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

100

0

120

0

ns

µs

ns

AVAV

t

CS

ELWL

t

50

0

50

0

WLWH

WP

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

WHDX

t

0

WHEH

t

WPH

30

0

30

0

WHWL

t

AS

AVWL

t

50

0

50

0

WLAX

AH

t

GHWL

t

V

High to Chip Enable Low

CC

50

0

50

0

VCHEL

VCS

t

Write Enable High to Output Enable Low

WHGL

OEH

(1,2)

t

RP Rise Time to V

500

t

VIDR

ID

PHPHH

t

RP Pulse Width

PLPX

RP

(1)

t

Program Erase Valid to RB Delay

RP High to Write Enable Low

90

ns

µs

t

BUSY

WHRL

t

4

RSP

PHWL

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

18/35

M36W108T, M36W108B

Figure 7. Flash Write AC Waveforms, W Controlled

tAVAV

A0-A19

VALID

tWLAX

tAVWL

tWHEH

EF

G

tELWL

tWHGL

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7

V

CCF

tVCHEL

RB

tWHRL

AI02512

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

19/35

M36W108T, M36W108B

Table 19. Flash Write AC Characteristics, Chip Enable Controlled

(T = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V

A

= 2.7V to 3.6V)

CCF

Flash Memory Chip

100 120

C = 30pF C = 100pF

Symbol

Alt

Parameter

Unit

L

Min

Max

Min

Max

t

WC

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

100

0

120

0

ns

µs

ns

AVAV

t

WS

WLEL

t

50

0

50

0

ELEH

CP

DS

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

EHDX

DH

t

WH

0

EHWH

t

CPH

30

0

20

0

EHEL

t

AS

AVEL

t

50

0

50

0

ELAX

AH

t

GHEL

t

V

CC

High to Write Enable Low

50

0

50

0

VCHWL

VCS

t

Chip Enable High to Output Enable Low

EHGL

OEH

VIDR

(1,2)

t

RP Rise Time to V

500

t

ID

PHPHH

t

RP Pulse Width

PLPX

RP

(1)

t

Program Erase Valid to RB Delay

RP High to Write Enable Low

90

ns

µs

t

BUSY

EHRL

t

4

t

RSP

PHWL

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

20/35

M36W108T, M36W108B

Figure 8. Flash Write AC Waveforms, EF Controlled

tAVAV

VALID

A0-A19

tELAX

tAVEL

tEHWH

W

G

tWLEL

tEHGL

tGHEL

tELEH

EF

tEHEL

tDVEH

VALID

tEHDX

DQ0-DQ7

V

CCF

tVCHWL

RB

tEHRL

AI02513

Note: Address are latched on the falling edge of EF, Data is latched on the rising edge of EF.

Figure 9. Flash Read and Write AC Waveforms, RP Related

EF

tPHEL

W

tPHWL

RB

tPLPX

RP

tPHPHH

tPLYH

AI02514

21/35

M36W108T, M36W108B

(1)

Table 20. Flash Data Polling and Toggle Bits AC Characteristics

(T = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V

A

= 2.7V to 3.6V)

CCF

Flash Memory Chip

100

C = 30pF

120

C = 100pF

Symbol

Parameter

Unit

L

Min

Max

Min

Max

Write Enable High to DQ7 Valid (Program, W Controlled)

10

1.0

10

2400

10

1.0

10

2400

60

ms

sec

µs

t

WHQ7V

Write Enable High to DQ7 Valid (Chip Erase, W

Controlled)

60

2400

60

Chip Enable High to DQ7 Valid (Program, EF Controlled)

2400

60

t

EHQ7V

Chip Enable High to DQ7 Valid (Chip Erase, EF

Controlled)

1.0

sec

t

Q7 Valid to Output Valid (Data Polling)

40

2400

60

50

2400

60

ns

µs

Q7VQV

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Chip Erase)

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Chip Erase)

10

1.0

10

1.0

10

t

WHQV

sec

µs

2400

60

2400

60

t

EHQV

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

22/35

M36W108T, M36W108B

Figure 10. Flash Data Polling DQ7 AC Waveforms

23/35

M36W108T, M36W108B

Figure 11. Flash Data Toggle DQ6, DQ2 AC Waveforms

24/35

M36W108T, M36W108B

Figure 12. Flash Data Polling Flowchart

Figure 13. Flash Data Toggle Flowchart

START

READ

DQ2, DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

NO

DQ2, DQ6

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ7

READ DQ2, DQ6

DQ7

=

DATA

YES

NO

DQ2, DQ6

=

TOGGLE

NO

YES

FAIL

PASS

FAIL

PASS

AI01369

AI01873

25/35

M36W108T, M36W108B

Table 21. SRAM Read AC Characteristics

(T = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V

A

= 2.7 V to 3.6 V)

CCS

SRAM Chip

100

Symbol

Parameter

Unit

C = 100pF

L

Min

Max

t

Read Cycle Time

100

ns

AVAV

t

Address Valid to Output Valid

100

50

AVQV

t

Chip Enable 1 Low to Output Valid

Chip Enable 2 High to Output Valid

Output Enable Low to Output Valid

Chip Enable 1 Low to Output Transition

E1LQV

t

E2HQV

t

GLQV

t

10

5

E1LQX

t

Chip Enable 2 High to Output Transition

Output Enable Low to Output Transition

Chip Enable 1 High to Output Hi-Z

Chip Enable 2 Low to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

E2HQX

t

GLQX

t

0

30

E1HQZ

t

0

E2LQZ

t

0

GHQZ

t

15

0

AXQX

(1)

Chip Enable 1 Low or Chip Enable 2 High to Power Up

Chip Enable 1 High or Chip Enable 2 Low to Power Down

Chip Enable Recovery Time

t

PU

PD

(1)

(2)

100

ns

0

t

CCR

Note: 1. Sampled only. Not 100% tested.

2. See Flash-SRAM Switching Waveforms.

Figure 14. SRAM Read Mode AC Waveforms, Address Controlled

tAVAV

A0-A16

VALID

tAVQV

tAXQX

DQ0-DQ7

DATA VALID

AI02436

Note: E1S = Low, E2S = High, G = Low, W = High.

26/35

M36W108T, M36W108B

Figure 15. SRAM Read AC Waveforms, E1S, E2S or G Controlled

tAVAV

A0-A16

E1S

VALID

tAVQV

tE1LQV

tAXQX

tE1HQZ

tE1LQX

tE2HQV

tE2LQZ

E2S

tE2HQX

tGLQV

tGHQZ

G

tGLQX

DQ0-DQ7

DATA VALID

AI02435

Note: Write Enable (W) = High.

Figure 16. SRAM Stand-by AC Waveforms

E1S

E2S

tPU

tPD

I

CC4

50%

I

CC5

AI02517

27/35

M36W108T, M36W108B

Table 22. SRAM Write AC Characteristics

(T = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; V

A

= 2.7 V to 3.6 V)

CCS

SRAM Chip

100

Symbol

Parameter

Unit

C = 100pF

L

Min

Max

t

Write Cycle Time

100

0

ns

AVAV

t

Address Valid to Write Enable Low

Address Valid to Write Enable High

Write Enable Pulse Width

AVWL

t

80

70

0

AVWH

t

WLWH

t

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Output Transition

Write Enable Low to Output Hi-Z

WHAX

t

0

WHDX

t

0

WHQX

t

0

30

WLQZ

t

Address Valid to Chip Enable 1 Low

Address Valid to Chip Enable 2 High

Chip Enable 1 High to Address Transition

Chip Enable 2 Low to Address Transition

Input Valid to Write Enable High

0

AVE1L

t

0

AVE2H

t

0

E1HAX

t

0

E2LAX

t

40

DVWH

t

Input Valid to Chip Enable 1 High

Input Valid to Chip Enable 2 Low

DVE1H

t

DVE2L

Figure 17. SRAM Write AC Waveforms, W Controlled

tAVAV

A0-A16

VALID

tAVWH

tAVE1L

tAVE2H

tWHAX

E1S

E2S

tAVWL

tWLWH

W

tWLQZ

tWHQX

tWHDX

tDVWH

INPUT VALID

DQ0-DQ7

AI02434

Note: Output Enable (G) = Low.

28/35

M36W108T, M36W108B

Figure 18. SRAM Write AC Waveforms, E1S Controlled

tAVAV

A0-A16

E1S

VALID

tAVE1L

tAVWL

tE1HAX

E2S

W

tDVE1H

INPUT VALID

tWHDX

DQ0-DQ7

AI02433

Note: Output Enable (G) = High.

Figure 19. SRAM Write AC Waveforms, E2S Controlled

tAVAV

A0-A16

E1S

VALID

tAVE2H

tAVWL

tE2LAX

E2S

W

tDVE2L

INPUT VALID

tWHDX

DQ0-DQ7

AI02432

Note: Output Enable (G) = High.

29/35

M36W108T, M36W108B

(1, 2)

Table 23. SRAM Low V Data Retention Characteristics

CC

(T = 0 to 70 °C; V

A

= 2.7 V to 3.6 V)

CCS

Symbol

Parameter

Test Condition

Min

Max

20

Unit

V

= 3V, E1S ≥ V

– 0.2V,

CCS

I

Supply Current (Data Retention)

µA

CCDR

E2S ≥ V

– 0.2V or E2S ≤ 0.2V, f = 0

– 0.2V,E2S ≤ 0.2V, f = 0

CCS

V

DR

E1S ≥ V

Supply Voltage (Data Retention)

Chip Disable to Power Down

Operation Recovery Time

2

0

5

3.6

V

t

– 0.2V,E2S ≤ 0.2V, f = 0

CCS

ns

ms

CDR

t

R

Note: 1. All other Inputs V ≤ V – 0.2V or V ≤ 0.2V.

IH

CC

IL

2. Sampled only. Not 100% tested.

Figure 20. SRAM Low V Data Retention AC Waveforms, E1S Controlled

CC

tCDR

DATA RETENTION MODE

tR

V

CCS

2.7 V

2.2 V

V

DR

E1S ≥ V

– 0.2V

CCS

E1S

V

SS

AI02438

30/35

M36W108T, M36W108B

Figure 21. SRAM Low V Data Retention AC Waveforms, E2S Controlled

CC

DATA RETENTION MODE

V

CCS

E2S

2.7 V

tCDR

tR

V

DR

E2S ≤ 0.2V

0.4 V

V

SS

AI02437

Figure 22. Flash-SRAM Switching Waveforms

EF

tCCR

E1S

E2S

AI02510

31/35

M36W108T, M36W108B

Table 24. Ordering Information Scheme

Example:

M36W108T

100 ZM

1

T

Product Family

M36 = MMP (Flash + SRAM)

Operating Voltage

W = 2.7V to 3.6V

SRAM Chip size & organization

1 = 1 Mbit (128Kb x8)

Flash Chip size & orgnization

08 = 8 Mbit (1Mb x8), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

100 = 100 ns

120 = 120 ns

Package

ZM = LBGA48: 1mm pitch

ZN = LGA48: 1mm pitch

Temperature Range

1 = 0 to 70 °C

5 = –20 to 85 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

The M36W108T and M36W108B are replaced respectively by the new version M36W108AT and

M36W108AB.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

32/35

M36W108T, M36W108B

Table 25. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data

mm

inches

Symb

Typ

Min

1.150

0.250

–

Max

1.350

0.350

–

Typ

Min

0.045

0.010

–

Max

0.053

0.014

–

A

A1

A2

b

1.250

0.300

0.950

0.400

0.049

0.012

0.037

0.016

0.350

0.450

0.150

10.200

–

0.014

0.018

0.006

0.402

–

ddd

D

10.000

5.000

1.000

12.000

7.000

0.500

9.800

0.394

0.197

0.039

0.472

0.276

0.020

0.386

D1

e

–

E

11.800

12.200

–

0.465

0.480

–

E1

SD

SE

–

Figure 23. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline

D

D1

SD

BALL "A1"

SE

E

E1

ddd

e

b

A

A2

A1

BGA-Z01

Drawing is not to scale.

33/35

M36W108T, M36W108B

Table 26. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data

mm

inches

Symb

Typ

Min

Max

Typ

Min

Max

A

b

0.950

0.450

10.000

5.000

9.200

1.000

12.000

7.000

10.200

0.500

0.900

1.000

0.037

0.018

0.394

0.197

0.362

0.039

0.472

0.276

0.402

0.020

0.035

0.039

0.420

0.480

0.017

0.019

D

9.800

10.200

0.386

0.402

D1

D2

e

–

E

11.800

12.200

0.465

0.480

E1

E2

SD

SE

–

Figure 24. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline

D

D2

D1

SD

LAND "A1"

SE

E

E2 E1

e

b

A

LGA-Z02

Drawing is not to scale.

34/35

M36W108T, M36W108B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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http://www.st.com

35/35


型号：	M36W108B120ZN6
厂家：	ST
描述：	SPECIALTY MEMORY CIRCUIT, PBGA48, LGA-48 闪存存储内存集成电路静态存储器
文件：	总35页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36W108B120ZN6 [STMICROELECTRONICS]

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