M36W416TG70ZA1T_技术文档

M36W416TG

M36W416BG

16 Mbit (1Mb x16, Boot Block) Flash Memory

and 4Mbit (256Kb x16) SRAM, Multiple Memory Product

PRELIMINARY DATA

FEATURES SUMMARY

■ MULTIPLE MEMORY PRODUCT

SRAM

■ 4 Mbit (256Kb x 16)

– 16 Mbit (1Mb x 16) Boot Block Flash Memory

– 4 Mbit (256Kb x 16) SRAM

■ ACCESS TIME: 70ns

■ SUPPLY VOLTAGE

■ LOW V

DATA RETENTION: 1.5V

DDS

– V

= V

= 2.7V to 3.3V

DDF

DDQF

DDS

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

= V

= 2.7V to 3.3V

DDS

= 12V for Fast Program (optional)

PPF

Figure 1. Packages

■ ACCESS TIME: 70ns, 85ns

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M36W416TG: 88CEh

– Bottom Device Code, M36W416BG: 88CFh

FBGA

FLASH MEMORY

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

Stacked LFBGA66 (ZA)

12 x 8mm

■ PROGRAMMING TIME

– 10µs typical

– Double Word Programming Option

■ BLOCK LOCKING

– All blocks locked at Power up

– Any combination of blocks can be locked

– WP for Block Lock-Down

F

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ SECURITY

– 64 bit user programmable OTP cells

– 64 bit unique device identifier

– One parameter block permanently lockable

November 2002

1/62

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M36W416TG, M36W416BG

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A18-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

and VDDS Supply Voltages.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDF

and V

Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DDS

DDQF

Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PPF

SSF

and V

Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SSS

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Stacked LFBGA66-12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline15

Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Package Mechanical Data . 15

Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . . 16

Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package). 17

2/62

M36W416TG, M36W416BG

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

FLASH DEVICE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

FLASH SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Flash Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . 20

FLASH BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FLASH COMMAND INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12. Read Block Lock Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 13. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . 26

FLASH BLOCK LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 16. Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3/62

M36W416TG, M36W416BG

FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

V

Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PP

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 17. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18. Flash Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . 33

Figure 14. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . 34

Table 20. Flash Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . 35

Figure 15. Flash Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 21. Flash Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V . . . 39

IL

Figure 18. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20. SRAM Write AC Waveforms, WS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 21. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . 43

Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 43

Table 23. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 24. SRAM Low V

Data Retention AC Waveforms, E1 or UB / LB Controlled . . 45

S S S

DDS

Table 24. SRAM Low V

Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 25. Top Boot Block Addresses, M36W416TG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Bottom Boot Block Addresses, M36W416BG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4/62

M36W416TG, M36W416BG

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 27. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 31. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 32. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 25. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 27. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 30. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 59

Table 33. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 34. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 35. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5/62

M36W416TG, M36W416BG

SUMMARY DESCRIPTION

The M36W416TG is a low voltage Multiple Memo-

ry Product which combines two memory devices;

a 16 Mbit boot block Flash memory and a 4 Mbit

SRAM. Recommended operating conditions do

not allow both the Flash memory and the SRAM

memory to be active at the same time.

Table 1. Signal Names

A0-A17

Flash and SRAM Address Inputs

A18-A19

DQ0-DQ15

Address Inputs for Flash Chip only

Data Input/Output

The memory is offered in a Stacked LFBGA66

(12x8mm, 8 x 8 active ball, 0.8 mm pitch) package

and is supplied with all the bits erased (set to ‘1’).

V

Flash Power Supply

DDF

V

Flash Power Supply for I/O Buffers

DDQF

Flash Optional Supply Voltage for Fast

Program & Erase

Figure 2. Logic Diagram

V

PPF

V

DDS

DDQF

V

Flash Ground

SSF

DDS

SSS

V

DDF

PPF

SRAM Power Supply

SRAM Ground

20

16

A0-A19

DQ0-DQ15

NC

Not Connected Internally

E

Flash control functions

F

G

W

F

E

Chip Enable input

Output Enable input

Write Enable input

Reset input

F

G

F

RP

WP

W

F

M36W416TG

M36W416BG

RP

F

E1

S

WP

Write Protect input

F

E2

S

SRAM control functions

G

W

S

E1 , E2

Chip Enable inputs

S

UB

LB

G

Output Enable input

Write Enable input

S

W

S

UB

Upper Byte Enable input

Lower Byte Enable input

S

V

SSS

SSF

AI07940

LB

S

6/62

M36W416TG, M36W416BG

Figure 3. LFBGA Connections (Top view through package)

7/62

M36W416TG, M36W416BG

SIGNAL DESCRIPTION

See Figure 2 Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

of Chip Enable or a change of the address is re-

quired to ensure valid data outputs.

SRAM Chip Enable (E1 , E2 ). The Chip En-

S

Address Inputs (A0-A17). Addresses A0-A17

are common inputs for the Flash and the SRAM

components. The Address Inputs select the cells

in the memory array to access during Bus Read

operations. During Bus Write operations they con-

trol the commands sent to the Command Interface

of the internal state machine. The Flash memory is

able inputs activate the SRAM memory control

logic, input buffers and decoders. E1 at V or

S

IH

E2 at V deselects the memory and reduces the

S

IL

power consumption to the standby level. E1 or

S

E2 can also be used to control writing to the

S

SRAM memory array, while W remains at V It

S

IL.

is not allowed to set E at V and, E1 at V or

F

IL

S

IL

accessed through the Chip Enable (E ) and Write

E2 at V at the same time.

F

S

IL

Enable (W ) signals, while the SRAM is accessed

through two Chip Enable (ES) and Write Enable

F

SRAM Write Enable (W ). The Write Enable in-

put controls writing to the SRAM memory array.

W is active low.

S

(W ) signals.

S

Address Inputs (A18-A19). Addresses A18-A19

are inputs for the Flash component only. The

Flash memory is accessed through the Chip En-

SRAM Output Enable (G ). The Output Enable

gates the outputs through the data buffers during

S

a read operation of the SRAM memory. G is ac-

S

able (E ) and Write Enable (W ) signals

F

tive low.

Data Inputs/Outputs (DQ0-DQ15). The Data I/

O output the data stored at the selected address

during a Bus Read operation or input a command

or the data to be programmed during a Write Bus

operation.

SRAM Upper Byte Enable (UB ). The Upper

Byte Enable enables the upper bytes for SRAM

S

(DQ8-DQ15). UB is active low.

S

SRAM Lower Byte Enable (LB ). The

Lower

Byte Enable enables the lower bytes for SRAM

(DQ0-DQ7). LB is active low.

S

Flash Chip Enable (E ). The Chip Enable input

F

S

activates the Flash memory control logic, input

buffers, decoders and sense amplifiers. When

V

and V

Supply Voltages. V

DDF

pro-

DDF

DDS

vides the power supply to the internal core of the

Flash Memory device. It is the main power supply

for all operations (Read, Program and Erase).

Chip Enable is at V and Reset is at V the device

IL

IH

is in active mode. When Chip Enable is at V the

IH

memory is deselected, the outputs are high imped-

ance and the power consumption is reduced to the

standby level.

V

and V

Supply Voltage (2.7V to 3.3V).

DDS

DDQF

V

provides the power supply for the Flash

DDQF

memory I/O pins and V

supply for the SRAM control pins. This allows all

Outputs to be powered independently of the Flash

provides the power

DDS

Flash Output Enable (G ). The Output Enable

controls the data outputs during the Bus Read op-

eration of the Flash memory.

F

core power supply, V

. V

can be tied to

DDF

DDQF

Flash Write Enable (W ). The Write Enable con-

F

V

DDS.

trols the Bus Write operation of the Flash memo-

ry’s Command Interface. The data and address

inputs are latched on the rising edge of Chip En-

able, E , or Write Enable, W , whichever occurs

V

Program Supply Voltage. V

is both a

PPF

control input and a power supply pin for the Flash

memory. The two functions are selected by the

voltage range applied to the pin. The Supply Volt-

F

first.

age V

and the Program Supply Voltage V

DDF

PPF

Flash Write Protect (WP ). Write Protect is an

F

can be applied in any order.

input that gives an additional hardware protection

If V is kept in a low voltage range (0V to 3.6V)

PPF

for each block. When Write Protect is at V , the

IL

V

is seen as a control input. In this case a volt-

PPF

Lock-Down is enabled and the protection status of

the block cannot be changed. When Write Protect

age lower than V

gives an absolute protection

PPLK

against program or erase, while V

ables these functions (see Table 6, DC Character-

istics for the relevant values). V is only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

> V

en-

PPF

PP1

is at V , the Lock-Down is disabled and the block

IH

can be locked or unlocked. (refer to Table 6, Read

Protection Register and Protection Register Lock).

PPF

Flash Reset (RP ). The Reset input provides a

F

hardware reset of the Flash memory. When Reset

is at V , the memory is in reset mode: the outputs

IL

are high impedance and the current consumption

is minimized. After Reset all blocks are in the

If V

is in the range 11.4V to 12.6V it acts as a

PPF

power supply pin. In this condition V

stable until the Program/Erase algorithm is com-

pleted (see Table 19 and 20).

must be

PPF

Locked state. When Reset is at V , the device is

IH

in normal operation. Exiting reset mode the device

enters read array mode, but a negative transition

8/62

M36W416TG, M36W416BG

V

and V

Ground. V

and V are the

SSS

pacitor close to the pin. See Figure 9, AC

Measurement Load Circuit. The PCB trace

widths should be sufficient to carry the re-

SSF

SSS

SSF

ground reference for all voltage measurements in

the Flash and SRAM chips, respectively.

quired V

program and erase currents.

PPF

Note: Each device in a system should have V

D-

, V

DF DDQF

and V

decoupled with a 0.1µF ca-

PPF

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate

power supplies and grounds and are distinguished

simultaneous read operations on the Flash and

the SRAM which would result in a data bus con-

tention. Therefore it is recommended to put the

SRAM in the high impedance state when reading

the Flash and vice versa (see Table 2 Main Oper-

ation Modes for details).

by three chip enable inputs: E for the Flash mem-

F

ory and E1 and E2 for the SRAM.

S

Recommended operating conditions do not allow

both the Flash and the SRAM to be in active mode

at the same time. The most common example is

Figure 4. Functional Block Diagram

V

PPF

DDQF

DDF

E

G

F

W

RP

WP

Flash Memory

16 Mbit (x16)

A18-A19

A0-A17

V

SSF

V

DQ0-DQ15

DDS

E1

S

E2

S

SRAM

G

W

4 Mbit (x16)

S

UB

LB

V

SSS

AI07941

9/62

M36W416TG, M36W416BG

Table 2. Main Operation Modes

Operation

E

G

W

RP

WP

X

V

E1

E2

G

W

UB

LB

S

DQ7-DQ0 DQ15-DQ8

Data Output

F

PPF

S

Mode

V

Read

Don’t care

or

SRAM must be disabled

IL

IH

V

DDF

V

IH

V

IH

Write

X

Data Input

IL

V

PPFH

Block

Locking

V

X

Don’t care

SRAM must be disabled

X

IL

IH

IL

Standby

Reset

X

Don’t care

Any SRAM mode is allowed

Hi-Z

IH

V

X

IL

Output

Disable

V

IH

V

IH

Don’t care

Any SRAM mode is allowed

Hi-Z

IL

IH

V

Flash must be disabled

Data out Word Read

IL

IH

IL

IH

IL

IH

V

Read

Write

Data out

Hi-Z

IL

IH

V

Data out

IL

X

V

Data in Word Write

IL

X

V

Data in

Hi-Z

IH

V

IL

Data in

IH

Standby/

Power

Down

V

X

Hi-Z

IH

IL

Any Flash mode is allowable

V

IH

V

IH

X

V

IH

V

X

Hi-Z

IL

Data

Retention

V

IH

V

IH

X

V

IH

V

IH

V

IH

V

Any Flash mode is allowable

IL

IH

IL

Output

Disable

V

IH

V

IL

IH

Note: X = Don’t care = V or V , V = 12V ± 5%.

PPFH

IL

IH

10/62

M36W416TG, M36W416BG

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 3. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–40

–55

–0.5

–0.6

–0.5

Max

85

(1)

T

°C

V

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Flash Supply Voltage

Program Voltage

T

125

150

BIAS

T

STG

V

IO

V

+0.3

DDQF

V

, V

3.8

13

V

DDF DDQF

V

PPF

V

SRAM Supply Voltage

3.8

V

DDS

Note: 1. Depends on range.

11/62

M36W416TG, M36W416BG

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 4,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 4. Operating and AC Measurement Conditions

SRAM

70

Flash Memory

70/85

Parameter

Units

Min

Max

–

Min

2.7

Max

3.3

85

V

Supply Voltage

–

V

DDF

= V

Supply Voltage

DDS

2.7

– 40

3.3

85

2.7

DDQF

Ambient Operating Temperature

– 40

°C

pF

Load Capacitance (C )

30

50

L

Input Rise and Fall Times

1V/ns

5ns

0 to V

DDQF

Input Pulse Voltages

V

DDQF

V

DDQF

/2

V /2

DDQF

Input and Output Timing Ref. Voltages

Figure 5. AC Measurement I/O Waveform

Figure 6. AC Measurement Load Circuit

V

DDQF

V

DDQ

V

/2

DDQ

V

DDQF

0V

V

DDF

25kΩ

AI90258

DEVICE

UNDER

TEST

Note: V

means V

= V

DDQF DDS

DDQ

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI90259

L

Table 5. Device Capacitance

Symbol

Parameter

Test Condition

Typ

Max

12

Unit

C

V

= 0V, f=1 MHz

Input Capacitance

Output Capacitance

pF

IN

C

OUT

V

OUT

15

Note: Sampled only, not 100% tested.

12/62

M36W416TG, M36W416BG

Table 6. DC Characteristics

Symbol

Parameter

Device

Flash & SRAM

Flash

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V ≤ V ≤ V

Input Leakage Current

LI

IN

DDQF

0V ≤ V

≤ V

±10

µA

OUT

DDQF

I

LO

Output Leakage Current

≤ V

OUT

DDQF,

SRAM

Flash

±1

50

µA

SRAM Outputs Hi-Z

E = V

± 0.2V

F

DDQF

15

7

RP = V

F

DDQ

E1 ≥ V

– 0.2V

S

DDS

V

≥ V

– 0.2V or V

DDS IN

IN

≤ 0.2V

15

µA

I

V

DD

Standby Current

f = fmax (A0-A17 and DQ0-

DDS

DQ15 only)

SRAM

f = 0 (G , W , UB and LB )

S

E1 ≥ V

– 0.2V

S

DDS

V

≥ V

– 0.2V or

7

15

IN

DDS

V

IN

≤ 0.2V, f = 0

I

RP = V

± 0.2V

SSF

Supply Current (Reset)

Supply Current

Flash

SRAM

Flash

15

50

12

µA

DDD

F

f = fmax = 1/

,

AVAV

5.5

mA

V

≤ 0.2V, I

= 0 mA

IN

OUT

I

DD

f = 1MHz,

≤ 0.2V, I

1.5

10

3

mA

= 0 mA

IN

OUT

I

E = V , G = V f = 5 MHz

F IL F IH,

Supply Current (Read)

Supply Current (Program)

20

DDR

Program in progress

= 12V ± 5%

V

PPF

I

DDW

Program in progress

= V

10

5

20

mA

µA

V

PPF

DDF

Erase in progress

= 12V ± 5%

V

PPF

I

Supply Current (Erase)

Flash

DDE

Erase in progress

5

20

V

= V

PPF

DDF

Supply Current

(Program/Erase Suspend)

E = V

± 0.2V,

F

DDQF

I

Flash

50

DDES

Erase suspended

Program Current

(Read or Standby)

I

V

> V

400

µA

PP1

PPF

DDF

Program Current

(Read or Standby)

I

≤ V

Flash

5

µA

PP2

PPF

DDF

I

RP = V

± 0.2V

Program Current (Reset)

PPR

F

SSF

V

= 12V ± 0.5V

PPF

10

mA

Program in progress

Program Current

(Program)

I

Flash

PPW

V

= V

PPF

DDF

5

mA

Program in progress

13/62

M36W416TG, M36W416BG

Symbol

Parameter

Device

Test Condition

= 12V ± 0.5V

Min

Typ

Max

Unit

V

PPF

10

mA

Erase in progress

I

Program Current (Erase)

Flash

PPE

V

= V

PPF

DDF

5

µA

V

Erase in progress

V

= V

≥ 2.7V

Input Low Voltage

Input High Voltage

Flash & SRAM

–0.3

0.7

0.8

IL

DDQF

DDS

V

DDQF

V

IH

≥ 2.7V

V

DDQF

+0.3

V

= V

= V min

DDS DD

DDQF

V

Output Low Voltage

Output High Voltage

Flash & SRAM

0.1

V

OL

I

OL

= 100µA

= V

= V min

DD

V

–0.1

DDQF

DDS

DDQ

V

OH

I

= –100µA

OH

Program Voltage

(Program or Erase

operations)

V

Flash

1.65

11.4

3.6

12.6

1

V

PP1

Program Voltage

(Program or Erase

operations)

V

PPFH

Program Voltage

(Program and Erase lock-

out)

V

PPLK

V

DDF

Supply Voltage

V

LKO

2

(Program and Erase lock-

out)

14/62

M36W416TG, M36W416BG

PACKAGE MECHANICAL

Figure 7. Stacked LFBGA66-12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline

D

D2

D1

SE

b

E

E1

BALL "A1"

e

ddd

FE

FD

SD

e

A

A2

A1

BGA-Z12

Note: Drawing is not to scale.

Table 7. Stacked LFBGA66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, Package Mechanical Data

millimeters

inches

Symbol

Typ

Min

Max

Typ

Min

Max

A

A1

A2

b

1.400

0.0551

0.300

0.0118

1.100

0.0433

0.400

12.000

5.600

8.800

0.300

0.500

0.0157

0.4724

0.2205

0.3465

0.0118

0.0197

D

–

D1

D2

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.600

1.200

0.400

–

0.3150

0.2205

0.0315

0.0630

0.0472

0.0157

–

E1

e

FD

FE

SD

SE

15/62

M36W416TG, M36W416BG

Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)

16/62

M36W416TG, M36W416BG

Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)

17/62

M36W416TG, M36W416BG

PART NUMBERING

Table 8. Ordering Information Scheme

Example:

M36W416 T

G

70 ZA

6

T

Device Type

M36 = MMP (Flash + SRAM)

Operating Voltage

W = V

= 2.7V to 3.3V, V

= V

= 2.7V to 3.3V

DDQF

DDF

DDS

SRAM Chip Size & Organization

4 = 4 Mbit (256Kb x 16 bit)

Flash Chip Size & Organization

16 = 16 Mbit (x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

SRAM Component

G = 4Mb, 0.16µm, 70ns, 3V

Speed

70 = 70ns

85 = 85ns

Package

ZA = LFBGA66: 12x8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70°C

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 9. Daisy Chain Ordering Scheme

Example:

M36W416TG

-ZA T

Device Type

M36W416TG

Daisy Chain

-ZA = LFBGA66: 12x8mm, 0.8mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

18/62

M36W416TG, M36W416BG

FLASH DEVICE

The M36W416TG contains one 16 Mbit Flash

memory. This section describes how to use the

Flash device and all signals refer to the Flash de-

vice.

FLASH SUMMARY DESCRIPTION

The Flash Memory is a 16 Mbit (1 Mbit x 16) non-

volatile device that can be erased electrically at

the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (2.7 to 3.6V)

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

supply. V

is used to drive the I/O pin down to

DDQF

1.65V. An optional 12V V

vided to speed up customer programming.

power supply is pro-

PPF

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system design. The Protection Register is divid-

ed into two 64 bit segments, the first one contains

a unique device number written by ST, while the

second one is one-time-programmable by the us-

er. The user programmable segment can be per-

manently protected. The Security Block,

parameter block 0, can be permanently protected

by the user. Figure 11, shows the Flash Security

Block Memory Map.

The device features an asymmetrical blocked ar-

chitecture with an array of 39 blocks: 8 Parameter

Blocks of 4 KWords and 31 Main Blocks of 32

KWords. The M36W416TG has the Parameter

Blocks at the top of the memory address space

while the M36W416BG locates the Parameter

Blocks starting from the bottom. The memory

maps are shown in Figure 10, Block Addresses.

The Flash Memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

When V

≤ V

all blocks are protected

PPF

PPLK

against program or erase. All blocks are locked at

Power Up.

19/62

M36W416TG, M36W416BG

Figure 10. Flash Block Addresses

Top Boot Block Addresses

Bottom Boot Block Addresses

FFFFF

4 KWords

FF000

32 KWords

F8000

F7FFF

Total of 8

4 KWord Blocks

F0000

Total of 31

32 KWord Blocks

F8FFF

4 KWords

F8000

F7FFF

32 KWords

F0000

0FFFF

32 KWords

4 KWords

08000

07FFF

Total of 31

07000

32 KWord Blocks

Total of 8

0FFFF

4 KWord Blocks

32 KWords

08000

07FFF

00FFF

00000

32 KWords

4 KWords

00000

AI90256

Note: Also see Appendix A, Tables 25 and 26 for a full listing of the Flash Block Addresses.

Figure 11. Flash Security Block and Protection Register Memory Map

PROTECTION REGISTER

88h

SECURITY BLOCK

User Programmable OTP

85h

84h

Parameter Block # 0

Unique device number

81h

Protection Register Lock

2

1

0

80h

AI07905

20/62

M36W416TG, M36W416BG

FLASH BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 2, Main Operation Modes, for a

summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Characteristics, for details of the timing require-

ments.

Output Disable. The data outputs are high im-

pedance when the Output Enable is at V .

IH

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at V and the device is in

IH

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

able must be at V in order to perform a read op-

V

during a program or erase operation, the de-

IL

IH

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 12, Flash Read Mode AC Waveforms, and

Table 18, Flash Read AC Characteristics, for de-

tails of when the output becomes valid.

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity even if Chip Enable is Low, V , and the supply

IL

current is reduced to I

. The data Inputs/Out-

DD1

puts will still output data if a bus Read operation is

in progress.

Reset. During Reset mode when Output Enable

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

is Low, V , the memory is deselected and the out-

puts are high impedance. The memory is in Reset

IL

mode when Reset is at V . The power consump-

IL

and Write Enable are at V with Output Enable at

tion is reduced to the Standby level, independently

IL

V . Commands, Input Data and Addresses are

latched on the rising edge of Write Enable or Chip

Enable, whichever occurs first.

See Figures 13 and 14, Flash Write AC Wave-

forms, and Tables 19 and 20, Flash Write AC

from the Chip Enable, Output Enable or Write En-

IH

able inputs. If Reset is pulled to V during a Pro-

SS

gram or Erase, this operation is aborted and the

memory content is no longer valid.

21/62

M36W416TG, M36W416BG

FLASH COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time during, to

monitor the progress of the operation, or the Pro-

gram/Erase states. See Appendix 29, Table 33,

Write State Machine Current/Next, for a summary

of the Command Interface.

Area, allowing programming equipment or appli-

cations to automatically match their interface to

the characteristics of the device. One Bus Write

cycle is required to issue the Read Query Com-

mand. Once the command is issued subsequent

Bus Read operations read from the Common

Flash Interface Memory Area. See Appendix B,

Common Flash Interface, Tables 27, 28, 29, 30,

31 and 32 for details on the information contained

in the Common Flash Interface memory area.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Erase command.

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

. Com-

DD

LKO

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 10, Com-

mands, in conjunction with the text descriptions

below.

Read Memory Array Command

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Erase aborts if Reset turns to V . As data integrity

IL

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

Read Status Register Command

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register at any address, until another

command is issued. See Table 17, Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 14, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 28, Erase Flowchart and

Pseudo Code, for a suggested flowchart for using

the Erase command.

Program Command

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program Command.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code, the

Block Lock and Lock-Down Status, or the Protec-

tion and Lock Register. See Tables 11, 12 and 13

for the valid address.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 14, Program, Erase

Times and Program/Erase Endurance Cycles.

Read CFI Query Command

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Programming aborts if Reset goes to V . As data

integrity cannot be guaranteed when the program

IL

22/62

M36W416TG, M36W416BG

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix C, Figure 25, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Protection Program commands will also be ac-

cepted. The block being erased may be protected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programmed correctly.

Double Word Program Command

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

Chip Enable to V . Program/Erase is aborted if

IH

Reset turns to V .

IL

See Appendix C, Figure 27, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

29, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

ed when V is not at V

. The command can

but the result is

PPFH

PP

PPFH

be executed if V is below V

PP

not guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

Program/Erase Resume Command

■ The first bus cycle sets up the Double Word

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

See Appendix C, Figure 27, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

29, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Resume command.

ming aborts if Reset goes to V . As data integrity

IL

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 26, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Protection Register Program Command

The Protection Register Program command is

used to Program the 64 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The first bus cycle sets up the Protection

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Block Lock, Block Lock-Down or

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register protects bit 2 of the Protec-

tion Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of the Security Block (see Figure 11,

Flash Security Block and Protection Register

Memory Map). Attempting to program a previously

protected Protection Register will result in a Status

Register error. The protection of the Protection

23/62

M36W416TG, M36W416BG

Register and/or the Security Block is not revers-

ible.

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock command.

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 31, Protection

Register Program Flowchart and Pseudo Code,

for the flowchart for using the Protection Register

Program command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 16 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Block Lock-Down Command

Two Bus Write cycles are required to issue the

Block Lock command.

A locked block cannot be Programmed or Erased,

or have its protection status changed when WP is

F

■ The first bus cycle sets up the Block Lock

low, V . When WP is high, V the Lock-Down

IL F IH,

command.

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

■ The second Bus Write cycle latches the block

address.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 16 shows the protection status after issuing

a Block Lock command.

command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation.

Block Unlock Command

The Blocks Unlock command is used to unlock a

block, allowing the block to be programmed or

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 16 shows the protection sta-

tus after issuing a Block Lock-Down command.

Refer to the section, Block Locking, for a detailed

explanation.

24/62

M36W416TG, M36W416BG

Table 10. Flash Commands

Bus Write Operations

No. of

Commands

1st Cycle

2nd Cycle

Addr

3nd Cycle

Addr

Cycles

Bus

Op.

Bus

Op.

Bus

Op.

Addr Data

Data

Read

Addr

Read Memory Array

Read Status Register

1+

Write

X

FFh

70h

Data

Read

Status

Register

X

Signature

Read Electronic Signature

Read CFI Query

Erase

1+

2

Write

X

90h

98h

20h

Signature

Read

Write

(2)

Addr

CFI Addr

Query

D0h

Block

Addr

40h or

10h

Data

Input

Program

2

3

Write

X

Write

Addr

Data

Input

Data

Input

(3)

30h

Addr 1

Write

Addr 2

Double Word Program

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

1

Write

X

50h

B0h

D0h

Block

Address

Block Lock

2

Write

X

60h

C0h

Write

01h

D0h

2Fh

Block

Address

Block Unlock

Block Lock-Down

Block

Address

Protection Register

Program

Data

Input

Address

Note: 1. X = Don’t Care.

2. The signature addresses are listed in Tables 11, 12 and 13.

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 11. Read Electronic Signature

E

G

W

Code

Device

A0

A1

A2-A7

A8-A19

DQ0-DQ7

DQ8-DQ15

F

Manufacture.

Code

V

IL

V

IH

V

IL

V

IL

0

Don’t Care

20h

00h

IL

V

M36W416TG

M36W416BG

0

Don’t Care

CEh

CFh

88h

IL

IH

IL

Device Code

V

IH

V

IL

IH

Note:

RP = V .

F IH

25/62

M36W416TG, M36W416BG

Table 12. Read Block Lock Signature

E

G

W

Block Status

Locked Block

A0

A1 A2-A7

A8-A11

A12-A19

DQ0 DQ1 DQ2-DQ15

F

V

IL

V

IH

V

IL

V

0

Don’t Care Block Address

1

0

00h

IL

IH

V

IL

V

Unlocked Block

IL

IH

Locked-Down

Block

(1)

V

IL

V

IH

0

Don’t Care Block Address

1

00h

IL

IH

X

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

Table 13. Read Protection Register and Lock Register

E

G

W

Word

A0-A7

A8-A19

DQ0

DQ1

DQ2

DQ3-DQ7 DQ8-DQ15

F

OTP Prot.

data

Security

prot. data

V

IL

V

IH

Lock

80h Don’t Care

0

00h

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h Don’t Care

82h Don’t Care

83h Don’t Care

84h Don’t Care

ID data

IL

ID data

85h Don’t Care OTP data

86h Don’t Care OTP data

87h Don’t Care OTP data

88h Don’t Care OTP data

OTP data

OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

Table 14. Program, Erase Times and Program/Erase Endurance Cycles

M36W416TG

Parameter

Word Program

Test Conditions

Unit

Min

Typ

10

Max

200

5

V

PP

= V

DD

µs

V

= 12V ±5%

= V

Double Word Program

10

µs

PP

0.16

0.32

0.02

0.04

1

s

PP

Main Block Program

V

5

s

PP

DD

V

= 12V ±5%

= V

4

s

PP

Parameter Block Program

Main Block Erase

V

4

s

PP

DD

= 12V ±5%

= V

10

s

PP

V

1

s

PP

DD

= 12V ±5%

= V

0.8

s

PP

Parameter Block Erase

V

PP

DD

Program/Erase Cycles (per Block)

100,000

cycles

26/62

M36W416TG, M36W416BG

FLASH BLOCK LOCKING

The Flash memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their lock status cannot be

changed using software commands alone. A

Locked or Unlocked block can be Locked-Down by

issuing the Lock-Down command. Locked-Down

blocks revert to the Locked state when the device

is reset or powered-down.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■ V ≤ V

- the third level offers a complete

PP

PPLK

The Lock-Down function is dependent on the WP

hardware protection against program and erase

on all blocks.

F

input pin. When WP =0 (V ), the blocks in the

F

IL

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

The lock status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 16, de-

WP =1 (V ) the Lock-Down function is disabled

F

IH

fines all of the possible protection states (WP ,

F

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be relocked

DQ1, DQ0), and Appendix C, Figure 30, shows a

flowchart for the locking operations.

Reading a Block’s Lock Status

(1,1,1) and unlocked (1,1,0) as desired while WP

F

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 12,

will output the lock status of that block. The lock

status is represented by DQ0 and DQ1. DQ0 indi-

cates the Block Lock/Unlock status and is set by

the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

remains high. When WP is low , blocks that were

F

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

F

resets all blocks , including those in Lock-Down, to

the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the protection status will be changed. After

completing any desired lock, read, or program op-

erations, resume the erase operation with the

Erase Resume command.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Unlocked State

Locking operations cannot be performed during a

program suspend. Refer to Appendix D, Com-

mand Interface and Program/Erase Controller

State, for detailed information on which com-

mands are valid during erase suspend.

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

27/62

M36W416TG, M36W416BG

Table 15. Block Lock Status

Item

Address

Data

Block Lock Configuration

LOCK

Block is Unlocked

Block is Locked

DQ0=0

DQ0=1

DQ1=1

xx002

Block is Locked-Down

Table 16. Protection Status

Current

(1)

Next Protection Status

(1)

Protection Status

(WP , DQ1, DQ0)

F

(WP , DQ1, DQ0)

F

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

After

WP transition

Program/Erase

Current State

Allowed

F

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The protection status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block)

as read in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

F

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

F

IH

28/62

M36W416TG, M36W416BG

FLASH STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

or Output Enable returns to V . Either Chip En-

IH

able or Output Enable must be toggled to update

the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

The bits in the Status Register are summarized in

Table 17, Status Register Bits. Refer to Table 17

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

V

Status (Bit 3). The V

Status bit can be

PP

used to identify an invalid voltage on the V pin

during Program and Erase operations. The V

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

PP

cur if V becomes invalid during an operation.

PP

After the Program/Erase Controller completes its

When the V Status bit is Low (set to ‘0’), the volt-

PP

operation the Erase Status, Program Status, V

age on the V pin was sampled at a valid voltage;

PP

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

29/62

M36W416TG, M36W416BG

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 17. Status Register Bits

Bit

Name

Logic Level

Definition

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

PP

Status

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

30/62

M36W416TG, M36W416BG

Figure 12. Flash Read Mode AC Waveforms

tAVAV

VALID

A0-A19

tAVQV

tAXQX

E

F

tELQV

tELQX

tEHQX

tEHQZ

G

F

tGLQV

tGHQX

tGHQZ

tGLQX

DQ0-DQ15

VALID

OUTPUTS

ENABLED

ADDR. VALID

CHIP ENABLE

DATA VALID

STANDBY

AI07906

Table 18. Flash Read AC Characteristics

Flash

Unit

Symbol

Alt

Parameter

70

85

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

Max

Min

ns

AVAV

RC

t

ACC

AVQV

(1)

t

Address Transition to Output Transition

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

0

t

OH

AXQX

(1)

(2)

(1)

(2)

(1)

t

Min

Max

Min

Max

Min

ns

t

OH

EHQX

t

20

70

0

20

85

0

t

HZ

EHQZ

t

Chip Enable Low to Output Valid

t

CE

ELQV

ELQX

t

LZ

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

t

0

t

OH

GHQX

t

20

0

20

0

t

DF

GHQZ

t

OE

GLQV

GLQX

t

OLZ

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

F

ELQV GLQV

F

31/62

M36W416TG, M36W416BG

Figure 13. Flash Write AC Waveforms, Write Enable Controlled

32/62

M36W416TG, M36W416BG

Table 19. Flash Write AC Characteristics, Write Enable Controlled

Flash

Unit

Symbol

Alt

Parameter

70

45

0

85

45

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

AVWH

AS

DS

CS

t

DVWH

t

ELWL

t

70

85

ELQV

(1,2)

Output Valid to V

Low

0

t

PPF

QVVPL

t

Output Valid to Write Protect Low

V High to Write Enable High

PPF

QVWPL

(1)

t

200

0

200

0

t

VPS

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

WHAX

AH

t

0

WHDX

WHEH

DH

CH

t

0

t

25

20

25

45

25

20

25

45

WHEL

WHGL

t

WHWL

WPH

t

WLWH

WP

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V

< 3.6V).

PPF

33/62

M36W416TG, M36W416BG

Figure 14. Flash Write AC Waveforms, Chip Enable Controlled

34/62

M36W416TG, M36W416BG

Table 20. Flash Write AC Characteristics, Chip Enable Controlled

Flash

Unit

Symbol

Alt

Parameter

70

45

0

85

45

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

AVEH

AS

DS

AH

t

DVEH

t

Chip Enable High to Address Transition

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

EHAX

t

0

EHDX

DH

t

CPH

25

0

25

0

EHEL

t

EHGL

t

WH

EHWH

t

CP

45

70

45

85

ELEH

t

ELQV

(1,2)

Output Valid to V

Low

Min

0

ns

t

PPF

QVVPL

t

Data Valid to Write Protect Low

V High to Chip Enable High

PPF

QVWPL

(1)

t

200

0

200

0

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

Write Protect High to Chip Enable High

WLEL

t

45

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V

< 3.6V).

PPF

35/62

M36W416TG, M36W416BG

Figure 15. Flash Power-Up and Reset AC Waveforms

W , E ,G

tPHWL

tPHEL

tPHGL

F

tPHWL

tPHEL

tPHGL

RP

F

tVDHPH

tPLPH

Reset

V

, V

DDF

DDQF

Power-Up

AI07909b

Table 21. Flash Power-Up and Reset AC Characteristics

Flash

Symbol

Parameter

Test Condition

Unit

70

85

During

Program and

Erase

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip Enable

Low, Output Enable Low

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

F

36/62

M36W416TG, M36W416BG

SRAM DEVICE

This section describes how to use the SRAM and

all signals refer to it.

SRAM SUMMARY DESCRIPTION

The SRAM is a 4 Mbit asynchronous random ac-

cess memory which features super low voltage op-

eration and low current consumption with an

access time of 70 ns under all conditions. The

memory operations can be performed using a sin-

gle low voltage supply, 2.7V to 3.3V, which is the

same as the Flash component’s voltage supply.

Figure 16. SRAM Logic Diagram

DATA IN DRIVERS

A0-A10

256Kb x 16

RAM Array

DQ0-DQ7

2048 x 2048

DQ8-DQ15

COLUMN DECODER

UB_S

W_S

A11-A17

G_S

LB_S

E1_S

E2_S

POWER-DOWN

CIRCUIT

UB_S

LB_S

AI07939

37/62

M36W416TG, M36W416BG

SRAM OPERATIONS

There are five standard operations that control the

SRAM component. These are Bus Read, Bus

Write, Standby/Power-down, Data Retention and

Output Disable. A summary is shown in Table 2,

Main Operation Modes

E1 , the rising edge of W or the falling edge of

S S

E2 , whichever occurs first.

S

If the Output is enabled (E1 =V , E2 =V and

S

IL

S

IH

G =V ), then W will return the outputs to high im-

S

IL

S

pedance within t

of its falling edge. Care must

WLQZ

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

be taken to avoid bus contention in this type of op-

eration. The Data input must be valid for t

be-

DVWH

mode whenever Write Enable, W , is at V , Out-

S

IH

DVE1H

put Enable, G , is at V , Chip Enable, E1 , is at

S

IL

V , Chip Enable, E2 , is at V , and one or both of

the falling edge of E2 , whichever occurs first, and

IL

S

IH

S

the Byte Enable inputs, UB and LB is/are at V .

remain valid for t

, t

or t

(see Table

S

IL

WHDX E1HAX

E2LAX

23, Figures 20, 21, 22 and 23).

Valid data will be available on the output pins after

a time of t after the last stable address. If the

Chip Enable or Output Enable access times are

Standby/Power-Down. The SRAM component

has a chip enabled power-down feature which in-

vokes an automatic standby mode (see Table 22,

Figure 19). The SRAM is in Standby mode when-

AVQV

not met, data access will be measured from the

limiting parameter (t

, t

, or t

) rath-

E1LQV E2HQV

GLQV

er than the address. Data out may be indetermi-

nate at t , t and t , but data lines

ever either Chip Enable is deasserted, E1 at V

S IH

or E2 at V . It is also possible when UB and LB

S

E1LQX E2HQX

GLQX

S

IL

S

will always be valid at t

17 and 18).

(see Table 22, Figures

are at V .

AVQV

IH

Data Retention. The SRAM data retention per-

formance as V goes down to V are de-

Write. Write operations are used to write data to

DDS

DR

the SRAM. The SRAM is in Write mode whenever

scribed in Table 24 and Figure 24. In E1

controlled data retention mode, the minimum

standby current mode is entered when

S

W and E1 are at V , and E2 is at V . Either

S

IL

S

IH

the Chip Enable inputs, E1 and E2 , or the Write

S

Enable input, W , must be deasserted during ad-

dress transitions for subsequent write cycles.

E1 ≥ V

– 0.2V

and

E2 ≤ 0.2V

or

S

DDS

S

E2 ≥ V

– 0.2V. In E2 controlled data reten-

S

tion mode, minimum standby current mode is en-

A Write operation is initiated when E1 is at V ,

S

IL

tered when E2 ≤ 0.2V.

S

E2 is at V and W is at V . The data is latched

S

IH

S

IL

on the falling edge of E1 , the rising edge of E2

Output Disable. The data outputs are high im-

S

or the falling edge of W , whichever occurs last.

pedance when the Output Enable, G , is at V

S

S IH

The Write cycle is terminated on the rising edge of

with Write Enable, W , at V .

S IH

38/62

M36W416TG, M36W416BG

Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UB = LB = V

S

IL

tAVAV

VALID

A0-A17

tAVQV

tAXQX

DATA VALID

DQ0-DQ15

DATA VALID

AI07942

Note: E1 = Low, E2 = High, G = Low, W = High.

S

Figure 18. SRAM Read AC Waveforms, G Controlled

S

tAVAV

A0-A17

VALID

tE1LQV

tE1HQZ

E1

S

tE1LQX

tE2HQV

tE2LQZ

tBHQZ

E2

S

tE2HQX

tBLQV

UB , LB

S

tBLQX

tGLQV

tGHQZ

G

S

tGLQX

DQ0-DQ15

DATA VALID

AI07943

Note: Write Enable (W ) = High. Address Valid prior to or at the same time as E1 , UB and LB going Low.

S

Figure 19. SRAM Standby AC Waveforms

E1

S

E2

S

tPU

tPD

I

DD

50%

AI07913

39/62

M36W416TG, M36W416BG

Table 22. SRAM Read AC Characteristics

SRAM

Symbol

Alt

Parameter

Unit

Min

Max

t

Read Cycle Time

70

ns

AVAV

RC

t

ACC

Address Valid to Output Valid

70

AVQV

t

OH

Address Transition to Output Transition

UB , LB Disable to Hi-Z Output

10

AXQX

t

BHZ

25

70

BHQZ

S

t

UB , LB Access Time

S S

BLQV

AB

t

UB , LB Enable to Low-Z Output

S S

5

BLQX

BLZ

t

E1LQV

t

Chip Enable 1 Low or Chip Enable 2 High to Output Valid

70

ns

ACS1

t

E2HQV

t

Chip Enable 1 Low or Chip Enable 2 High to Output

Transition

E1LQX

t

10

CLZ1

t

E2HQX

t

E1HQZ

t

Chip Enable High or Chip Enable 2 Low to Output Hi-Z

25

HZCE

t

E2LQZ

t

OHZ

Output Enable High to Output Hi-Z

25

35

ns

GHQZ

t

Output Enable Low to Output Valid

GLQV

OE

t

OLZ

Output Enable Low to Output Transition

Chip Enable 1 High or Chip Enable 2 Low to Power Down

5

0

GLQX

(1)

70

t

PD

(1)

Chip Enable 1 Low or Chip Enable 2 High to Power Up

ns

PU

Note: 1. Sampled only. Not 100% tested.

40/62

M36W416TG, M36W416BG

Figure 20. SRAM Write AC Waveforms, W Controlled

S

tAVAV

A0-A17

VALID

tAVWH

tE1LWH

tE2HWH

tWHAX

E1

S

E2

S

tAVWL

tWLWH

W

S

tBLWH

UB , LB

S

G

S

tGHQZ

tDVWH

INPUT VALID

tWHDZ

Note 2

DQ0-DQ15

AI07944

Note: W , E1 , E2 , UB and/or LB must be asserted to initiate a write cycle. Output Enable (G ) = Low (otherwise, DQ0-DQ15 are high

S

impedance). If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

2. The I/O pins are in output mode and input signals must not be applied.

41/62

M36W416TG, M36W416BG

Figure 21. SRAM Write AC Waveforms, E1 Controlled

S

tAVAV

A0-A17

VALID

tAVE1H

tAVE2L

tE1LE1H

tE2HE2L

tAVE1L

tAVE2H

tE1HAX

tE2LAX

E1

S

E2

S

tWLE1H

tWLE2L

W

S

tBLE1H

tBLE2L

UB , LB

S

G

S

tDVE1H

tDVE2L

tE1HDZ

tE2LDZ

tGHQZ

DQ0-DQ15

INPUT VALID

Note 3

AI07945

Note: 1. W , E1 , E2 , UB and/or LB must be asserted to initiate a write cycle. Output Enable (G ) = Low (otherwise, DQ0-DQ15 are high

S

impedance). If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

2. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

3. The I/O pins are in output mode and input signals must not be applied.

42/62

M36W416TG, M36W416BG

Figure 22. SRAM Write AC Waveforms, W Controlled with G Low

S

tAVAV

VALID

A0-A17

tAVWH

tE1LWH

tE2HWH

tWHAX

E1

S

E2

S

tBLWH

UB , LB

S

tAVWL

tWLWH

W

S

tWHQX

tWHDZ

tWLQZ

tDVWH

DQ0-DQ15

INPUT VALID

AI07946

Note: 1. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

Figure 23. SRAM Write Cycle Waveform, UB and LB Controlled, G Low

S

tAVAV

VALID

A0-A17

tAVBH

tE1LBH

tE2HBH

E1

S

E2

S

tAVBL

tBLBH

tBHAX

UB , LB

S

tWLBH

W

S

tDVBH

INPUT VALID

tBHDZ

DQ0-DQ15

AI07947

Note: 1. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.

S

43/62

M36W416TG, M36W416BG

Table 23. SRAM Write AC Characteristics

SRAM

Symbol

Alt

Parameter

Unit

Min

Max

t

WC

Write Cycle Time

70

ns

AVAV

t

,

AVE1L

t

,

AVE2H

t

AS

Address Valid to Beginning of Write

0

ns

AVWL,

t

AVBL

t

,

Address Valid to Chip Enable 1 Low or Chip Enable 2

High

AVE1H

t

60

ns

AW

AVE2L

t

Address Valid to Write Enable High

AVWH

AW

t

BLWH

t

BLE1H

t

UB , LB Valid to End of Write

60

30

ns

BW

DW

S

BLE2L

AVBH

t

UB , LB Low to UB , LB High

S S S S

BLBH

t

,

DVE1H

t

DVE2L

Input Valid to End of Write

t

DVWH

t

DVBH

t

,

E1HAX

t

,

E2LAX

t

End of Write to Address Change

Address Transition to End of Write

0

ns

WR

WHAX

BHAX

t

,

E1HDZ

t

E2LDZ

t

HD

t

WHDZ

t

BHDZ

t

,

E1LE1H

t

Chip Enable 1 Low to End of Write

Chip Enable 2 High to End of Write

60

ns

E1LBH

CW1

t

E1LWH

t

E2HE2L,

t

E2HBH,

E2HWH

CW2

t

Output Enable High to Output Hi-Z

Write Enable High to Input Transition

Write Enable Low to UB , LB High

25

ns

GHQZ

GHZ

t

5

WHQX

DH

t

WP

50

WLBH

S

t

Write Enable Low to Output Hi-Z

WLQZ

WHZ

t

WLWH

t

Write Enable Pulse Width

50

ns

WLE1H

WP

t

WLE2L

44/62

M36W416TG, M36W416BG

Figure 24. SRAM Low V

Data Retention AC Waveforms, E1 or UB / LB Controlled

DDS

S

DATA RETENTION MODE

V

DDS

V

DDS (min)

tCDR

tR

E1 or

S

UB , LB

S

AI07918

Table 24. SRAM Low V

Data Retention Characteristic

DDS

Symbol

Parameter

Test Condition

Min

Typ

Max Unit

V

= 1.5V, E1 ≥ V

– 0.2V,

Supply Current (Data

Retention)

DDS

S

DDS

I

3

10

µA

V

DDDR

≥ V – 0.2V or V ≤ 0.2V

DDS IN

IN

Supply Voltage (Data

Retention)

V

1.5

3.3

DR

t

Chip Disable to Power Down

Operation Recovery Time

0

ns

CDR

t

R

70

Note: 1. All other Inputs V ≤ V

–0.2V or V ≤ 0.2V.

IL

IH

DDS

2. Sampled only. Not 100% tested.

45/62

M36W416TG, M36W416BG

APPENDIX A. BLOCK ADDRESS TABLES

Table 25. Top Boot Block Addresses,

M36W416TG

Table 26. Bottom Boot Block Addresses,

M36W416BG

Size

(KWord)

Size

#

Address Range

#

Address Range

(KWord)

32

4

0

4

FF000-FFFFF

FE000-FEFFF

FD000-FDFFF

FC000-FCFFF

FB000-FBFFF

FA000-FAFFF

F9000-F9FFF

F8000-F8FFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

F8000-FFFFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

99

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

8

7

6

4

5

4

3

4

2

4

1

4

0

4

46/62

M36W416TG, M36W416BG

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 27, 28,

29, 30, 31 and 32 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 32, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 27. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 28. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

Device Code

ST

88CEh

88CFh

Top

Bottom

01h

02h-0Fh

10h

reserved Reserved

0051h

"Q"

"R"

"Y"

11h

0052h

0059h

0003h

0000h

0035h

0000h

Query Unique ASCII String "QRY"

12h

13h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

Intel

compatible

14h

15h

Address for Primary Algorithm extended Query table (see Table 30)

P = 35h

NA

16h

17h

Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists)

18h

19h

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

1Ah

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

47/62

M36W416TG, M36W416BG

Table 29. CFI Query System Interface Information

Offset

Data

Description

Value

V

DD

V

DD

V

PP

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0027h

2.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0036h

00B4h

00C6h

3.6V

11.4V

12.6V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0005h

0003h

0000h

16µs

1s

Typical time-out per single word program = 2 µs

n

Typical time-out for Double Word Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

512µs

8s

Maximum time-out for word program = 2 times typical

n

Maximum time-out for Double Word Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

48/62

M36W416TG, M36W416BG

Table 30. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0015h

2 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0002h

0000h

n

4

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Ch

0002h

2Dh

2Eh

001Eh

0000h

Region 1 Information

Number of identical-size erase block = 001Eh+1

31

64 KByte

8

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

31

31h

32h

001Eh

0000h

Region 2 Information

Number of identical-size erase block = 001Eh+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

49/62

M36W416TG, M36W416BG

Table 31. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0066h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Chip Erase supported

(1 = Yes, 0 = No)

Suspend Erase supported

Suspend Program supported

Legacy Lock/Unlock supported

Queued Erase supported

No

Yes

No

Instant individual block locking supported (1 = Yes, 0 = No)

No

Protection bits supported

Page mode read supported

Synchronous read supported

(1 = Yes, 0 = No)

Yes

No

bit 31 to 9 Reserved; undefined bits are ‘0’

No

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

(P+B)h = 40h

0003h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

(P+C)h = 41h

(P+D)h = 42h

(P+E)h = 43h

0030h

00C0h

0001h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V

12V

01

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

(P+10)h = 45h

(P+11)h = 46h

(P+12)h = 47h

0080h

0000h

0003h

Protection Field 1: Protection Description

80h

00h

This field describes user-available. One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

8 Byte

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7

Lock/bytes JEDEC-plane physical low address

bit 8 to 15

Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2 = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2 = user programmable bytes

(P+13)h = 48h

Reserved

Note: 1. See Table 28, offset 15 for P pointer definition.

50/62

M36W416TG, M36W416BG

Table 32. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

Data

00XX

XXXX

Description

Protection Register Lock

64 bits: unique device number

64 bits: User Programmable OTP

51/62

M36W416TG, M36W416BG

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 25. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

Write 40h or 10h

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

F

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

V

Invalid

if (status_register.b3==1) /*V

invalid error */

PPF

b3 = 0

YES

Error (1, 2)

error_handler ( ) ;

Program

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI07919

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

52/62

M36W416TG, M36W416BG

Figure 26. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

F

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*V

PPF

invalid error */

PPF

b3 = 0

YES

Error (1, 2)

error_handler ( ) ;

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI07920

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

53/62

M36W416TG, M36W416BG

Figure 27. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

F

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI07921

54/62

M36W416TG, M36W416BG

Figure 28. Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

F

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*V

error_handler ( ) ;

invalid error */

PPF

Error (1)

PPF

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI07922

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

55/62

M36W416TG, M36W416BG

Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

Write 70h

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

F

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI07923

56/62

M36W416TG, M36W416BG

Figure 30. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

writeToFlash (any_address, 0x60) ; /*configuration setup*/

Write 60h

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Write 90h

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI04364

57/62

M36W416TG, M36W416BG

Figure 31. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

Write C0h

writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

F

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*V invalid error */

PPF

b3 = 0

YES

Error (1, 2)

error_handler ( ) ;

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI07924

Note: 1. Status check of b1 (Protected Block), b3 (V

a sequence.

Invalid) and b4 (Program Error) can be made after each program operation or after

PPF

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

58/62

M36W416TG, M36W416BG

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 33. Write State Machine Current/Next, sheet 1 of 2.

Command Input (and Next State)

Data

When

Read

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array

“1”

Array

Read Array Prog.Setup Ers. Setup

Read Array

Read Sts. Read Array

Read

Status

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Read

Elect.Sg.

Electronic

Signature

Program

Setup

Erase

Setup

Read

“1”

“0”

“1”

Read Array

Status

Read CFI

Query

Program

Setup

Erase

Setup

Read

CFI

Read Array

Status

Lock

(complete)

Lock Cmd

Error

Lock

(complete)

Lock Setup

Status

Lock Command Error

Program

Lock Command Error

Lock Cmd

Error

Erase

Setup

Read

Read Array

Status

Setup

Lock

(complete)

Program

Setup

Erase

Setup

Read

Read Array

Status

Prot. Prog.

Setup

Protection Register Program

Protection Register Program continue

Prot. Prog.

(continue)

Prot. Prog.

(complete)

Program

Setup

Erase

Setup

Read

Status

Read Array

Program

Read Array

Status

Prog. Setup “1”

Program

“0”

Prog. Sus

Read Sts

Program (continue)

(continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

Status

Array

Status

(continue) Read Array (continue)

Program Prog. Sus Program

(continue) Read Array (continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Prog. Sus Prog. Sus

Read Sts Read Array

Read Array

Prog. Sus

Read

Elect.Sg.

Electronic Prog. Sus

Signature Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

(continue) Read Array (continue)

Prog. Sus

Read CFI

Prog. Sus

CFI

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Read Sts Read Array

“1”

“0”

“1”

Read Array

(continue) Read Array (continue)

Program

(complete)

Program

Setup

Erase

Setup

Read

Status

Array

Read Array

Status

Erase

Setup

Erase

Erase Command Error

(continue) CmdError (continue)

Erase

Cmd.Error

Program

Setup

Erase

Setup

Read

Read Array

Status

Erase

(continue)

Erase Sus

Read Sts

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Array

Program Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

Setup

Read Array (continue) Read Array (continue)

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase Sus Erase Sus

Read Sts Read Array

Read Array (continue) Read Array (continue)

Erase Sus

Read

Elect.Sg.

Electronic Erase Sus

Signature Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array (continue) Read Array (continue)

Erase Sus

Read CFI

Erase Sus

CFI

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Sts Read Array

“1”

Read Array

Read Array (continue) Read Array (continue)

Erase

(complete)

Program

Setup

Erase

Read

Status

Read Array

Setup

Read Array

Status

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

59/62

M36W416TG, M36W416BG

Table 34. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Read CFI

Query

(98h)

Unlock

Confirm

(D0h)

Current State

Read Elect.Sg.

(90h)

Lock Setup

(60h)

Prot. Prog.

Setup (C0h)

Lock Confirm

(01h)

Lock Down

Confirm (2Fh)

Prot. Prog.

Setup

Read Array

Read Elect.Sg. Read CFI Query

Lock Setup

Read Array

Prot. Prog.

Setup

Read Status

Prot. Prog.

Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Read CFI Query Read Elect.Sg. Read CFI Query

Prot. Prog.

Setup

Read Array

Lock (complete)

Read Array

Lock Setup

Lock Command Error

Prot. Prog.

Setup

Lock Cmd Error Read Elect.Sg. Read CFI Query

Lock Setup

Prot. Prog.

Setup

Lock (complete) Read Elect.Sg. Read CFI Query

Read Array

Prot. Prog.

Setup

Protection Register Program

Prot. Prog.

(continue)

Protection Register Program (continue)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Setup

Prog. Setup

Program

(continue)

Program (continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Program Suspend Read Array

Read Status

Prog. Suspend Prog. Suspend Prog. Suspend

Read Array Read Elect.Sg. Read CFI Query

Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Read CFI

Read Elect.Sg. Read CFI Query

Program

(complete)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFIQuery

Read Array

Setup

Erase

(continue)

Erase Setup

Erase Command Error

Erase

Cmd.Error

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

Setup

Erase (continue)

Erase Suspend Erase Suspend Erase Suspend

Read Status Read Elect.Sg. Read CFI Query

Erase

(continue)

Lock Setup

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read Array Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Erase Suspend Erase Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read CFI Query Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase

Prot. Prog.

Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

60/62

M36W416TG, M36W416BG

REVISION HISTORY

Table 35. Document Revision History

Date

Version

Revision Details

19-Nov-2002

1.0

First Issue

61/62

M36W416TG, M36W416BG

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong -

India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

www.st.com

62/62


型号：	M36W416TG70ZA1T
厂家：	ST
描述：	16 Mbit 1Mb x16, Boot Block Flash Memory and 4Mbit 256Kb x16 SRAM, Multiple Memory Product 16兆位1Mb的X16 ，引导块闪存，并为4Mbit 256Kb的SRAM X16 ，多重内存产品闪存静态存储器
文件：	总62页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36W416TG70ZA1T [STMICROELECTRONICS]

相关型号：

M36W416TG70ZA6

M36W416TG70ZA6T

M36W416TG70ZA6T

M36W416TG85ZA1

M36W416TG85ZA1T

M36W416TG85ZA1T

M36W416TG85ZA6

M36W416TG85ZA6T

M36W416TG85ZA6T

M36W416TGZA

M36W432

M36W432-ZAT