M36W432TG70ZA6T [STMICROELECTRONICS]
32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product; 32兆位的2Mb X16 ,引导块闪存和4兆位256Kb的SRAM X16 ,多重内存产品型号: | M36W432TG70ZA6T |
厂家: | ST |
描述: | 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product |
文件: | 总66页 (文件大小:439K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M36W432TG
M36W432BG
32 Mbit (2Mb x16, Boot Block) Flash Memory
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY
■ MULTIPLE MEMORY PRODUCT
SRAM
■ 4 Mbit (256Kb x 16)
– 32 Mbit (2Mb x 16), Boot Block, Flash Memory
– 4 Mbit (256Kb x 16) SRAM Memory
■ SUPPLY VOLTAGE
■ ACCESS TIME: 70ns
■ LOW V
DATA RETENTION: 1.5V
DDS
– V
– V
– V
= 2.7V to 3.3V
DDF
DDS
PPF
■ POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
= V
= 2.7V to 3.3V
DDQF
= 12V for Fast Program (optional)
Figure 1. Package
■ ACCESS TIME: 70ns, 85ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M36W432TG: 88BAh
– Bottom Device Code, M36W432BG: 88BBh
FBGA
FLASH MEMORY
■ MEMORY BLOCKS
– Parameter Blocks (Top or Bottom Location)
– Main Blocks
Stacked LFBGA66 (ZA)
12 x 8 mm
■ PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option
■ BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
F
■ AUTOMATIC STANDBY MODE
■ PROGRAM and ERASE SUSPEND
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ COMMON FLASH INTERFACE
■ SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device identifier
November 2002
1/66
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M36W432TG, M36W432BG
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
V
V
V
Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDF
and V
Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDS
DDQF
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PPF
SSF
and V
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SSS
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline16
Table 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data . . . 16
Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . . 17
Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package). 18
2/66
M36W432TG, M36W432BG
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FLASH DEVICE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FLASH SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Flash Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FLASH BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FLASH COMMAND INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Flash Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Flash Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Flash Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Flash Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. Flash Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . 28
FLASH BLOCK LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. Flash Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. Flash Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/66
M36W432TG, M36W432BG
FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
V
Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PPF
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. Flash Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. Flash Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21. Flash Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Flash Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. Flash Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. SRAM Write AC Waveforms, WS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . 45
Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 45
Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24. SRAM Low V
Data Retention AC Waveforms, E1 or UB / LB Controlled . . 47
S S S
DDS
DDS
Table 25. SRAM Low V
Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX A. FLASH BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 26. Top Boot Block Addresses, M36W432TG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Bottom Boot Block Addresses, M36W432BG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 30. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 31. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. Flash Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 58
Figure 29. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 31. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
APPENDIX D. FLASH COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. 63
Table 34. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5/66
M36W432TG, M36W432BG
SUMMARY DESCRIPTION
The M36W432TG is a low voltage Multiple Memo-
ry Product which combines two memory devices;
a 32 Mbit boot block Flash memory and a 4 Mbit
SRAM. Recommended operating conditions do
not allow both the Flash and SRAM devices to be
active at the same time.
The memory is offered in a Stacked LFBGA66
(12x8mm, 8x8 active ball array, 0.8 mm pitch)
package and is supplied with all the bits erased
(set to ‘1’).
Table 1. Signal Names
Address Inputs common to the Flash
and SRAM chips
A0-A17
A18-A20
Address Inputs for Flash Chip only
Data Input/Output
DQ0-DQ15
V
DDF
Flash Power Supply
V
Flash Power Supply for I/O Buffers
DDQF
Flash Optional Supply Voltage for Fast
Program & Erase
Figure 2. Logic Diagram
V
PPF
V
V
V
V
V
DDS
Flash Ground
SSF
DDS
SSS
DDQF
V
V
DDF
PPF
SRAM Power Supply
SRAM Ground
21
16
A0-A20
DQ0-DQ15
NC
Not Connected Internally
Flash control functions
E
G
F
F
F
F
F
E
Chip Enable input
Output Enable input
Write Enable input
Reset input
F
W
G
F
RP
WP
W
F
M36W432TG
M36W432BG
RP
F
E1
E2
G
S
S
S
S
S
S
WP
Write Protect input
F
SRAM control functions
E1 , E2
Chip Enable inputs
S
S
W
G
Output Enable input
Write Enable input
UB
LB
S
W
S
UB
Upper Byte Enable input
Lower Byte Enable input
S
LB
V
V
SSS
S
SSF
AI07925
6/66
M36W432TG, M36W432BG
Figure 3. LFBGA Connections (Top view through package)
7/66
M36W432TG, M36W432BG
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1 , E2 ). The Chip En-
S
S
Address Inputs (A0-A17). Addresses A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1 at V or
S
IH
E2 at V deselects the memory and reduces the
S
IL
power consumption to the standby level. E1 and
S
E2 can also be used to control writing to the
S
SRAM memory array, while W remains at V It
S
IL.
is not allowed to set E at V E1 at V and E2
F
IL,
S
IL
S
accessed through the Chip Enable (E ) and Write
at V at the same time.
F
IH
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
SRAM Write Enable (W ). The Write Enable in-
put controls writing to the SRAM memory array.
W is active low.
S
S
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals
SRAM Output Enable (G ). The Output Enable
gates the outputs through the data buffers during
S
a read operation of the SRAM memory. G is ac-
S
tive low.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
SRAM Upper Byte Enable (UB ). The Upper
Byte Enable enables the upper bytes for SRAM
S
(DQ8-DQ15). UB is active low.
S
SRAM Lower Byte Enable (LB ). The
Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LB is active low.
S
Flash Chip Enable (E ). The Chip Enable input
F
S
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
V
Supply Voltage (2.7V to 3.3V). V
pro-
DDF
DDF
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
able is at V and Reset is at V the device is in ac-
IL
IH
tive mode. When Chip Enable is at V
the
IH
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
stand-by level.
V
and V
Supply Voltage (2.7V to 3.3V).
DDS
DDQF
V
provides the power supply for the Flash
DDQF
memory I/O pins and V
supply for the SRAM control pins. This allows all
Outputs to be powered independently of the Flash
provides the power
DDS
Flash Output Enable (G ). The Output Enable
controls data outputs during the Bus Read opera-
tion of the memory.
F
core power supply, V
. V
can be tied to
DDF
DDQF
Flash Write Enable (W ). The Write Enable
F
V
.
DDS
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
V
Program Supply Voltage. V
is both a
PPF
PPF
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
Enable, E , or Write Enable, W , whichever oc-
F
F
curs first.
age V
and the Program Supply Voltage V
DDF
PPF
Flash Write Protect (WP ). Write Protect is an
F
can be applied in any order.
input that gives an additional hardware protection
If V is kept in a low voltage range (0V to 3.6V)
PPF
for each block. When Write Protect is at V , the
IL
V
is seen as a control input. In this case a volt-
PPF
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
age lower than V
gives an absolute protection
PPLK
against program or erase, while V
ables these functions (see Table 6, DC Character-
istics for the relevant values). V is only
> V
en-
PPF
PP1
is at V , the Lock-Down is disabled and the block
IH
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
PPF
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Quadruple Word Program
the results are uncertain.
Flash Reset (RP ). The Reset input provides a
hardware reset of the Flash memory. When Reset
F
is at V , the memory is in reset mode: the outputs
IL
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
If V
is in the range 11.4V to 12.6V it acts as a
PPF
Locked state. When Reset is at V , the device is
IH
power supply pin. In this condition V
must be
PPF
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
8/66
M36W432TG, M36W432BG
stable until the Program/Erase algorithm is com-
pleted (see Table 20 and 21).
Note: Each device in a system should have V
D-
, V
DF DDQF
and V
decoupled with a 0.1µF ca-
PPF
pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the re-
V
and V
Ground. V
and V
are the
SSF
SSS
SSF
SSS
ground references for all voltage measurements in
the Flash and SRAM chips, respectively.
quired V
program and erase currents.
PPF
9/66
M36W432TG, M36W432BG
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
by three chip enable inputs: E for the Flash mem-
F
ory and, E1 and E2 for the SRAM.
S
S
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
Figure 4. Functional Block Diagram
V
V
V
PPF
DDQF
DDF
E
G
F
F
F
F
F
W
RP
WP
Flash Memory
32 Mbit (x16)
A18-A20
A0-A17
V
SSF
V
DQ0-DQ15
DDS
E1
E2
G
S
S
S
S
S
S
SRAM
4 Mbit (x16)
W
UB
LB
V
SSS
AI07926
10/66
M36W432TG, M36W432BG
Table 2. Main Operation Modes
Operation
E
G
W
RP
WP
X
V
E1 E2
G
W
UB
LB
S
DQ15-DQ8 DQ7-DQ0
Data Output
F
F
F
F
F
PPF
S
S
S
S
S
Mode
V
V
V
V
Read
Don’t care
or
SRAM must be disabled
SRAM must be disabled
IL
IL
IL
IH
IH
V
DDF
V
V
IH
V
V
IH
Write
X
Data Input
IL
V
PPFH
Block
Locking
V
V
V
V
V
X
X
Don’t care
SRAM must be disabled
X
IL
IH
IL
Standby
Reset
X
X
X
X
X
Don’t care
Don’t care
Any SRAM mode is allowed
Any SRAM mode is allowed
Hi-Z
Hi-Z
IH
IH
V
X
X
X
IL
Output
Disable
V
IL
V
IH
V
IH
V
IH
Don’t care
Any SRAM mode is allowed
Hi-Z
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Read
Read
Read
Write
Write
Write
Flash must be disabled
Flash must be disabled
Flash must be disabled
Flash must be disabled
Flash must be disabled
Flash must be disabled
Data out Word Read
IL
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
IL
IL
IL
IH
IH
IH
IL
IL
IL
Data out
Hi-Z
Hi-Z
IH
V
Data out
IH
IL
IL
IL
V
V
V
V
V
V
V
X
Data in Word Write
IL
IL
IL
IL
V
IH
X
X
X
X
X
X
Data in
Hi-Z
Hi-Z
V
Data in
IL
IH
IH
IH
Standby/
Power
Down
V
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
IL
Any Flash mode is allowable
Any Flash mode is allowable
V
V
IH
X
X
X
X
X
V
V
X
X
IH
IL
Data
Retention
V
V
IH
X
X
Output
Disable
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
V
V
V
V
V
V
Any Flash mode is allowable
Any Flash mode is allowable
Any Flash mode is allowable
Hi-Z
Hi-Z
Hi-Z
IH
IH
IH
IH
IH
IH
IL
IL
IL
Output
Disable
V
V
V
V
IH
Output
Disable
V
IH
IL
Note: 1. X = Don’t Care = V or V , V = 12V ± 5%.
PPFH
IL
IH
2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
11/66
M36W432TG, M36W432BG
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–40
–40
–55
–0.5
–0.6
–0.6
–0.5
Max
85
(1)
T
°C
°C
°C
V
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Flash Supply Voltage
Program Voltage
T
125
150
BIAS
T
STG
V
IO
V
+0.3
DDQF
V
, V
3.8
13
V
DDF DDQF
V
PPF
V
V
SRAM Supply Voltage
3.8
V
DDS
Note: 1. Depends on range.
12/66
M36W432TG, M36W432BG
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 4,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 4. Operating and AC Measurement Conditions
SRAM
70
Flash Memory
70/85
Parameter
Units
Min
Max
–
Min
2.7
Max
3.3
3.3
85
V
V
Supply Voltage
–
V
V
DDF
V
Supply Voltage
2.7
– 40
3.3
85
2.7
DDQF = DDS
Ambient Operating Temperature
– 40
°C
pF
Load Capacitance (C )
30
50
L
Input Rise and Fall Times
1V/ns
5ns
0 to V
0 to V
DDQF
Input Pulse Voltages
V
V
DDQF
V
DDQF
/2
V /2
DDQF
Input and Output Timing Ref. Voltages
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
V
DDQF
V
DDQ
V
/2
DDQ
V
DDQF
V
0V
DDF
25kΩ
AI90166
DEVICE
UNDER
TEST
Note: V
means V
= V
DDQF DDS
DDQ
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI90167
L
Table 5. Device Capacitance
Symbol
Parameter
Test Condition
Typ
12
Max
12
Unit
C
V
= 0V, f=1 MHz
= 0V, f=1 MHz
Input Capacitance
Output Capacitance
pF
pF
IN
IN
C
V
OUT
20
15
OUT
Note: Sampled only, not 100% tested.
13/66
M36W432TG, M36W432BG
Table 6. DC Characteristics
Symbol
Parameter
Device
Test Condition
Min
Typ
Max
±1
Unit
µA
Flash &
SRAM
I
0V ≤ V ≤ V
Input Leakage Current
LI
IN
DDQF
0V ≤ V
0V ≤ V
≤ V
Flash
±10
±1
µA
OUT
DDQF
I
Output Leakage Current
LO
≤ V
OUT
DDQF,
SRAM
µA
SRAM Outputs Hi-Z
E = V
± 0.2V
± 0.2V
DDQF
F
DDQF
Flash
15
7
50
15
µA
µA
RP = V
F
E1 ≥ V
– 0.2V
S
DDS
V
≥ V – 0.2V or V ≤ 0.2V
DDS IN
IN
f = fmax (A0-A17 and DQ0-
DQ15 only)
I
I
V
Standby Current
DDS
DD
SRAM
f = 0 (G , W , UB and LB )
S
S
S
S
E1 ≥ V
– 0.2V
S
DDS
V
≥ V
– 0.2V or V ≤ 0.2V,
7
15
µA
IN
DDS
IN
f = 0
RP = V ± 0.2V
SSF
Supply Current (Reset)
Supply Current
Flash
SRAM
Flash
Flash
15
50
12
µA
DDD
F
f = fmax = 1/
,
AVAV
5.5
mA
V
V
≤ 0.2V, I
= 0 mA
IN
OUT
I
DD
f = 1MHz,
≤ 0.2V, I = 0 mA
1.5
9
3
mA
mA
mA
IN
OUT
I
I
E = V , G = V f = 5MHz
F IL F IH,
Supply Current (Read)
Supply Current (Program)
18
10
DDR
Program in progress
= 12V ± 5%
5
V
PPF
DDW
Program in progress
= V
10
5
20
20
20
50
mA
mA
mA
µA
V
PPF
DDF
Erase in progress
= 12V ± 5%
V
PPF
I
Supply Current (Erase)
Flash
Flash
DDE
Erase in progress
10
V
PPF
= V
DDF
Supply Current
(Program/Erase Suspend)
E = V
± 0.2V,
F
DDQF
I
15
1
DDWES
Erase suspended
V
V
≤ V
> V
SSF
5
400
5
µA
µA
µA
PPF
DDF
Program Current
(Read or Standby)
I
Flash
Flash
PPS
PPF
DDF
I
RP = V
± 0.2V
Program Current (Reset)
1
1
PPR
F
Program in progress
= 12V ± 5%
10
5
mA
µA
V
PPF
Program Current
(Program)
I
Flash
Flash
PPW
Program in progress
= V
1
3
1
V
PPF
DDF
Erase in progress
= 12V ± 5%
10
5
mA
µA
V
PPF
I
Program Current (Erase)
PPE
Erase in progress
= V
V
PPF
DDF
14/66
M36W432TG, M36W432BG
Symbol
Parameter
Device
Test Condition
Min
–0.3
0.7
Typ
Max
Unit
Flash &
SRAM
V
IL
V
V
= V
= V
≥ 2.7V
Input Low Voltage
0.8
V
DDQF
DDQF
DDS
V
Flash &
SRAM
DDQF
V
IH
≥ 2.7V
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
DDS
V
+0.3
DDQF
V
V
= V = V min
DDS DD
Flash and
SRAM
DDQF
V
OL
0.1
I
OL
= 100µA
= V
= V min
DD
V
Flash &
SRAM
DDQF
DDS
DDQF
V
OH
I
= –100µA
–0.1
OH
Program Voltage
(Program or Erase
operations)
V
Flash
Flash
Flash
Flash
1.65
3.6
12.6
1
V
V
V
V
PPL
Program Voltage
(Program or Erase
operations)
V
11.4
PPH
Program Voltage
(Program and Erase lock-
out)
V
PPLK
V
DDF
Supply Voltage
V
2
(Program and Erase lock-
out)
LKO
15/66
M36W432TG, M36W432BG
PACKAGE MECHANICAL
Figure 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline
D
D2
D1
SE
b
E
E1
BALL "A1"
e
ddd
FE
FD
SD
e
A
A2
A1
BGA-Z12
Note: Drawing is not to scale.
Table 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.400
0.0551
0.300
0.0118
1.100
0.0433
0.400
12.000
5.600
8.800
0.300
0.500
0.0157
0.4724
0.2205
0.3465
0.0118
0.0197
D
–
–
–
–
–
–
–
–
D1
D2
ddd
E
–
–
–
–
0.100
0.0039
8.000
5.600
0.800
1.600
1.200
0.400
0.400
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3150
0.2205
0.0315
0.0630
0.0472
0.0157
0.0157
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E1
e
FD
FE
SD
SE
16/66
M36W432TG, M36W432BG
Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)
17/66
M36W432TG, M36W432BG
Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)
18/66
M36W432TG, M36W432BG
PART NUMBERING
Table 8. Ordering Information Scheme
Example:
M36 W 4 32T G 70 ZA 6 T
Device Type
M36 = MMP (Flash + SRAM)
Operating Voltage
W = V
= 2.7V to 3.3V, V
= V
= 2.7V to 3.3V
DDQF
DDF
DDS
SRAM Chip Size & Organization
4 = 4 Mbit (256Kb x 16)
Flash Device Size & Organization
32 = 32 Mbit (x16), Boot Block, Flash memory
Array Matrix
T = Top Boot
B = Bottom Boot
SRAM Device
G = 4Mb, 0.16µm, 70ns, 3V
Speed
70 = 70ns
85 = 85ns
Package
ZA = LFBGA66: 12 x 8mm, 0.8mm pitch
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Option
T = Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
Table 9. Daisy Chain Ordering Scheme
Example:
M36W432TG
-ZA T
Device Type
M36W432TG
Daisy Chain
-ZA = LFBGA66: 12 x 8mm, 0.8mm pitch
Option
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
19/66
M36W432TG, M36W432BG
FLASH DEVICE
The M36W432TG contains one 32 Mbit Flash
memory. This section describes how to use the
Flash device and all signals refer to the Flash de-
vice.
FLASH SUMMARY DESCRIPTION
The Flash Memory is a 32 Mbit (2 Mbit x 16) device
that can be erased electrically at block level and
programmed in-system on a Word-by-Word basis.
These operations can be performed using a single
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
low voltage (2.7 to 3.6V) supply. V
allows to
DDQF
drive the I/O pin down to 1.65V. An optional 12V
power supply is provided to speed up cus-
V
PPF
tomer programming.
The device features an asymmetrical blocked ar-
chitecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWords and 63 Main Blocks of 32
KWords. The M36W432TG has the Parameter
Blocks at the top of the memory address space
while the M36W432BG locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 10, Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
The device includes a Protection Register to in-
crease the protection of a system design. The Pro-
tection Register is divided into two segments, the
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanently
protected. Figure 11, shows the Protection Regis-
ter Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
When V
≤ V
all blocks are protected
PPF
PPLK
20/66
M36W432TG, M36W432BG
Figure 10. Flash Block Addresses
Top Boot Block Addresses
Bottom Boot Block Addresses
1FFFFF
4 KWords
1FF000
1FFFFF
32 KWords
32 KWords
1F8000
1F7FFF
Total of 8
4 KWord Blocks
1F0000
Total of 63
32 KWord Blocks
1F8FFF
4 KWords
1F8000
1F7FFF
32 KWords
1F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 63
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
008000
007FFF
000FFF
000000
32 KWords
4 KWords
000000
AI90164
Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses.
Figure 11. Protection Register Memory Map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
Unique device number
81h
(1)
Protection Register Lock
2
1
0
80h
AI07927
Note: 1. Bit 2 of the Protection Register Lock must not be programmed to 0.
21/66
M36W432TG, M36W432BG
FLASH BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 2, Main Operation Modes, for a
summary.
See Figures 13 and 14, Flash Write AC Wave-
forms, and Tables 20 and 21, Write AC Character-
istics, for details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at V .
IH
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
when Chip Enable is at V and the device is in
IH
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
able must be at V in order to perform a read op-
IL
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 12, Flash Read Mode AC Waveforms, and
Table 19, Flash Read AC Characteristics, for de-
tails of when the output becomes valid.
V
during a program or erase operation, the de-
IH
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, V , and the supply
current is reduced to I
IL
. The data Inputs/Out-
DD1
Read mode is the default state of the device when
exiting Reset or after power-up.
puts will still output data if a bus Read operation is
in progress.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
Reset. During Reset mode when Output Enable
is Low, V , the memory is deselected and the out-
IL
puts are high impedance. The memory is in Reset
and Write Enable are at V with Output Enable at
mode when Reset is at V . The power consump-
IL
IL
V . Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
IH
able inputs. If Reset is pulled to V
during a Pro-
SSF
gram or Erase, this operation is aborted and the
memory content is no longer valid.
22/66
M36W432TG, M36W432BG
FLASH COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See Table 10, Command
Codes, for a summary of the commands and see
Appendix 30, Table 34, Write State Machine Cur-
rent/Next, for a summary of the Command Inter-
face.
Table 10. Flash Command Codes
Hex Code
01h
Command
Block Lock confirm
10h
Program
20h
Erase
2Fh
Block Lock-Down confirm
30h
Double Word Program
Program
40h
50h
55h
56h
Clear Status Register
Reserved
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
Quadruple Word Program
set or whenever V
is lower than V
. Com-
LKO
DDF
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 11, Com-
mands, in conjunction with the text descriptions
below.
Block Lock, Block Unlock, Block Lock-
Down
60h
70h
90h
98h
B0h
C0h
Read Status Register
Read Electronic Signature
Read CFI Query
Read Memory Array Command
The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is-
sue the Read Memory Array command and return
the memory to Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. When a device Reset occurs, the
memory defaults to Read mode.
Program/Erase Suspend
Protection Register Program
Program/Erase Resume, Block Unlock
confirm
D0h
FFh
Read Memory Array
Read Status Register Command
The Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register at any address, until another
command is issued. See Table 18, Status Register
Bits, for details on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
Read CFI Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or appli-
cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com-
mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See Appendix B,
Common Flash Interface, Tables 28, 29, 30, 31,
32 and 33 for details on the information contained
in the Common Flash Interface memory area.
Read Electronic Signature Command
Block Erase Command
The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protec-
tion and Lock Register. See Tables 12, 13 and 14
for the valid address.
The Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
command.
■ The first bus cycle sets up the Erase command.
23/66
M36W432TG, M36W432BG
■ The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V . As data integrity
IL
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 26, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Erase aborts if Reset turns to V . As data integrity
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 15, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
IL
Quadruple Word Program Command
This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when VPPF is not at V
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
.
PPH
See Appendix C, Figure 29, Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.
Program Command
■ The first bus cycle sets up the Quadruple Word
Program Command.
■ The second bus cycle latches the Address and
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command.
the Data of the first word to be written.
■ The first bus cycle sets up the Program
■ The third bus cycle latches the Address and the
command.
Data of the second word to be written.
■ The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 15, Program, Erase
Times and Program/Erase Endurance Cycles.
■ The fourth bus cycle latches the Address and
the Data of the third word to be written.
■ The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V . As data integrity
IL
Programming aborts if Reset goes to V . As data
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 27, Quadruple Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Quadruple Word Program
command.
IL
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix C, Figure 25, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Clear Status Register Command
Double Word Program Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0. Programming should not be attempt-
ed when V
is not at V
.
PPF
PPH
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
Program/Erase Suspend Command
■ The second bus cycle latches the Address and
The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase control-
ler.
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
24/66
M36W432TG, M36W432BG
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron-
ic Signature and Read CFI Query commands. Ad-
ditionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, Block Lock-Down or
Protection Program commands will also be ac-
cepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protec-
tion Program commands. When the Program/
Erase Resume command is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.
Protection Register Memory Map). Attempting to
program a previously protected Protection Regis-
ter will result in a Status Register error. The pro-
tection of the Protection Register is not reversible.
The Protection Register Program cannot be sus-
pended.
Block Lock Command
The Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
■ The first bus cycle sets up the Block Lock
command.
Chip Enable to V . Program/Erase is aborted if
IH
■ The second Bus Write cycle latches the block
Reset turns to V .
IL
address.
See Appendix C, Figure 28, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, and Figure 30, Erase Suspend &
Resume Flowchart and Pseudo Code for flow-
charts for using the Program/Erase Suspend com-
mand.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 17 shows the protection status after issuing
a Block Lock command.
The Block Lock bits are volatile, once set they re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister.
See Appendix C, Figure 28, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, and Figure 30, Erase Suspend &
Resume Flowchart and Pseudo Code for flow-
charts for using the Program/Erase Resume com-
mand.
Block Unlock Command
The Blocks Unlock command is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are required to is-
sue the Blocks Unlock command.
■ The first bus cycle sets up the Block Unlock
command.
■ The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 17 shows the protection status after issuing
a Block Unlock command. Refer to the section,
Block Locking, for a detailed explanation.
Block Lock-Down Command
A locked block cannot be Programmed or Erased,
Protection Register Program Command
The Protection Register Program command is
used to Program the 128 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
or have its protection status changed when WP is
F
low, V . When WP is high, V the Lock-Down
Two write cycles are required to issue the Protec-
tion Register Program command.
■ The first bus cycle sets up the Protection
IL
F
IH,
function is disabled and the locked blocks can be
individually unlocked by the Block Unlock com-
mand.
Register Program command.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latches the block
address.
The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure 11,
25/66
M36W432TG, M36W432BG
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table. 17 shows the protection sta-
tus after issuing a Block Lock-Down command.
Refer to the section, Block Locking, for a detailed
explanation.
Table 11. Flash Commands
Bus Write Operations
Commands
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
Read Memory
Array
1+ Write
1+ Write
X
X
X
FFh
RA
X
RD
SRD
IDh
Read
Read Status
Register
70h Read
90h Read
Read Electronic
Signature
(2)
1+ Write
1+ Write
SA
Read CFI Query
Erase
X
X
98h Read QA
20h Write BA
40h
QD
2
Write
D0h
Program
2
Write
X
X
or
10h
Write PA
PD
Double Word
3
Write
30h Write PA1 PD1 Write PA2 PD2
(3)
Program
Quadruple Word
(6)
5
1
1
1
Write
Write
Write
Write
X
X
X
X
Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
56h
(4)
Program
Clear Status
Register
50h
Program/Erase
Suspend
B0h
D0h
Program/Erase
Resume
Block Lock
2
2
2
Write
Write
Write
X
X
X
60h Write BA
60h Write BA
01h
D0h
2Fh
Block Unlock
Block Lock-Down
60h Write
BA
Protection
Register Program
2
Write
X
C0h Write PRA PRD
Note: 1. X = Don’t Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),
QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad-
dress, PRD=Protection Register Data.
2. The signature addresses are listed in Tables 12, 13 and 14.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
5. 55h is reserved.
6. To be characterized.
26/66
M36W432TG, M36W432BG
Table 12. Flash Read Electronic Signature
E
G
W
Code
Device
A0
A1
A2-A7
A8-A20
DQ0-DQ7
DQ8-DQ15
F
F
F
Manufacture.
Code
V
V
IL
V
V
V
IL
0
Don’t Care
20h
00h
IL
IH
IL
V
V
V
V
V
V
V
V
M36W432TG
M36W432BG
0
0
Don’t Care
Don’t Care
BAh
BBh
88h
88h
IL
IL
IH
IH
IH
IL
Device Code
V
IH
V
IL
IL
IL
Note:
RP = V .
IH
Table 13. Flash Read Block Lock Signature
E
G
W
Block Status
Locked Block
A0
A1 A2-A7
A8-A11
A12-A20
DQ0 DQ1 DQ2-DQ15
F
F
F
V
IL
V
V
IH
V
IL
V
0
0
Don’t Care Block Address
Don’t Care Block Address
1
0
0
0
00h
00h
IL
IL
IH
IH
V
V
V
V
V
V
V
IL
V
Unlocked Block
IL
IH
Locked-Down
Block
(1)
V
IL
V
IH
0
Don’t Care Block Address
1
00h
IL
IL
IH
X
Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.
Table 14. Flash Read Protection Register and Lock Register
E
G
W
Word
A0-A7
A8-A20
DQ0
DQ1
DQ2
DQ3-DQ7 DQ8-DQ15
F
F
F
OTP Prot.
data
Don’t Care
See note (1)
Don’t
V
IL
V
V
IH
Lock
80h Don’t Care Don’t Care
Don’t Care
Care
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
81h Don’t Care
82h Don’t Care
83h Don’t Care
84h Don’t Care
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
ID data
ID data
ID data
ID data
ID data
85h Don’t Care OTP data
86h Don’t Care OTP data
87h Don’t Care OTP data
88h Don’t Care OTP data
89h Don’t Care OTP data
8Ah Don’t Care OTP data
8Bh Don’t Care OTP data
8Ch Don’t Care OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP 1
OTP 2
OTP 3
OTP 4
OTP 5
OTP 6
OTP 7
Note: 1. DQ2 in the Protection Lock Register must not be programmed to 0.
27/66
M36W432TG, M36W432BG
Table 15. Flash Program, Erase Times and Program/Erase Endurance Cycles
Flash Device
Parameter
Test Conditions
Unit
Min
Typ
10
Max
200
200
200
5
V
PPF
= V
DDF
Word Program
µs
V
V
V
= 12V ±5%
= 12V ±5%
= 12V ±5%
= V
Double Word Program
10
µs
PPF
PPF
PPF
V
Quadruple Word Program
10
µs
(1)
(1)
s
0.16/0.08
0.32
Main Block Program
Parameter Block Program
Main Block Erase
5
s
PPF
DDF
V
= 12V ±5%
4
s
PPF
0.02/0.01
V
= V
0.04
1
4
s
PPF
DDF
V
V
V
= 12V ±5%
10
10
10
10
s
PPF
PPF
= V
V
1
s
DD DDF
= 12V ±5%
= V
0.4
0.4
s
s
PPF
Parameter Block Erase
V
PPF
DDF
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands
respectively.
28/66
M36W432TG, M36W432BG
FLASH BLOCK LOCKING
The M36W432TG features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down State
Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
■ Lock/Unlock - this first level allows software-
only control of block locking.
■ Lock-Down - this second level requires
hardware interaction before locking can be
changed.
■ V
PPF
≤ V
- the third level offers a complete
PPLK
The Lock-Down function is dependent on the WP
hardware protection against program and erase
on all blocks.
F
input pin. When WP =0 (V ), the blocks in the
F
IL
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 17, de-
WP =1 (V ) the Lock-Down function is disabled
F
IH
fines all of the possible protection states (WP ,
F
(1,1,1) and Locked-Down blocks can be individu-
ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be relocked
DQ1, DQ0), and Appendix C, Figure 31, shows a
flowchart for the locking operations.
Reading a Block’s Lock Status
(1,1,1) and unlocked (1,1,0) as desired while WP
F
The lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h to the device. Subse-
quent reads at the address specified in Table 13,
will output the protection status of that block. The
lock status is represented by DQ0 and DQ1. DQ0
indicates the Block Lock/Unlock status and is set
by the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
ing Lock-Down. DQ1 indicates the Lock-Down sta-
tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
remains high. When WP is low , blocks that were
F
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was high. Device reset or power-down
F
resets all blocks , including those in Lock-Down, to
the Locked state.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
The following sections explain the operation of the
locking system.
Locked State
The default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Unlocked State
Locking operations cannot be performed during a
program suspend. Refer to Appendix D, Com-
mand Interface and Program/Erase Controller
State, for detailed information on which com-
mands are valid during erase suspend.
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
29/66
M36W432TG, M36W432BG
Table 16. Flash Block Lock Status
Item
Address
Data
Block Lock Configuration
Block is Unlocked
LOCK
DQ0=0
DQ0=1
DQ1=1
xx002
Block is Locked
Block is Locked-Down
Table 17. Flash Protection Status
Current
(1)
Next Protection Status
(1)
Protection Status
(WP , DQ1, DQ0)
F
(WP , DQ1, DQ0)
F
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
After
WP transition
Program/Erase
Current State
Allowed
F
1,0,0
yes
no
1,0,1
1,0,1
1,1,1
1,1,1
0,0,1
0,0,1
1,0,0
1,0,0
1,1,0
1,1,0
0,0,0
0,0,0
1,1,1
1,1,1
1,1,1
1,1,1
0,1,1
0,1,1
0,0,0
0,0,1
0,1,1
0,1,1
1,0,0
1,0,1
(2)
1,0,1
1,1,0
1,1,1
0,0,0
yes
no
yes
no
(2)
0,0,1
(3)
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = V and A0 = V .
IH
IL
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
F
3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.
F
IH
30/66
M36W432TG, M36W432BG
FLASH STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, re-
fer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the maximum num-
ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
or Output Enable returns to V . Either Chip En-
IH
able or Output Enable must be toggled to update
the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver-
ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
The bits in the Status Register are summarized in
Table 18, Status Register Bits. Refer to Table 18
in conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Pro-
gram/Erase Controller is inactive, and the device
is ready to process a new command.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High .
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
V
Status (Bit 3). The V
Status bit can be
PPF
PPF
used to identify an invalid voltage on the V
during Program and Erase operations. The V
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
pin
PPF
PPF
cur if V
becomes invalid during an operation.
PPF
After the Program/Erase Controller completes its
When the V
voltage on the V
Status bit is Low (set to ‘0’), the
PPF
operation the Erase Status, Program Status, V
pin was sampled at a valid
PPF
PPF
Status and Block Lock Status bits should be tested
for errors.
Status bit is High (set to
PPF
, the memory is pro-
PPLK
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus-
pend command being issued therefore the memo-
ry may still complete the operation rather than
entering the Suspend mode.
Status bit can only be re-
PPF
31/66
M36W432TG, M36W432BG
should only be considered valid when the Pro-
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being is-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
Table 18. Flash Status Register Bits
Bit
Name
Logic Level
Definition
’1’
’0’
’1’
’0’
’1’
’0’
’1’
’0’
’1’
Ready
7
P/E.C. Status
Busy
Suspended
6
5
4
Erase Suspend Status
Erase Status
In progress or Completed
Erase Error
Erase Success
Program Error
Program Status
Program Success
V
V
Invalid, Abort
OK
PPF
PPF
V
PPF
Status
3
2
’0’
’1’
’0’
’1’
’0’
Suspended
Program Suspend Status
In Progress or Completed
Program/Erase on protected Block, Abort
No operation to protected blocks
1
0
Block Protection Status
Reserved
Note: Logic level ’1’ is High, ’0’ is Low.
32/66
M36W432TG, M36W432BG
Figure 12. Flash Read Mode AC Waveforms
tAVAV
VALID
A0-A20
tAVQV
tAXQX
E
F
tELQV
tELQX
tEHQX
tEHQZ
G
F
tGLQV
tGHQX
tGHQZ
tGLQX
VALID
DQ0-DQ15
OUTPUTS
ENABLED
ADDR. VALID
CHIP ENABLE
DATA VALID
STANDBY
AI07928
Table 19. Flash Read AC Characteristics
Flash
Unit
Symbol
Alt
Parameter
70
70
70
85
85
85
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
Max
Min
ns
ns
ns
AVAV
RC
t
t
ACC
AVQV
(1)
t
Address Transition to Output Transition
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
0
0
0
0
t
OH
AXQX
(1)
(1)
(2)
(1)
(1)
(1)
(2)
(1)
t
Min
Max
Max
Min
Min
Max
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
t
OH
EHQX
t
20
70
0
20
85
0
t
HZ
EHQZ
t
Chip Enable Low to Output Valid
t
t
CE
ELQV
ELQX
t
LZ
Chip Enable Low to Output Transition
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
t
0
0
t
OH
GHQX
t
20
20
0
20
20
0
t
DF
GHQZ
t
t
t
OE
GLQV
GLQX
t
OLZ
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t
- t
after the falling edge of E without increasing t
.
ELQV
F
ELQV GLQV
F
33/66
M36W432TG, M36W432BG
Figure 13. Flash Write AC Waveforms, Write Enable Controlled
34/66
M36W432TG, M36W432BG
Table 20. Flash Write AC Characteristics, Write Enable Controlled
Flash
Unit
Symbol
Alt
Parameter
70
70
45
45
0
85
85
45
45
0
t
t
WC
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
Address Valid to Write Enable High
Data Valid to Write Enable High
Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
AVWH
AS
DS
CS
t
t
t
DVWH
t
ELWL
t
70
85
ELQV
(1,2)
Output Valid to V
PPF
Low
0
0
0
0
t
QVVPL
t
Output Valid to Write Protect Low
V High to Write Enable High
PPF
QVWPL
(1)
t
200
0
200
0
t
VPS
VPHWH
t
t
t
Write Enable High to Address Transition
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Protect High to Write Enable High
WHAX
AH
t
0
0
WHDX
WHEH
DH
CH
t
t
0
0
t
25
20
25
45
45
25
20
25
45
45
WHEL
WHGL
t
t
t
WHWL
WPH
t
t
WLWH
WP
t
WPHWH
Note: 1. Sampled only, not 100% tested.
2. Applicable if V is seen as a logic input (V
< 3.6V).
PPF
PPF
35/66
M36W432TG, M36W432BG
Figure 14. Flash Write AC Waveforms, Chip Enable Controlled
36/66
M36W432TG, M36W432BG
Table 21. Flash Write AC Characteristics, Chip Enable Controlled
Flash
Unit
Symbol
Alt
Parameter
70
70
45
45
0
85
85
45
45
0
t
t
WC
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
Address Valid to Chip Enable High
Data Valid to Chip Enable High
AVEH
AS
DS
AH
t
t
t
t
DVEH
t
Chip Enable High to Address Transition
Chip Enable High to Data Transition
Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Chip Enable Low to Chip Enable High
Chip Enable Low to Output Valid
EHAX
t
0
0
EHDX
DH
t
t
CPH
25
25
0
25
25
0
EHEL
t
EHGL
t
t
WH
EHWH
t
t
CP
45
70
45
85
ELEH
t
ELQV
(1,2)
Output Valid to V
Low
Min
Min
Min
Min
Min
0
0
0
0
ns
ns
ns
ns
ns
t
PPF
QVVPL
t
Data Valid to Write Protect Low
High to Chip Enable High
QVWPL
(1)
t
V
PPF
200
0
200
0
t
VPS
VPHEH
t
t
CS
Write Enable Low to Chip Enable Low
Write Protect High to Chip Enable High
WLEL
t
45
45
WPHEH
Note: 1. Sampled only, not 100% tested.
2. Applicable if V is seen as a logic input (V
< 3.6V).
PPF
PPF
37/66
M36W432TG, M36W432BG
Figure 15. Flash Power-Up and Reset AC Waveforms
W , E ,G
tPHWL
tPHEL
tPHGL
F
F
F
tPHWL
tPHEL
tPHGL
RP
F
tVDHPH
tPLPH
Reset
V
, V
DDF
DDQF
Power-Up
AI07931
Table 22. Flash Power-Up and Reset AC Characteristics
Flash
Symbol
Parameter
Test Condition
Unit
70
85
During
Program and
Erase
t
t
t
PHWL
Min
50
50
µs
Reset High to Write Enable Low, Chip Enable
Low, Output Enable Low
PHEL
PHGL
others
Min
Min
30
30
ns
ns
(1,2)
(3)
Reset Low to Reset High
100
100
t
PLPH
Supply Voltages High to Reset High
Min
50
50
µs
t
VDHPH
Note: 1. The device Reset is possible but not guaranteed if t
2. Sampled only, not 100% tested.
< 100ns.
PLPH
3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
F
38/66
M36W432TG, M36W432BG
SRAM DEVICE
This section describes how to use the SRAM de-
vice and all signals refer to it
SRAM SUMMARY DESCRIPTION
The SRAM is a 4Mbit asynchronous random ac-
cess memory which features a super low voltage
operation and low current consumption with an ac-
cess time of 70 ns under all conditions. The mem-
ory operations can be performed using a single
low voltage supply, 2.7V to 3.3V, which is the
same as the Flash voltage supply.
Figure 16. SRAM Logic Diagram
DATA IN DRIVERS
A0-A10
256Kb x 16
RAM Array
DQ0-DQ7
2048 x 2048
DQ8-DQ15
COLUMN DECODER
UBS
WS
A11-A17
GS
LBS
E1S
E2S
POWER-DOWN
CIRCUIT
UBS
LBS
AI07939
39/66
M36W432TG, M36W432BG
SRAM OPERATIONS
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
If the Output is enabled (E1 =V , E2 =V and
S IL S IH
G =V ), then W will return the outputs to high im-
S
IL
S
pedance within t
of its falling edge. Care must
WLQZ
be taken to avoid bus contention in this type of op-
eration. The Data input must be valid for t
be-
DVWH
fore the rising edge of Write Enable, for t
DVE1H
before the rising edge of E1 or for t
before
S
DVE2L
the falling edge of E2 , whichever occurs first, and
S
mode whenever Write Enable, W , is at V , Out-
S
IH
remain valid for t
, t
or t
(see Table
WHDX E1HAX
E2LAX
put Enable, G , is at V , Chip Enable, E1 , is at
S
IL
S
24, SRAM Write AC Characteristics, Figures 20,
21, 22 and 23).
V , Chip Enable, E2 , is at V , and Byte Enable
IL
S
IH
inputs, UB and LB are at V .
S
S
IL
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 23,
SRAM Read AC Characteristics, Figure 19, SRAM
Standby AC Waveforms). The SRAM is in Standby
mode whenever either Chip Enable is deasserted,
Valid data will be available on the output pins after
a time of t after the last stable address. If the
Chip Enable or Output Enable access times are
AVQV
not met, data access will be measured from the
limiting parameter (t
, t
, or t
) rath-
E1LQV E2HQV
GLQV
er than the address. Data out may be indetermi-
nate at t , t and t , but data lines
E1 at V or E2 at V . It is also possible when
S
IH
S
IL
E1LQX E2HQX
GLQX
UB and LB are at V .
S
S
IH
will always be valid at t
(see Table 23, Table
AVQV
23, Figures 17 and 18, SRAM Read AC Character-
istics).
Write. Write operations are used to write data to
Data Retention. The SRAM data retention per-
formance as V goes down to V are de-
DDS
DR
scribed in Table 25, SRAM Low V
Data
DDS
Retention Characteristic, and Figure 24, SRAM
Low V Data Retention AC Waveforms, E1 or
the SRAM. The SRAM is in Write mode whenever
DDS
S
W and E1 are at V , and E2 is at V . Either
S
S
IL
S
IH
UB / LB Controlled. In E1 controlled data reten-
S
S
S
the Chip Enable inputs, E1 and E2 , or the Write
S
S
tion mode, the minimum standby current mode is
entered when E1 ≥ V – 0.2V and E2 ≤ 0.2V
Enable input, W , must be deasserted during ad-
S
S
DDS
S
dress transitions for subsequent write cycles.
or E2 ≥ V
– 0.2V. In E2 controlled data re-
S
DDS
S
A Write operation is initiated when E1 is at V ,
S
IL
tention mode, minimum standby current mode is
E2 is at V and W is at V . The data is latched
S
IH
S
IL
entered when E2 ≤ 0.2V.
S
on the falling edge of E1 , the rising edge of E2
S
S
Output Disable. The data outputs are high im-
or the falling edge of W , whichever occurs last.
S
pedance when the Output Enable, G , is at V
S
IH
The Write cycle is terminated on the rising edge of
with Write Enable, W , at V .
S
IH
E1 , the rising edge of W or the falling edge of
S
S
E2 , whichever occurs first.
S
40/66
M36W432TG, M36W432BG
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DATA VALID
DQ0-DQ15
DATA VALID
AI07942
Note: E1 = Low, E2 = High, G = Low, UB and/or LB = High, W = High.
S
S
S
S
S
S
Figure 18. SRAM Read AC Waveforms, G Controlled
S
tAVAV
A0-A17
VALID
tE1LQV
tE1HQZ
E1
S
tE1LQX
tE2HQV
tE2LQZ
E2
S
tE2HQX
tBLQV
tBHQZ
UB , LB
S
S
tBLQX
tGLQV
tGHQZ
G
S
tGLQX
DQ0-DQ15
DATA VALID
AI07943
Note: Write Enable (W ) = High. Address Valid prior to or at the same time as E1 , UB and LB going Low.
S
S
S
S
Figure 19. SRAM Standby AC Waveforms
E1
S
E2
S
tPU
tPD
I
DD
50%
AI07913
41/66
M36W432TG, M36W432BG
Table 23. SRAM Read AC Characteristics
SRAM
Symbol
Alt
Parameter
Unit
Min
Max
t
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
AVAV
RC
t
t
ACC
Address Valid to Output Valid
70
AVQV
t
t
OH
Address Transition to Output Transition
UB , LB Disable to Hi-Z Output
10
AXQX
t
t
BHZ
25
70
BHQZ
S
S
t
t
UB , LB Access Time
S S
BLQV
AB
t
t
UB , LB Enable to Low-Z Output
S S
5
BLQX
BLZ
t
E1LQV
t
Chip Enable 1 Low or Chip Enable 2 High to Output Valid
70
ns
ns
ns
ACS1
t
E2HQV
t
Chip Enable 1 Low or Chip Enable 2 High to Output
Transition
E1LQX
t
10
CLZ1
t
E2HQX
t
E1HQZ
t
Chip Enable High or Chip Enable 2 Low to Output Hi-Z
25
HZCE
t
E2LQZ
t
t
OHZ
Output Enable High to Output Hi-Z
25
35
ns
ns
ns
ns
GHQZ
t
t
Output Enable Low to Output Valid
GLQV
OE
t
t
OLZ
Output Enable Low to Output Transition
Chip Enable 1 High or Chip Enable 2 Low to Power Down
5
0
GLQX
(1)
70
t
t
PD
(1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
ns
PU
Note: 1. Sampled only. Not 100% tested.
42/66
M36W432TG, M36W432BG
Figure 20. SRAM Write AC Waveforms, W Controlled
S
tAVAV
A0-A17
VALID
tAVWH
tE1LWH
tE2HWH
tWHAX
E1
S
E2
S
tAVWL
tWLWH
W
S
tBLWH
UB , LB
S
S
G
S
tGHQZ
tDVWH
INPUT VALID
tWHDZ
Note 2
DQ0-DQ15
AI07944
Note: 1. W , E1 , E2 , UB and/or LB must be asserted to initiate a write cycle. Output Enable (G ) = Low (otherwise, DQ0-DQ15 are high
S
S
S
S
S
S
impedance). If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
S
2. The I/O pins are in output mode and input signals must not be applied.
43/66
M36W432TG, M36W432BG
Figure 21. SRAM Write AC Waveforms, E1 Controlled
S
tAVAV
A0-A17
VALID
tAVE1H
tAVE2L
tE1LE1H
tE2HE2L
tAVE1L
tAVE2H
tE1HAX
tE2LAX
E1
S
E2
S
tWLE1H
tWLE2L
W
S
tBLE1H
tBLE2L
UB , LB
S
S
G
S
tDVE1H
tDVE2L
tE1HDZ
tE2LDZ
tGHQZ
DQ0-DQ15
INPUT VALID
Note 3
AI07945
Note: 1. W , E1 , E2 , UB and/or LB must be asserted to initiate a write cycle. Output Enable (G ) = Low (otherwise, DQ0-DQ15 are high
S
S
S
S
S
S
impedance). If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
S
2. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
S
3. The I/O pins are in output mode and input signals must not be applied.
44/66
M36W432TG, M36W432BG
Figure 22. SRAM Write AC Waveforms, W Controlled with G Low
S
S
tAVAV
VALID
A0-A17
tAVWH
tE1LWH
tE2HWH
tWHAX
E1
S
E2
S
tBLWH
UB , LB
S
S
tAVWL
tWLWH
W
S
tWHQX
tWHDZ
tWLQZ
tDVWH
INPUT VALID
DQ0-DQ15
AI07946
Note: 1. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
S
Figure 23. SRAM Write Cycle Waveform, UB and LB Controlled, G Low
S
S
S
tAVAV
VALID
A0-A17
tAVBH
tE1LBH
tE2HBH
E1
S
E2
S
tAVBL
tBLBH
tBHAX
UB , LB
S
S
tWLBH
W
S
tDVBH
INPUT VALID
tBHDZ
DQ0-DQ15
AI07947
Note: 1. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
S
45/66
M36W432TG, M36W432BG
Table 24. SRAM Write AC Characteristics
SRAM
Symbol
Alt
Parameter
Unit
Min
Max
t
t
WC
Write Cycle Time
70
ns
AVAV
t
,
AVE1L
t
t
,
AVE2H
t
AS
Address Valid to Beginning of Write
0
ns
AVWL,
t
AVBL
t
t
,
Address Valid to Chip Enable 1 Low or Chip Enable 2
High
AVE1H
t
t
60
60
ns
ns
AW
AVE2L
t
Address Valid to Write Enable High
AVWH
AW
t
BLWH
t
t
t
BLE1H
t
UB , LB Valid to End of Write
60
60
30
ns
ns
ns
BW
BW
DW
S
S
BLE2L
AVBH
t
t
t
UB , LB Low to UB , LB High
S S S S
BLBH
t
,
,
DVE1H
t
DVE2L
Input Valid to End of Write
t
DVWH
t
DVBH
t
,
E1HAX
t
t
t
,
E2LAX
t
End of Write to Address Change
Address Transition to End of Write
0
0
ns
ns
WR
WHAX
BHAX
t
,
,
E1HDZ
t
E2LDZ
t
HD
t
WHDZ
t
BHDZ
t
,
E1LE1H
t
t
Chip Enable 1 Low to End of Write
Chip Enable 2 High to End of Write
60
60
ns
ns
E1LBH
CW1
t
E1LWH
t
E2HE2L,
t
t
t
E2HBH,
E2HWH
CW2
t
t
Output Enable High to Output Hi-Z
Write Enable High to Input Transition
Write Enable Low to UB , LB High
25
25
ns
ns
ns
ns
GHQZ
GHZ
t
t
5
WHQX
DH
t
t
WP
50
WLBH
S
S
t
t
Write Enable Low to Output Hi-Z
WLQZ
WHZ
t
WLWH
t
t
Write Enable Pulse Width
50
ns
WLE1H
WP
t
WLE2L
46/66
M36W432TG, M36W432BG
Figure 24. SRAM Low V
Data Retention AC Waveforms, E1 or UB / LB Controlled
DDS
S
S
S
DATA RETENTION MODE
V
DDS
V
V
DDS (min)
DDS (min)
tCDR
tR
E1 or
S
UB , LB
S
S
AI07918
Table 25. SRAM Low V
Data Retention Characteristic
DDS
Symbol
Parameter
Test Condition
= 1.5V, E1 ≥ V – 0.2V,
DDS
Min
Typ
Max Unit
V
V
DDS
S
I
Supply Current (Data Retention)
3
10
µA
DDDR
≥ V – 0.2V or V ≤ 0.2V
DDS IN
IN
V
Supply Voltage (Data Retention)
Chip Disable to Power Down
Operation Recovery Time
1.5
0
3.3
V
DR
t
ns
ns
CDR
t
70
R
2. Sampled only. Not 100% tested.
47/66
M36W432TG, M36W432BG
APPENDIX A. FLASH BLOCK ADDRESS TABLES
Table 26. Top Boot Block Addresses,
M36W432TG
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F00000-F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
Size
(KWord)
#
Address Range
0
4
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
48/66
M36W432TG, M36W432BG
Table 27. Bottom Boot Block Addresses,
M36W432BG
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
Size
#
Address Range
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
49/66
M36W432TG, M36W432BG
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
structure is read from the memory. Tables 28, 29,
30, 31, 32 and 33 show the addresses used to re-
trieve the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 33, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
command to return to Read mode.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
Table 28. Query Structure Overview
Offset
00h
Sub-section Name
Description
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Reserved
10h
CFI Query Identification String
System Interface Information
Device Geometry Definition
1Bh
27h
Additional information specific to the Primary
Algorithm (optional)
P
A
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Note: Query data are always presented on the lowest order data outputs.
Table 29. CFI Query Identification String
Offset
Data
Description
Value
00h
0020h
Manufacturer Code
Device Code
ST
88BAh
88BBh
Top
Bottom
01h
02h-0Fh
10h
reserved Reserved
0051h
"Q"
"R"
"Y"
11h
0052h
0059h
0003h
0000h
0035h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII String "QRY"
12h
13h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
Intel
compatible
14h
15h
Address for Primary Algorithm extended Query table (see Table 31)
P = 35h
NA
16h
17h
Alternate Vendor Command Set and Control Interface ID Code second vendor -
specified algorithm supported (0000h means none exists)
18h
19h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
1Ah
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
50/66
M36W432TG, M36W432BG
Table 30. CFI Query System Interface Information
Offset
Data
Description
Value
V
Logic Supply Minimum Program/Erase or Write voltage
DDF
DDF
1Bh
0027h
2.7V
3.6V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
V
Logic Supply Maximum Program/Erase or Write voltage
1Ch
1Dh
1Eh
0036h
00B4h
00C6h
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
VPPF [Programming] Supply Minimum Program/Erase voltage
11.4V
12.6V
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
V
PPF
[Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
n
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0004h
000Ah
0000h
0005h
0005h
0003h
0000h
16µs
16µs
1s
Typical time-out per single word program = 2 µs
n
Typical time-out for Double/ Quadruple Word Program = 2 µs
n
Typical time-out per individual block erase = 2 ms
n
NA
Typical time-out for full chip erase = 2 ms
n
512µs
512µs
8s
Maximum time-out for word program = 2 times typical
n
Maximum time-out for Double/ Quadruple Word Program = 2 times typical
n
Maximum time-out per individual block erase = 2 times typical
n
NA
Maximum time-out for chip erase = 2 times typical
51/66
M36W432TG, M36W432BG
Table 31. Device Geometry Definition
Offset Word
Data
Description
Value
Mode
n
27h
0016h
4 MByte
Device Size = 2 in number of bytes
28h
29h
0001h
0000h
x16
Async.
Flash Device Interface Code description
2Ah
2Bh
0003h
0000h
n
8
2
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
2Ch
0002h
2Dh
2Eh
003Eh
0000h
Region 1 Information
Number of identical-size erase block = 003Eh+1
63
64 KByte
8
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase block = 0007h+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 KByte
8
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
8 KByte
63
31h
32h
003Eh
0000h
Region 2 Information
Number of identical-size erase block = 003Eh=1
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
64 KByte
52/66
M36W432TG, M36W432BG
Table 32. Primary Algorithm-Specific Extended Query Table
Offset
Data
Description
Value
(1)
P = 35h
(P+0)h = 35h
(P+1)h = 36h
(P+2)h = 37h
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+7)h = 3Ch
(P+8)h = 3Dh
0050h
0052h
0049h
0031h
0030h
0066h
0000h
0000h
0000h
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
Major version number, ASCII
Minor version number, ASCII
"1"
"0"
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
Chip Erase supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
Suspend Erase supported
Suspend Program supported
Legacy Lock/Unlock supported
Queued Erase supported
No
Yes
Yes
No
Instant individual block locking supported (1 = Yes, 0 = No)
No
Protection bits supported
Page mode read supported
Synchronous read supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
Yes
Yes
No
bit 31 to 9 Reserved; undefined bits are ‘0’
No
(P+9)h = 3Eh
0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
bit 0
bit 7 to 1
Program supported after Erase Suspend (1 = Yes, 0 = No)
Reserved; undefined bits are ‘0’
Yes
(P+A)h = 3Fh
(P+B)h = 40h
0003h
0000h
Block Lock Status
Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte
bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
(P+C)h = 41h
(P+D)h = 42h
(P+E)h = 43h
0030h
00C0h
0001h
V
V
Logic Supply Optimum Program/Erase voltage (highest performance)
3V
12V
01
DDF
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 mV
Supply Optimum Program/Erase voltage
PPF
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
(P+F)h = 44h
(P+10)h = 45h
(P+11)h = 46h
(P+12)h = 47h
0080h
0000h
0003h
0003h
Protection Field 1: Protection Description
80h
00h
This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
8 Byte
8 Byte
The following bytes are factory pre-programmed and user-programmable.
bit 0 to 7
Lock/bytes JEDEC-plane physical low address
bit 8 to 15
Lock/bytes JEDEC-plane physical high address
n
bit 16 to 23 "n" such that 2 = factory pre-programmed bytes
n
bit 24 to 31 "n" such that 2 = user programmable bytes
(P+13)h = 48h
Reserved
Note: 1. See Table 29, offset 15 for P pointer definition.
53/66
M36W432TG, M36W432BG
Table 33. Security Code Area
Offset
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
Data
00XX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Description
Protection Register Lock
64 bits: unique device number
128 bits: User Programmable OTP
54/66
M36W432TG, M36W432BG
APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES
Figure 25. Flash Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
Write 40h or 10h
/*or writeToFlash (any_address, 0x10) ; */
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
F
F
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*V
invalid error */
PPF
PPF
b3 = 0
YES
Error (1, 2)
error_handler ( ) ;
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI07932
Note: 1. Status check of b1 (Protected Block), b3 (V
a sequence.
Invalid) and b4 (Program Error) can be made after each program operation or after
PPF
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
55/66
M36W432TG, M36W432BG
Figure 26. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
F
F
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*V
invalid error */
PPF
PPF
b3 = 0
YES
Error (1, 2)
error_handler ( ) ;
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI07933
Note: 1. Status check of b1 (Protected Block), b3 (V
a sequence.
Invalid) and b4 (Program Error) can be made after each program operation or after
PPF
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
56/66
M36W432TG, M36W432BG
Figure 27. Quadruple Word Program Flowchart and Pseudo Code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
Write 56h
Write Address 1
& Data 1 (3)
writeToFlash (any_address, 0x56) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
F
F
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*V
invalid error */
PPF
PPF
b3 = 0
YES
Error (1, 2)
error_handler ( ) ;
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI07934
Note: 1. Status check of b1 (Protected Block), b3 (V
a sequence.
Invalid) and b4 (Program Error) can be made after each program operation or after
PPF
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
57/66
M36W432TG, M36W432BG
Figure 28. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
F
F
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
b2 = 1
YES
Program Complete
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
}
Read data from
another address
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
Write FFh
Read Data
}
}
Program Continues
AI07935
58/66
M36W432TG, M36W432BG
Figure 29. Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
F
F
NO
b7 = 1
} while (status_register.b7== 0) ;
YES
NO
YES
NO
NO
V
Invalid
Error (1)
if (status_register.b3==1) /*V
error_handler ( ) ;
invalid error */
PPF
PPF
b3 = 0
YES
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
Command
Sequence Error (1)
b4, b5 = 1
NO
error_handler ( ) ;
if ( (status_register.b5==1) )
/* erase error */
b5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI07936
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
59/66
M36W432TG, M36W432BG
Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code
Start
erase_suspend_command ( ) {
Write B0h
Write 70h
writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
F
F
NO
NO
} while (status_register.b7== 0) ;
b7 = 1
YES
if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
b6 = 1
YES
Erase Complete
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
Write D0h
Write FFh
Read Data
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
Erase Continues
AI07937
60/66
M36W432TG, M36W432BG
Figure 31. Locking Operations Flowchart and Pseudo Code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (any_address, 0x60) ; /*configuration setup*/
Write 60h
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
Write
01h, D0h or 2Fh
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
writeToFlash (any_address, 0x90) ;
Write 90h
Read Block
Lock States
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
NO
Locking
change
/*Check the locking state (see Read Block Signature table )*/
confirmed?
YES
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
Write FFh
}
End
AI04364
61/66
M36W432TG, M36W432BG
Figure 32. Protection Register Program Flowchart and Pseudo Code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
Write C0h
writeToFlash (any_address, 0xC0) ;
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
F
F
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*V
invalid error */
PPF
PPF
b3 = 0
YES
Error (1, 2)
error_handler ( ) ;
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI07938
Note: 1. Status check of b1 (Protected Block), b3 (V
a sequence.
Invalid) and b4 (Program Error) can be made after each program operation or after
PPF
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
62/66
M36W432TG, M36W432BG
APPENDIX D. FLASH COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE
Table 34. Write State Machine Current/Next, sheet 1 of 2.
Command Input (and Next State)
Data
When
Read
Current
State
SR
bit 7
Read
Array
(FFh)
Program
Setup
(10/40h)
Erase
Setup
(20h)
Erase
Confirm
(D0h)
Prog/Ers
Suspend
(B0h)
Prog/Ers
Resume
(D0h)
Read
Status
(70h)
Clear
Status
(50h)
Read Array
“1”
“1”
Array
Read Array Prog.Setup Ers. Setup
Read Array
Read Sts. Read Array
Read
Status
Program
Setup
Erase
Setup
Read
Status
Read Array
Read Array
Read Array
Read Array
Read Array
Status
Read
Elect.Sg.
Electronic
Signature
Program
Setup
Erase
Setup
Read
“1”
“1”
“1”
“1”
“1”
“1”
“0”
“1”
Read Array
Read Array
Read Array
Status
Read CFI
Query
Program
Setup
Erase
Setup
Read
CFI
Read Array
Status
Lock
(complete)
Lock Cmd
Error
Lock
(complete)
Lock Setup
Status
Status
Status
Status
Status
Lock Command Error
Program
Lock Command Error
Lock Cmd
Error
Erase
Setup
Read
Read Array
Read Array
Read Array
Read Array
Status
Setup
Lock
(complete)
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Status
Prot. Prog.
Setup
Protection Register Program
Protection Register Program continue
Prot. Prog.
(continue)
Prot. Prog.
(complete)
Program
Setup
Erase
Setup
Read
Status
Status
Status
Read Array
Read Array
Program
Read Array
Status
Prog. Setup “1”
Program
“0”
Prog. Sus
Read Sts
Program (continue)
Program (continue)
(continue)
Prog. Sus
“1”
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
Status
Array
Status
(continue) Read Array (continue)
Program Prog. Sus Program
(continue) Read Array (continue)
Prog. Sus
“1”
Prog. Sus
Read Array
Program Suspend to
Read Array
Prog. Sus Prog. Sus
Read Sts Read Array
Read Array
Prog. Sus
Read
Elect.Sg.
Electronic Prog. Sus
Signature Read Array
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
“1”
(continue) Read Array (continue)
Prog. Sus
Read CFI
Prog. Sus
CFI
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
“1”
“1”
“1”
“1”
“0”
“1”
“1”
Read Array
(continue) Read Array (continue)
Program
(complete)
Program
Setup
Erase
Setup
Read
Status
Status
Status
Status
Status
Array
Read Array
Read Array
Read Array
Status
Erase
Setup
Erase
Erase
Erase
Erase Command Error
Erase Command Error
(continue) CmdError (continue)
Erase
Cmd.Error
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Read Array
Status
Erase
(continue)
Erase Sus
Read Sts
Erase (continue)
Erase (continue)
Erase Sus
Read Sts
Erase Sus
Read Array
Program Erase Sus
Erase
Erase Sus
Erase
Erase
Erase Sus Erase Sus
Read Sts Read Array
Setup
Read Array (continue) Read Array (continue)
Erase Sus
Read Array
Erase Sus
Read Array
Program
Setup
Erase Sus
Erase
Erase Sus
Erase Sus Erase Sus
Read Sts Read Array
Read Array (continue) Read Array (continue)
Erase Sus
Read
Elect.Sg.
Electronic Erase Sus
Signature Read Array
Program
Setup
Erase Sus
Erase
Erase Sus
Erase
Erase Sus Erase Sus
Read Sts Read Array
“1”
Read Array (continue) Read Array (continue)
Erase Sus
Read CFI
Erase Sus
CFI
Program
Setup
Erase Sus
Erase
Erase Sus
Erase
Erase Sus Erase Sus
Read Sts Read Array
“1”
“1”
Read Array
Read Array (continue) Read Array (continue)
Erase
(complete)
Program
Setup
Erase
Read
Status
Read Array
Read Array
Setup
Read Array
Status
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
63/66
M36W432TG, M36W432BG
Table 35. Write State Machine Current/Next, sheet 2 of 2.
Command Input (and Next State)
Read CFI
Query
(98h)
Unlock
Confirm
(D0h)
Current State
Read Elect.Sg.
(90h)
Lock Setup
(60h)
Prot. Prog.
Setup (C0h)
Lock Confirm
(01h)
Lock Down
Confirm (2Fh)
Prot. Prog.
Setup
Read Array
Read Elect.Sg. Read CFI Query
Read Elect.Sg. Read CFI Query
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Read Array
Read Array
Read Array
Prot. Prog.
Setup
Read Status
Prot. Prog.
Setup
Read Elect.Sg. Read Elect.Sg. Read CFI Query
Read CFI Query Read Elect.Sg. Read CFI Query
Prot. Prog.
Setup
Read Array
Lock (complete)
Read Array
Lock Setup
Lock Command Error
Prot. Prog.
Setup
Lock Cmd Error Read Elect.Sg. Read CFI Query
Lock Setup
Lock Setup
Prot. Prog.
Setup
Lock (complete) Read Elect.Sg. Read CFI Query
Read Array
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(continue)
Protection Register Program (continue)
Prot. Prog.
Prot. Prog.
Lock Setup
Read Elect.Sg. Read CFI Query
(complete)
Read Array
Setup
Prog. Setup
Program
Program
(continue)
Program (continue)
Prog. Suspend Prog. Suspend Prog. Suspend
Program
(continue)
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Read Status
Prog. Suspend Prog. Suspend Prog. Suspend
Read Array Read Elect.Sg. Read CFI Query
Read Elect.Sg. Read CFI Query
Program
(continue)
Prog. Suspend Prog. Suspend Prog. Suspend
Read Elect.Sg. Read Elect.Sg. Read CFI Query
Program
(continue)
Prog. Suspend Prog. Suspend Prog. Suspend
Program
(continue)
Read CFI
Read Elect.Sg. Read CFI Query
Program
(complete)
Prot. Prog.
Lock Setup
Read Elect.Sg. Read CFIQuery
Read Array
Read Array
Setup
Erase
(continue)
Erase Setup
Erase Command Error
Erase
Cmd.Error
Prot. Prog.
Lock Setup
Read Elect.Sg. Read CFI Query
Setup
Erase (continue)
Erase (continue)
Erase Suspend Erase Suspend Erase Suspend
Read Ststus Read Elect.Sg. Read CFI Query
Erase
(continue)
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Erase Suspend Erase Suspend
Read Array Read Elect.Sg. Read CFI Query
Erase
(continue)
Erase Suspend Erase Suspend Erase Suspend
Read Elect.Sg. Read Elect.Sg. Read CFI Query
Erase
(continue)
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Erase Suspend Erase Suspend
Read CFI Query Read Elect.Sg. Read CFI Query
Erase
(continue)
Erase
Prot. Prog.
Setup
Read Elect.Sg. Read CFI Query
(complete)
Read Array
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
64/66
M36W432TG, M36W432BG
REVISION HISTORY
Table 36. Document Revision History
Date
Version
Revision Details
19-Nov-2002
1.0
First Issue
65/66
M36W432TG, M36W432BG
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2002 STMicroelectronics - All Rights Reserved
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66/66
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