M36WT864BF70ZA6 [STMICROELECTRONICS]
SPECIALTY MEMORY CIRCUIT, PBGA96, 8 X 14 MM, 0.80 MM PITCH, STACK, LFBGA-96;
| 型号： | M36WT864BF70ZA6 |
| 厂家： | 
ST |
| 描述： | SPECIALTY MEMORY CIRCUIT, PBGA96, 8 X 14 MM, 0.80 MM PITCH, STACK, LFBGA-96 |
| 文件： | 总92页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36WT864TF
M36WT864BF
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory
and 8 Mbit (512K x16) SRAM, Multiple Memory Product
PRODUCT PREVIEW
FEATURES SUMMARY
■ SUPPLY VOLTAGE
SRAM
■ 8 Mbit (512K x 16 bit)
■ EQUAL CYCLE and ACCESS TIMES: 70ns
– V
– V
– V
= 1.65V to 2.2V
DDF
DDS
PPF
= V
= 2.7V to 3.3V
DDQF
■ LOW STANDBY CURRENT
= 12V for Fast Program (optional)
■ LOW V
DATA RETENTION: 1.5V
DDS
■ ACCESS TIME: 70, 85, 100ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
■ TRI-STATE COMMON I/O
■ AUTOMATIC POWER DOWN
– Manufacturer Code: 20h
Figure 1. Packages
– Top Device Code, M36WT864TF: 8810h
– Bottom Device Code, M36WT864BF: 8811h
FLASH MEMORY
■ PROGRAMMING TIME
– 8µs by Word typical for Fast Factory Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■ MEMORY BLOCKS
FBGA
– Multiple Bank Memory Array: 4 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■ DUAL OPERATIONS
Stacked LFBGA96 (ZA)
8 x 14mm
– Program Erase in one Bank while Read in
others
– No delay between Read and Write operations
■ BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
■ SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently lockable
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
July 2002
1/92
This is preliminary information on a new product now in development. Details are subject to change without notice.
M36WT864TF, M36WT864BF
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A19-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Clock (KF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Wait (WAITF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
V
V
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDF
and V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DDS
DDQF
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PPF
V
and V
Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SSF , SSQF
SSS
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 11
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Flash Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FLASH BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FLASH COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16
2/92
M36WT864TF, M36WT864BF
Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Flash Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . 22
COMMAND INTERFACE - FACTORY PROGRAM COMMANDS. . . . . . . . . . . . . . . . . . . . . . . . . 23
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Enhanced Factory Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Program and Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Flash Factory Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program/Erase Controller Status Bit (SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
V
PPF
Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Flash Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/92
M36WT864TF, M36WT864BF
FLASH CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Wait Polarity Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Output Configuration Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Flash Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. Wait Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FLASH READ MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Single Synchronous Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FLASH DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FLASH BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES. . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Flash Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/92
M36WT864TF, M36WT864BF
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Flash DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 19. Flash DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. Flash Asynchronous Random Access Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . 45
Figure 12. Flash Asynchronous Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Flash Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Flash Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. Flash Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 15. Flash Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22. Flash Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 17. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 24. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 18. Flash Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 25. Flash Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 19. SRAM Address Controlled, Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms. . . . . . . . . . . . 56
Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms . . . . . . . . . . . . . 57
Table 26. SRAM Read and Standby AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 22. SRAM Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 23. SRAM Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 24. SRAM Write AC Waveforms, UB/LB Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 27. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25. SRAM Low VDD Data Retention AC Waveforms, E1S Controlled. . . . . . . . . . . . . . . . . 61
Figure 26. SRAM Low VDD Data Retention AC Waveforms, E2S Controlled. . . . . . . . . . . . . . . . . 61
Table 28. SRAM Low VDD Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline
62
Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Package Mechanical Data62
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
APPENDIX A. FLASH BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5/92
M36WT864TF, M36WT864BF
Table 32. Flash Top Boot Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 33. Flash Bottom Boot Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
APPENDIX B. FLASH COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 34. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 35. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 36. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 37. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 38. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 39. Protection Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 40. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 41. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 42. Bank and Erase Block Region 1 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 43. Bank and Erase Block Region 2 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 28. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 31. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 79
Figure 32. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 33. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 34. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 35. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 83
Figure 36. Enhanced Factory Program Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 37. Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
APPENDIX D. FLASH COMMAND INTERFACE STATE TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 44. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 45. Command Interface States - Modify Table, Next Output. . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 46. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 47. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6/92
M36WT864TF, M36WT864BF
SUMMARY DESCRIPTION
The M36WT864 is a low voltage Multiple Memory
Product which combines two memory devices; a
64 Mbit Multiple Bank Flash memory and an 8 Mbit
SRAM. Recommended operating conditions do
not allow both the Flash and the SRAM to be ac-
tive at the same time.
Table 1. Signal Names
A0-A18
Address Inputs
A19-A21
DQ0-DQ15
Address Inputs for Flash Chip only
Data Input/Output
The memory is offered in a Stacked LFBGA96 (8
x 14mm, 0.8 mm pitch) package and is supplied
with all the bits erased (set to ‘1’).
V
Flash Power Supply
DDF
V
Flash Power Supply for I/O Buffers
DDQF
Flash Optional Supply Voltage for Fast
Program & Erase
Figure 2. Logic Diagram
V
PPF
V
V
V
V
Flash Ground
SSF
V
V
DDQF
DDS
Flash Ground for I/O Buffers
SRAM Power Supply
SRAM Ground
SSQF
DDS
SSS
V
V
PPF
DDF
22
16
DQ0-DQ15
A0-A21
EF
NC
DU
Not Connected Internally
Do Not Use as Internally Connected
GF
Flash control functions
WF
WAITF
LF
Latch Enable input
RPF
WPF
LF
EF
Chip Enable input
Output Enable input
Write Enable input
Reset input
M36WT864TF
M36WT864BF
GF
KF
WF
E1S
E2S
GS
RPF
WPF
KF
Write Protect input
Flash Burst Clock
Wait Data in Burst Mode
WS
UBS
LBS
WAITF
SRAM control functions
E1S, E2S
GS
Chip Enable inputs
V
V
SSF
SSS
Output Enable input
Write Enable input
V
SSQF
WS
AI06270
UBS
Upper Byte Enable input
Lower Byte Enable input
LBS
7/92
M36WT864TF, M36WT864BF
Figure 3. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
NC
NC
A4
NC
NC
#A
#B
A
NC
NC
NC
NC
A11
A12
A13
A15
A16
DU
A18
LBS
A17
A7
A19
NC
V
V
V
WS
KF
A21
NC
SSS
SSS
PPF
A5
B
E2S
V
DDS
C
A3
NC
V
V
A9
DDF
LF
SSF
A2
D
NC
WPF
RP
A20
A8
A10
A14
WAITF
DQ7
DQ15
E
A1
A6
UBS
DQ2
DQ1
DQ9
DU
WF
DQ5
DQ12
DQ4
F
A0
DQ8
DQ0
GF
DQ10
DQ3
DQ11
DQ13
DQ14
DQ6
DU
G
GS
E1S
EF
DU
DU
H
J
DU
V
V
V
V
DDS
DDS
DDQF
SSS
SSS
V
K
V
V
V
V
V
V
V
SSS
SSQF
NC
DDQF
DDF
SSS
SSQF
SSF
NC
NC
NC
#C
#D
NC
NC
NC
NC
AI06271
8/92
M36WT864TF, M36WT864BF
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
When Reset is at V , the device is in normal op-
IH
eration. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
Address Inputs (A0-A18). Addresses
A0-A18
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (EF) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Address Inputs (A19-A21). Addresses A19-A21
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (EF). The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to Table 19, DC Characteristics).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is at V
IL
and it is inhibited when Latch Enable is at V .
IH
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF). The clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V . Clock is don't care during
IL
asynchronous read and in write operations.
Flash Wait (WAITF). Wait is a Flash output signal
used during synchronous read to indicate whether
the data on the output bus are valid. This output is
high impedance when Flash Chip Enable is at V
IH
able is at V and Reset is at V the device is in ac-
or Flash Reset is at V . It can be configured to be
IL
IH
IL
tive mode. When Chip Enable is at V
the
active during the wait cycle or one clock cycle in
advance. The WAITF signal is not gated by Output
Enable.
IH
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
stand-by level.
SRAM Chip Enable (E1S, E2S). The Chip En-
Flash Output Enable (GF). The Output Enable
controls data outputs during the Bus Read opera-
tion of the memory.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the memory’s
Command Interface. The data and address inputs
are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at V or
IH
E2S at V deselects the memory and reduces the
IL
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at V It
IL.
is not allowed to set EF at V E1S at V and E2S
IL,
IL
at V at the same time.
IH
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V , the
IL
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UBS is active low.
When Write Protect is at V , the Lock-Down is
IH
disabled and the Locked-Down blocks can be
locked or unlocked. (refer to Table 13, Lock Sta-
tus).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable input enables the lower byte for
SRAM (DQ0-DQ7). LBS is active low.
V , the memory is in reset mode: the outputs are
IL
high impedance and the current consumption is
reduced to the Reset Supply Current I
. Refer to
DD2
V
Supply Voltage. V
supply to the internal core of the Flash memory de-
provides the power
DDF
DDF
Table 2, DC Characteristics - Currents for the val-
ue of I After Reset all blocks are in the Locked
DD2.
state and the Configuration Register is reset.
9/92
M36WT864TF, M36WT864BF
vice. It is the main power supply for all Flash oper-
ations (Read, Program and Erase).
is only sampled at the beginning of a program or
erase; a change in its value after the operation has
started does not have any effect and program or
erase operations continue.
V
and V
Supply Voltage. V
pro-
vides the power supply for the Flash memory I/O
pins and V provides the power supply for the
DDQF
DDS
DDQF
If V
is in the range of V
it acts as a power
PPHF
DDS
PPF
SRAM control and I/O pins. This allows all Outputs
to be powered independently from the Flash core
supply pin. In this condition V
until the Program/Erase algorithm is completed.
must be stable
PPF
power supply, V
it can use a separate supply.
. V
can be tied to V
or
DDF
DDQF
DDS
V
and V
V
SSS
and V Grounds. V
are the ground references for all voltage
,
V
SSQF
SSF , SSQF
SSS
SSF
V
Program Supply Voltage. V
is both a
PPF
measurements in the Flash (core and I/O Buffers)
and SRAM chips, respectively.
Note: Each device in a system should have
PPF
Flash control input and a Flash power supply pin.
The two functions are selected by the voltage
range applied to the pin.
V
and V
decoupled with a 0.1µF ceramic
DDF
PPF
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10, AC Measurement Load Circuit. The
PCB trace widths should be sufficient to carry
If V
)
DDQF
PPF
V
PPF
age lower than V
tion against program or erase, while V
enables these functions (see Tables 18 and 19,
DC Characteristics for the relevant values). V
PP1F
the required V
program and erase currents.
PPF
PPF
10/92
M36WT864TF, M36WT864BF
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF for the Flash mem-
ory and, E1S and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
Figure 4. Functional Block Diagram
V
V
V
DDF DDQF PPF
EF
GF
WF
RPF
WPF
LF
Flash Memory
64 Mbit (x16)
WAITF
KF
A19-A21
A0-A18
V
V
SSQF
SSF
V
DQ0-DQ15
DDS
E1S
E2S
GS
SRAM
8 Mbit (x 16)
WS
UBS
LBS
V
SSS
AI06272
11/92
M36WT864TF, M36WT864BF
Table 2. Main Operation Modes
Operation Mode EF
GF
WF
LF
RPF WAITF E1S E2S GS WS UBS, LBS DQ15-DQ0
(2)
V
V
V
V
V
Bus Read
Bus Write
SRAM must be disabled
SRAM must be disabled
Data Output
V
IL
IL
IL
IH
IH
IH
IL
(2)
V
IH
V
V
Data Input
IL
V
IL
Data Output
Address
Latch
V
V
V
V
X
SRAM must be disabled
SRAM must be disabled
IL
IL
IH
IL
IH
(3)
or Hi-Z
Output
Disable
V
V
V
IH
V
IH
V
V
X
Hi-Z
IH
Standby
Reset
X
X
X
X
X
X
Hi-Z
Hi-Z
Any SRAM mode is allowed
Any SRAM mode is allowed
Hi-Z
Hi-Z
IH
IH
V
X
IL
Data out
Word Read
V
V
V
V
V
Read
Write
Flash must be disabled
Flash must be disabled
IL
IL
IH
IH
IL
IH
IL
IL
Data in
Word Write
V
V
V
V
IL
V
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
IH
Standby/
Power Down
V
Any Flash mode is allowable
X
X
X
X
IL
IL
V
X
X
IH
Data
Retention
Any Flash mode is allowable
Any Flash mode is allowable
V
IH
V
V
X
X
X
X
Hi-Z
Hi-Z
Output
Disable
V
V
V
IH
IL
IH
IH
Note: 1. X = Don't care.
2. L can be tied to V if the valid address has been previously latched.
IH
3. Depends on G.
4. WAIT signal polarity is configured using the Set Configuration Register command.
12/92
M36WT864TF, M36WT864BF
Flash Memory Component
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In synchronous burst mode,
data is output on each clock cycle at frequencies
of up to 54MHz.
The Flash memory is a 64 Mbit (4Mbit x16) non-
volatile Flash memory that may be erased electri-
cally at block level and programmed in-system on
a Word-by-Word basis using a 1.65V to 2.2V V
supply for the circuitry and a 1.65V to 3.3V V
DD
DDQ
supply for the Input/Output pins. An optional 12V
power supply is provided to speed up cus-
tomer programming.
The device features an Automatic Standby mode.
During asynchronous read operations, after a bus
inactivity of 150ns, the device automatically
switches to the Automatic Standby mode. In this
condition the power consumption is reduced to the
V
PPF
The device features an asymmetrical block archi-
tecture with an array of 135 blocks divided into 4
Mbit banks. There are 15 banks each containing 8
main blocks of 32 KWords, and one parameter
bank containing 8 parameter blocks of 4 KWords
and 7 main blocks of 32 KWords. The Multiple
Bank Architecture allows Dual Operations, while
programming or erasing in one bank, Read opera-
tions are possible in other banks. Only one bank at
a time is allowed to be in Program or Erase mode.
It is possible to perform burst reads that cross
bank boundaries. The bank architecture is sum-
marized in Table 3, and the memory maps are
shown in Figure 5. The Parameter Blocks are lo-
cated at the top of the memory address space for
the M36WT864TF, and at the bottom for the
M36WT864BF.
standby value I
and the outputs are still driven.
DD4
The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
≤ V
all blocks are protected
PPF
PPLK
against program or erase. All blocks are locked at
Power- Up.
The device includes a Protection Register and a
Security Block to increase the protection of a sys-
tem’s design. The Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 128 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 6, shows the Security Block and
Protection Register Memory Map.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V . There are two Enhanced Factory
DD
programming commands available to speed up
programming.
SRAM Component
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The SRAM is an 8 Mbit (512Kb x16) asynchronous
random access memory which features a super
low voltage operation and low current consump-
tion with an access time of 70ns. The memory op-
erations can be performed using a single low
voltage supply, 2.7V to 3.3V.
13/92
M36WT864TF, M36WT864BF
Table 3. Flash Bank Architecture
Number
Parameter Bank
Bank 0
Bank Size
Parameter Blocks
Main Blocks
4 Mbits
4 Mbits
4 Mbits
4 Mbits
8 blocks of 4 KWords
7 blocks of 32 KWords
8 blocks of 32 KWords
8 blocks of 32 KWords
8 blocks of 32 KWords
-
-
-
Bank 1
Bank 2
Bank 13
Bank 14
4 Mbits
4 Mbits
-
-
8 blocks of 32 KWords
8 blocks of 32 KWords
Figure 5. Flash Block Addresses
Top Boot Block
Bottom Boot Block
Address lines A21-A0
Address lines A21-A0
000000h
32 KWord
007FFFh
000000h
000FFFh
4 KWord
8 Main
Blocks
8 Parameter
Blocks
Bank 14
038000h
32 KWord
03FFFFh
007000h
4KWord
Parameter
Bank
007FFFh
008000h
00FFFFh
32 KWord
7 Main
Blocks
038000h
03FFFFh
040000h
047FFFh
32 KWord
32 KWord
300000h
32 KWord
307FFFh
8 Main
Blocks
8 Main
Blocks
Bank 2
Bank 0
Bank 1
Bank 2
338000h
32 KWord
33FFFFh
340000h
32 KWord
377FFFh
078000h
07FFFFh
080000h
087FFFh
32 KWord
32 KWord
8 Main
Blocks
8 Main
Blocks
Bank 1
378000h
32 KWord
37FFFFh
380000h
32 KWord
387FFFh
0B8000h
0BFFFFh
0C0000h
0C7FFFh
32 KWord
32 KWord
8 Main
Blocks
8 Main
Blocks
Bank 0
3D8000h
32 KWord
3BFFFFh
3C0000h
32 KWord
3C7FFFh
0F8000h
0FFFFFh
32 KWord
7 Main
Blocks
3F0000h
32 KWord
Parameter
Bank
3F7FFFh
3F8000h
3F8FFFh
3C0000h
3C7FFFh
4 KWord
32 KWord
32 KWord
8 Parameter
Blocks
8 Main
Blocks
Bank 14
3FF000h
3FFFFFh
3F8000h
3FFFFFh
4 KWord
AI06273
14/92
M36WT864TF, M36WT864BF
FLASH BUS OPERATIONS
There are six standard bus operations that control
the Flash device. These are Bus Read, Bus Write,
Address Latch, Output Disable, Standby and Re-
set. See Table 2, Main Operating Modes, for a
summary.
the Latch Enable should be tied to V during the
bus write operation.
See Figures 16 and 17, Write AC Waveforms, and
Tables 23 and 24, Write AC Characteristics, for
details of the timing requirements.
IH
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at V during address latch opera-
IL
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high imped-
ance when the Output Enable is at V .
IH
Output Enable must be at V in order to perform a
IL
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures 11, 12, 13 and 14 Read AC Wave-
forms, and Tables 21 and 22 Read AC Character-
istics, for details of when the output becomes
valid.
when Chip Enable and Reset are at V . The pow-
IH
er consumption is reduced to the stand-by level
and the outputs are set to high impedance, inde-
pendently from the Output Enable or Write Enable
inputs. If Chip Enable switches to V during a pro-
IH
gram or erase operation, the device enters Stand-
by mode when finished.
Reset. During Reset mode the memory is dese-
Bus Write. Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
lected and the outputs are high impedance. The
memory is in Reset mode when Reset is at V .
IL
when Chip Enable and Write Enable are at V with
IL
The power consumption is reduced to the Standby
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
Output Enable at V . Commands, Input Data and
IH
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
V
during a Program or Erase, this operation is
SS
aborted and the memory content is no longer valid.
15/92
M36WT864TF, M36WT864BF
FLASH COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
Table 4. Command Codes
Hex Code
01h
Command
Block Lock Confirm
03h
Set Configuration Register Confirm
Alternative Program Setup
Block Erase Setup
10h
20h
The Command Interface is reset to read mode
when power is first applied, when exiting from Re-
2Fh
Block Lock-Down Confirm
Enhanced Factory Program Setup
Double Word Program Setup
Program Setup
30h
set or whenever V
is lower than V
. Com-
DD
LKO
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to read mode.
35h
40h
Refer to Table 4, Command Codes and Appendix
D, Tables 44, 45, 46 and 47, Command Interface
States - Modify and Lock Tables, for a summary of
the Command Interface.
The Command Interface is split into two types of
commands: Standard commands and Factory
Program commands. The following sections ex-
plain in detail how to perform each command.
50h
Clear Status Register
56h
Quadruple Word Program Setup
Block Lock Setup, Block Unlock Setup,
Block Lock Down Setup and Set
Configuration Register Setup
60h
70h
75h
Read Status Register
Quadruple Enhanced Factory Program
Setup
80h
90h
98h
B0h
C0h
Bank Erase Setup
Read Electronic Signature
Read CFI Query
Program/Erase Suspend
Protection Register Program
Program/Erase Resume, Block Erase
Confirm, Bank Erase Confirm, Block
Unlock Confirm or Enhanced Factory
Program Confirm
D0h
FFh
Read Array
16/92
M36WT864TF, M36WT864BF
COMMAND INTERFACE - STANDARD COMMANDS
The following commands are the basic commands
used to read, write to and configure the device.
Refer to Table 5, Standard Commands, in con-
junction with the following text descriptions.
Read CFI Query Command
The Read CFI Query command is used to read
data from the Common Flash Interface (CFI). The
Read CFI Query Command consists of one Bus
Write cycle, to an address within one of the banks.
Once the command is issued subsequent Bus
Read operations in the same bank read from the
Common Flash Interface.
If a Read CFI Query command is issued in a bank
that is executing a Program or Erase operation the
bank will go into Read CFI Query mode, subse-
quent Bus Read cycles will output the CFI data
and the Program/Erase controller will continue to
Program or Erase in the background. This mode
supports asynchronous or single synchronous
reads only, it does not support page mode or syn-
chronous burst reads.
Read Array Command
The Read Array command returns the addressed
bank to Read Array mode. One Bus Write cycle is
required to issue the Read Array command and re-
turn the addressed bank to Read Array mode.
Subsequent read operations will read the ad-
dressed location and output the data. A Read Ar-
ray command can be issued in one bank while
programming or erasing in another bank. However
if a Read Array command is issued to a bank cur-
rently executing a Program or Erase operation the
command will be executed but the output data is
not guaranteed.
Read Status Register Command
The status of the other banks is not affected by the
command (see Table 11). After issuing a Read
CFI Query command, a Read Array command
should be issued to the addressed bank to return
the bank to Read Array mode.
The Status Register indicates when a Program or
Erase operation is complete and the success or
failure of operation itself. Issue a Read Status
Register command to read the Status Register
content. The Read Status Register command can
be issued at any time, even during Program or
Erase operations.
The following read operations output the content
of the Status Register of the addressed bank. The
Status Register is latched on the falling edge of E
or G signals, and can be read until E or G returns
See Appendix C, Common Flash Interface, Tables
34, 35, 36, 37, 38, 40, 41, 42 and 43 for details on
the information contained in the Common Flash In-
terface memory area.
Clear Status Register Command
The Clear Status Register command can be used
to reset (set to ‘0’) error bits 1, 3, 4 and 5 in the Sta-
tus Register. One bus write cycle is required to is-
sue the Clear Status Register command. After the
Clear Status Register command the bank returns
to read mode.
to V . Either E or G must be toggled to update the
IH
latched data. See Table 8 for the description of the
Status Register Bits. This mode supports asyn-
chronous or single synchronous reads only.
Read Electronic Signature Command
The error bits in the Status Register do not auto-
matically return to ‘0’ when a new command is is-
sued. The error bits in the Status Register should
be cleared before attempting a new Program or
Erase command.
The Read Electronic Signature command reads
the Manufacturer and Device Codes, the Block
Locking Status, the Protection Register, and the
Configuration Register.
The Read Electronic Signature command consists
of one write cycle to an address within one of the
banks. A subsequent Read operation in the same
bank will output the Manufacturer Code, the De-
vice Code, the protection Status of the blocks in
the targeted bank, the Protection Register, or the
Configuration Register (see Table 6).
If a Read Electronic Signature command is issued
in a bank that is executing a Program or Erase op-
eration the bank will go into Read Electronic Sig-
nature mode, subsequent Bus Read cycles will
output the Electronic Signature data and the Pro-
gram/Erase controller will continue to program or
erase in the background. This mode supports
asynchronous or single synchronous reads only, it
does not support page mode or synchronous burst
reads.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error. The Block
Erase command can be issued at any moment, re-
gardless of whether the block has been pro-
grammed or not.
Two Bus Write cycles are required to issue the
command.
■ The first bus cycle sets up the Erase command.
■ The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
17/92
M36WT864TF, M36WT864BF
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits 4 and 5 are set and the
command aborts. Erase aborts if Reset turns to
CFI Query command, all other commands will be
ignored. A Bank Erase operation cannot be sus-
pended.
V . As data integrity cannot be guaranteed when
the Erase operation is aborted, the block must be
erased again.
IL
Refer to Dual Operations section for detailed infor-
mation about simultaneous operations allowed in
banks not being erased. Typical Erase times are
given in Table 14, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Erase operations the bank containing the
block being erased will only accept the Read Ar-
ray, Read Status Register, Read Electronic Signa-
ture, Read CFI Query and the Program/Erase
Suspend command, all other commands will be ig-
nored. Refer to Dual Operations section for de-
tailed information about simultaneous operations
allowed in banks not being erased. Typical Erase
times are given in Table 14, Program, Erase
Times and Program/Erase Endurance Cycles.
Program Command
The memory array can be programmed word-by-
word. Only one Word in one bank can be pro-
grammed at any one time. Two bus write cycles
are required to issue the Program Command.
■ The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
After programming has started, read operations in
the bank being programmed output the Status
Register content.
See Appendix C, Figure 32, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
for using the Block Erase command.
During Program operations the bank being pro-
grammed will only accept the Read Array, Read
Status Register, Read Electronic Signature, Read
CFI Query and the Program/Erase Suspend com-
mand. Refer to Dual Operations section for de-
tailed information about simultaneous operations
allowed in banks not being programmed. Typical
Program times are given in Table 14, Program,
Erase Times and Program/Erase Endurance Cy-
cles.
Bank Erase Command
The Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
’1’. All previous data in the bank is lost. The Bank
Erase command will ignore any protected blocks
within the bank. If all blocks in the bank are pro-
tected then the Bank Erase operation will abort
and the data in the bank will not be changed. The
Status Register will not output any error.
Two Bus Write cycles are required to issue the
command.
■ The first bus cycle sets up the Bank Erase
Programming aborts if Reset goes to V . As data
IL
integrity cannot be guaranteed when the program
operation is aborted, the memory location must be
reprogrammed.
See Appendix C, Figure 28, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
command.
■ The second latches the bank address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Bank Erase
Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. A
Bank Erase operation cannot be suspended.
One bus write cycle is required to issue the Pro-
gram/Erase command. Once the Program/Erase
Controller has paused bits SR7, SR6 and/ or SR2
of the Status Register will be set to ‘1’. The com-
mand can be addressed to any bank.
Reset turns to V . As data integrity cannot be
IL
guaranteed when the Erase operation is aborted,
the bank must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Bank Erase operations the bank being
erased will only accept the Read Array, Read Sta-
tus Register, Read Electronic Signature and Read
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array (cannot read the suspended block),
Read Status Register, Read Electronic Signature
and Read CFI Query commands. Additionally, if
the suspend operation was Erase then the Clear
status Register, Program, Block Lock, Block Lock-
Down or Block Unlock commands will also be ac-
cepted. The block being erased may be protected
18/92
M36WT864TF, M36WT864BF
by issuing the Block Lock, Block Lock-Down or
Protection Register Program commands. Only the
blocks not being erased may be read or pro-
grammed correctly. When the Program/Erase Re-
sume command is issued the operation will
complete. Refer to the Dual Operations section for
detailed information about simultaneous opera-
tions allowed during Program/Erase Suspend.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register. Bit 1 of the Pro-
tection Lock Register also protects bit 2 of the Pro-
tection Lock Register. Programming bit 2 of the
Protection Lock Register will result in a permanent
protection of Parameter Block #0 (see Figure 6,
Security Block and Protection Register Memory
Map). Attempting to program a previously protect-
ed Protection Register will result in a Status Reg-
ister error. The protection of the Protection
Register and/or the Security Block is not revers-
ible.
During a Program/Erase Suspend, the device can
be placed in standby mode by taking Chip Enable
to V . Program/Erase is aborted if Reset turns to
IH
V .
IL
See Appendix C, Figure 31, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
33, Erase Suspend & Resume Flowchart and
Pseudo Code for flowcharts for using the Program/
Erase Suspend command.
Program/Erase Resume Command
The Protection Register Program cannot be sus-
pended. See Appendix C, Figure 35, Protection
Register Program Flowchart and Pseudo Code,
for a flowchart for using the Protection Register
Program command.
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend command has paused
it. One Bus Write cycle is required to issue the
command. The command can be written to any
address.
The Program/Erase Resume command does not
change the read mode of the banks. If the sus-
pended bank was in Read Status Register, Read
Electronic signature or Read CFI Query mode the
bank remains in that mode and outputs the corre-
sponding data. If the bank was in Read Array
mode subsequent read operations will output in-
valid data.
If a Program command is issued during a Block
Erase Suspend, then the erase cannot be re-
sumed until the programming operation has com-
pleted. It is possible to accumulate suspend
operations. For example: suspend an erase oper-
ation, start a programming operation, suspend the
programming operation then read the array. See
Appendix C, Figure 31, Program Suspend & Re-
sume Flowchart and Pseudo Code, and Figure 33,
Erase Suspend & Resume Flowchart and Pseudo
Code for flowcharts for using the Program/Erase
Resume command.
Set Configuration Register Command.
The Set Configuration Register command is used
to write a new value to the Burst Configuration
Control Register which defines the burst length,
type, X latency, Synchronous/Asynchronous Read
mode and the valid Clock edge configuration.
Two Bus Write cycles are required to issue the Set
Configuration Register command.
■ The first cycle writes the setup command and
the address corresponding to the Configuration
Register content.
■ The second cycle writes the Configuration
Register data and the confirm command.
Once the command is issued the memory returns
to Read mode.
The value for the Configuration Register is always
presented on A0-A15. CR0 is on A0, CR1 on A1,
etc.; the other address bits are ignored.
Block Lock Command
The Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
Protection Register Program Command
The Protection Register Program command is
used to Program the 128 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister and the Protection Register Lock. The
segment is programmed 16 bits at a time. When
shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.
Two write cycles are required to issue the Protec-
tion Register Program command.
■ The first bus cycle sets up the Protection
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 13 shows the Lock Status after issuing a
Block Lock command.
Register Program command.
19/92
M36WT864TF, M36WT864BF
The Block Lock bits are volatile, once set they re-
main set until a hardware reset or power-down/
power-up. They are cleared by a Block Unlock
command. Refer to the section, Block Locking, for
a detailed explanation. See Appendix C, Figure
34, Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock command.
Block Lock-Down Command
A locked or unlocked block can be locked-down by
issuing the Block Lock-Down command. A locked-
down block cannot be programmed or erased, or
have its protection status changed when WP is
low, V . When WP is high, V the Lock-Down
IL
IH,
function is disabled and the locked blocks can be
individually unlocked by the Block Unlock com-
mand.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
Block Unlock Command
The Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are required to is-
sue the Block Unlock command.
■ The first bus cycle sets up the Block Lock
■ The first bus cycle sets up the Block Unlock
command.
command.
■ The second Bus Write cycle latches the block
■ The second Bus Write cycle latches the block
address.
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table. 13 shows the Lock Status af-
ter issuing a Block Lock-Down command. Refer to
the section, Block Locking, for a detailed explana-
tion and Appendix C, Figure 34, Locking Opera-
tions Flowchart and Pseudo Code, for a flowchart
for using the Lock-Down command.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 13 shows the protection status after issuing
a Block Unlock command. Refer to the section,
Block Locking, for a detailed explanation and Ap-
pendix C, Figure 34, Locking Operations Flow-
chart and Pseudo Code, for a flowchart for using
the Unlock command.
20/92
M36WT864TF, M36WT864BF
Table 5. Flash Standard Commands
Commands
Bus Operations
1st Cycle
Add
2nd Cycle
Add
Op.
Write
Write
Write
Write
Data
FFh
70h
90h
98h
Op.
Data
RD
Read Array
1+
1+
1+
1+
BKA
WA
Read
Read
(2)
Read Status Register
Read Electronic Signature
Read CFI Query
BKA
BKA
BKA
SRD
ESD
QD
BKA
(2)
Read
Read
BKA
(2)
BKA
Clear Status Register
Block Erase
1
2
2
2
1
1
2
2
2
2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
BKA
BKA
BKA
BKA
X
50h
20h
Write
Write
Write
BA
BKA
WA
D0h
D0h
PD
Bank Erase
80h
Program
40h or 10h
B0h
Program/Erase Suspend
Program/Erase Resume
Protection Register Program
Set Configuration Register
Block Lock
X
D0h
PRA
CRD
BKA
BKA
BKA
C0h
Write
Write
Write
Write
Write
PRD
03h
01h
D0h
2Fh
PRA
CRD
BA
60h
60h
Block Unlock
60h
BA
Block Lock-Down
60h
BA
Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,
QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection
Register Data, CRD=Configuration Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.
21/92
M36WT864TF, M36WT864BF
Table 6. Electronic Signature Codes
Code
Address (h)
Data (h)
0020
Manufacturer Code
Bank Address + 00
Bank Address + 01
Bank Address + 01
Top
Device Code
8810
Bottom
8811
Lock
0001
Unlocked
0000
Block Protection
Block Address + 02
Locked and Locked-Down
0003
Unlocked and Locked-Down
0002
Reserved
Bank Address + 03
Bank Address + 05
Reserved
CR
Configuration Register
ST Factory Default
0006
Security Block Permanently Locked
OTP Area Permanently Locked
0002
Protection Register Lock
Bank Address + 80
0004
Security Block and OTP Area Permanently
Locked
0000
Bank Address + 81 Unique Device
Bank Address + 84
Number
Protection Register
Bank Address + 85
Bank Address + 8C
OTP Area
Note: CR=Configuration Register.
Figure 6. Flash Security Block and Protection Register Memory Map
PROTECTION REGISTER
8Ch
SECURITY BLOCK
Parameter Block # 0
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
2
1
0
AI06181
22/92
M36WT864TF, M36WT864BF
COMMAND INTERFACE - FACTORY PROGRAM COMMANDS
The Factory Program commands are used to
speed up programming. They require V to be at
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
PPF
V
. Refer to Table 7, Factory Program Com-
PPH
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
mands, in conjunction with the following text de-
scriptions.
Double Word Program Command
the Data of the first word to be written.
The Double Word Program command improves
the programming throughput by writing a page of
two adjacent words in parallel. The two words
must differ only for the address A0.
■ The third bus cycle latches the Address and the
Data of the second word to be written.
■ The fourth bus cycle latches the Address and
the Data of the third word to be written.
Programming should not be attempted when V
PPF
■ The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the pro-
gramming has started.
is not at V
. The command can be executed if
PPH
V
is below V
but the result is not guaran-
PPF
PPH
teed.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
Programming aborts if Reset goes to V . As data
IL
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Read operations in the bank being programmed
output the Status Register content after the pro-
gramming has started.
During Double Word Program operations the bank
being programmed will only accept the Read Ar-
ray, Read Status Register, Read Electronic Signa-
ture and Read CFI Query command, all other
commands will be ignored. Dual operations are
not supported during Double Word Program oper-
ations and it is not recommended to suspend a
Double Word Program operation. Typical Program
times are given in Table 14, Program, Erase
Times and Program/Erase Endurance Cycles.
During Quadruple Word Program operations the
bank being programmed will only accept the Read
Array, Read Status Register, Read Electronic Sig-
nature and Read CFI Query command, all other
commands will be ignored.
Dual operations are not supported during Quadru-
ple Word Program operations and it is not recom-
mended to suspend a Quadruple Word Program
operation. Typical Program times are given in Ta-
ble 14, Program, Erase Times and Program/Erase
Endurance Cycles.
See Appendix C, Figure 30, Quadruple Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Quadruple Word Program
command.
Enhanced Factory Program Command
Programming aborts if Reset goes to V . As data
IL
The Enhanced Factory Program command can be
used to program large streams of data within any
one block. It greatly reduces the total program-
ming time when a large number of Words are writ-
ten to a block at any one time.
The use of the Enhanced Factory Program com-
mand requires certain operating conditions.
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
See Appendix C, Figure 29, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
■ V
■ V
must be set to V
PPH
PPF
Quadruple Word Program Command
must be within operating range
DD
The Quadruple Word Program command im-
proves the programming throughput by writing a
page of four adjacent words in parallel. The four
words must differ only for the addresses A0 and
A1.
■ Ambient temperature, T must be 25°C ± 5°C
A
■ The targeted block must be unlocked
Dual operations are not supported during the En-
hanced Factory Program operation and the com-
mand cannot be suspended.
For optimum performance the Enhanced Factory
Program commands should be limited to a maxi-
mum of 10 program/erase cycles per block. If this
Programming should not be attempted when V
PPF
is not at V
. The command can be executed if
PPH
V
is below V
but the result is not guaran-
PPF
PPH
teed.
23/92
M36WT864TF, M36WT864BF
limit is exceeded the internal algorithm will contin-
ue to work properly but some degradation in per-
formance is possible. Typical Program times are
given in Table 14.
The Enhanced Factory Program command has
four phases: the Setup Phase, the Program Phase
to program the data to the memory, the Verify
Phase to check that the data has been correctly
programmed and reprogram if necessary and the
Exit Phase. Refer to Table 7, Enhanced Factory
Program Command and Figure 36, Enhanced
Factory Program Flowchart.
Setup Phase. The Enhanced Factory Program
command requires two Bus Write operations to ini-
tiate the command.
■ The first bus cycle sets up the Enhanced
Factory Program command.
■ The second bus cycle confirms the command.
The Status Register P/E.C. Bit 7 should be read to
check that the P/E.C. is ready. After the confirm
command is issued, read operations output the
Status Register data. The read Status Register
command must not be issued as it will be
interpreted as data to program.
Program Phase. The Program Phase requires
n+1 cycles, where n is the number of Words (refer
to Table 7, Enhanced Factory Program Command
and Figure 36, Enhanced Factory Program Flow-
chart).
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data. The Program/Erase Controller
checks the stream of data with the data that was
programmed in the Program Phase and repro-
grams the memory location if necessary.
Three successive steps are required to execute
the Verify Phase of the command.
1. Use one Bus Write operation to latch the Start
Address and the first Word, to be verified. The
Status Register bit SR0 should be read to check
that the Program/Erase Controller is ready for
the next Word.
2. Each subsequent Word to be verified is latched
with a new Bus Write operation. The Words
must be written in the same order as in the
Program Phase. The address can remain the
Start Address or be incremented. If any address
that is not in the same block as the Start
Address is given, the Verify Phase terminates.
Status Register bit SR0 should be read to check
that the P/E.C. is ready for the next Word.
3. Finally, after all Words have been verified, write
one Bus Write operation with data FFFFh to any
address outside the block containing the Start
Address, to terminate the Verify Phase.
If the Verify Phase is successfully completed the
memory returns to the Read mode. If the Program/
Erase Controller fails to reprogram a given loca-
tion, the error will be signaled in the Status Regis-
ter.
Three successive steps are required to issue and
execute the Program Phase of the command.
1. Use one Bus Write operation to latch the Start
Address and the first Word to be programmed.
The Status Register Bank Write Status bit SR0
should be read to check that the P/E.C. is ready
for the next Word.
Exit Phase. Status Register P/E.C. bit SR7 set to
‘1’ indicates that the device has returned to Read
mode. A full Status Register check should be done
to ensure that the block has been successfully pro-
grammed. See the section on the Status Register
for more details.
Quadruple Enhanced Factory Program
Command
The Quadruple Enhanced Factory Program com-
mand can be used to program one or more pages
of four adjacent words in parallel. The four words
2. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address can either remain the Start Address, in
which case the P/E.C. increments the address
location or the address can be incremented in
which case the P/E.C. jumps to the new
address. If any address that is not in the same
block as the Start Address is given with data
FFFFh, the Program Phase terminates and the
Verify Phase begins. The Status Register bit
SR0 should be read between each Bus Write
cycle to check that the P/E.C. is ready for the
next Word.
3. Finally, after all Words have been programmed,
write one Bus Write operation with data FFFFh
to any address outside the block containing the
Start Address, to terminate the programming
phase. If the data is not FFFFh, the command is
ignored.
must differ only for the addresses A0 and A1. V
PPF
must be set to V
during Quadruple Enhanced
PPH
Factory Program.
It has four phases: the Setup Phase, the Load
Phase where the data is loaded into the buffer, the
combined Program and Verify Phase where the
loaded data is programmed to the memory and
then automatically checked and reprogrammed if
necessary and the Exit Phase. Unlike the En-
hanced Factory Program it is not necessary to re-
submit the data for the Verify Phase. The Load
Phase and the Program and Verify Phase can be
repeated to program any number of pages within
the block.
The memory is now set to enter the Verify Phase.
24/92
M36WT864TF, M36WT864BF
Setup Phase. The Quadruple Enhanced Factory
Program command requires one Bus Write opera-
tion to initiate the load phase. After the setup
command is issued, read operations output the
Status Register data. The Read Status Register
command must not be issued as it will be
interpreted as data to program.
Load Phase. The Load Phase requires 4 cycles
to load the data (refer to Table 7, Factory Program
Commands and Figure 37, Quadruple Enhanced
Factory Program Flowchart). Once the first Word
of each Page is written it is impossible to exit the
Load phase until all four Words have been written.
cycle to check that the P/E.C. is ready for the
next Word.
The memory is now set to enter the Program and
Verify Phase.
Program and Verify Phase. In the Program and
Verify Phase the four Words that were loaded in
the Load Phase are programmed in the memory
array and then verified by the Program/Erase Con-
troller. If any errors are found the Program/Erase
Controller reprograms the location. During this
phase the Status Register shows that the Pro-
gram/Erase Controller is busy, Status Register bit
SR7 set to ‘0’, and that the device is not waiting for
new data, Status Register bit SR0 set to ‘1’. When
Status Register bit SR0 is set to ‘0’ the Program
and Verify phase has terminated.
Two successive steps are required to issue and
execute the Load Phase of the Quadruple En-
hanced Factory Program command.
1. Use one Bus Write operation to latch the Start
Address and the first Word of the first Page to
be programmed. For subsequent Pages the first
Word address can remain the Start Address (in
which case the next Page is programmed) or
can be any address in the same block. If any
address is given that is not in the same block as
the Start Address, the device enters the Exit
Phase. For the first Load Phase Status Register
bit SR7 should be read after the first Word has
been issued to check that the command has
been accepted (bit 7 set to ‘0’). This check is not
required for subsequent Load Phases. Status
Register bit SR0 should be read to check that
the P/E.C. is ready for the next Word.
2. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address is only checked for the first Word of
each Page as the order of the Words to be
programmed is fixed. The Status Register bit
SR0 should be read between each Bus Write
Once the Verify Phase has successfully complet-
ed subsequent pages in the same block can be
loaded and programmed. The device returns to
the beginning of the Load Phase by issuing one
Bus Write operation to latch the Address and the
first of the four new Words to be programmed.
Exit Phase. Finally, after all the pages have been
programmed, write one Bus Write operation with
data FFFFh to any address outside the block con-
taining the Start Address, to terminate the Load
and Program and Verify Phases.
If the Program and Verify Phase has successfully
completed the memory returns to Read mode. If
the P/E.C. fails to program and reprogram a given
location, the error will be signaled in the Status
Register.
Status Register bit SR7 set to ‘1’ and bit 0 set to ‘0’
indicate that the device has returned to Read
mode. A full Status Register check should be done
to ensure that the block has been successfully pro-
grammed. See the section on the Status Register
for more details.
25/92
M36WT864TF, M36WT864BF
Table 7. Flash Factory Program Commands
Bus Write Operations
3rd
Command
Phase
1st
2nd
Add
Final -1
Final
Add
Data
Data Add
Data
Add
Data
Add
Data
(4)
3
5
2
BKA
35h
WA1 PD1 WA2
WA1 PD1 WA2
PD2
Double Word Program
Quadruple Word
BKA
56h
30h
PD2
PD1
WA3
PD3
PAn
WA4
NOT
PD4
(5)
Program
Setup,
Enhanced
Factory
(2)
(3)
+n BKA
+1
BA
D0h
FFFFh
WA1
WAn
(2)
Program
WA1
Program
(6)
NOT
n
+1
(2)
(3)
(3)
(7)
(3)
Verify, Exit
PD1
75h
PD2
PD1
PD3
PD2
PAn
PD3
FFFFh
PD4
WA1
WA2
WA3
WAn
WA3
(2)
WA1
Setup,
(2)
(7)
(7)
5
BKA
WA1
WA2
WA4
first Load
First
Program &
Verify
Automatic
Quadruple
Enhanced
Factory
Program
(5,6)
Subsequent
Loads
WA1i
WA2i
(7)
WA3i
(7)
WA4i
(7)
4
1
PD1i
PD2i
PD3i
PD4i
(2)
Subsequent
Program &
Verify
Automatic
NOT
WA1
(2)
Exit
FFFFh
Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address.
2. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1.
3. Address can remain Starting Address WA1 or be incremented.
4. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
5. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
6. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and
check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed.
7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent
Words in each Page can be written to any address.
26/92
M36WT864TF, M36WT864BF
FLASH STATUS REGISTER
The Flash memory contains a Status Register
which provides information on the current or previ-
ous Program or Erase operations. Issue a Read
Status Register command to read the contents of
the Status Register, refer to Read Status Register
Command section for more details. To output the
contents, the Status Register is latched and updat-
ed on the falling edge of the Chip Enable or Output
Enable signals and can be read until Chip Enable
tion has been suspended or is going to be sus-
pended in the addressed block. When the Erase
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
SR7 is set within the Erase Suspend Latency time
of the Program/Erase Suspend command being
issued therefore the memory may still complete
the operation rather than entering the Suspend
mode.
or Output Enable returns to V . The Status Reg-
IH
ister can only be read using single asynchronous
or single synchronous reads. Bus Read opera-
tions from any address within the bank, always
read the Status Register during Program and
Erase operations.
The various bits convey information about the sta-
tus and any errors of the operation. Bits SR7, SR6,
SR2 and SR0 give information on the status of the
device and are set and reset by the device. Bits
SR5, SR4, SR3 and SR1 give information on er-
rors, they are set by the device but must be reset
by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status
Register should be reset before issuing another
command. SR7 to SR1 refer to the status of the
device while SR0 refers to the status of the ad-
dressed bank.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit
can be used to identify if the memory has failed to
verify that the block or bank has erased correctly.
When the Erase Status bit is High (set to ‘1’), the
Program/Erase Controller has applied the maxi-
mum number of pulses to the block or bank and
still failed to verify that it has erased correctly. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status Bit (SR4). The Program Status
bit is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver-
ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
The bits in the Status Register are summarized in
Table 8, Status Register Bits. Refer to Table 8 in
conjunction with the following text descriptions.
Program/Erase Controller Status Bit (SR7).
The Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive in any bank. When the Program/Erase
Controller Status bit is Low (set to ‘0’), the Pro-
gram/Erase Controller is active; when the bit is
High (set to ‘1’), the Program/Erase Controller is
inactive, and the device is ready to process a new
command.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
V
Status Bit (SR3). The V
Status bit can
PPF
PPF
be used to identify an invalid voltage on the V
PPF
pin during Program and Erase operations. The
pin is only sampled at the beginning of a Pro-
V
PPF
gram or Erase operation. Indeterminate results
After the Program/Erase Controller completes its
can occur if V
ation.
becomes invalid during an oper-
PPF
operation the Erase Status, Program Status, V
PPF
Status and Block Lock Status bits should be tested
for errors.
When the V
voltage on the V
Status bit is Low (set to ‘0’), the
PPF
pin was sampled at a valid
PPF
Erase Suspend Status Bit (SR6). The
Suspend Status bit indicates that an Erase opera-
Erase
Status bit is High (set to
PPF
27/92
M36WT864TF, M36WT864BF
V
Lockout Voltage, V
, the memory is pro-
PPLK
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Bank Write/Multiple Word Program Status Bit
(SR0). The Bank Write Status bit indicates wheth-
er the addressed bank is programming or erasing.
In Enhanced Factory Program mode the Multiple
Word Program bit shows if a Word has finished
programming or verifying depending on the phase.
The Bank Write Status bit should only be consid-
ered valid when the Program/Erase Controller Sta-
tus SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit
and the Bank Write Status bit are Low (set to ‘0’),
the addressed bank is executing a Program or
Erase operation. When the Program/Erase Con-
troller Status bit is Low (set to ‘0’) and the Bank
Write Status bit is High (set to ‘1’), a Program or
Erase operation is being executed in a bank other
than the one being addressed.
In Enhanced Factory Program mode if Multiple
Word Program Status bit is Low (set to ‘0’), the de-
vice is ready for the next Word, if the Multiple Word
Program Status bit is High (set to ‘1’) the device is
not ready for the next Word.
PPF
tected and Program and Erase operations cannot
be performed.
Once set High, the V
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Status bit can only be re-
PPF
Program Suspend Status Bit (SR2). The Pro-
gram Suspend Status bit indicates that a Program
operation has been suspended in the addressed
block. When the Program Suspend Status bit is
High (set to ‘1’), a Program/Erase Suspend com-
mand has been issued and the memory is waiting
for a Program/Erase Resume command. The Pro-
gram Suspend Status should only be considered
valid when the Program/Erase Controller Status
bit is High (Program/Erase Controller inactive).
SR2 is set within the Program Suspend Latency
time of the Program/Erase Suspend command be-
ing issued therefore the memory may still com-
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status Bit (SR1). The Block
Protection Status bit can be used to identify if a
Program or Block Erase operation has tried to
modify the contents of a locked block.
Note: Refer to Appendix C, Flowcharts and Pseu-
do Codes, for using the Status Register.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
28/92
M36WT864TF, M36WT864BF
Table 8. Flash Status Register Bits
Bit
Name
Type LogicLevel
Definition
'1'
Ready
SR7 P/E.C. Status
Status
'0'
Busy
'1'
Erase Suspended
SR6 Erase Suspend Status
SR5 Erase Status
Status
'0'
Erase In progress or Completed
Erase Error
'1'
Error
'0'
Erase Success
'1'
Program Error
SR4 Program Status
Error
'0'
Program Success
V
V
Invalid, Abort
OK
'1'
PPF
V
Status
SR3
Error
'0'
PPF
PPF
'1'
Program Suspended
SR2 Program Suspend Status Status
'0'
'1'
'0'
Program In Progress or Completed
Program/Erase on protected Block, Abort
No operation to protected blocks
SR1 Block Protection Status
Error
SR7 = ‘0’ Program or erase operation in addressed bank
SR7 = ‘1’ No Program or erase operation in the device
'0'
'1'
Bank Write Status
Status
Program or erase operation in a bank other than
SR7 = ‘0’
the addressed bank
SR7 = ‘1’ Not Allowed
SR0
SR7 = ‘0’ the device is NOT ready for the next word
'1'
'0'
Multiple Word Program
Status (Enhanced
Not Allowed
SR7 = ‘1’
Status
SR7 = ‘0’ the device is ready for the next Word
SR7 = ‘1’ the device is exiting from EFP
Factory Program mode)
Note: Logic level '1' is High, '0' is Low.
29/92
M36WT864TF, M36WT864BF
FLASH CONFIGURATION REGISTER
The Flash memory contains a Configuration Reg-
ister which is used to configure the type of bus ac-
cess that the memory will perform. Refer to Read
Modes section for details on read operations.
The Configuration Register is set through the
Command Interface. After a Reset or Power-Up
the device is configured for asynchronous page
read (CR15 = 1). The Configuration Register bits
are described in Table 9. They specify the selec-
tion of the burst length, burst type, burst X latency
and the Read operation. Refer to Figures 7 and 8
for examples of synchronous burst configurations.
Refer to Figure 7, X-Latency and Data Output
Configuration Example.
Wait Polarity Bit (CR10)
In synchronous burst mode the Wait signal indi-
cates whether the output data are valid or a WAIT
state must be inserted. The Wait Polarity bit is
used to set the polarity of the Wait signal. When
the Wait Polarity bit is set to ‘0’ the Wait signal is
active Low. When the Wait Polarity bit is set to ‘1’
the Wait signal is active High (default).
Data Output Configuration Bit (CR9)
The Data Output Configuration bit determines
whether the output remains valid for one or two
clock cycles. When the Data Output Configuration
Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the
output data is valid for two clock cycles.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch be-
tween asynchronous and synchronous Bus Read
operations. When the Read Select bit is set to ’1’,
read operations are asynchronous; when the
Read Select bit is set to ’0’, read operations are
synchronous. Synchronous Burst Read is support-
ed in both parameter and main blocks and can be
performed across banks.
The Data Output Configuration depends on the
condition:
■ t > t
+ t
QVK_CPU
K
KQV
where t is the clock period, t
setup time required by the system CPU and t
is the data
K
QVK_CPU
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
KQV
is the clock to data valid time. If this condition is not
satisfied, the Data Output Configuration bit should
be set to ‘1’ (two clock cycles). Refer to Figure 7,
X-Latency and Data Output Configuration Exam-
ple.
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available. For correct operation the
X-Latency bits can only assume the values in Ta-
ble 9, Configuration Register.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied:
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the
Wait output pin, WAIT. When the Wait bit is ’0’ the
Wait output pin is asserted during the wait state.
When the Wait bit is ’1’ (default) the Wait output
pin is asserted one clock cycle before the wait
state.
WAIT is asserted during a continuous burst and
also during a 4 or 8 burst length if no-wrap config-
uration is selected. WAIT is not asserted during
asynchronous reads, single synchronous reads or
during latency in synchronous reads.
1. Depending on whether t
or t
is
DELAY
AVK_CPU
supplied either one of the following two
equations must be satisfied:
(n + 1) t ≥ t
- t
+ t
K
ACC AVK_CPU QVK_CPU
(n + 2) t ≥ t
+ t
+ t
DELAY QVK_CPU
K
ACC
2. and also
t > t
Burst Type Bit (CR7)
+ t
QVK_CPU
The Burst Type bit is used to configure the se-
quence of addresses read as sequential or inter-
leaved. When the Burst Type bit is ’0’ the memory
outputs from interleaved addresses; when the
Burst Type bit is ’1’ (default) the memory outputs
from sequential addresses. See Tables 10, Burst
Type Definition, for the sequence of addresses
output from a given starting address in each mode.
K
KQV
where
n is the chosen X-Latency configuration code
t is the clock period
K
t
is clock to address valid, L Low, or E
AVK_CPU
Low, whichever occurs last
t
is address valid, L Low, or E Low to clock,
DELAY
Valid Clock Edge Bit (CR6)
whichever occurs last
The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during Syn-
chronous Burst Read operations. When the Valid
Clock Edge bit is ’0’ the falling edge of the Clock is
t
is the data setup time required by the
QVK_CPU
system CPU,
t
t
is the clock to data valid time
is the random access time of the device.
KQV
ACC
30/92
M36WT864TF, M36WT864BF
the active edge; when the Valid Clock Edge bit is
’1’ the rising edge of the Clock is active.
In continuous burst mode the burst sequence can
cross bank boundaries.
Wrap Burst Bit (CR3)
In continuous burst mode or in 4, 8 words no-wrap,
depending on the starting address, the device as-
serts the WAIT output to indicate that a delay is
necessary before the data is output.
If the starting address is aligned to a 4 word
boundary no wait states are needed and the WAIT
output is not asserted.
The burst reads can be confined inside the 4 or 8
Word boundary (wrap) or overcome the boundary
(no wrap). The Wrap Burst bit is used to select be-
tween wrap and no wrap. When the Wrap Burst bit
is set to ‘0’ the burst read wraps; when it is set to
‘1’ the burst read does not wrap.
Burst length Bits (CR2-CR0)
If the starting address is shifted by 1,2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 64 word boundary, to
indicate that the device needs an internal delay to
read the successive words in the array. WAIT will
be asserted only once during a continuous burst
access. See also Table 10, Burst Type Definition.
The Burst Length bits set the number of Words to
be output during a Synchronous Burst Read oper-
ation as result of a single address latch cycle.
They can be set for 4 words, 8 words or continu-
ous burst, where all the words are read sequential-
ly.
CR14, CR5 and CR4 are reserved for future use.
31/92
M36WT864TF, M36WT864BF
Table 9. Flash Configuration Register
Bit
Description
Value
Description
0
1
Synchronous Read
CR15
CR14
Read Select
Asynchronous Read (Default at power-on)
Reserved
010
011
100
101
111
2 clock latency
3 clock latency
4 clock latency
CR13-CR11
X-Latency
5 clock latency
Reserved
Other configurations reserved
0
1
0
1
0
1
0
1
0
1
WAIT is active Low
WAIT is active high (default)
Data held for one clock cycle
Data held for two clock cycles
WAIT is active during wait state
WAIT is active one data cycle before wait state (default)
Interleaved
CR10
CR9
CR8
CR7
Wait Polarity
Data Output
Configuration
Wait Configuration
Burst Type
Sequential (default)
Falling Clock edge
CR6
CR5-CR4
CR3
Valid Clock Edge
Rising Clock edge
Reserved
0
Wrap
Wrap Burst
1
No Wrap
001
010
111
4 words
CR2-CR0
Burst Length
8 words
Continuous (CR7 must be set to ‘1’)
32/92
M36WT864TF, M36WT864BF
Table 10. Burst Type Definition
Start
Address
4 Words
8 Words
Sequential
Continuous Burst
Sequential
Interleaved
0-1-2-3
Interleaved
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
0-1-2-3-4-5-6...
1-2-3-4-5-6-7...
2-3-4-5-6-7-8...
3-4-5-6-7-8-9...
1-0-3-2
2
2-3-0-1
3
3-2-1-0
...
7
7-4-5-6
7-6-5-4
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
7-8-9-10-11-12-13...
...
60
61
62
60-61-62-63-64-65-66...
61-62-63-WAIT-64-65-66...
62-63-WAIT-WAIT-64-65-66...
63-WAIT-WAIT-WAIT-64-65-
66...
63
Sequential
0-1-2-3
Interleaved
Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9...
3-4-5-6-7-8-9-10
Interleaved
0
1
1-2-3-4
2
2-3-4-5
3
3-4-5-6
...
7
7-8-9-10
7-8-9-10-11-12-13-14
Same as for Wrap
(Wrap /No Wrap
has no effect on
Continuous Burst )
...
60-61-62-63-64-65-66-
67
60
61
62
63
60-61-62-63
61-62-63-WAIT-64-65-
66-67-68
61-62-63-WAIT-64
62-63-WAIT-
WAIT-64-65
62-63-WAIT-WAIT-64-
65-66-67-68-69
63-WAIT-WAIT-
WAIT-64-65-66
63-WAIT-WAIT-WAIT-
64-65-66-67-68-69-70
33/92
M36WT864TF, M36WT864BF
Figure 7. X-Latency and Data Output Configuration Example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
A21-A0
tDELAY
VALID ADDRESS
tAVK_CPU
tQVK_CPU
tK
tQVK_CPU
tACC
tKQV
DQ15-DQ0
VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
AI06182
Figure 8. Wait Configuration Example
E
K
L
A21-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA NOT VALID VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI06972
34/92
M36WT864TF, M36WT864BF
FLASH READ MODES
Flash Read operations can be performed in two
different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t
care’ for the data output, the read operation is
Asynchronous; if the data output is synchronized
with clock, the read operation is Synchronous.
The Read mode and data output format are deter-
mined by the Configuration Register. (See Config-
uration Register section for details). All banks
supports both asynchronous and synchronous
read operations. The Multiple Bank architecture
allows read operations in one bank, while write op-
erations are being executed in another (see Ta-
bles 11 and 12).
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are con-
figured in the Configuration Register.
A burst sequence is started at the first clock edge
(rising or falling depending on Valid Clock Edge bit
CR6 in the Configuration Register) after the falling
edge of Latch Enable. Addresses are internally in-
cremented and after a delay of 2 to 5 clock cycles
(X latency bits CR13-CR11) the corresponding
data are output on each clock cycle.
The number of Words to be output during a Syn-
chronous Burst Read operation can be configured
as 4 or 8 Words or Continuous (Burst Length bits
CR2-CR0). The data can be configured to remain
valid for one or two clock cycles (Data Output Con-
figuration bit CR9).
The order of the data output can be modified
through the Burst Type and the Wrap Burst bits in
the Configuration Register. The burst sequence
may be configured to be sequential or interleaved
(CR7). The burst reads can be confined inside the
4 or 8 Word boundary (Wrap) or overcome the
boundary (No Wrap). If the starting address is
aligned to a 4 Word Page the wrapped configura-
tion has no impact on the output sequence. Inter-
leaved mode is not allowed in Continuous Burst
Read mode or with No Wrap sequences.
Asynchronous Read Mode
In Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corre-
sponding to the address latched, that is the mem-
ory array, Status Register, Common Flash
Interface or Electronic Signature depending on the
command issued. CR15 in the Configuration Reg-
ister must be set to ‘1’ for Asynchronous opera-
tions.
In Asynchronous Read mode a Page of data is in-
ternally read and stored in a Page Buffer. The
Page has a size of 4 Words and is addressed by
A0 and A1 address inputs. The address inputs A0
and A1 are not gated by Latch Enable in Asyn-
chronous Read mode.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur. This delay
will depend on the starting address of the burst se-
quence; the worst case delay will occur when the
sequence is crossing a 64 word boundary and the
starting address was at the end of a four word
boundary.
The first read operation within the Page has a
longer access time (T , Random access time),
acc
subsequent reads within the same Page have
much shorter access times. If the Page changes
then the normal, longer timings apply again.
WAIT is asserted during X latency and the Wait
state and is only deasserted when output data are
valid. In Continuous Burst Read mode a Wait state
will occur when crossing the first 64 Word bound-
ary. If the burst starting address is aligned to a 4
Word Page, the Wait state will not occur.
Asynchronous Read operations can be performed
in two different ways, Asynchronous Random Ac-
cess Read and Asynchronous Page Read. Only
Asynchronous Page Read takes full advantage of
the internal page storage so different timings are
applied.
The WAIT signal can be configured to be active
Low or active High (default) by setting CR10 in the
Configuration Register. The WAIT signal is mean-
ingful only in Synchronous Burst Read mode, in
other modes, WAIT is always asserted (except for
Read Array mode).
See Table 21, Asynchronous Read AC Character-
istics, Figure 11, Asynchronous Random Access
Read AC Waveform and Figure 12, Asynchronous
Page Read AC Waveform for details.
Synchronous Burst Read Mode
In Synchronous Burst Read mode the data is out-
put in bursts synchronized with the clock. It is pos-
sible to perform burst reads across bank
boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read opera-
tions, such as Read Status Register, Read CFI
and Read Electronic Signature, Single Synchro-
nous Read or Asynchronous Random Access
Read must be used.
See Table 22, Synchronous Read AC Character-
istics and Figure 13, Synchronous Burst Read AC
Waveform for details.
Single Synchronous Read Mode
Single Synchronous Read operations are similar
to Synchronous Burst Read operations except that
only the first data output after the X latency is valid.
Other Configuration Register parameters have no
effect on Single Synchronous Read operations.
35/92
M36WT864TF, M36WT864BF
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is al-
ways asserted.
See Table 22, Synchronous Read AC Character-
istics and Figure 14, Single Synchronous Read AC
Waveform for details.
FLASH DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the Flash mem-
ory provides flexibility for software developers by
allowing code and data to be split with 4Mbit gran-
ularity. The Dual Operations feature simplifies the
software management of the device and allows
code to be executed from one bank while another
bank is being programmed or erased.
then a Program command can be issued to anoth-
er block, so the device can have one block in
Erase Suspend mode, one programming and oth-
er banks in Read mode. Bus Read operations are
allowed in another bank between setup and con-
firm cycles of program or erase operations. The
combination of these features means that read op-
erations are possible at any moment.
Tables 11 and 12 show the dual operations possi-
ble in other banks and in the same bank. Note that
only the commonly used commands are repre-
sented in these tables. For a complete list of pos-
sible commands refer to Appendix D, Command
Interface State Tables.
The Dual operations feature means that while pro-
gramming or erasing in one bank, Read opera-
tions are possible in another bank with zero
latency (only one bank at a time is allowed to be in
Program or Erase mode). If a Read operation is re-
quired in a bank which is programming or erasing,
the Program or Erase operation can be suspend-
ed. Also if the suspended operation was Erase
Table 11. Dual Operations Allowed In Other Banks
Commands allowed in another bank
Read
Status
Register
Read Read
CFI Electronic Program
Program/ Program/
Erase Erase
Suspend Resume
Status of bank
Read
Array
Erase
Query
Signature
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
–
Yes
Yes
Yes
–
Yes
–
Programming
Yes
Yes
Erasing
Yes
Yes
–
–
–
Program Suspended
Erase Suspended
Yes
Yes
–
–
Yes
Yes
Yes
Yes
Yes
–
–
Table 12. Dual Operations Allowed In Same Bank
Commands allowed in same bank
Read
Status
Register
Read
Program/ Program/
Erase Erase
Suspend Resume
Status of bank
Read
Array
Read
CFI Query
Electronic Program
Signature
Erase
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
–
Yes
Yes
Yes
–
Yes
–
(2)
Programming
–
(2)
Erasing
–
–
–
–
(1)
Program Suspended
Erase Suspended
–
–
Yes
Yes
Yes
(1)
(1)
–
–
Yes
Yes
Note: 1. Not allowed in the Block or Word that is being erased or programmed.
2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
36/92
M36WT864TF, M36WT864BF
FLASH BLOCK LOCKING
The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.
Locked or Locked-Down using the appropriate
software commands. A locked block can be un-
locked by issuing the Unlock command.
Lock-Down State
■ Lock/Unlock - this first level allows software-
Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status can-
not be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. Locked-
Down blocks revert to the Locked state when the
device is reset or powered-down.
only control of block locking.
■ Lock-Down - this second level requires
hardware interaction before locking can be
changed.
■ V
≤ V
- the third level offers a complete
PPLK
PPF
hardware protection against program and erase
on all blocks.
The Lock-Down function is dependent on the WP
input pin. When WP=0 (V ), the blocks in the
IL
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 13, de-
fines all of the possible protection states (WP,
DQ1, DQ0), and Appendix C, Figure 34, shows a
flowchart for the locking operations.
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WP=1 (V ) the Lock-Down function is disabled
IH
(1,1,x) and Locked-Down blocks can be individual-
ly unlocked to the (1,1,0) state by issuing the soft-
ware command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains high. When WP is low , blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was high. Device reset or power-down
resets all blocks , including those in Lock-Down, to
the Locked state.
Reading a Block’s Lock Status
The lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h to the device. Subse-
quent reads at the address specified in Table 6,
will output the protection status of that block. The
lock status is represented by DQ0 and DQ1. DQ0
indicates the Block Lock/Unlock status and is set
by the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
ing Lock-Down. DQ1 indicates the Lock-Down sta-
tus and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
The following sections explain the operation of the
locking system.
Locked State
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend. Refer to Appendix , Command
Interface State Table, for detailed information on
which commands are valid during erase suspend.
The default status of all blocks on power-up or af-
ter a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
37/92
M36WT864TF, M36WT864BF
Table 13. Flash Lock Status
Current
(1)
Next Protection Status
(WP, DQ1, DQ0)
(1)
Protection Status
(WP, DQ1, DQ0)
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
Program/Erase
Current State
After
WP transition
Allowed
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
(2)
no
yes
no
1,0,1
1,1,1
1,1,1
0,0,1
1,0,0
1,1,0
1,1,0
0,0,0
1,1,1
1,1,1
1,1,1
0,1,1
0,0,1
0,1,1
0,1,1
1,0,0
1,0,1
1,1,0
1,1,1
0,0,0
yes
(2)
no
no
0,0,1
0,1,1
0,0,0
0,1,1
0,1,1
0,1,1
1,0,1
0,0,1
(3)
0,1,1
1,1,1 or 1,1,0
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = V and A0 = V .
IH
IL
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.
IH
38/92
M36WT864TF, M36WT864BF
FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of
Program/ Erase cycles per block are shown in Ta-
ble 14. In the Flash memory the maximum number
of Program/ Erase cycles depends on the voltage
supply used.
Table 14. Flash Program, Erase Times and Endurance Cycles
Typicalafter
100k W/E
Cycles
Parameter
Condition
Min
Typ
Unit
Max
(2)
0.3
1
3
2.5
s
Parameter Block (4 KWord) Erase
Main Block (32 KWord) Erase
Preprogrammed
Not Preprogrammed
Preprogrammed
Not Preprogrammed
(3)
0.8
1.1
3
4
4
s
s
s
s
Bank (4Mbit) Erase
4.5
40
ms
ms
Parameter Block (4 KWord) Program
(3)
300
Main Block (32 KWord) Program
(3)
10
5
10
100
10
µs
µs
Word Program
Program Suspend Latency
Erase Suspend Latency
5
20
µs
Main Blocks
100,000
100,000
cycles
cycles
s
Program/Erase Cycles (per Block)
Parameter Blocks
0.3
0.9
3.5
2.5
4
Parameter Block (4 KWord) Erase
Main Block (32 KWord) Erase
Bank (4Mbit) Erase
s
s
(4)
Bank (4Mbit) Program (Quad-Enhanced Factory Program)
s
t.b.a.
510
8
4Mbit Program
Quadruple Word
ms
µs
(3)
100
Word/ Double Word/ Quadruple Word Program
Parameter Block (4 KWord)
Quadruple Word
8
ms
(3)
Program
Word
32
ms
Quadruple Word
Word
64
ms
ms
(3)
Main Block (32 KWord) Program
256
Main Blocks
Parameter Blocks
1000 cycles
2500 cycles
Program/Erase Cycles (per Block)
Note: 1. T = –40 to 85°C; V = 1.65V to 2.2V; V = 1.65V to 3.3V.
DDQ
A
DD
2. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).
3. Excludes the time needed to execute the command sequence.
4. t.b.a. = to be announced
39/92
M36WT864TF, M36WT864BF
SRAM OPERATIONS
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The data is output ei-
ther by x8 (DQ0-DQ7) or x16 (DQ0-DQ15) de-
pending on which of the LBS and UBS signals are
enabled. The SRAM is in Read mode whenever
Chip Enable, E2S, and Write Enable, WS, are at
LBS are High, the data is latched on the falling
edge of UBS, or LBS , whichever occurs first.
The Write cycle is terminated on the rising edge of
E1S, WS , UBS or LBS, whichever occurs first.
If the Output is enabled (E1S=V , E2S=V ,
IL
IH
GS=V and UBS=LBS=V ), then WS will return
IL
IL
the outputs to high impedance within t
of its
WLQZ
falling edge. Care must be taken to avoid bus con-
tention in this type of operation. The Data input
must be valid for t
Write Enable, for t
before the rising edge of
before the rising edge of
DVWH
DVEH
V , and Output Enable, GS, and Chip Enable E1S
IH
E1S or for t
before the rising edge of UBS/
DVBH
are at V .
IL
LBS, whichever occurs first, and remain valid for
, t and t respectively.
Valid data will be available on the output pins after
t
WHDX EHDX
BHDX
a time of t
after the last stable address. If the
AVQV
(see Table 27, Figure 22, 23 and 24).
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 26,
Figure 19). The SRAM is in Standby mode when-
, t
, or t
) rather
GLQV
ELQV EHQV
than the address. Data out may be indeterminate
at t , t and t , but data lines will al-
ELQX GLQX
BLQX
ever either Chip Enable is deasserted, E1S at V
IH
ways be valid at t
and 20).
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
Write Enable, WS, and Chip Enable, E1S, are at
(see Table 26, Figures 19
AVQV
or E2S at V .
IL
Data Retention. The SRAM data retention per-
formances as V go down to V are described
DDS
DR
in Table 28 and Figures 25 and 26. In E1S con-
trolled data retention mode, the minimum standby
current mode is entered when E1S ≥ V
V , and Chip Enable, E2S, is at V .
IL
IH
– 0.2V
DDS
Either the Chip Enable input, E1S or the Write En-
able input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
and E2S ≤ 0.2V or E2S ≥ V
– 0.2V. In E2S
DDS
controlled data retention mode, minimum standby
current mode is entered when E2S ≤ 0.2V.
A Write operation is initiated when E1S is at V ,
IL
Output Disable. The SRAM is in the output dis-
E2S is at V and WS is at V . When UBS or LBS
IH
IL
able state when GS and WS are both at V , refer
IH
are Low, the data is latched on the falling edge of
E1S, or WS, whichever occurs first. When UBS or
to Table 2 for more details.
40/92
M36WT864TF, M36WT864BF
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 15. Absolute Maximum Ratings
Value
Symbol
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Min
–40
–40
–65
–0.5
–0.2
–0.2
–0.2
Max
85
Unit
°C
T
A
T
125
155
°C
BIAS
T
°C
STG
V
V
+0.6
Input or Output Voltage
Supply Voltage
V
IO
DDQF
V
2.45
3.3
V
DDF
V
/ V
Input/Output Supply Voltage
Program Voltage
V
DDQF
DDS
V
14
V
PPF
I
Output Short Circuit Current
100
100
mA
hours
O
t
Time for V at V
PPF PPFH
VPPFH
41/92
M36WT864TF, M36WT864BF
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 16, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
SRAM
Flash Memory
70/ 85/ 100
Parameter
70
Units
Min
–
Max
–
Min
1.65
2.7
Max
2.2
V
V
V
Supply Voltage
V
V
V
DD
Supply Voltage
2.7
3.3
3.3
DDQ
PPF
Supply Voltage (Factory environment)
11.4
12.6
V
+0
DDQ
.4
V
PPF
Supply Voltage (Application environment)
-0.4
V
Ambient Operating Temperature
– 40
85
2
– 40
85
°C
pF
ns
V
Load Capacitance (C )
30
30
L
Input Rise and Fall Times
5
0 to V
0 to V
V
Input Pulse Voltages
DDF
DDQ
V
/2
/2
Input and Output Timing Ref. Voltages
V
DDF
DDQ
Figure 9. AC Measurement I/O Waveform
Figure 10. AC Measurement Load Circuit
V
DDQF
V
DDF
V
/2
DDF
V
DDQF
V
0V
DDF
16.7kΩ
AI06110
DEVICE
UNDER
TEST
Note: V
= V
DDS
DDF
C
L
16.7kΩ
0.1µF
0.1µF
C
includes JIG capacitance
L
AI06274
Table 17. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
8
Unit
C
IN
V
= 0V
= 0V
6
8
pF
pF
IN
C
OUT
V
OUT
12
Note: Sampled only, not 100% tested.
42/92
M36WT864TF, M36WT864BF
Table 18. Flash DC Characteristics - Currents
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Typ
Max
±1
Unit
µA
I
0V ≤ V ≤ V
LI
IN
DDQ
I
LO
0V ≤ V
≤ V
OUT DDQ
±1
µA
Supply Current
Asynchronous Read (f=6MHz)
E = V , G = V
3
6
mA
IL
IH
4 Word
8 Word
6
8
13
14
10
16
18
25
mA
mA
mA
mA
mA
mA
Supply Current
Synchronous Read (f=40MHz)
I
DD1
Continuous
4 Word
6
7
Supply Current
Synchronous Read (f=54MHz)
8 Word
10
13
Continuous
Supply Current
(Reset)
I
I
I
RP = V ± 0.2V
10
10
10
50
50
50
µA
µA
µA
DD2
DD3
DD4
SS
E = V ± 0.2V
Supply Current (Standby)
DD
Supply Current (Automatic
Standby)
E = V , G = V
IL
IH
V
= V
PPH
8
10
8
15
20
15
20
mA
mA
mA
mA
PPF
Supply Current (Program)
Supply Current (Erase)
V
= V
= V
PPF
PPF
DD
(1)
I
DD5
V
PPH
V
= V
DD
10
PPF
Program/Erase in one
Bank, Asynchronous
Read in another Bank
13
26
mA
Supply Current
(Dual Operations)
(1,2)
(1)
I
DD6
Program/Erase in one
Bank, Synchronous
Read in another Bank
16
10
30
50
mA
µA
Supply Current Program/ Erase
Suspended (Standby)
E = V ± 0.2V
I
I
DD
DD7
V
V
V
= V
PPH
2
5
5
mA
µA
mA
µA
µA
µA
µA
PPF
V
V
Supply Current (Program)
Supply Current (Erase)
PPF
V
= V
= V
0.2
2
PPF
PPF
DD
(1)
PP1
5
PPH
PPF
V
= V
DD
0.2
100
0.2
0.2
5
PPF
= V
400
5
PPF
PPH
I
V
V
Supply Current (Read)
PP2
PPF
V
≤ V
≤ V
PPF
DD
DD
(1)
Supply Current (Standby)
V
PPF
5
I
PPF
PP3
Note: 1. Sampled only, not 100% tested.
2. V Dual Operation current is the sum of read and program or erase currents.
DD
43/92
M36WT864TF, M36WT864BF
Table 19. Flash DC Characteristics - Voltages
Symbol
Parameter
Input Low Voltage
Test Condition
Min
Typ
Max
Unit
V
V
IL
–0.5
0.4
V
V
V
–0.4
V
+ 0.4
DDQ
Input High Voltage
Output Low Voltage
Output High Voltage
V
IH
DDQ
V
OL
I
= 100µA
OL
0.1
V
V
I
= –100µA
–0.1
V
OH
OH
DDQ
V
V
Program Voltage-Logic
Program, Erase
Program, Erase
1
1.8
12
1.95
12.6
0.9
V
PP1
PPF
PPF
V
PPH
V
Program Voltage Factory
11.4
V
V
Program or Erase Lockout
V Lock Voltage
DD
V
PPLK
V
LKO
1
V
V
RPH
RP pin Extended High Voltage
3.3
V
Table 20. SRAM DC Characteristics
Symbol
Parameter
Test Condition
= 3.3V, f = 1/t
Min
Typ
Max
Unit
V
,
AVAV
DDS
(1,2)
Operating Supply Current
70ns
35
mA
I
DD1
I
= 0mA
OUT
V
= 3.3V, f = 1MHz,
DDS
(3)
Operating Supply Current
4
mA
µA
I
DD2
I
= 0mA
OUT
V
= 3.3V, f = 0,
DDS
I
E1 ≥ V
–0.2V or E2 ≤ 0.2V or
DDS
Standby Supply Current CMOS
1
20
SB
LB=UB ≥ V
–0.2V
DDS
I
0V ≤ V ≤ V
IN DDS
Input Leakage Current
Output Leakage Current
–1
–1
1
1
µA
µA
LI
(4)
I
LO
0V ≤ V
≤ V
DDS
OUT
V
+
DDS
0.3
V
Input High Voltage
2.2
V
IH
V
Input Low Voltage
Output High Voltage
Output Low Voltage
–0.3
2.4
0.6
0.4
V
V
V
IL
V
OH
I
= –1.0mA
= 2.1mA
OH
V
I
OL
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. E1 = V AND E2 = V LB OR/AND UB = V , V = V OR V .
IL
IH,
IL
IN
IL
IH
3. E1 ≤ 0.2V AND E2 ≥ V
–0.2V, LB OR/AND UB ≤ 0.2V, V ≤ 0.2V OR V ≥ V
–0.2V.
DDS
DDS
IN
IN
4. Output disabled.
44/92
M36WT864TF, M36WT864BF
Figure 11. Flash Asynchronous Random Access Read AC Waveforms
45/92
M36WT864TF, M36WT864BF
Figure 12. Flash Asynchronous Page Read AC Waveforms
46/92
M36WT864TF, M36WT864BF
Table 21. Flash Asynchronous Read AC Characteristics
M36WT864TF/BF
Unit
Symbol
Alt
Parameter
70
85
85
85
25
100
100
100
25
(3)
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid (Random)
Address Valid to Output Valid (Page)
Address Transition to Output Transition
Chip Enable Low to Wait Valid
Min
Max
Max
Min
Max
Max
Min
Max
Min
Max
Max
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
RC
70
70
20
(3)
(3)
t
t
ACC
AVQV
t
t
PAGE
AVQV1
(1)
t
0
0
18
85
0
0
18
100
0
t
OH
AXQX
(3)
t
ELTV
14
70
(2)
(3)
t
Chip Enable Low to Output Valid
t
t
CE
ELQV
(1)
t
LZ
Chip Enable Low to Output Transition
Chip Enable High to Wait Hi-Z
0
ELQX
(3)
t
20
0
20
0
EHTZ
20
(1)
(1)
(2)
(1)
(1)
(1)
t
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
0
t
OH
EHQX
EHQZ
GLQV
GLQX
(3)
t
20
25
0
20
25
0
t
t
t
t
HZ
20
t
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable High to Output Transition
20
OE
t
0
0
OLZ
t
0
0
OH
GHQX
(3)
t
Output Enable High to Output Hi-Z
Address Valid to Latch Enable High
Chip Enable Low to Latch Enable High
Latch Enable High to Address Transition
Latch Enable Pulse Width
Max
Min
Min
Min
Min
Max
Min
20
10
10
10
10
85
0
20
10
10
10
10
100
0
ns
ns
ns
ns
ns
ns
ns
t
DF
20
GHQZ
t
t
t
t
10
10
10
10
AVLH
AVADVH
ELADVH
t
ELLH
t
LHAX
ADVHAX
t
t
ADVLADVH
LLLH
(3)
t
t
t
Latch Enable Low to Output Valid (Random)
Latch Enable High to Output Enable Low
LLQV
ADVLQV
70
t
0
LHGL
ADVHGL
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t
3. To be characterized.
- t
after the falling edge of E without increasing t
.
ELQV
ELQV GLQV
47/92
M36WT864TF, M36WT864BF
Figure 13. Flash Synchronous Burst Read AC Waveforms
48/92
M36WT864TF, M36WT864BF
Figure 14. Flash Single Synchronous Read AC Waveforms
49/92
M36WT864TF, M36WT864BF
Figure 15. Flash Clock input AC Waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
Table 22. Flash Synchronous Read AC Characteristics
M36WT864TF/BF
Symbol
Alt
Parameter
Unit
70
85
9
100
t
t
AVCLKH
Address Valid to Clock High
Chip Enable Low to Clock High
Chip Enable Low to Wait Valid
Min
Min
Max
9
9
9
9
ns
ns
ns
AVKH
t
t
ELCLKH
9
ELKH
(3)
t
18
18
ELTV
EHEL
EHTZ
14
14
20
Chip Enable Pulse Width
(subsequent synchronous reads)
(3)
(3)
t
Min
14
14
ns
t
t
Chip Enable High to Wait Hi-Z
Clock High to Address Transition
Max
Min
20
10
20
10
ns
ns
t
10
KHAX
CLKHAX
t
t
Clock High to Output Valid
Clock High to WAIT Valid
KHQV
(3)
t
t
Max
Min
18
4
18
4
ns
ns
CLKHQV
14
KHTV
t
t
Clock High to Output Transition
Clock High to WAIT Transition
KHQX
4
CLKHQX
KHTX
t
t
ADVLCLKH
Latch Enable Low to Clock High
Clock Period (f=40MHz)
Min
Min
Min
9
9
9
ns
ns
ns
LLKH
25
25
t
t
CLK
KHKH
Clock Period (f=54MHz)
18.5
4.5
t
t
Clock High to Clock Low
Clock Low to Clock High
KHKL
Min
5
3
5
3
ns
ns
KLKH
t
f
Clock Fall or Rise Time
Max
3
t
r
Note: 1. Sampled only, not 100% tested.
2. For other timings please refer to Table 21, Asynchronous Read AC Characteristics.
3. To be characterized.
50/92
M36WT864TF, M36WT864BF
Figure 16. Flash Write AC Waveforms, Write Enable Controlled
51/92
M36WT864TF, M36WT864BF
Table 23. Flash Write AC Characteristics, Write Enable Controlled
M36WT864TF/BF
Symbol
Alt
Parameter
Unit
70
85
85
10
50
100
(3)
t
t
Address Valid to Next Address Valid
Address Valid to Latch Enable High
Address Valid to Write Enable High
Min
Min
Min
100
10
ns
ns
ns
AVAV
WC
70
t
10
AVLH
(4)
(3)
t
50
t
WC
45
45
AVWH
(3)
t
t
Data Valid to Write Enable High
Min
Min
Min
50
10
0
50
10
0
ns
ns
ns
DVWH
DS
t
Chip Enable Low to Latch Enable High
Chip Enable Low to Write Enable Low
10
ELLH
t
t
0
ELWL
CS
(3)
Chip Enable Low to Output Valid
Min
85
100
ns
t
70
ELQV
Chip Enable High to Clock Valid
Output Enable High to Write Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
Min
Min
Min
Min
Min
9
9
9
ns
ns
ns
ns
ns
t
ELKV
t
20
10
10
0
20
10
10
0
20
10
10
0
GHWL
t
LHAX
t
LLLH
(4)
Write Enable High to Address Valid
t
t
WHAV
(4)
t
t
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Latch Enable Low
Write Enable High to Write Enable Low
Write Enable High to Output Valid
Min
Min
Min
Min
Min
Min
Min
Min
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
AH
WHAX
t
WHDX
WHEH
DH
CH
t
t
0
0
(2)
(3)
25
0
25
0
t
25
WHEL
t
0
0
WHGL
t
0
0
WHLL
t
t
WPH
25
25
110
25
125
WHWL
(3)
t
WHQV
95
45
(3)
t
t
Write Enable Low to Write Enable High
Min
Min
50
0
50
0
ns
ns
WLWH
WP
t
Output (Status Register) Valid to V
Low
0
QVVPL
PPF
Output (Status Register) Valid to Write Protect
Low
t
Min
0
0
0
ns
QVWPL
t
t
V
High to Write Enable High
Min
Min
Min
Min
200
200
200
200
200
200
200
200
200
200
200
200
ns
ns
ns
ns
VPHWH
VPS
PPF
t
Write Enable High to V
Low
WHVPL
PPF
t
t
Write Enable High to Write Protect Low
Write Protect High to Write Enable High
WHWPL
WPHWH
Note: 1. Sampled only, not 100% tested.
2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a
WHEL
software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a
different bank t is 0ns.
WHEL
3. To be characterized.
4. Meaningful only if LF is always kept low.
52/92
M36WT864TF, M36WT864BF
Figure 17. Flash Write AC Waveforms, Chip Enable Controlled
53/92
M36WT864TF, M36WT864BF
Table 24. Flash Write AC Characteristics, Chip Enable Controlled
M36WT864TF/BF
Symbol
Alt
Parameter
Unit
70
85
100
(3)
t
t
Address Valid to Next Address Valid
Min
85
100
ns
AVAV
WC
70
45
(3)
t
t
Address Valid to Chip Enable High
Address Valid to Latch Enable High
Data Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
50
10
50
0
50
10
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVEH
WC
t
10
AVLH
(3)
t
t
DVEH
DS
AH
DH
45
t
t
t
Chip Enable High to Address Transition
Chip Enable High to Input Transition
Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Chip Enable Low to Clock Valid
0
EHAX
t
0
25
0
0
0
EHDX
t
t
WPH
25
0
25
0
EHEL
t
EHGL
t
t
0
0
0
EHWH
CH
t
9
9
9
ELKV
ELEH
(3)
t
t
Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
Chip Enable Low to Output Valid
50
10
85
20
10
10
50
10
100
20
10
10
WP
45
t
t
10
ELLH
(3)
ELQV
GHEL
70
t
Output Enable High to Chip Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
20
10
10
t
LHAX
t
LLLH
(2)
(3)
Write Enable High to Chip Enable Low
Write Enable High to Output Valid
Write Enable Low to Chip Enable Low
Min
Min
Min
Min
Min
Min
25
110
0
25
125
0
ns
ns
ns
ns
ns
ns
t
25
WHEL
t
95
0
WHQV
t
t
WLEL
CS
t
Chip Enable High to V
Low
PPF
200
200
0
200
200
0
200
200
0
EHVPL
t
Chip Enable High to Write Protect Low
EHWPL
t
Output (Status Register) Valid to V
Low
QVVPL
PPF
Output (Status Register) Valid to Write Protect
Low
t
Min
0
0
0
ns
QVWPL
t
t
V
High to Chip Enable High
Min
Min
200
200
200
200
200
200
ns
ns
VPHEH
VPS
PPF
t
Write Protect High to Chip Enable High
WPHEH
Note: 1. Sampled only, not 100% tested.
2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a
WHEL
software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a
different bank t is 0ns.
WHEL
3. To be characterized.
54/92
M36WT864TF, M36WT864BF
Figure 18. Flash Reset and Power-up AC Waveforms
tPHWL
tPLWL
tPLEL
tPLGL
tPLLL
WF, EF, GF, LF
tPHEL
tPHGL
tPHLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06281
Table 25. Flash Reset and Power-up AC Characteristics
Symbol
Parameter
Test Condition
During Program
70
10
20
85
10
20
100
10
Unit
µs
Reset Low to
Min
Min
t
PLWL
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
t
t
PLEL
PLGL
During Erase
20
µs
t
Other Conditions
Min
80
80
80
30
ns
ns
PLLL
Reset High to
t
t
PHWL
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
t
PHEL
PHGL
Min
30
30
t
PHLL
(1,2)
(3)
RP Pulse Width
Min
Min
50
50
50
50
50
50
ns
µs
t
PLPH
Supply Voltages High to Reset
High
t
VDHPH
Note: 1. The device Reset is possible but not guaranteed if t
2. Sampled only, not 100% tested.
< 50ns.
PLPH
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
55/92
M36WT864TF, M36WT864BF
Figure 19. SRAM Address Controlled, Read AC Waveforms
tAVAV
A0-A18
VALID
tAVQV
tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI05839
Note: E1S = Low, E2S = High, GS = Low, WS = High, UBS = Low and/or LBS = Low.
Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms
tAVAV
A0-A18
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E1S
E2S
tELQX
tGLQV
tGHQZ
GS
tGLQX
DQ0-DQ15
VALID
tBLQV
tBHQZ
UBS, LBS
tBLQX
AI06282
Note: Write Enable (WF) = High
56/92
M36WT864TF, M36WT864BF
Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms
E1S, UBS, LBS
E2S
tPU
tPD
I
DD
50%
I
SB
AI06283
Table 26. SRAM Read and Standby AC Characteristics
M36WT864TF/BF
Symbol
Parameter
Unit
70
70
70
t
Read Cycle Time
Min
Max
Min
ns
ns
ns
AVAV
t
Address Valid to Output Valid
AVQV
(1)
Data hold from address change
5
25
70
5
t
AXQX
(2,3,4)
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Max
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
BHQZ
t
BLQV
(1)
t
BLQX
(2,3,4)
Max
Max
Min
25
70
5
EHQZ
t
Chip Enable Low to Output Valid
ELQV
(1)
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
t
ELQX
(2,3,4)
Max
Max
Min
25
35
5
GHQZ
t
Output Enable Low to Output Valid
GLQV
(1)
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
t
GLQX
(4)
Max
Min
0
t
t
PD
PU
(4)
70
Note: 1. Test conditions assume transition timing reference level = 0.3V
or 0.7V
.
DDS
DDS
2. At any given temperature and voltage condition, t
any given device.
is less than t
, t
is less than t
and t
is less than t
for
GHQZ
GLQX BHQZ
BLQX
EHQZ
ELQX
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters.
57/92
M36WT864TF, M36WT864BF
Figure 22. SRAM Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A18
VALID
tAVWH
tAVEL
tELWH
tWLWH
tWHAX
E1S
E2S
tAVWL
WS
tWLQZ
tWHQX
tWHDX
DQ0-DQ15
UBS, LBS
DATA INPUT
tDVWH
tBLBH
AI06284
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
58/92
M36WT864TF, M36WT864BF
Figure 23. SRAM Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A18
VALID
tAVEH
tELEH
tAVEL
tEHAX
E1S
E2S
tAVWL
tWLEH
WS
tEHDX
DQ0-DQ15
DATA INPUT
tDVEH
tBLBH
UBS, LBS
AI06285
Figure 24. SRAM Write AC Waveforms, UB/LB Controlled
tAVAV
A0-A18
VALID
tAVBH
tBHAX
E1S
E2S
tAVWL
tWLBH
WS
tWLQZ
tBHDX
DQ0-DQ15
DATA (1)
DATA INPUT
tDVBH
tAVBL
tBLBH
UBS, LBS
AI06286
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
59/92
M36WT864TF, M36WT864BF
Table 27. SRAM Write AC Characteristics
M36WT864TF/BF
Symbol
Parameter
Unit
70
70
60
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to LBS, UBS High
Address Valid to LBS, UBS Low
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
LBS, UBS High to Address Transition
LBS, UBS High to Input Transition
LBS, UBS Low to LBS, UBS High
LBS, UBS Low to Chip Enable High
LBS, UBS Low to Write Enable High
Input Valid to LBS, UBS High
AVBH
t
AVBL
t
60
0
AVEH
t
AVEL
t
60
0
AVWH
t
AVWL
t
0
BHAX
t
0
BHDX
t
60
60
60
30
30
30
0
BLBH
t
BLEH
t
BLWH
t
DVBH
t
Input Valid to Chip Enable High
DVEH
t
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to LBS, UBS High
Chip Enable Low to Chip Enable High
Chip Enable Low to Write Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to LBS, UBS High
Write Enable Low to Chip Enable High
Write Enable Low to Output Hi-Z
Write Enable Low to Write Enable High
DVWH
t
EHAX
t
0
EHDX
t
60
60
60
0
ELBH
t
ELEH
t
ELWH
t
WHAX
t
0
WHDX
(1)
5
t
WHQX
t
60
60
20
50
WLBH
t
WLEH
(1,2,3)
t
WLQZ
t
Min
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQZ
WHQX
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
3. Tested initially and after any design or process changes that may affect these parameters.
60/92
M36WT864TF, M36WT864BF
Figure 25. SRAM Low V Data Retention AC Waveforms, E1S Controlled
DD
DATA RETENTION MODE
3.3V
2.7V
V
DDS
V
> 1.5V
DR
tCDR
E1S ≥ V
tR
– 0.2V or UBS = LBS ≥ V
– 0.2V
DR
DR
E1S or UBS/LBS
AI06287
Figure 26. SRAM Low V Data Retention AC Waveforms, E2S Controlled
DD
DATA RETENTION MODE
3.3V
V
2.7V
DDS
V
> 1.5V
DR
tCDR
tR
E2S ≥ 0.2V
E2S
AI06288
Table 28. SRAM Low V Data Retention Characteristics
DD
Symbol
Parameter
Test Condition
Min
Typ
Max
10
Unit
V
DD
= 1.5V, E1S ≥ V
–0.2V or
DDS
(1)
Supply Current (Data Retention)
E2S ≤ 0.2V or
5
µA
I
DDDR
UBS = LBS ≥ V
–0.2V, f = 0
DDS
Chip Deselected to Data
Retention Time
(1,2)
0
ns
ns
V
t
CDR
(2)
t
Operation Recovery Time
t
R
AVAV
E1S ≥ V
UBS = LBS ≥ V
–0.2V or E2S ≤ 0.2V or
DDS
(1)
Supply Voltage (Data Retention)
1.5
V
DR
–0.2V, f = 0
DDS
Note: 1. All other Inputs at V ≥ V
–0.2V or V ≤ 0.2V.
IL
IH
DDS
2. Tested initially and after any design or process that may affect these parameters. t
AVAV
is Read cycle time.
3. No input may exceed V
+0.2V.
DDS
61/92
M36WT864TF, M36WT864BF
PACKAGE MECHANICAL
Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline
D
D1
SE
E
E2 E1
b
e
BALL "A1"
ddd
FE1 FE
FD
A
SD
A2
A1
BGA-Z31
Note: Drawing is not to scale.
Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.400
0.0551
0.300
0.0118
0.960
0.400
8.000
5.600
0.0378
0.0157
0.3150
0.2205
0.350
7.900
–
0.450
0.0138
0.3110
–
0.0177
D
8.100
0.3189
D1
ddd
E
–
–
0.100
0.0039
14.000
7.200
10.400
0.800
1.200
3.400
1.800
0.400
0.400
13.900
14.100
0.5512
0.2835
0.4094
0.0315
0.0472
0.1339
0.0709
0.0157
0.0157
0.5472
0.5551
E1
E2
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
FE1
SD
SE
62/92
M36WT864TF, M36WT864BF
PART NUMBERING
Table 30. Ordering Information Scheme
Example:
M36WT864TF
70 ZA
6
T
Device Type
M36 = MMP (Flash + SRAM)
Architecture
W = Multiple Bank, Burst mode
Operating Voltage
T = V
= 1.65V to 2.2V; V
= V
= 2.7V to 3.3V
DDF
DDS
DDQF
SRAM Chip Size & Organization
8 = 8 Mbit (512K x16-bit)
Device Function
64T = 64 Mbit (x16), Multiple Bank, Top Boot
64B = 64 Mbit (x16), Multiple Bank, Bottom Boot
B = SRAM Asynchronous 70ns
Speed
70 = 70ns
85 = 85ns
10 = 100ns
Package
ZA = LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch
Temperature Range
6 = –40 to 85°C
Option
T = Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-
tions (Speed, Package, etc...) or for further information on any aspect of this device, please contact the
STMicroelectronics Sales Office nearest to you.
63/92
M36WT864TF, M36WT864BF
REVISION HISTORY
Table 31. Document Revision History
Date
Version
Revision Details
10-Jul-2002
1.0
First Issue
64/92
M36WT864TF, M36WT864BF
APPENDIX A. FLASH BLOCK ADDRESS TABLES
Table 32. Flash Top Boot Block Addresses
Size
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
Bank
#
Address Range
(KWord)
0
4
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
65/92
M36WT864TF, M36WT864BF
79
80
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
Note: There are two Bank Regions, Region 1 contains all the banks
that are made up of main blocks only, Region 2 contains the
banks that are made up of the parameter and main blocks.
66/92
M36WT864TF, M36WT864BF
Table 33. Flash Bottom Boot Block Addresses
Size
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
Bank
#
Address Range
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
98
97
96
95
67/92
M36WT864TF, M36WT864BF
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
Note: There are two Bank Regions, Region 1 contains all the banks
that are made up of main blocks only, Region 2 contains the
banks that are made up of the parameter and main blocks.
68/92
M36WT864TF, M36WT864BF
APPENDIX B. FLASH COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
36, 37, 38, 40 and 1 show the addresses used to
retrieve the data. The Query data is always pre-
sented on the lowest order data outputs (DQ0-
DQ7), the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 1, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
Array command to return to Read mode.
When the Read CFI Query Command is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 34, 35,
Table 34. Query Structure Overview
Offset
00h
Sub-section Name
Description
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Reserved
10h
CFI Query Identification String
System Interface Information
Device Geometry Definition
1Bh
27h
Additional information specific to the Primary
Algorithm (optional)
P
A
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Lock Protection Register
Unique device Number and
User Programmable OTP
80h
Security Code Area
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 35, 36, 37, 38, 40 and 1. Query data is always presented on the lowest order data outputs.
Table 35. CFI Query Identification String
Offset
Sub-section Name
Description
Value
00h
0020h
Manufacturer Code
Device Code
ST
8810h
8811h
Top
Bottom
01h
02h
03h
reserved
reserved
reserved
0051h
Reserved
Reserved
Reserved
04h-0Fh
10h
"Q"
"R"
"Y"
11h
0052h
Query Unique ASCII String "QRY"
12h
0059h
13h
0003h
Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
14h
0000h
15h
offset = P = 0039h
0000h
Address for Primary Algorithm extended Query table (see Table 37)
p = 39h
NA
16h
17h
0000h
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported
18h
0000h
19h
value = A = 0000h
0000h
Address for Alternate Algorithm extended Query table
NA
1Ah
69/92
M36WT864TF, M36WT864BF
Table 36. CFI Query System Interface Information
Offset
Data
Description
Value
V
V
V
V
Logic Supply Minimum Program/Erase or Write voltage
DD
1Bh
0017h
1.7V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 millivolts
Logic Supply Maximum Program/Erase or Write voltage
DD
1Ch
1Dh
1Eh
0022h
0017h
00C0h
2.2V
1.7V
12V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 millivolts
[Programming] Supply Minimum Program/Erase voltage
PPF
PPF
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 millivolts
[Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 millivolts
n
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0003h
000Ah
0000h
0003h
0004h
0002h
0000h
16µs
8µs
Typical time-out per single byte/word program = 2 µs
n
Typical time-out for quadruple word program = 2 µs
n
1s
Typical time-out per individual block erase = 2 ms
n
NA
Typical time-out for full chip erase = 2 ms
n
128µs
128µs
4s
Maximum time-out for word program = 2 times typical
n
Maximum time-out for quadruple word = 2 times typical
n
Maximum time-out per individual block erase = 2 times typical
n
NA
Maximum time-out for chip erase = 2 times typical
Table 37. Device Geometry Definition
Offset Word
Data
Description
Value
Mode
n
27h
0017h
8 MByte
Device Size = 2 in number of bytes
28h
29h
0001h
0000h
x16
Async.
Flash Device Interface Code description
2Ah
2Bh
0003h
0000h
n
8 Byte
2
Maximum number of bytes in multi-byte program or page = 2
2Ch
0002h
Number of identical sized erase block regions within the device
bit 7 to 0 = x = number of Erase Block Regions
2Dh
2Eh
007Eh
0000h
Region 1 Information
Number of identical-size erase blocks = 007Eh+1
127
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
64 KByte
8
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase blocks = 0007h+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 KByte
NA
35h
38h
0000h
Reserved for future erase block region information
70/92
M36WT864TF
M36WT864BF
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory
and 8 Mbit (512K x16) SRAM, Multiple Memory Product
PRODUCT PREVIEW
July 2002
1/92
This is preliminary information on a new product now in development. Details are subject to change without notice.
M36WT864TF, M36WT864BF
Offset
Data
Description
Value
V
DD
Logic Supply Optimum Program/Erase voltage (highest performance)
(P+C)h = 45h
0018h
1.8V
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
V
PPF
Supply Optimum Program/Erase voltage
(P+D)h = 46h
00C0h
12V
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
Table 39. Protection Register Information
Offset
Data
Description
Value
Number of protection register fields in JEDEC ID space. 0000h indicates that
256 fields are available.
(P+E)h = 47h
0001h
1
(P+F)h = 48h
(P+10)h = 49h
(P+11)h = 4Ah
(P+12)h= 4Bh
0080h
0000h
0003h
0004h
Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
0080h
Bits 8-15 Upper byte of protection register address
n
8 Bytes
Bits 16-23 2 bytes in factory pre-programmed region
n
Bits 24-31 2 bytes in user programmable region
16 Bytes
Table 40. Burst Read Information
Data
Description
Value
Offset
(P+13)h = 4Ch
0003h
Page-mode read capability
8 Bytes
n
bits 0-7
’n’ such that 2 HEX value represents the number of read-
page bytes. See offset 28h for device word width to
determine page-mode data output width.
(P+14)h = 4Dh
(P+15)h = 4Eh
0003h
0001h
Number of synchronous mode read configuration fields that follow.
Synchronous mode read capability configuration 1
3
4
bit 3-7
Reserved
n+1
bit 0-2
’n’ such that 2
HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear
bursts that will output data until the internal burst counter
reaches the end of the device’s burstable address space.
This field’s 3-bit value can be written directly to the read
configuration register bit 0-2 if the device is configured for its
maximum word width. See offset 28h for word width to
determine the burst data output width.
(P+16)h = 4Fh
(P+17)h = 50h
0002h
0007h
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
8
Cont.
Table 41. Bank and Erase Block Region Information
M36WT864TF (top)
M36WT864BF (bottom)
Description
Offset
Data
Offset
Data
(P+18)h =51h
02h
(P+18)h =51h
02h
Number of Bank Regions within the device
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks
that are made up of the parameter and main blocks.
72/92
M36WT864TF, M36WT864BF
Table 42. Bank and Erase Block Region 1 Information
M36WT864TF (top)
M36WT864BF (bottom)
Description
Offset
Data
0Fh
00h
Offset
Data
01h
00h
(P+19)h =52h
(P+1A)h =53h
(P+19)h =52h
(P+1A)h =53h
Number of identical banks within Bank Region 1
Number of program or erase operations allowed in region 1:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+1B)h =54h
(P+1C)h =55h
11h
00h
(P+1B)h =54h
(P+1C)h =55h
11h
00h
Number of program or erase operations allowed in other banks
while a bank in same region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other banks
while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+1D)h =56h
(P+1E)h =57h
00h
01h
(P+1D)h =56h
(P+1E)h =57h
00h
02h
Types of erase block regions in region 1
n = number of erase block regions with contiguous same-size
erase blocks.
(2)
Symmetrically blocked banks have one blocking region.
(P+1F)h =58h
(P+20)h =59h
(P+21)h =5Ah
(P+22)h =5Bh
(P+23)h =5Ch
(P+24)h =5Dh
07h
00h
00h
01h
64h
00h
(P+1F)h =58h
(P+20)h =59h
(P+21)h =5Ah
(P+22)h =5Bh
(P+23)h =5Ch
(P+24)h =5Dh
07h
00h
20h
00h
64h
00h
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 1 (Erase Block Type 1): BIts per cell, internal
ECC
(P+25)h =5Eh
(P+26)h =5Fh
01h
03h
(P+25)h =5Eh
(P+26)h =5Fh
01h
03h
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved 5Eh 01 5Eh 01
Bank Region 1 (Erase Block Type 1): Page mode and
synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+27)h =60h
(P+28)h =61h
(P+29)h =62h
(P+2A)h =63h
(P+2B)h =64h
(P+2C)h =65h
06h
00h
00h
01h
64h
00h
Bank Region 1 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
73/92
M36WT864TF, M36WT864BF
M36WT864TF (top)
Offset Data
M36WT864BF (bottom)
Description
Offset
Data
Bank Regions 1 (Erase Block Type 2): BIts per cell, internal
ECC
(P+2D)h =66h
01h
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
Bank Region 1 (Erase Block Type 2): Page mode and
synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+2E)h =67h
03h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks
that are made up of the parameter and main blocks.
Table 43. Bank and Erase Block Region 2 Information
M36WT864TF (top)
M36WT864BF (bottom)
Description
Offset
Data
01h
00h
Offset
Data
0Fh
00h
(P+27)h =60h
(P+28)h =61h
(P+2F)h =68h
(P+30)h =69h
Number of identical banks within bank region 2
Number of program or erase operations allowed in bank region
2:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+29)h =62h
(P+2A)h =63h
(P+2B)h =64h
(P+2C)h =65h
11h
00h
00h
02h
(P+31)h =6Ah
(P+32)h =6Bh
(P+33)h =6Ch
(P+34)h =6Dh
11h
00h
00h
01h
Number of program or erase operations allowed in other banks
while a bank in this region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other banks
while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in region 2
n = number of erase block regions with contiguous same-size
erase blocks.
(2)
Symmetrically blocked banks have one blocking region.
(P+2D)h =66h
(P+2E)h =67h
(P+2F)h =68h
(P+30)h =69h
(P+31)h =6Ah
(P+32)h =6Bh
06h
00h
00h
01h
64h
00h
(P+35)h =6Eh
(P+36)h =6Fh
(P+37)h =70h
(P+38)h =71h
(P+39)h =72h
(P+3A)h =73h
07h
00h
00h
01h
64h
00h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): BIts per cell, internal
ECC
(P+33)h =6Ch
01h
(P+3B)h =74h
01h
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
74/92
M36WT864TF, M36WT864BF
M36WT864TF (top)
M36WT864BF (bottom)
Description
Offset
Data
Offset
Data
Bank Region 2 (Erase Block Type 1): Page mode and
synchronous
mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+34)h =6Dh
03h
(P+3C)h =75h
03h
(P+35)h =6Eh
(P+36)h =6Fh
(P+37)h =70h
(P+38)h =71h
(P+39)h =72h
(P+3A)h =73h
07h
00h
02h
00h
64h
00h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
(P+3B)h =74h
01h
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
Bank Region 2 (Erase Block Type 2): Page mode and
synchronous
mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+3C)h =75h
03h
(P+3D)h =76h
(P+3E)h =77h
(P+3D)h =76h
(P+3E)h =77h
Feature Space definitions
Reserved
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 con-
tains the banks that are made up of the parameter and main blocks.
75/92
M36WT864TF, M36WT864BF
APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES
Figure 28. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
Write 40h or 10h
writeToFlash (bank_address, 0x40) ;
/*or writeToFlash (bank_address, 0x10) ; */
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
NO
V
Invalid
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
PP
SR3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
SR4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06170
Note: 1. Status check of SR1 (Protected Block), SR3 (V (V
PP
) Invalid) and SR4 (Program Error) can be made after each program oper-
PPF
ation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
76/92
M36WT864TF, M36WT864BF
Figure 29. Double Word Program Flowchart and Pseudo code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (bank_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
SR7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
PP
SR3 = 0
YES
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
Program
SR4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06171
Note: 1. Status check of b1 (Protected Block), b3 (V (V
PP
) Invalid) and b4 (Program Error) can be made after each program operation
PPF
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
77/92
M36WT864TF, M36WT864BF
Figure 30. Quadruple Word Program Flowchart and Pseudo Code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
Write 56h
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
Write Address 1
& Data 1 (3)
writeToFlash (bank_address, 0x56) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
SR7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
PP
SR3 = 0
YES
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
Program
SR4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.SR==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06977
Note: 1. Status check of SR1 (Protected Block), SR3 (V (V
PP
) Invalid) and SR4 (Program Error) can be made after each program oper-
PPF
ation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
78/92
M36WT864TF, M36WT864BF
Figure 31. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
SR2 = 1
YES
Program Complete
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
}
Read data from
another address
else
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
Write FFh
Read Data
}
}
Program Continues
AI06173
79/92
M36WT864TF, M36WT864BF
Figure 32. Block Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (bank_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
NO
SR7 = 1
} while (status_register.SR7== 0) ;
YES
NO
YES
NO
NO
V
Invalid
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
PP
Error (1)
SR3 = 0
YES
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
Command
Sequence Error (1)
SR4, SR5 = 1
NO
error_handler ( ) ;
if ( (status_register.SR5==1) )
/* erase error */
SR5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06174
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
80/92
M36WT864TF, M36WT864BF
Figure 33. Erase Suspend & Resume Flowchart and Pseudo Code
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
Read Status
Register
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
NO
NO
} while (status_register.SR7== 0) ;
SR7 = 1
YES
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
SR6 = 1
YES
Erase Complete
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
Write D0h
Write FFh
Read Data
/*read or program data from another address*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
Erase Continues
AI06175
81/92
M36WT864TF, M36WT864BF
Figure 34. Locking Operations Flowchart and Pseudo Code
Start
locking_operation_command (address, lock_operation) {
Write 60h
writeToFlash (bank_address, 0x60) ; /*configuration setup*/
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
Write
01h, D0h or 2Fh
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
writeToFlash (bank_address, 0x90) ;
Write 90h
Read Block
Lock States
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
NO
Locking
change
/*Check the locking state (see Read Block Signature table )*/
confirmed?
YES
writeToFlash (bank_address, 0xFF) ; /*Reset to Read Array mode*/
Write FFh
}
End
AI06176
82/92
M36WT864TF, M36WT864BF
Figure 35. Protection Register Program Flowchart and Pseudo Code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (bank_address, 0xC0) ;
Write C0h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
NO
SR7 = 1
YES
} while (status_register.SR7== 0) ;
NO
V
Invalid
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
PP
SR3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
SR4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
SR1 = 0
YES
End
}
AI06177
Note: 1. Status check of SR1 (Protected Block), SR3 (V (V
PP
) Invalid) and SR4 (Program Error) can be made after each program oper-
PPF
ation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
83/92
M36WT864TF, M36WT864BF
Figure 36. Enhanced Factory Program Flowchart
SETUP PHASE
Start
VERIFY PHASE
Write PD1
Address WA1(
Write 30h
Address WA1
1)
Write D0h
Address WA1
Read Status
Register
Read Status
Register
NO
SR0 = 0?
YES
NO
SR7 = 0?
Check SR4, SR3
Write PD2
YES
1)
and SR1 for program,
Address WA2(
V
PP and Lock Errors
NO
SR0 = 0?
YES
Exit
Read Status
Register
Write PD1
Address WA1
PROGRAM PHASE
NO
SR0 = 0?
Read Status
Register
YES
Write PDn
Address WAn(
NO
1)
SR0 = 0?
YES
Read Status
Register
Write PD2
Address WA2(
1)
NO
Read Status
Register
SR0 = 0?
YES
NO
Write FFFFh
SR0 = 0?
YES
Address Block WA1
=
/
EXIT PHASE
Write PDn
Address WAn(
1)
Read Status
Register
Read Status
Register
NO
SR7 = 1?
YES
NO
SR0 = 0?
Check Status
Register for Errors
YES
Write FFFFh
=
Address Block WA1
/
End
Note 1. Address can remain Starting Address WA1 or be incremented.
AI06160
84/92
M36WT864TF, M36WT864BF
Enhanced Factory Program Pseudo Code
efp_command(addressFlow,dataFlow,n)
/* n is the number of data to be programmed */
{
/* setup phase */
writeToFlash(addressFlow[0],0x30);
writeToFlash(addressFlow[0],0xD0);
status_register=readFlash(any_address);
if (status_register.b7==1){
/*EFP aborted for an error*/
if (status_register.b4==1) /*program error*/
error_handler();
if (status_register.b3==1) /*VPP invalid error*/
error_handler();
if (status_register.b1==1) /*program to protect block error*/
error_handler();
}
else{
/*Program Phase*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.b0==1)
/*Ready for first data*/
for (i=0; i++; i< n){
writeToFlash(addressFlow[i],dataFlow[i]);
/* status register polling*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.b0==1);
/* Ready for a new data */
}
writeToFlash(another_block_address,FFFFh);
/* Verify Phase */
for (i=0; i++; i< n){
writeToFlash(addressFlow[i],dataFlow[i]);
/* status register polling*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
} while (status_register.b0==1);
/* Ready for a new data */
}
writeToFlash(another_block_address,FFFFh);
/* exit program phase */
/* Exit Phase */
/* status register polling */
do{
status_register=readFlash(any_address);
/* E or G must be toggled */
} while (status_register.b7==0);
if (status_register.b4==1) /*program failure error*/
error_handler();
if (status_register.b3==1) /*VPP invalid error*/
error_handler();
if (status_register.b1==1) /*program to protect block error*/
error_handler();
}
}
85/92
M36WT864TF, M36WT864BF
Figure 37. Quadruple Enhanced Factory Program Flowchart
SETUP PHASE
LOAD PHASE
Start
Write PD1
Address WA1
1)
(
Write 75h
Address WA1
Read Status
Register
FIRST
LOAD PHASE
Write PD1
Address WA1
NO
NO
NO
SR0 = 0?
YES
Read Status
Register
Write PD2
Address WA2
2)
(
NO
SR7 = 0?
YES
Read Status
Register
Check SR4, SR3
and SR1 for program,
SR0 = 0?
V
and Lock Errors
PP
YES
Write PD3
Address WA3
Exit
2)
(
Read Status
Register
SR0 = 0?
YES
Write PD4
Address WA4
2)
(
EXIT PHASE
PROGRAM AND
VERIFY PHASE
Write FFFFh
Address =Block WA1
/
Read Status
Register
NO
NO
Check Status
Register for Errors
SR0 = 0?
YES
End
Last Page?
YES
Note 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be
any address in the same block.
2.The address is only checked for the first Word of each Page as the order to program the Words is fixed
so subsequent Words in each Page can be written to any address.
AI06178
86/92
M36WT864TF, M36WT864BF
Quadruple Enhanced Factory Program Pseudo Code
quad_efp_command(addressFlow,dataFlow,n)
/* n is the number of pages to be programmed.*/
{
/* Setup phase */
writeToFlash(addressFlow[0],0x75);
for (i=0; i++; i< n){
/*Data Load Phase*/
/*First Data*/
writeToFlash(addressFlow[i],dataFlow[i,0]);
/*at the first data of the first page, Quad-EFP may be aborted*/
if (First_Page) {
status_register=readFlash(any_address);
if (status_register.b7==1){
/*EFP aborted for an error*/
if (status_register.b4==1) /*program error*/
error_handler();
if (status_register.b3==1) /*VPP invalid error*/
error_handler();
if (status_register.b1==1) /*program to protect block error*/
error_handler();
}
}
/*2nd data*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
}while (status_register.b0==1)
writeToFlash(addressFlow[i],dataFlow[i,1]);
/*3rd data*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
}while (status_register.b0==1)
writeToFlash(addressFlow[i],dataFlow[i,2]);
/*4th data*/
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
}while (status_register.b0==1)
writeToFlash(addressFlow[i],dataFlow[i,3]);
/* Program&Verify Phase */
do{
status_register=readFlash(any_address);
/* E or G must be toggled*/
}while (status_register.b0==1)
}
/* Exit Phase */
writeToFlash(another_block_address,FFFFh);
/* status register polling */
do{
status_register=readFlash(any_address);
/* E or G must be toggled */
} while (status_register.b7==0);
if (status_register.b1==1) /*program to protected block error*/
error_handler();
if (status_register.b3==1) /*VPP invalid error*/
error_handler();
if (status_register.b4==1) /*program failure error*/
error_handler();
}
}
87/92
M36WT864TF, M36WT864BF
APPENDIX D. FLASH COMMAND INTERFACE STATE TABLES
Table 44. Command Interface States - Modify Table, Next State
Next CI State After Command Input
Erase
Confirm
P/E
Block
Read
Program Program
Erase,
Bank
Erase
Setup
(3,4)
Clear
status
Register
(5)
Quad- Resume, Program/ Read
Electronic
signature,
Read CFI
Query
WP
DWP,
Current CI State
Read
EFP
Setup
EFP
Setup
Block
Erase
Status
setup
(3,4)
QWP
Setup
(3,4)
(2)
Array
Unlock Suspend Register
confirm,
EFP
Confirm
Program
Setup
Program
Setup
Quad-EFP
Setup
Ready
Ready
Erase Setup EFP Setup
Ready
Lock/CR Setup
Ready (Lock Error)
Ready
Ready (Lock Error)
Setup
OTP
OTPBusy
Busy
Setup
Program Busy
Program
Suspended
Busy
Program Busy
Program Busy
Program
Program
Busy
Suspend
Setup
Program Suspended
Ready (error)
Program Suspended
Ready (error)
Erase Busy
Erase
Suspended
Busy
Erase Busy
Erase Busy
Erase
Program in
Erase
Suspend
Erase
Suspended
Suspend
Setup
Erase Suspended
Erase Busy
Erase Suspended
Program in Erase Suspend Busy
Program in
Erase
Suspend
Suspended
Busy
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Program
in Erase
Suspend
Program in
Erase
Suspend
Busy
Suspend
Program in Erase Suspend Suspended
Program in Erase Suspend Suspended
Lock/CR Setup
in Erase Suspend
Erase
Suspend
Erase Suspend (Lock Error)
Ready (error)
Erase Suspend (Lock Error)
Ready (error)
Setup
EFP Busy
(6)
Busy
Verify
Setup
Busy
EFP
EFPBusy
EFPVerify
(6)
(6)
(6)
Quad EFP Busy
Quad
EFP
Quad EFP Busy
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-
tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.
2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-
put.
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.
5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is
first EFP Address. Any other commands are treated as data.
88/92
M36WT864TF, M36WT864BF
Table 45. Command Interface States - Modify Table, Next Output
Next Output State After Command Input (6)
Erase
Confirm
P/E
Resume,
Block
Unlock
confirm,
EFP
Block
Erase,
Bank
Erase
Setup
(3,4)
Read
Program
DWP,
QWP
Setup
(3,4)
Quad-
EFP
Setup
Program/
Erase
Suspend Register
Read
Status
Electronic
signature,
Read CFI
Query
Clear status
Register
(5)
Read
Current CI State
EFP
Setup
(2)
Array
Confirm
Program Setup
Erase Setup
OTP Setup
Program in
Erase Suspend
Status Register
EFP Setup
EFP Busy
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Lock/CR Setup
in Erase
Status Register
Suspend
Status
Register
Output
Unchanged
Status
Register
OTP Busy
Array
Array
Status Register
Status Register
Output Unchanged
Ready
Program Busy
Erase Busy
Program/Erase
Electronic
Signature/
CFI
Status
Register
Output
Unchanged
Program in
Erase Suspend
Busy
Output Unchanged
Program in
Erase Suspend
Suspended
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-
tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.
2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-
put.
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.
5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A
bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode, depending on the
command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the
bank’s output state.
89/92
M36WT864TF, M36WT864BF
Table 46. Command Interface States - Lock Table, Next State
Next CI State After Command Input
Block
Lock-Down
EFP Exit,
P/E. C.
Operation
Completed
Illegal
Command
(5)
Current CI State
Lock/CR
Block Lock
Confirm
Set CR
OTP Setup
(4)
Quad EFP
(4)
Setup
Confirm
(3)
Confirm
Exit
Lock/CR
Setup
Ready
OTP Setup
Ready
N/A
Lock/CR Setup
Ready (Lock error)
Ready
Ready (Lock error)
N/A
N/A
Setup
OTP
OTP Busy
Busy
Ready
N/A
Setup
Program Busy
Program Busy
Program
Erase
Busy
Suspend
Setup
Ready
N/A
Program Suspended
Ready (error)
N/A
Busy
Erase Busy
Ready
Lock/CR
Setup in
Erase
Suspend
Erase Suspended
N/A
Suspend
Setup
Busy
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Program in Erase Suspend Suspended
Erase Suspend
N/A
Program in
Erase
Suspend
Erase
Suspended
Suspend
N/A
Lock/CR Setup
in Erase Suspend
Erase Suspend (Lock
error)
Erase Suspend (Lock error)
N/A
Setup
Ready (error)
N/A
N/A
(2)
(2)
(2)
Busy
Verify
Setup
EFP Verify
Ready
EFP
EFP Busy
EFP Busy
(2)
Ready
N/A
EFP Verify
EFP Verify
(2)
Quad EFP Busy
QuadEFP
Quad EFP
(2)
Busy
Ready
Ready
Quad EFP Busy
(2)
Busy
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-
tory Program, P/E. C. = Program/Erase Controller.
2. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad EFP are busy if Block Address is
first EFP Address. Any other commands are treated as data.
3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
4. If the P/E.C. is active, both cycles are ignored.
5. Illegal commands are those not defined in the command set.
90/92
M36WT864TF, M36WT864BF
Table 47. Command Interface States - Lock Table, Next Output
Next Output State After Command Input
Block
Lock-Down
EFP Exit,
Quad EFP
P/E. C.
Operation
Completed
Illegal
Command
(4)
Current CI State
Lock/CR
Block Lock
Confirm
Set CR
OTP Setup
(3)
(3)
Setup
Confirm
(2)
Confirm
Exit
Program Setup
Erase Setup
OTP Setup
Program in Erase
Suspend
Output
Unchanged
Status Register
EFP Setup
EFP Busy
EFP Verify
Quad EFP Setup
Quad EFP Busy
Lock/CR Setup
Output
Unchanged
Status Register
Array
Status Register
Output
Lock/CR Setup in
Erase Suspend
Output
Unchanged Unchanged
OTP Busy
Status Register
Output Unchanged
Output Unchanged
Array
Ready
Program Busy
EraseBusy
Program/Erase
Output
Output
Unchanged Unchanged
Status Register
Array
Program in Erase
Suspend Busy
Program in Erase
Suspend
Suspended
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-
tory Program, P/E. C. = Program/Erase Controller.
2. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
3. If the P/E.C. is active, both cycles are ignored.
4. Illegal commands are those not defined in the command set.
91/92
M36WT864TF, M36WT864BF
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
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92/92
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