M40SZ100W [STMICROELECTRONICS]
5V or 3V NVRAM SUPERVISOR FOR LPSRAM; 5V或3V NVRAM监督员LPSRAM
| 型号： | M40SZ100W |
| 厂家： | 
ST |
| 描述： | 5V or 3V NVRAM SUPERVISOR FOR LPSRAM |
| 文件： | 总19页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M40SZ100Y
M40SZ100W
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
FEATURES SUMMARY
■ CONVERT LOW POWER SRAMs INTO
Figure 1. 16-pin SOIC Package
NVRAMs
■ 5V OR 3V OPERATING VOLTAGE
■ PRECISION POWER MONITORING and
16
POWER SWITCHING CIRCUITRY
1
■ AUTOMATIC WRITE-PROTECTION WHEN
V
IS OUT-OF-TOLERANCE
CC
SO16 (MQ)
■ CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40SZ100Y: V = 4.5 to 5.5V;
CC
Figure 2. 28-pin SOIC Package*
4.20V ≤ V
≤ 4.50V
PFD
– M40SZ100W: V = 2.7 to 3.6V;
CC
2.55V ≤ V
≤ 2.70V
PFD
SNAPHAT (SH)
Battery
■ RESET OUTPUT (RST) FOR POWER ON
RESET
■ 1.25V REFERENCE (for PFI/PFO)
■ LESS THAN 10ns CHIP ENABLE ACCESS
PROPAGATION DELAY (at 5V)
■ OPTIONAL PACKAGING INCLUDES A 28-
®
LEAD SOIC and SNAPHAT TOP (to be
ordered separately)
28
1
■ 28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
SOH28 (MH)
■ BATTERY LOW PIN (BL)
* Contact Local Sales Office
September 2003
1/19
Rev. 1.3
M40SZ100Y, M40SZ100W
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SOIC16 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SOIC28 Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Hookup (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Load Circuit (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Input/Output Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Down Timing (Figure 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Up Timing (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-on Reset Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset Input (RSTIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RSTIN Timing Waveform (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SNAPHAT® Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M40SZ100Y, M40SZ100W
SUMMARY DESCRIPTION
The M40SZ100Y/W NVRAM Controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A preci-
sion voltage reference and comparator monitors
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a sol-
dered holder. Providing non-volatility becomes a
“SNAP.” This feature is also available in the “top-
less” 16-pin SOIC package (MQ).
the V input for an out-of-tolerance condition.
CC
When an invalid V
tioned chip enable output (E
condition occurs, the condi-
CC
) is forced inactive
CON
to write protect the stored data in the SRAM. Dur-
ing a power failure, the SRAM is switched from the
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount-
ing. The SNAPHAT housing is also keyed to pre-
vent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4ZXX-BR00SH” (see Table 13, page 17).
V
pin to the lithium cell within the SNAPHAT (or
CC
external battery for the 16-lead SOIC) to provide
the energy required for data retention. On a sub-
sequent power-up, the SRAM remains write pro-
tected until a valid power condition returns.
The 28-pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a sep-
®
arate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent im-
proper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
Caution: Do not place the SNAPHAT battery top
in conductive foam, as this will drain the lithium
button-cell battery.
Figure 3. Logic Diagram
Table 1. Signal Names
E
Chip Enable Input
(1)
V
V
CC BAT
E
Conditioned Chip Enable Output
Reset Output (Open Drain)
Reset Input
CON
RST
RSTIN
BL
V
OUT
Battery Low Output (Open Drain)
Supply Voltage Output
Supply Voltage
E
BL
E
V
OUT
M40SZ100Y
M40SZ100W
PFI
CON
V
CC
PFO
RST
RSTIN
(1)
Back-up Supply Voltage
V
BAT
PFI
PFO
Power Fail Input
Power Fail Output
Ground
V
SS
V
SS
AI03933
NC
Not Connected Internally
Note: 1. For SO16 only.
Note: 1. For 16-pin SOIC package only.
3/19
M40SZ100Y, M40SZ100W
Figure 4. SOIC16 Connections
Figure 5. SOIC28 Connections
1
2
3
4
5
6
7
8
9
28
27
V
CC
BL
NC
NC
NC
V
26
NC
NC
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
25
NC
OUT
24
NC
NC
NC
PFI
NC
E
RST
NC
V
OUT
23
NC
NC
PFI
BL
E
M40SZ100Y
M40SZ100W
22
NC
M40SZ100Y
M40SZ100W
RSTIN
PFO
21
NC
20
RSTIN
NC
V
BAT
10
11
12
13
14
19
NC
RST
NC
NC
E
V
E
CON
SS
18
NC
NC
17
AI03935
16
PFO
V
15
SS
CON
AI03934
Note: 1. DU = Do Not Use
Figure 6. Block Diagram
V
V
CC
OUT
V
BAT
(1)
COMPARE
BL
V
= 2.5V
= 2.5V
BL
COMPARE
V
SO
POR
COMPARE
V
= 4.4V
PFD
(2.65V for SZ100W)
(1)
RST
E
RSTIN
E
CON
PFI
PFO
COMPARE
1.25V
AI04766
Note: Open drain output
4/19
M40SZ100Y, M40SZ100W
Figure 7. Hardware Hookup
3.0V, 3.3V or 5V
Regulator
Unregulated
Voltage
V
V
V
E
V
OUT
IN
CC
CC
V
CC
0.1µF
M40SZ100Y
M40SZ100W
1Mb or 4Mb
LPSRAM
0.1µF
E
From Microprocessor
RSTIN
PFI
E
CON
PFO
R1
R2
To Microprocessor NMI
To Microprocessor Reset
To Battery Monitor Circuit
V
RST
BL
SS
(1)
V
BAT
AI04767
Note: 1. User supplied for the 16-pin package
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
SNAPHAT
SOIC
–40 to 85
–55 to 125
T
Storage Temperature (V Off)
CC
STG
°C
(1)
SLD
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
V
IO
–0.3 to V +0.3
V
V
CC
M40SZ100Y
M40SZ100W
–0.3 to 7
V
Supply Voltage
CC
–0.3 to 4.6
V
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
5/19
M40SZ100Y, M40SZ100W
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. DC and AC Measurement Conditions
Parameter
M40SZ100Y
4.5 to 5.5V
–40 to 85°C
100pF
M40SZ100W
2.7 to 3.6V
–40 to 85°C
50pF
V
CC
Supply Voltage
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 5ns
≤ 5ns
0.2 to 0.8V
0.2 to 0.8V
Input Pulse Voltages
CC
CC
0.3 to 0.7V
0.3 to 0.7V
Input and Output Timing Ref. Voltages
CC
CC
Figure 8. AC Testing Load Circuit
Figure 9. AC Testing Input/Output Waveforms
333Ω
DEVICE
UNDER
TEST
0.8V
CC
0.7V
CC
1.73V
0.3V
CC
C
= 100pF
or 50pF
L
0.2V
CC
AI02568
C
includes JIG capacitance
L
AI02393
Note: 1. CL = 100pF for M40SZ100Y and 50pF for M40SZ100W.
Table 4. Capacitance
(1,2)
Symbol
Min
Max
7
Unit
pF
Parameter
C
Input Capacitance
Output Capacitance
IN
(3)
10
pF
C
OUT
Note: 1. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected
6/19
M40SZ100Y, M40SZ100W
Table 5. DC Characteristics
M40SZ100Y
Typ
M40SZ100W
Unit
(1)
Sym
Parameter
Test Condition
Min
Max
Min
Typ
Max
I
Supply Current
Outputs open
1
0.5
mA
nA
CC
Data Retention Mode
I
50
2
200
50
200
CCDR
(2)
Current
Input Leakage
Current
0V ≤ V ≤ V
±1
25
±1
25
µA
nA
µA
mA
µA
IN
CC
(3)
I
LI
Input Leakage
Current (PFI)
–25
–25
2
Output Leakage
Current
(4)
LO
0V ≤ V
≤ V
CC
±1
±1
I
OUT
V
Current
OUT
(5)
V
V
> V – 0.3
CC
175
100
100
100
I
OUT
OUT1
(Active)
V
Current
OUT
I
> V
– 0.3
BAT
OUT2
OUT
(Battery Back-up)
Battery Voltage
Input High Voltage
Input Low Voltage
Output High
(6)
(6)
V
2.5
3.0
V
2.5
3.0
V
V
V
BAT
3.5
3.5
V
0.7V
+ 0.3 0.7V
V
+ 0.3
IH
CC
CC
CC
CC
V
0.3V
0.3V
CC
–0.3
2.4
–0.3
IL
CC
V
I
= –1.0mA
= –1.0µA
2.4
2.5
V
OH
OH
(7)
Voltage
V
Battery Back-
OH
(8)
V
OHB
I
2.5
2.9
3.5
0.4
0.4
2.9
3.5
0.4
0.4
V
V
V
OUT2
up
I
= 3.0mA
Output Low Voltage
Output Low Voltage
OL
V
OL
I
OL
= 10mA
(9)
(open drain)
Power-fail Deselect
Voltage
V
4.20
4.40
4.50
2.55
2.60
2.70
V
PFD
V
V
= 5V(Y)
= 3V(V)
CC
CC
PFI Input Threshold
PFI Hysteresis
1.225 1.250
1.275
70
1.225 1.250
1.275
70
V
mV
V
V
PFI
PFI Rising
20
20
Battery Back-up
Switchover Voltage
V
2.5
2.5
SO
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
A
CC
2. Measured with V
and E
open.
OUT
CON
3. RSTIN internally pulled-up to V through 100kΩ resistor.
CC
4. Outputs deselected.
5. External SRAM must match SUPERVISOR chip V specification (3V or 5V).
CC
6. For rechargeable back-up, V
7. For PFO pin (CMOS).
(max) may be considered V – 0.5V.
CC
BAT
8. Chip Enable output (E
duce battery life.
) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will re-
CON
9. For RST & BL pins (Open Drain).
7/19
M40SZ100Y, M40SZ100W
OPERATION
The M40SZ100Y/W, as shown in Figure 7, page 5,
can control one (two, if placed in parallel) standard
low-power SRAM. This SRAM must be configured
to have the chip enable input disable all other input
signals. Most slow, low-power SRAMs are config-
ured like this, however many fast SRAMs are not.
During normal operating conditions, the condi-
supply has reached V
put, to allow for processor stabilization (see Figure
11, page 10).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40SZ100Y/W NVRAM Control-
ler. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40SZ100Y/W and SRAMs to be “Don't care”
, independent of the E in-
PFD
tioned chip enable (E
) output pin follows the
CON
chip enable (E) input pin with timing shown in Ta-
ble 6, page 10. An internal switch connects V to
CC
V
. This switch has a voltage drop of less than
OUT
0.3V (I
).
OUT1
When V degrades during a power failure, E
CC
CON
once V
falls below V
(min) (see Figure 10,
CC
PFD
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
page 9). The SRAM should also guarantee data
retention down to V = 2.0V. The chip enable ac-
CC
as V
falls below an out-of-tolerance threshold
). For the M40SZ100Y/W the power fail de-
CC
cess time must be sufficient to meet the system
needs with the chip enable propagation delays in-
cluded.
(V
PFD
tection value associated with V
ble 5, page 7.
is shown in Ta-
PFD
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
,
WPT
E
is unconditionally driven high, write protect-
CON
ing the SRAM. A power failure during a WRITE cy-
cle may corrupt data at the currently addressed
location, but does not jeopardize the rest of the
SRAM's contents. At voltages below V
(min),
PFD
the user can be assured the memory will be write
protected within the Write Protect Time (t ) pro-
SRAMs can then be added to the I
value of
CCDR
WPT
the M40SZ100Y/W to determine the total current
requirements for data retention. The available bat-
vided the V fall time does not exceed t (see Ta-
CC
F
®
ble 6, page 10).
tery capacity for the SNAPHAT of your choice
As V
continues to degrade, the internal switch
(see Table 13, page 17) can then be divided by
this current to determine the amount of data reten-
tion available.
CC
disconnects V and connects the internal battery
CC
to V
. This occurs at the switchover voltage
OUT
(V ). Below the V , the battery provides a volt-
SO
SO
CAUTION: Take care to avoid inadvertent dis-
age V
to the SRAM and can supply current
(see Table 5, page 7).
OHB
charge through V
been attached.
and E
after battery has
OUT
CON
I
OUT2
When V
rises above V , V
is switched
CC
SO
OUT
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
back to the supply voltage. Output E
active for t
is held in-
CON
(120ms maximum) after the power
CER
8/19
M40SZ100Y, M40SZ100W
Figure 10. Power Down Timing
V
CC
V
V
V
V
(max)
(min)
PFD
PFD
PFD
SO
tF
tFB
E
E
tWPT
V
OHB
CON
RST
PFO
VALID
AI03936
9/19
M40SZ100Y, M40SZ100W
Figure 11. Power Up Timing
V
CC
V
V
V
(max)
(min)
PFD
PFD
PFD
V
SO
tR
tRB
tCER
E
E
tEPD
tEPD
V
OHB
CON
tREC
RST
PFO
VALID
AI03937
Table 6. Power Down/Up AC Characteristics
(1)
Symbol
Min
Max
Unit
µs
Parameter
(2)
V
V
(max) to V
(min) to V
(min) V Fall Time
300
t
PFD
PFD
CC
F
(3)
V
Fall Time
10
15
10
µs
t
PFD
SS CC
FB
t
PFI to PFO Propagation Delay
V (min) to V (max) V Rise Time
PFD
25
µs
µs
ns
ns
µs
ms
ms
µs
PFD
t
R
PFD
CC
M40SZ100Y
M40SZ100W
10
15
t
Chip Enable Propagation Delay (Low or High)
V to V (min) V Rise Time
SS
EPD
t
1
RB
PFD
CC
t
Chip Enable Recovery
V (max) to RST High
PFD
40
40
40
120
200
200
CER
t
REC
t
Write Protect Time
WPT
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after V
PFD CC
PFD
passes V
(min).
PFD
3. V
(min) to V fall time of less than tFB may cause corruption of RAM data.
PFD
SS
10/19
M40SZ100Y, M40SZ100W
Power-on Reset Output
Reset Input (RSTIN)
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40SZ100Y/W has a reset output (RST) pin which
The M40SZ100Y/W provides one independent in-
put which can generate an output reset. The dura-
tion and function of this reset is identical to a reset
generated by a power cycle. Table 7 and Figure 12
illustrate the AC reset characteristics of this func-
is guaranteed to be low by V
(see Table 5,
PFD
page 7). This signal is an open drain configuration.
An appropriate pull-up resistor to V should be
tion. Pulses shorter than t
will not generate a
CC
RLRH
chosen to control the rise time. This signal will be
valid for all voltage conditions, even when V
reset condition. RSTIN is internally pulled up to
through a 100kΩ resistor.
V
CC
CC
equals V (with valid battery voltage).
SS
Once V
exceeds the power failure detect volt-
, an internal timer keeps RST low for
CC
age V
PFD
t
to allow the power supply to stabilize.
REC
Figure 12. RSTIN Timing Waveform
RSTIN
tRLRH
RST (1)
tR1HRH
AI04768
Note: With pull-up resistor
Table 7. Reset AC Characteristics
(1)
Symbol
Min
200
40
Max
Unit
ns
Parameter
(2)
RSTIN Low to RSTIN High
RSTIN High to RST High
t
RLRH
(3)
200
ms
t
R1HRH
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).
A
CC
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. C = 5pF (see Figure 8, page 6).
L
11/19
M40SZ100Y, M40SZ100W
Battery Low Pin
The M40SZ100Y/W automatically performs bat-
tery voltage monitoring upon power-up, and at fac-
tory-programmed time intervals of at least 24
hours. The Battery Low (BL) pin will be asserted if
the battery voltage is found to be less than approx-
imately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
curs after V drops below V
er returns, PFO is forced high, irrespective of V
(min). When pow-
PFD
CC
PFI
for the write protect time (t
), which is the time
REC
from V
(max) until the inputs are recognized. At
PFD
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to V and PFO
SS
left unconnected.
V
Noise And Negative Going Transients
CC
I
transients, including those produced by output
CC
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
promised due to the fact that a nominal V
is
CC
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
The M40SZ100Y/W only monitors the battery
below V by as much as one volt. These negative
SS
when a nominal V is applied to the device. Thus
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
CC
applications which require extensive durations in
the battery back-up mode should be powered-up
periodically (at least once every few months) in or-
der for this technique to be beneficial. Additionally,
if a battery low is indicated, data integrity should
be verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
mends connecting a schottky diode from V
to
CC
V
(cathode connected to V , anode to V ).
SS
CC SS
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
an appropriate pull-up resistor to V
chosen to control the rise time.
Power-fail Input/Output
should be
CC
Figure 13. Supply Voltage Protection
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (independent from the
V
V
comparator). If PFI is less than the power-fail
CC
PFD
threshold (V ), the Power-Fail Output (PFO) will
PFI
V
go low. This function is intended for use as an un-
der-voltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 7, page 5) to either the
unregulated DC input (if it is available) or the reg-
CC
0.1µF
DEVICE
ulated output of the V regulator. The voltage di-
CC
vider can be set up such that the voltage at PFI
V
SS
falls below V
several milliseconds before the
PFI
regulated V
input to the M40SZ100Y/W or the
CC
microprocessor drops below the minimum operat-
ing voltage.
AI00622
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
12/19
M40SZ100Y, M40SZ100W
PACKAGE MECHANICAL INFORMATION
Figure 14. SO16 – 16-lead Plastic Small Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 8. SO16 – 16-lead Plastic Small Plastic Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.75
0.25
1.60
0.46
0.25
10.00
4.00
–
Typ.
Max.
0.069
0.010
0.063
0.018
0.010
0.394
0.158
–
A
A1
A2
B
0.10
0.004
0.35
0.19
9.80
3.80
–
0.014
0.007
0.386
0.150
–
C
D
E
e
1.27
0.050
H
5.80
0.40
0°
6.20
1.27
8°
0.228
0.016
0°
0.244
0.050
8°
L
a
N
16
16
CP
0.10
0.004
13/19
M40SZ100Y, M40SZ100W
Figure 15. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 9. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
14/19
M40SZ100Y, M40SZ100W
Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Note: Drawing is not to scale.
Table 10. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
15/19
M40SZ100Y, M40SZ100W
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Note: Drawing is not to scale.
Table 11. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
16/19
M40SZ100Y, M40SZ100W
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M40SZ
100Y
MQ
6
TR
Device Type
M40SZ
Supply Voltage and Write Protect Voltage
100Y = V
= 4.5 to 5.5V; V
= 4.2 to 4.5V
= 2.6 to 2.7V
CC
PFD
100W = V
= 2.7 to 3.6V; V
PFD
CC
Package
MQ = SO16
(1,2)
MH
= SOH28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
®
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ) which is ordered separately under the part number
“M4ZXX-BR00SHX” in plastic tube or “M4ZXX-BR00SHXTR” in Tape & Reel form.
2. Contact Local Sales Office
Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH” in conductive foam as it will drain the lithium button-cell bat-
tery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
®
Table 13. SNAPHAT Battery Table
Part Number
M4Z28-BR00SH
M4Z32-BR00SH
Description
Package
SH
SNAPHAT Housing for 48mAh Battery
SNAPHAT Housing for 120mAh Battery
SH
17/19
M40SZ100Y, M40SZ100W
REVISION HISTORY
Table 14. Document Revision History
Date
Rev. #
1.0
Revision Details
December 2001
13-May-02
01-Aug-02
First Issue
1.1
Modify reflow time and temperature footnote (Table 2)
Add marketing status (Figure 2; Table 12)
1.2
15-Sep-03
1.3
Remove reference to M68xxx (obsolete) part (Figure 7); update disclaimer
18/19
M40SZ100Y, M40SZ100W
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ER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER, ZEROPOWER,
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NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
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3V, 3V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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