M41ST85W-70MH6TR [STMICROELECTRONICS]
1 TIMER(S), REAL TIME CLOCK, PDSO28, 0.330 INCH, SNAPHAT, PLASTIC, SOH-28;
| 型号： | M41ST85W-70MH6TR |
| 厂家： | 
ST |
| 描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28, 0.330 INCH, SNAPHAT, PLASTIC, SOH-28 时钟 光电二极管 外围集成电路 |
| 文件： | 总32页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41ST85Y
M41ST85W
512 Kbit (64 bit x 8) Serial Access RTC
and NVRAM SUPERVISOR
PRELIMINARY DATA
FEATURES SUMMARY
■ 3V or 5V OPERATING VOLTAGE
Figure 1. Packages
2
■ SERIAL INTERFACE SUPPORTS I C BUS
(400 KHz)
SNAPHAT (SH)
Battery & Crystal
■ NVRAM SUPERVISOR for EXTERNAL
LPSRAM
■ OPTIMIZED for MINIMAL INTERCONNECT to
MCU
■ 2.5 to 5.5V CLOCK OPERATING VOLTAGE
■ AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
■ CHOICE of POWER-FAIL DESELECT
28
VOLTAGES
1
– M41ST85Y: V = 4.5 to 5.5V;
CC
SOH28 (MH)
V
PFD
= 4.40 ± 0.10V
– M41ST85W: V = 2.7 to 3.6V;
CC
V
PFD
= 2.65 ± 0.05V
■ 1.25V REFERENCE (for PFI/PFO)
■ COUNTERS FOR TENTHS/HUNDREDTHS of
SECONDS, SECONDS, MINUTES, HOURS,
DAY, DATE, MONTH, YEAR, and CENTURY
■ 44 BYTES of GENERAL PURPOSE RAM
■ PROGRAMMABLE ALARM AND INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
■ WATCHDOG TIMER
■ MICROPROCESSOR POWER-ON RESET
■ BATTERY LOW FLAG
■ ULTRA-LOW BATTERY SUPPLY CURRENT
of 500nA (MAX)
■ PACKAGING INCLUDES a28-LEAD SOIC and
SNAPHAT TOP (to be Ordered Separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL
January 2001
1/32
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M41ST85Y, M41ST85W
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SOIC Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware Hookup (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Bus Data Transfer Sequence (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Cycle Timing: RTC & External SRAM Control Signals (Figure 8.). . . . . . . . . . . . . . . . . . . . . . 9
Bus Timing Requirements Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AC Characteristics (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Slave Address Location (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Mode Sequences (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternate Read Mode Sequences (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TIMEKEEPER Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER Register Map (Table 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Back-Up Mode Alarm Waveform (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alarm Interrupt Reset Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Alarm Repeat Modes (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Square Wave Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Square Wave Output Frequency (Table 5.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RSTIN1 & RSTIN2 Timing Waveforms (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-fail INPUT/OUTPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Crystal Accuracy Across Temperature (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Calibration Waveform (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/32
M41ST85Y, M41ST85W
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute Maximum Ratings (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC Measurement Conditions (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Testing Load Circuit (Figure 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Testing Input/Output Waveforms (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Capacitance (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating Modes (Table 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Crystal Electrical Characteristics (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power Down/Up Mode AC Waveforms (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Down/Up AC Characteristics (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
M41ST85Y, M41ST85W
SUMMARY DESCRIPTION
The M41ST85Y/W Serial TIMEKEEPER/Control-
ler SRAM is a low power 512 bit static CMOS
SRAM organized as 64 words by 8 bits. A built-in
32.768 kHz oscillator (external crystal controlled)
and 8 bytes of the SRAM (see Table 6, page 19)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
29 (leap year - valid until year 2100), 30 and 31
day months are made automatically. The ninth
clock address location controls user access to the
clock information and also stores the clock soft-
ware calibration setting.
The M41ST85Y/W is supplied in a 28 lead SOIC
SNAPHAT package (which integrates both crystal
and battery in a single SNAPHAT top). The 28 pin
330mil SOIC provides sockets with gold plated
contacts at both ends for direct connection to a
separate SNAPHAT housing containing the bat-
tery and crystal. The unique design allows the
SNAPHAT battery/crystal package to be mounted
on top of the SOIC package after the completion of
the surface mount process.
An additional 12 bytes of RAM provide status/con-
trol of Alarm, Watchdog and Square Wave func-
tions. Addresses and data are transferred serially
2
via a two line, bi-directional I C interface. The
built-in address register is incremented automati-
cally after each write or read data byte. The
M41ST85Y/W has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power fail-
ure occurs.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
Functions available to the user include a non-vol-
atile, time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. Other features include a Power-On
Reset as well as two additional debounced inputs
(RSTIN1 and RSTIN2) which can also generate an
output Reset (RST). The eight clock address loca-
tions contain the century, year, month, date, day,
hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28,
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is “M4TXX-BR12SH” (see Table 18, page 30).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
4/32
M41ST85Y, M41ST85W
Figure 2. Logic Diagram
Table 1. Signal Names
E
Conditioned Chip Enable Output
External Chip Enable
CON
EX
V
CC
Interrupt/Frequency Test/Out
Output (Open Drain)
IRQ/FT/OUT
PFI
Power Fail Input
Power Fail Output
Reset Output (Open Drain)
Reset 1 Input
SCL
SDA
E
CON
PFO
RST
RST
EX
M41ST85Y
M41ST85W
IRQ/FT/OUT
SQW
RSTIN1
RSTIN2
SCL
RSTIN1
RSTIN2
WDI
Reset 2 Input
Serial Clock Input
Serial Data Input/Output
Square Wave Output
Watchdog Input
Supply Voltage
PFO
SDA
V
OUT
PFI
SQW
WDI
V
CC
V
SS
AI03658
V
OUT
Voltage Output
V
Ground
SS
Figure 3. SOIC Connections
SQW
NC
1
2
3
4
5
6
28
27
26
25
24
23
V
CC
EX
NC
IRQ/FT/OUT
NC
V
OUT
NC
NC
NC
NC
NC
7 M41ST85Y 22
PFI
NC
M41ST85W
WDI
RSTIN1
RSTIN2
NC
8
21
20
19
18
17
16
15
9
SCL
NC
10
11
12
13
14
RST
NC
NC
PFO
SDA
V
SS
E
CON
AI03659
5/32
M41ST85Y, M41ST85W
Figure 4. Block Diagram
REAL TIME CLOCK
CALENDAR
SDA
44 BYTES
USER RAM
2
I
C
INTERFACE
AF
RTC w/ALARM
& CALIBRATION
SCL
IRQ/FT/OUT(1)
SQW
WDF
WATCHDOG
32KHz
OSCILLATOR
Crystal
SQUARE WAVE
WDI
V
V
CC
OUT
V
BAT
BL
COMPARE
COMPARE
V
=
BL
2.5V
V
=
SO
2.5V
V
=
PFD
4.4V
POR
COMPARE
(2.65V for ST85W)
RST (1)
RSTIN1
RSTIN2
E
CON
EX
PFI
PFO
COMPARE
1.25V
Note: 1. Open drain output
AI03932
6/32
M41ST85Y, M41ST85W
Figure 5. Hardware Hookup
Regulator
Unregulated
Voltage
V
V
V
V
E
V
IN
CC
CC
OUT
CC
E
CON
M68Z128Y/W
or
EX
M68Z512Y/W
SCL
WDI
SDA
RST
RSTIN1
RSTIN2
RST
SQW
To LED Display
To NMI
Pushbutton
Reset
R1
R2
PFO
PFI
IRQ/FT/OUT
To INT
V
SS
AI03660
7/32
M41ST85Y, M41ST85W
OPERATING MODES
The M41ST85Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con-
tained inthe device can then be accessed sequen-
tially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
The M41ST85Y/W clock continually monitors V
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
CC
for an out-of tolerance condition. Should V fall
CC
below V
, the device terminates an access in
PFD
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
falls below V , the device automati-
CC
SO
cally switches over to the battery and powers
down into an ultra low currentmode of operation to
conserve battery life. As system power returns and
Acknowledge. Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
V
rises above V , the battery is disconnected,
CC
SO
and the power supply is switched to external V
Write protection continues until V reaches V
.
CC
CC
PFD
plus t
.
REC
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
8/32
M41ST85Y, M41ST85W
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
Figure 8. Write Cycle Timing: RTC & External SRAM Control Signals
EX
tEXPD
tEXPD
E
CON
AI03663
9/32
M41ST85Y, M41ST85W
Figure 9. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Table 2. AC Characteristics
Symbol
Parameter
Min
0
Max
Unit
kHz
µs
f
t
SCL Clock Frequency
400
SCL
Time the bus must be free before a new transmission can start
M41ST85Y
1.3
BUF
10
15
t
EX to E
Propagation Delay
CON
ns
EXPD
M41ST85W
t
SDA and SCL Fall Time
Data Hold Time
300
ns
F
t
t
0
µs
HD:DAT
HD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
t
Clock High Period
Clock Low Period
600
1.3
ns
µs
ns
ns
HIGH
t
LOW
t
SDA and SCL Rise Time
Data Setup Time
300
R
(1)
100
600
600
t
SU:DAT
START Condition Setup Time
(only relevant for a repeated start condition)
t
ns
ns
SU:STA
t
STOP Condition Setup Time
SU:STO
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
10/32
M41ST85Y, M41ST85W
Read Mode
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
10, page 12) and again after it has received the
word address and each data byte.
In this mode the master reads the M41ST85Y/W
slave after setting the slave address (see Figure
10, page 12). Following the write mode control bit
(R/W=0) and the acknowledge bit, the word ad-
dress ‘An’ is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ mode control bit
(R/W=1). At this point the master transmitter be-
comes the master receiver.
Battery Low Warning
The M41ST85Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up
sequence, this indicates that the battery is below
approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
The data byte which was addressed will be trans-
mitted and the master receiver will send an ac-
knowledge bit to the slave transmitter. The
address pointer is only incremented on reception
of an acknowledge bit. The M41ST85Y/W slave
transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and
acknowledges the new byte and the address
pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 11,
page 12).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a RAM address.
An alternate READ mode may also be implement-
ed whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 12, page 12).
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
is
CC
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
may be replaced while V
device.
is applied to the
CC
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
Write Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 13, page 13. Following the
START condition and slave address, a logic ‘0’ (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
The M41ST85Y/W only monitors the battery when
a nominal V isapplied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
11/32
M41ST85Y, M41ST85W
Figure 10. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
Figure 11. Read Mode Sequences
BUS ACTIVITY:
MASTER
WORD
ADDRESS (n)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
Figure 12. Alternate Read Mode Sequences
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
12/32
M41ST85Y, M41ST85W
Figure 13. Write Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (n)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
13/32
M41ST85Y, M41ST85W
CLOCK OPERATION
The eight byte clock register (see Table 3, page
15) is used to both set the clock and to read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the firstfour registers. Bits D6 and D7 of clock reg-
ister 3 (Century/Hours Register) contain the CEN-
TURY ENABLE Bit (CEB) and the CENTURY Bit
(CB). Setting CEB to a ‘1’ will cause CB to toggle,
either from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of
the century (depending upon its initial state). If
CEB is set to a ‘0’, CB will not toggle. Bits D0
through D2 of register 4 contain the Day (day of
week). Registers 5, 6 and 7 contain the Date (day
of month), Month and Years. The ninth clock reg-
ister is the ControlRegister (this is described in the
Clock Calibration section). Bit D7 of register 1 con-
tains the STOP Bit (ST). Setting this bit to a ‘1’ will
cause the oscillator to stop. If the device is
expected to spend a significant amount of time on
the shelf, the oscillator may be stopped to reduce
current drain. When reset to a ‘0’ the oscillator
restarts within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed
independently. Provision has been made to
assure that a clock update does not occur while
any of the seven clock addresses are being read.
If a clock address is being read, an update of the
clock registers will be halted. This will prevent a
transition of data during the read.
Note: Upon power-up following a power failure,
the HT bit will automatically be set to a ‘1’. This will
prevent the clock from updating the TIMEKEEPER
registers, and will allow the user to read the exact
time of the power-down event. Resetting the HT bit
to a ‘0’ will allow the clock to update the TIME-
KEEPER registers with the current time.
forcing E
volts of the V
long as V remains at an out-of tolerance condi-
tion. When V
Switchover Voltage (V ), power input is switched
from the V pin to the SNAPHAT battery and the
clock registers and external SRAM are maintained
from the attached battery supply.
All outputs become high impedance. The V
is capable of supplying 100 µA of current to the
attached memory with less than 0.3 volts drop
under this condition. On power up, when V
returns to a nominal value, write protection contin-
to a high level. This level is within 0.2
CON
. E
will remain at this level as
BAT
CON
CC
falls below the Battery Back-up
CC
SO
CC
pin
OUT
CC
ues for t by inhibiting E . The RST signal
REC
CON
also remains active during this time (see Figure
21, page 26).
Note: Most low power SRAMs on the market
today can be used with the M41ST85Y/W RTC
SUPERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all
other inputs to the SRAM. This allows inputs to the
M41ST85Y/W and SRAMs to be Don’t Care once
V
fallsbelow V
(min). The SRAM should also
PFD
CC
guarantee data retention down to V =2.0 volts.
CC
The chip enable access time must be sufficient to
meet the system needs with the chip enable output
propagation delays included. If the SRAM includes
a second chip enable pin (E2), this pin should be
tied to V
.
OUT
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
Data Retention Mode
With valid V applied, the M41ST85Y/W can be
CC
the SRAMs can then be added to the I
value of
BAT
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M41ST85Y/W will automatically deselect, write
protecting itself (and any external SRAM) when
the M41ST85Y/W to determine the total current
requirements for data retention. The available bat-
tery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 18,
page 30).
V
falls between V
(max) and V
(min).
CC
PFD
PFD
This is accomplished by internally inhibiting
access to the clock registers. At this time, the
Reset pin (RST) is driven active and will remain
For afurther more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
active until V returns to nominal levels. External
CC
RAM access is inhibited in a similar manner by
14/32
M41ST85Y, M41ST85W
TIMEKEEPER Registers
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Square
Wave Registers store data in Binary Format.
The M41ST85Y/W offers 20 internal registers
which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
TM
referred to as BiPORT
TIMEKEEPER cells).
Table 3. TIMEKEEPER Register Map
Address
Data
Function/Range
BCD Format
D7
D6
0.1 Seconds
10 Seconds
D5
D4
D3
D2
D1
D0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
0.01 Seconds
Seconds
Seconds
Seconds
Minutes
Century/Hour
Day
00-99
00-59
00-59
0-1/00-23
01-7
ST
0
10 Minutes
Minutes
CEB
0
CB
0
10 Hours
Hours (24 Hour Format)
Day of Week
Date: Day of Month
Month
0
0
0
0
0
10 Date
Date
01-31
01-12
00-99
0
0
0
10M
Month
10 Years
Year
Year
OUT
WDS
AFE
FT
S
Calibration
Control
Watchdog
Al Month
Al Date
Al Hour
Al Min
BMB4 BMB3 BMB2 BMB1 BMB0
RB1
RB0
SQWE
ABE
AI 10 Date
AI 10 Hour
Al 10M
Alarm Month
Alarm Date
01-12
01-31
00-23
00-59
00-59
RPT4 RPT5
RPT3
RPT2
RPT1
WDF
0
HT
Alarm Hour
Alarm 10 Minutes
Alarm 10 Seconds
Alarm Minutes
Alarm Seconds
Al Sec
AF
0
0
BL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
0
0
0
0
Reserved
Reserved
Reserved
SQW
0
0
0
0
0
0
RS3
RS2
RS1
RS0
Keys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag
0 = Must be set to zero
BL = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
AF = Alarm flag
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
15/32
M41ST85Y, M41ST85W
Setting Alarm Clock Registers
tion activates the IRQ/FT/OUT pin. To disable
alarm, write ‘0’ to the Alarm Date Register and to
RPT5–RPT1. The IRQ/FT/OUT output is cleared
by a read to the Flags register. This read of the
Flags register will also reset the Alarm Flag (D6;
Register 0Fh).
Address locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41ST85Y/W is in the
battery back-up to serve as a system wake-up call.
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarmin Bat-
tery Back-up Mode Enable) and AFE are set. The
ABE and AFE bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST85Y/W was in the de-
select mode during power-up. Figure 14, page 16
illustrates the back-up mode alarm timing.
Bits RPT5–RPT1 put the alarm in the repeat mode
of operation. Table 4, page 17 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
Figure 14. Back-Up Mode Alarm Waveform
V
V
CC
PFD
V
SO
tREC
AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
16/32
M41ST85Y, M41ST85W
Figure 15. Alarm Interrupt Reset Waveforms
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT
AI03664
Table 4. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per Month
Once per Year
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds). If the processor does not
reset the timer within the specified period, the
M41ST85Y/W sets the WDF (Watchdog Flag) and
generates a watchdog interrupt or a microproces-
sor reset.
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a write of the Watch-
dog Register. The time-out period then starts over.
Note: The WDI pin should be tied to V if not
SS
used.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be writ-
ten into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
Note: If the Square Wave function is enabled, the
accuracy of the Watchdog Timer will be a function
of the selected resolution.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ‘0’, the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a ‘1’, the
watchdog will output a negative pulse on the RST
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the frequency test func-
tion is activated, the watchdog function prevails
and the frequency test function is denied. The
OUT function has the lowest priority and will only
be enabled when the Watchdog Register (09h),
AFE Bit and FT Bit are ‘0.’
pin for t
. The Watchdog register, FT, AFE, ABE
REC
and SQWE Bits will reset to a ‘0’ at the end of a
Watchdog time-out when the WDS bit is set to a
‘1’.
17/32
M41ST85Y, M41ST85W
Square Wave Output
The M41ST85Y/W offers the user a programma-
ble square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish
the square wave output frequency. These fre-
quencies are listed in Table 5. Once the selection
of the SQW frequency has been completed, the
SQW pin can be turned on and off under software
control with the Square Wave Enable Bit (SQWE)
located in Register 0Ah.
Table 5. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
0
RS2
0
RS1
0
RS0
0
Frequency
None
32.768
8.192
4.096
2.048
1.024
512
256
128
64
Units
–
0
0
0
1
kHz
kHz
kHz
kHz
kHz
Hz
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Hz
1
0
0
0
Hz
1
0
0
1
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
18/32
M41ST85Y, M41ST85W
Power-on Reset
Reset Inputs (RSTIN1 & RSTIN2)
The M41ST85Y/W continuously monitors V
.
The M41ST85Y/W provides two independent in-
puts which can generate an output reset. The du-
ration and function of these resets is identical to a
reset generated by a power cycle. Table 6 and Fig-
ure 16 illustrate the AC reset characteristics of this
CC
When V
falls to the power fail detect trip point,
CC
the RST pulls low (open drain) and remains low on
power-up for t after V passes V . The
REC
CC
PFD
RST pin is an open drain output and an appropri-
ate pull-up resistor should be chosen to control
rise time.
function. Pulses shorter than t and t will not
R1
R2
generate a reset condition. RSTIN1 and RSTIN2
are each internally pulled up to V
100kΩ resistor.
through a
CC
Figure 16. RSTIN1 & RSTIN2 Timing Waveforms
RSTIN1
tR1
RSTIN2
tR2
RST (1)
tR1HRH
tR2HRH
Note: 1. With pull-up resistor
AI03665
Table 6. Reset AC Characteristics
Symbol
Parameter
Min
Max
Unit
(1)
RSTIN1 Low to RSTIN1 High
200
ns
t
t
R1
R2
(2)
RSTIN2 Low to RSTIN2 High
RSTIN1 High to RST High
RSTIN2 High to RST High
100
40
ms
ms
ms
(3)
(3)
200
200
t
R1HRH
40
t
R2HRH
Note: 1. Pulse width less than 50ns will result in no RESET (for noise immunity).
2. Pulse width less than 20ms will result in no RESET (for noise immunity).
3. C = 5pF (see Figure 19, page 23).
L
19/32
M41ST85Y, M41ST85W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (independent from the
128 or lengthened by 256 oscillator cycles. If a bi-
nary ‘1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
V
comparator). If PFI is less than the power-fail
PFD
threshold (V ), the Power-Fail Output (PFO) will
PFI
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 4, page 6) to either the
unregulated DC input (if it is available) or the reg-
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
ulated output of the V regulator. The voltage di-
CC
vider can be set up such that the voltage at PFI
falls below V
several milliseconds before the
PFI
regulated V input to the M41ST85Y/W orthe mi-
CC
croprocessor drops below the minimum operating
voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
Two methods are available for ascertaining how
much calibration a given M41ST85Y/W may re-
quire.
curs after V drops below V
(min). When pow-
CC
PFD
er returns, PFO is forced high, irrespective of V
PFI
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that ac-
cesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop bit (ST, D7 of 1h) is ‘0’,the Frequen-
cy Test bit (FT, D6 of 8h) is ‘1’, the Alarm Flag En-
able bit (AFE, D7 of Ah) is ‘0’, and the Watchdog
Steering bit (WDS, D7 of 9h) is ‘1’ or the Watchdog
Register (9h=0) is reset.
for the write protect time (t
), which is the time
REC
from V (max) until the inputs are recognized. At
PFD
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to V and PFO
SS
left unconnected.
Calibrating the Clock
The M41ST85Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not exceed +/–35 PPM
(parts per million) oscillator frequency error at
o
25 C, which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than +1/–2
PPM at 25°C.
The oscillation rate of crystals changes with tem-
perature (see Figure 17, page 21). Therefore, the
M41ST85Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure 18, page 21.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ‘1’ indi-
cates positive calibration, ‘0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor to V for proper
CC
operation. A 500 to10k resistor is recommended in
order to control the rise time. The FT bit is cleared
on power-down.
20/32
M41ST85Y, M41ST85W
Output Driver Pin
Initial Power-on Defaults
When the FT bit, AFE bit and watchdog register
are not set, the IRQ/FT/OUT pin becomes an out-
put driver that reflects the contents of D7 of the
Control Register. In other words, when D6 of loca-
tion 08h is a ‘0’, D7 of location 08h and 0Ah and
the watchdog register are a ‘0’ then the IRQ/FT/
OUT pin will be driven low.
Upon initial application of power to the device, the
following register bits are set to a ‘0’ state: Watch-
dog Register; FT; AFE; ABE and SQWE. The fol-
lowing bits are set to a‘1’ state: ST; OUT; and HT.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a “1” will cause CB to tog-
gle, either from a “0” to “1” or from “1” to “0” at the
turn of the century (depending upon its initial
state). If CEB is set to a “0”, CB will not toggle.
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Figure 17. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
= -0.038
(T - T0)2 ± 10%
∆F
F
ppm
–100
–120
C2
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 18. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
21/32
M41ST85Y, M41ST85W
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
SNAPHAT
SOIC
–40 to 85
–55 to 125
Storage Temperature (V
Off)
Off,Oscillator
CC
T
STG
°C
(1)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
260
°C
T
SLD
–0.3 to V +0.3
CC
V
V
V
IO
M41ST85Y
M41ST85W
–0.3 to 7
V
Supply Voltage
CC
–0.3 to 4.6
V
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
22/32
M41ST85Y, M41ST85W
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 8. DC and AC Measurement Conditions
Parameter
M41ST85Y
4.5 to 5.5V
–40 to 85°C
100pF
M41ST85W
2.7 to 3.6V
–40 to 85°C
50pF
V
Supply Voltage
CC
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
≤ 50ns
0.2 to 0.8V
0.2 to 0.8V
CC
CC
CC
CC
0.3 to 0.7V
0.3 to 0.7V
Input and Output Timing Ref. Voltages
Note: Output High Z is defined as the point where data is no longer driven (see Table 11, page 25).
Figure 19. AC Testing Load Circuit
Figure 20. AC Testing Input/Output Waveforms
645Ω
DEVICE
UNDER
TEST
0.8V
CC
0.7V
CC
(1)
C =100pF
L
1.75V
0.3V
CC
0.2V
CC
or 50pF
AI02568
C
includes JIG capacitance
L
AI03916
Note: 1. C = 100pF for the M41ST85Y, 50pF for the M41ST85W
L
Table 9. Capacitance
Symbol
Parameter
Min
Max
7
Unit
pF
C
IN
Input Capacitance
Output Capacitance
(1)
10
pF
C
OUT
t
Low-pass filter input time constant (SDA and SCL)
50
ns
LP
Note: Effective capacitance measured with power supply at 5V. Outputs are deselected.
1. Sampled only, not 100% tested.
23/32
M41ST85Y, M41ST85W
Table 10. DC Characteristics
Symb.
Parameter
Battery Current OSC ON
Battery Current OSC OFF
Test Condition
Min
Typ
400
50
Max
Unit
nA
500
T = 25°C, V
= 0V,
A
CC
= 3V
(6)
I
BAT
V
BAT
nA
M41ST85Y
M41ST85W
M41ST85Y
M41ST85W
1.4
750
1
mA
µA
I
Supply Current
f = 400kHz
CC1
mA
µA
SCL, SDA = V
– 0.3V
I
Supply Current (Standby)
CC
CC2
500
±1
25
0V ≤ V ≤ V
Input Leakage Current
µA
IN
CC
(1,2)
I
LI
0V ≤ V ≤ V
Input Leakage Current (PFI)
–25
2
nA
IN
CC
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
±1
µA
I
OUT
LO
M41ST85Y
M41ST85W
175
100
100
mA
mA
µA
V
(5)
V
Current (Active)
V
> V
CC
– 0.3V
– 0.3V
OUT1
I
OUT
OUT1
I
V
OUT
Current (Battery Back-up)
V
> V
OUT2
OUT2 BAT
V
0.7V
V
+ 0.3
Input High Voltage
Input Low Voltage
Battery Voltage
IH
CC
CC
0.3V
V
–0.3
V
IL
CC
V
3.0
2.9
V
V
BAT
V
I
= –1.0mA
OH
Output High Voltage
2.4
2.5
OH
(4)
V
OH
(Battery Back-up)
I
= –1.0µA
OUT2
3.6
0.4
0.4
V
V
V
V
OHB
I
= 3.0mA
= 10mA
OL
Output Low Voltage
OL
V
OL
(3)
I
Output Low Voltage (Open Drain)
M41ST85Y
M41ST85W
4.30
2.60
4.40
2.65
1.250
2.5
4.50
2.70
V
V
V
V
V
Power Fail Deselect
PFD
V
PFI Input Threshold
1.225
1.275
PFI
SO
V
Battery Back-up Switchover
Note: 1. Outputs Deselected.
2. RSTIN1 and RSTIN2 internally pulled-up to V through 100KΩ resistor. WDI internally pulled-down to V through 100KΩ resistor.
CC
SS
3. For IRQ/FT/OUT, RST pins (Open Drain).
4. Conditioned output (E
duce battery life.
) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will re-
CON
5. External SRAM must match RTC SUPERVISOR chip V
specification.
CC
6. Measured with V
and E
open.
CON
OUT
24/32
M41ST85Y, M41ST85W
Table 11. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.5 to 5.5V
or
3.0 to 3.6V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
OUT
Read
Active
IL
V
Read
High Z
High Z
High Z
Active
IH
(1)
Deselect
X
X
X
CMOS Standby
V
to V
(min)
PFD
SO
(1)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V .
IH
IL
7. See Table 10, page 24 for details.
Table 12. Crystal Electrical Characteristics
Symbol
Parameter
Typ
Min
Max
Unit
kHz
kΩ
f
Resonant Frequency
32.768
0
R
Series Resistance
Load Capacitance
60
S
(1)
12.5
pF
C
L
Note: These are externally supplied
1. Load capacitors are integrated within the M41ST85Y/W. Circuit board layout considerations for the 32.768 kHz crystal of minimum
trace lengths and isolation from RF generating signals should be taken into account.
ST Microelectronics recommends the KDS DT-38 Tuning Fork Type (thru-hole) or DMX-26 (SMD) quartz crystal for industrial tem-
perature operations.
KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.
25/32
M41ST85Y, M41ST85W
Figure 21. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
PFO
tDR
tREC
RECOGNIZED
RECOGNIZED
INPUTS
RST
DON’T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
E
CON
AI03661
Table 13. Power Down/Up AC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
V
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
CC
F
(2)
V
Fall Time
10
0
µs
µs
µs
µs
µs
ms
t
SS CC
FB
t
EX at V before Power Down
PD
IH
t
PFI to PFO Propagation Delay
15
25
PFD
t
V
V
(min) to V
(max) V
Rise Time
CC
10
1
R
PFD
SS
PFD
t
to V (min) V Rise Time
PFD CC
RB
t
Power up Deselect Time
40
200
REC
Note: 1. V
(max) to V (min) fall time of less than t may result in deselection/write protection not occurring until
PFD F
PFD
200µs after V passes V
(min).
CC
PFD
2. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SS FB
26/32
M41ST85Y, M41ST85W
PACKAGE MECHANICAL
Figure 22. SOH28 - 28 lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 14. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
27/32
M41ST85Y, M41ST85W
Figure 23. SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Min
Max
A
A1
A2
A3
B
0.3850
0.2850
0.2752
0.0150
0.0220
0.8598
0.5902
0.6280
0.1421
0.0902
6.73
6.48
0.2650
0.2551
0.46
21.21
14.22
15.55
3.20
0.0181
0.8350
0.5598
0.6122
0.1260
0.0799
D
E
eA
eB
L
2.03
28/32
M41ST85Y, M41ST85W
Figure 24. SH - SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH - SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
10.54
7.24
Typ
Min
Max
A
A1
A2
A3
B
0.4150
0.2850
0.2752
0.0150
0.0220
0.8598
0.5902
0.6280
0.1421
0.0902
6.73
6.48
0.2650
0.2551
6.99
0.38
0.46
21.21
14.22
15.55
3.20
0.56
0.0181
0.8350
0.5598
0.6122
0.1260
0.0799
D
21.84
14.99
15.95
3.61
E
eA
eB
L
2.03
2.29
29/32
M41ST85Y, M41ST85W
PART NUMBERING
Table 17. Ordering Information Scheme
Example:
M41ST
85Y
–70
MH
6
TR
Device Type
M41ST
Supply Voltage and Write Protect Voltage
85Y = V
= 4.5 to 5.5V; V
= 4.3 to 4.5V
= 2.6 to 2.7V
CC
PFD
85W = V
= 2.7 to 3.6V; V
PFD
CC
Speed
–70 = 70ns
–85 = 85ns
Package
(1)
MH = SO28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package ”M4TXX-BR12SH” in conductive foam since will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 18. SNAPHAT Battery Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Package
SH
Lithium Battery (48mAh) and Crystal SNAPHAT
Lithium Battery (120mAh) and Crystal SNAPHAT
SH
30/32
M41ST85Y, M41ST85W
REVISION HISTORY
Table 19. Document Revision History
Date
Revision Details
August 2000
08/24/00
First issue
Block Diagram added (Figure 3)
10/12/00
t
Tableremoved, cross references corrected
REC
12/18/00
Reformatted, TOC added, and PFI Input Leakage Current added (Table 10)
31/32
M41ST85Y, M41ST85W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
32/32
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