M41T81MQ6 [STMICROELECTRONICS]
1 TIMER(S), REAL TIME CLOCK, PDSO16, PLASTIC, SOIC-16;
| 型号： | M41T81MQ6 |
| 厂家： | 
ST |
| 描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO16, PLASTIC, SOIC-16 时钟 光电二极管 外围集成电路 |
| 文件： | 总28页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41T81
512 Bit (64 bit x 8)
SERIAL ACCESS RTC SRAM with ALARMS
PRELIMINARY DATA
FEATURES SUMMARY
■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE
Figure 1. Packages
■ COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
16
1
■ AUTOMATIC SWITCH-OVER and DESELECT
SO16 (MQ)
CIRCUITRY
2
■ SERIAL INTERFACE SUPPORTS I C BUS
SNAPHAT (SH)
Battery & Crystal
(400KHz PROTOCOL)
■ 44 BYTES OF GENERAL PURPOSE RAM
■ PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
■ WATCHDOG TIMER
■ LOW OPERATING CURRENT OF 400µA
28
■ OPERATING TEMPERATURE OF –40 TO
1
85°C
SO28 (MH)
■ ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA
March 2001
1/28
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M41T81
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
16-pin SOIC Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
28-pin SOIC Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Measurement I/O Waveform (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Bus Data Transfer Sequence (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledgement Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Timing Requirements Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slave Address Location (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Mode Sequence (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alternative Read Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up Mode AC Waveforms (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up Trip Points DC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/28
M41T81
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER® Register Map (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Alarm Interrupt Reset Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Alarm Repeat Modes (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Back-up Mode Alarm Waveform (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Square Wave Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square Wave Output Frequency (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crystal Accuracy Across Temperature (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Calibration (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SNAPHAT Battery/Crystal Table (Table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/28
M41T81
SUMMARY DESCRIPTION
The M41T81 Serial Access TIMEKEEPER SRAM
is a low power 512 bit static CMOS SRAM orga-
nized as 64 words by 8 bits. A built-in 32.768 KHz
oscillator (external crystal controlled) and 8 bytes
of the SRAM (see Table 10, page 16) are used for
the clock/calendar function and are configured in
binary coded decimal (BCD) format. An additional
12 bytes of RAM provide status/control of Alarm,
Watchdog and Square Wave functions. Address-
es and data are transferred serially via a two line,
clock address location controls user access to the
clock information and also stores the clock soft-
ware calibration setting.
The M41T81 is supplied in either a 28 lead SOIC
SNAPHAT package (which integrates both crystal
and battery in a single SNAPHAT top) or a 16 pin
SOIC. The 28 pin 330mil SOIC provides sockets
with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
2
bi-directional I C interface. The built-in address
register is incremented automatically after each
write or read data byte.
The M41T81 has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button supply when a power failure
occurs. Functions available to the user include a
non-volatile, time-of-day clock/calendar, Alarm in-
terrupts, Watchdog Timer and programmable
Square Wave output. The eight clock address lo-
cations contain the century, year, month, date,
day, hour, minute, second and tenths/hundredths
of a second in 24 hour BCD format. Corrections
for 28, 29 (leap year - valid until year 2100), 30 and
31 day months are made automatically. The ninth
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is “M4TXX-BR12SH” (see Table 14, page 22).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Figure 2. Logic Diagram
Table 1. Signal Names
(1)
Oscillator Input
XI
(1)
V
V
CC BAT
(1)
Oscillator Output
XO
Interrupt / Output Driver / Frequency
Test (Open Drain)
Square Wave (CMOS)
IRQ/OUT/
FT/SQW
(1)
(1)
XI
XO
SDA
Serial Data Input/Output
Serial Clock Input
M41T81
IRQ/FT/OUT/SQW
SCL
SDA
SCL
(1)
Battery Supply Voltage
V
BAT
V
Supply Voltage
Ground
CC
V
SS
V
SS
Note: 1. For SO16 package only
AI04613
Note: 1. For SO16 package only.
4/28
M41T81
Figure 3. 16-pin SOIC Connections
Figure 4. 28-pin SOIC Connections
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
NC
NC
NC
NC
CC
NC
IRQ/FT/OUT/SQW
V
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XI
XO
NC
NC
NC
NC
CC
NC
NC
NC
NC
NC
SCL
NC
NC
NC
SDA
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IRQ/FT/OUT/SQW
NC
NC
NC
SCL
SDA
M41T81
M41T81
9
V
BAT
10
11
12
13
14
V
SS
AI04614
V
SS
AI04615
Figure 5. Block Diagram
REAL TIME CLOCK
CALENDAR
SDA
SCL
44 BYTES
USER RAM
2
I C
INTERFACE
AF
RTC W/ALARM
& CALIBRATION
(1)
IRQ/FT/OUT
WDF
WATCHDOG
32KHz
OSCILLATOR
CRYSTAL
SQW
SQUARE WAVE
INTERNAL
POWER
V
CC
V
BAT
(2)
V
COMPARE
SO
V
= V
SO
PFD
WRITE PROTECT
COMPARE
Note 1. Open drain output
AI04616
Note 2. V
= V
– 0.5V (typ)
(SO)
(BAT)
5/28
M41T81
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Sym
Parameter
Value
Unit
°C
SNAPHAT
-40 to 85
-55 to 125
T
Storage Temperature (V Off, Oscillator Off)
STG
CC
SOIC
°C
(1)
SLD
Lead Solder Temperature for 10 Seconds
Input or Output Voltages
Output Current
260
°C
V
T
V
I
-0.3 to Vcc+0.3
IO
20
1
mA
W
O
P
D
Power Dissipation
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-Up Mode
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT socket.
6/28
M41T81
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
Unit
Supply Voltage (V
)
-0.3 to 7.0
-40 to 85
100
V
°C
pF
ns
V
CC
Ambient Operating Temperature (T )
A
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 50
0.2V to 0.8 V
CC
CC
CC
0.3V to 0.7 V
Input and Output Timing Ref. Voltages
V
CC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 6. AC Measurement I/O Waveform
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Table 4. Capacitance
Symbol
Parameter
Min
Max
Unit
C
Input Capacitance
Output Capacitance
7
pF
IN
(1)
10
50
pF
ns
C
OUT
t
Low-pass filter input time constant (SDA and SCL)
LP
Note: Effective capacitance measured with power supply at 5V . Sampled only, not 100% tested.
1. Outputs deselected.
7/28
M41T81
Table 5. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
Min
Typ
Max
±1
Unit
µA
µA
µA
µA
V
I
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
±1
I
Switch Freq = 400kHz
400
70
CC1
I
SCL,SDA = V -0.3V
Supply Current (standby)
Input Low Voltage
CC2
CC
V
IL
0.3V
CC
-0.3
V
IH
0.7V
V
CC
+ 0.8
Input High Voltage
V
CC
I
= 3.0mA
= 10mA
Output Low Voltage
0.4
0.4
V
OL
V
OL
Output Low Voltage (Open
Drain)
I
V
OL
(1)
(2)
I
= –1.0mA
Output High Voltage
2.4
2
V
V
V
OH
OH
(3)
Battery Supply Voltage
3
V
BAT
3.5
T = 25°C, V = 0V
A
CC
I
Battery Supply Current
0.8
1
µA
BAT
Oscillator ON, V
= 3V
BAT
Note: 1. For SQW output (only).
2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
3. For rechargeable back-up, V (max) may be considered V – 0.5V.
BAT
CC
Table 6. Crystal Electrical Characteristics
Sym
Parameter
Min
Typ
Max
Units
kHz
kΩ
f
Resonant Frequency
Series Resistance
Load Capacitance
32.768
O
R
60
S
C
12.5
pF
L
Note: Externally supplied if using the SO16 package.
Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
STMicroelectronics recommends the KDS DT-38 Tuning Fork Type (thru-hole) or DMX-26 (SMD) quartz crystal for industrial temper-
ature conditions.
KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.
All SNAPHAT battery/crystal tops meet these specifications.
8/28
M41T81
OPERATION
The M41T81 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 64 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
The M41T81 clock continually monitors Vcc for an
out-of tolerance condition. Should Vcc fall below
V
, the device terminates an access in progress
SO
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. The de-
vice also automatically switches over to the battery
and powers down into an ultra low current mode of
operation to conserve battery life. As system pow-
er returns and Vcc rises above Vso, the battery is
disconnected, and the power supply is switched to
external Vcc.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different IC’s. It consists of two lines: a bi-direc-
tional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
9/28
M41T81
Figure 7. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CHANGE OF
STOP
CONDITION
DATA ALLOWED
CONDITION
AI00587
Figure 8. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
10/28
M41T81
Figure 9. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Table 7. AC Characteristics
Sym
Parameter
Min
0
Typ
Max
Units
kHz
µs
f
SCL Clock Frequency
Clock Low Period
Clock High Period
400
SCL
t
1.3
600
LOW
t
ns
HIGH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time
300
300
ns
R
t
ns
F
t
600
600
ns
ns
HD:STA
(after this period the first clock pulse is generated)
START Condition Setup Time
(only relevant for a repeated start condition)
t
SU:STA
(1)
Data Setup Time
100
0
ns
µs
ns
t
SU:DAT
t
Data Hold Time
HD:DAT
t
STOP Condition Setup Time
600
SU:STO
Time the bus must be free before a new
transmission can start
t
1.3
µs
BUF
11/28
M41T81
Read Mode
In this mode the master reads the M41T81 slave
after setting the slave address (see Figure 11,
page 13). Following the write mode control bit (R/
W=0) and the acknowledge bit, the word address
‘An’ is written to the on-chip address pointer. Next
the START condition and slave address are re-
peated followed by the READ mode control bit (R/
W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only incre-
mented on reception of an acknowledge bit. The
M41T81 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
ther due to a Stop Condition or when the pointer
increments to a RAM address.
An alternate READ mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 12, page 13).
Write Mode
In this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 13, page 13. Following the START con-
dition and slave address, a logic ‘0’ (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The
data word to be written to the memory is strobed in
next and the internal address pointer is increment-
ed to the next memory location within the RAM on
the reception of an acknowledge clock. The
M41T81 slave receiver will send an acknowledge
clock to the master transmitter after it has received
the slave address (see Figure 8, page 10) and
again after it has received the word address and
each data byte.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
Figure 10. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
12/28
M41T81
Figure 11. Read Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (n)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
Figure 12. Alternative Read Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
Figure 13. Write Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (n)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
13/28
M41T81
Data Retention Mode
With valid V
applied, the M41T81 can be ac-
from the V
pin to the battery and the clock reg-
CC
CC
cessed as described above with read or write cy-
cles. Should the supply voltage decay, the
M41T81 will automatically deselect, write protect-
isters and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power
up, when Vcc returns to a nominal value, write pro-
tection continues for t
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
ing itself when Vcc falls between V
(max) and
PFD
V
(min). This is accomplished by internally in-
PFD
.
REC
hibiting access to the clock registers and SRAM.
When Vcc falls below the Battery Back-up
Switchover Voltage (V ), power input is switched
SO
Figure 14. Power Down/Up Mode AC Waveforms
V
CC
V
SO
tPD
tREC
SDA
SCL
DON'T CARE
AI00596
Table 8. Power Down/Up AC Characteristics
Symbol
Parameter
Min
0
Typ
Max
Unit
nS
t
SCL and SDA at V before Power Down
PD
IH
t
SCL and SDA at V after Power Up
10
µS
REC
IH
Note: V fall time should not exceed 5mV/µs.
CC
Table 9. Power Down/Up Trip Points DC Characteristics
Sym
Parameter
Min
Typ
– 0.50
Max
V – 0.20
BAT
Unit
(1)
V
– 0.70
V
Battery Back-up Switchover Voltage
V
V
SO
BAT
BAT
Note: All voltages referenced to V
.
SS
1. Switch-over and deselect point
14/28
M41T81
CLOCK OPERATION
The twenty byte clock register (see Table 10, page
16) is used to both set the clock and to read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers. Bits D6 and D7 of clock
register 3 (Century/Hours Register) contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a ‘1’ will cause CB to tog-
gle, either from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn
of the century (depending upon its initial state). If
CEB is set to a ‘0’, CB will not toggle. Bits D0
through D2 of register 4 contain the Day (day of
week). Registers 5, 6 and 7 contain the Date (day
of month), Month and Years. The ninth clock reg-
ister is the Control Register (this is described in the
Clock Calibration section). Bit D7 of register 1
contains the STOP Bit (ST). Setting this bit to a ‘1’
will cause the oscillator to stop. If the device is ex-
pected to spend a significant amount of time on
the shelf, the oscillator may be stopped to reduce
current drain. When reset to a ‘0’ the oscillator re-
starts within one second.
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be halted. This will prevent a transition
of data during the read.
Note: Upon power-up following a power failure,
the HT bit will automatically be set to a ‘1’. This will
prevent the clock from updating the TIMEKEEPER
registers, and will allow the user to read the exact
time of the power-down event. Resetting the HT
bit to a ‘0’ will allow the clock to update the TIME-
KEEPER registers with the current time.
TIMEKEEPER® Registers
The M41T81 offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flag, Square
Wave and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
TM
referred to as BiPORT
TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Square
Wave Registers store data in Binary Format.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
15/28
M41T81
Table 10. TIMEKEEPER® Register Map
Addr
Function/Range
BCD Format
D7
D6
0.1 Seconds
10 Seconds
10 Minutes
D5
D4
D3
D2
D1
D0
00h
01h
02h
0.01 Seconds
Seconds
Seconds
Seconds
Minutes
00-99
00-59
00-59
ST
0
Minutes
Century/ 0-1/00-
03h
CEB
CB
10 Hours
Hours (24 Hour Format)
Hour
23
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
0
0
0
0
0
0
0
0
0
Day of Week
Date: Day of Month
Month
Day
01-7
10 Date
Date
01-31
01-12
00-99
0
10M
Month
10 Years
Year
Year
OUT
0
FT
S
Calibration
Control
Watchdog
Al Month
Al Date
Al Hour
Al Min
BMB4
SQWE
RPT5
HT
BMB3
ABE
BMB2
BMB1
BMB0
RB1
RB0
AFE
RPT4
RPT3
RPT2
RPT1
WDF
0
Al 10M
Alarm Month
01-12
01-31
00-23
00-59
00-59
AI 10 Date
AI 10 Hour
Alarm Date
Alarm Hour
Alarm 10 Minutes
Alarm Minutes
Alarm Seconds
Alarm 10 Seconds
Al Sec
Flags
AF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
SQW
0
0
0
0
0
0
RS3
RS2
RS1
RS0
Keys:
AFE = Alarm Flag Enable Flag
S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
RB0-RB1 = Watchdog Resolution Bits
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag
0 = Must be set to zero
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
AF = Alarm flag
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
OUT = Output level
16/28
M41T81
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41T81 is in the bat-
tery back-up to serve as a system wake-up call.
tion activates the IRQ/FT/OUT/SQW pin. The
IRQ/FT/OUT/SQW output is cleared by a read to
the Flags register. This read of the Flags register
will also reset the Alarm Flag (D6; Register 0Fh).
The IRQ/FT/OUT/SQW pin can also be activated
in the battery back-up mode. The IRQ/FT/OUT/
SQW will go low if an alarm occurs and both ABE
(Alarm in Battery Back-up Mode Enable) and AFE
are set. The ABE and AFE bits are reset during
power-up, therefore an alarm generated during
power-up will only set AF. The user can read the
Flag Register at system boot-up to determine if an
alarm was generated while the M41T81 was in the
deselect mode during power-up. Figure 16, page
18 illustrates the back-up mode alarm timing.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 11, page 17 shows the possi-
ble configurations. Codes not listed in the table
default to the once per second mode to quickly
alert the user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
Figure 15. Alarm Interrupt Reset Waveforms
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT/SQW
AI04617
Table 11. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per Month
Once per Year
17/28
M41T81
Figure 16. Back-up Mode Alarm Waveform
V
V
CC
PFD
V
SO
tREC
AFE bit
AF bit in Flags Register
IRQ/FT/OUT/SQW
HIGH-Z
HIGH-Z
AI04618
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds). If the processor does not
reset the timer within the specified period, the
M41T81 sets the WDF (Watchdog Flag) and gen-
erates a watchdog interrupt.
The watchdog timer can be reset by having the mi-
croprocessor perform a write of the Watchdog
Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT/SQW pin. This
will also disable the watchdog function until it is
again programmed correctly. A read of the Flags
Register will reset the Watchdog Flag (Bit D7;
Register 0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set and the
frequency test function is activated, the watchdog
function prevails and the frequency test function is
denied.
Note: If the Square Wave function is enabled, the
accuracy of the Watchdog Timer will be a function
of the selected resolution.
18/28
M41T81
Square Wave Output
The M41T81 offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 bits located in 13h establish the
square wave output frequency. These frequen-
cies are listed in Table 12. Once the selection of
the SQW frequency has been completed, the IRQ/
FT/OUT/SQW pin can be turned on and off under
software control with the Square Wave Enable Bit
(SQWE) located in Register 0Ah.
Table 12. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
0
RS2
0
RS1
0
RS0
0
Frequency
None
32.768
8.192
4.096
2.048
1.024
512
Units
-
0
0
0
1
kHz
kHz
kHz
kHz
kHz
Hz
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
19/28
M41T81
Calibrating the Clock
The M41T81 is driven by a quartz controlled oscil-
lator with a nominal frequency of 32,768 Hz. The
devices are tested not exceed +/-35 PPM (parts
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that ac-
cesses the Calibration byte.
o
per million) oscillator frequency error at 25 C,
which equates to about +/-1.53 minutes per month
(see Figure 17, page 21). When the Calibration
circuit is properly employed, accuracy improves to
better than +1/-2 PPM at 25°C.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT/SQW pin. The pin will toggle at
512Hz, when the Stop bit (ST, D7 of 1h) is ‘0’,the
Frequency Test bit (FT, D6 of 8h) is ‘1’, the Alarm
Flag Enable bit (AFE, D7 of Ah) is ‘0’, and the
Square Wave Enable Bit (SQWE, D6 of 0Ah) is 0
and the Watchdog Register (9h=0) is reset.
The oscillation rate of crystals changes with tem-
perature. The M41T81 design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 18,
page 21. The number of times pulses which are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 8h. These bits
can be set to represent any value between 0 and
31 in binary form. Bit D5 is a Sign bit; ‘1’ indicates
positive calibration, ‘0’ indicates negative calibra-
tion. Calibration occurs within a 64 minute cycle.
The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128
or lengthened by 256 oscillator cycles. If a binary
‘1’ is loaded into the register, only the first 2 min-
utes in the 64 minute cycle will be modified; if a bi-
nary 6 is loaded, the first 12 will be affected, and
so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or -2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or -5.35 seconds per month which
corresponds to a total range of +5.5 or -2.75 min-
utes per month.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a -10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
The IRQ/FT/OUT/SQW pin is an open drain output
which requires a pull-up resistor to Vcc for proper
operation. A 500-10k resistor is recommended in
order to control the rise time. The FT bit is cleared
on power-down.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a “1” will cause CB to tog-
gle, either from a “0” to “1” or from “1” to “0” at the
turn of the century (depending upon its initial
state). If CEB is set to a “0”, CB will not toggle.
Output Driver Pin
When the FT bit, AFE bit, SQWE bit, and watch-
dog register are not set, the IRQ/FT/OUT/SQW pin
becomes an output driver that reflects the contents
of D7 of the Control Register. In other words, when
D7 (OUT Bit) and D6 (FT Bit) of address location
08h are a '0,' then the IRQ/FT/OUT/SQW pin will
be driven low.
Two methods are available for ascertaining how
much calibration a given M41T81 may require.
Note: The IRQ/FT/OUT/SQW pin is an open drain
which requires an external pull-up resistor (unless
the SQW function is enabled).
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number
of seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a ‘0’ state: Watch-
dog Register; AFE; ABE and SQWE. The follow-
ing bits are set to a ‘1’ state: ST; OUT; and HT.
20/28
M41T81
Figure 17. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
= -0.038
(T - T0)2 ± 10%
∆F
F
ppm
C2
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 18. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
21/28
M41T81
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M41T
81
MH
6
TR
Device Type
M41T
Supply Voltage and Write Protect Voltage
81 = V = 2.0 to 5.5V; V
= 2.7 to 2.8V
CC
PFD
Package
MQ = SO16
(1)
MH = SO28
Temperature Range
6 = –40°C to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT®) which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
Caution:Do NOT place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as this will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 14. SNAPHAT Battery/Crystal Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Package
SH
Lithium Battery (48mAh)/Crystal SNAPHAT
Lithium Battery (120mAh)/Crystal SNAPHAT
SH
22/28
M41T81
PACKAGE MECHANICAL INFORMATION
Figure 19. SO16 – 16-lead Plastic Small Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 15. SO16 – 16-lead Plastic Small Outline (150 mils body width), Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
1.75
0.25
1.60
0.46
0.25
10.00
4.00
–
Typ
Max
0.069
0.010
0.063
0.018
0.010
0.394
0.158
–
A
A1
A2
B
0.10
0.004
0.35
0.19
9.80
3.30
–
0.014
0.007
0.386
0.150
–
C
D
E
e
1.27
0.050
H
5.80
0.40
0°
6.20
1.27
8°
0.228
0.016
0°
0.244
0.050
8°
L
a
N
16
16
CP
0.10
0.004
23/28
M41T81
Figure 20. SO28 – 28-lead Plastic Small Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-B
Note: Drawing is not to scale.
Table 16. SO28 – 28-lead Plastic Small Outline, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Min
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
28
28
CP
0.10
0.004
24/28
M41T81
Figure 21. SH – 4-pin SNAPHAT Housing for 48 mAh Battery and Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 48 mAh Battery and Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
Typ
Max
0.385
0.285
0.275
0.015
0.022
0.860
0.590
A
A1
A2
A3
B
0
6.73
6.48
0.265
0.255
0
0.46
21.21
14.22
0.018
0.835
0.560
D
E
eA
eB
L
3.20
2.03
3.61
2.29
0.126
0.080
0.142
0.090
25/28
M41T81
Figure 22. SH – 4-pin SNAPHAT Housing for 120 mAh Battery and Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT Housing for 120 mAh Battery and Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
8.00
0.38
0.56
21.84
18.03
3.61
2.29
Typ
Max
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
A
A1
A2
A3
B
0
8.00
7.24
0.315
0.285
0
0.46
21.21
17.27
3.20
0.018
0.835
0.680
0.126
0.080
D
E
eB
L
2.03
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REVISION HISTORY
Table 19. Document Revision History
Date
Revision Details
October 2000
10/9/00
First Issue
Markups received October 6 entered
Reformatted
12/27/00
01/30/01
03/01/01
Correction of FEATURES SUMMARY, Supply Voltage (Table 13)
Text corrected in Watchdog, Output Driver pin sections
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M41T81
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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