M440T1MV [STMICROELECTRONICS]
3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER SRAM; 3.3V ， 32兆位（ 1024千位×32 ） TIMEKEEPER SRAM
| 型号： | M440T1MV |
| 厂家： | 
ST |
| 描述： | 3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER SRAM |
| 文件： | 总26页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M440T1MV
®
3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER SRAM
FEATURES SUMMARY
■
3.3V ± 10%
Figure 1. Package
■
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
■
■
■
PRECISION POWER MONITORING AND
POWER SWITCHING CIRCUITRY
AUTOMATIC WRITE-PROTECTION WHEN
M440T1MV
V
CC
IS OUT-OF-TOLERANCE
POWER-FAIL DESELECT VOLTAGE:
= 3.0 to 3.6V; 2.8V ≤ V ≤ 2.97V
–
V
CC
PFD
■
■
BATTERY LOW PIN (BL)
DUAL BATTERY SNAPHAT HOUSING IS
REPLACEABLE
®
■
85ns SRAM CHIP ENABLE ACCESS (70ns
ADDRESS ACCESS)
168-ball PBGA
Module
■
■
SLEEP MODE FUNCTION
150ns CLOCK ACCESS
October 2004
1/26
M440T1MV
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. PBGA Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. M440T1MV Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. M440T1MV PBGA Module Solution (Side/Top). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Memory Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Clock Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled. . . . . . 9
Figure 7. Memory READ Mode AC Waveforms, Address-Controlled. . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Clock READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled. . . . . . . 10
Figure 9. Clock READ Mode AC Waveforms, Address-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Memory/Clock READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled . . . . . . . . . . . . . . . . 11
Figure 11.Memory WRITE Mode AC Waveforms, Chip Enable-Controlled . . . . . . . . . . . . . . . . . . 12
Figure 12.Clock WRITE Mode AC Waveforms, WRITE Enable-Controlled . . . . . . . . . . . . . . . . . . 12
Figure 13.Clock WRITE Mode AC Waveforms, Chip Enable-Controlled. . . . . . . . . . . . . . . . . . . . . 13
Table 5. Memory/Clock WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reading and Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Watchdog Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Time of Day Alarm Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Battery Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/26
M440T1MV
Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.PBGA-ZA – 168-ball Plastic Ball Grid Array Package Outline . . . . . . . . . . . . . . . . . . . . 22
Table 14. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Mechanical Data . . . . . . . . . . . . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M440T1MV
SUMMARY DESCRIPTION
The M440T1MV TIMEKEEPER RAM is a 16Mbit,
®
The clock keeps track of tenths/hundredths of sec-
onds, seconds, minutes, hours, day, date, month,
and year information. The last day of the month is
automatically adjusted for months with less than
31 days, including leap year correction.
non-volatile static RAM organized as 1,024K by 32
bits and real time clock organized as 64 bytes by
8 bits. The special PBGA package provides a fully
integrated battery back-up memory and real time
clock solution. In the event of power instability or
absence, a self-contained battery maintains the
timekeeping operation and provides power for a
The clock operates in one of two formats:
–
–
a 12-hour mode with an AM/PM indicator; or
a 24-hour mode
CMOS static RAM. Control circuitry monitors V
CC
and invokes write protection to prevent data cor-
ruption in the memory and RTC.
The M440T1MV is in a 168-ball PBGA module that
integrates the RTC, the battery, and SRAM in one
package.
Figure 2. Logic Diagram
Table 1. Signal Names
A0 - A19
DQ0 - DQ31
DQC0 - DQC7
E1 - E4
EC
Address Inputs
NVRAM Data Input/Output
Clock Data Input/Output
NVRAM Chip Enable Inputs
Clock Chip Enable Input
NVRAM WRITE Enable Inputs
Clock WRITE Enable Input
Output Enable Input
V
CC
A0 – A19
DQ0 – DQ31
W1 - W4
WC
E1 – E4
DQC0 – DQC7
EC
BL
G
M440T1MV
W1 – W4
WC
GC
Clock Output Enable Input
IRQ
Battery Low Output (Open
Drain)
RSV1
RSV2
BL
G
IRQ
Interrupt Output (Open Drain)
Reserved
GC
RSV1
RSV2
NC
Reserved
V
SS
No Connect
AI04200
V
Supply Voltage
Ground
CC
V
SS
4/26
M440T1MV
Figure 3. PBGA Connections (Top View)
1
2
3
4
5
6
7
8
9
A15
A17
A13
A18
W1
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
E3
DQ31
DQ30
DQ29
W3
A16
A14
A12
A7
DQ28
DQ27
DQ24
DQ25
DQ26
M440T1MV
10
A6
11
12
13
14
15
A5
DQ16
DQ17
DQ18
DQ23
RSV1
DQ22
DQ21
DQ20
DQ19
DQ7
DQ6
DQ5
A19
DQ4
DQ0
DQ1
DQ2
16
17
18
19
AI04794
Note: This diagram is TOP VIEW perspective (view through package).
5/26
M440T1MV
Figure 4. M440T1MV Hardware Hookup
M48T224W
3.3V
V
OUTA
V
E
V
E
CC
1M x 8
CC
1M x 8
V
CC
6
SRAM
SRAM
A0-A5
E1
E2
CON
W
G
W
G
G
CON
G
W2
W1
EC
E
DQ0 - DQ7
INTB/INTB
DQC0 - DQC7
IRQ
W
WC
GC
E1
E2
E3
E4
G
E1
E2
E3
E4
BL
BL
V
OUTB
V
V
E
CC
CC
SLEEP
PAD
SLEEP
1M x 8
SRAM
1M x 8
SRAM
8kΩ
E3
E4
E
CON
G
W
G
W
V
THS
OUTA
CON
V
SS
G
W3
G
W4
AI04795
6/26
M440T1MV
Figure 5. M440T1MV PBGA Module Solution (Side/Top)
AI04628b
7/26
M440T1MV
OPERATION MODES
Memory READ Mode
Clock READ Mode
The M440T1MV is in the 32-bit READ Mode when-
ever W1 - W4 (WRITE Enable Byte 1 to 4) are high
and E1 - E4 - Chip Enable Bytes 1 to 4 are low
(see Table 2., page 8). The unique address spec-
ified by the 20 address inputs defines which one of
the 1,048,576 long words of data is to be access-
ed. Valid data will be available at the Data I/O pins
The clock is in the READ Mode whenever WC
(Clock WRITE Enable) is high and EC (Clock Chip
Enable) is low. The unique address specified by
the 6 Address Inputs defines which one of the 64
bytes of clock data is to be accessed. Valid data
will be available at the Data I/O pins (DQC0-7)
within Address Access Time (t
) after the last
AVQV
within Address Access Time (t
) after the last
AVQV
address input signal is stable, providing the EC
and GC access times are also satisfied. If the EC
and GC access times are not met, valid data will
be available after the latter of the Chip Enable Ac-
address input signal is stable, providing the E1-4
and G access times are also satisfied. If the E1-4
and G access times are not met, valid data will be
available after the latter of the Chip Enable Access
cess Times (t
) or Output Enable Access Time
ELQV
Times (t
) or Output Enable Access Time
ELQV
(t
GLQV
).
(t
).
GLQV
The state of the eight three-state Data I/O signals
is controlled by EC and G. If the outputs are acti-
The state of the thirty-two three-state Data I/O sig-
nals is controlled by E1-4 and G. If the outputs are
vated before t
, the data lines will be driven to
AVQV
activated before t
to an indeterminate state until t
, the data lines will be driven
an indeterminate state until t
Inputs are changed while EC and G remain active,
. If the Address
AVQV
AVQV
. If the Ad-
AVQV
dress Inputs are changed while E1-4 and G re-
main active, output data will remain valid for
output data will remain valid for Output Data Hold
Time (t
) but will go indeterminate until the
AXQX
Output Data Hold Time (t
) but will go indeter-
next Address Access. See section on Reading and
Setting the Clock under CLOCK OPERATION for
more details.
AXQX
minate until the next Address Access.
Table 2. Memory Operating Modes
DQ24- DQ16- DQ8- DQ0-
DQ31 DQ23 DQ15 DQ7
V
CC
Mode
E4 E3 E2 E1
G
W4 W3 W2 W1
Power
D
Byte WRITE
Byte WRITE
Byte WRITE
Byte WRITE
Byte WRITE
Byte WRITE
Byte WRITE
Byte WRITE
H
H
H
L
H
H
L
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
X
X
X
L
X
X
L
X
L
L
X
X
X
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Active
IN
D
Hi-Z Active
Hi-Z Active
Hi-Z Active
IN
D
H
H
X
L
X
X
H
L
Hi-Z
Hi-Z
Hi-Z
IN
D
H
X
X
L
X
H
H
L
Hi-Z
Hi-Z
Hi-Z
IN
D
X
X
X
L
H
H
H
L
Hi-Z
Hi-Z
Hi-Z
Active
IN
D
X
X
X
H
H
H
Hi-Z Active
Hi-Z Active
Hi-Z Active
IN
D
X
X
H
H
Hi-Z
Hi-Z
IN
D
X
H
Hi-Z
IN
2.97 to 3.6V
Long Word
WRITE
D
D
D
D
IN
L
L
L
L
H
L
L
L
L
Active
Active
IN
IN
IN
D
Byte READ
Byte READ
Byte READ
Byte READ
H
H
H
L
H
H
L
H
L
L
H
H
H
L
L
L
L
X
X
X
H
X
X
H
X
X
H
X
X
H
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
D
Hi-Z Active
Hi-Z Active
Hi-Z Active
OUT
Hi-Z
Hi-Z
D
H
H
OUT
D
H
Hi-Z
OUT
Long Word
READ
D
D
D
D
OUT
L
L
L
L
L
H
X
H
X
H
X
H
X
Active
Stdby
OUT
OUT
OUT
Deselect
H
H
H
H
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
V
to
SO
CMOS
Standby
Deselect
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(1)
V
(min)
PFD
Battery
(1)
Deselect
Hi-Z
Hi-Z Back-up
Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
1. See Table 12., page 20 for details.
8/26
M440T1MV
Table 3. Clock Operating Modes
V
Mode
Deselect
EC
GC
X
WC
DQC0 - 7
CC
V
IH
X
Hi-Z
V
V
D
WRITE
READ
READ
X
IL
IL
IN
2.97 to 3.6V
V
V
V
IH
D
OUT
IL
IL
V
V
IH
V
IH
Hi-Z
IL
V
to
SO
Deselect
X
X
X
X
X
Hi-Z
Hi-Z
(1)
V
(min)
PFD
(1)
Deselect
X
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
1. See Table 12., page 20 for details.
Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
tAVAV
A0-A19
E1 - E4
VALID
tAVQV
tELQV
tAXQX
tEHQZ
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ31
DATA OUT
AI05606
Figure 7. Memory READ Mode AC Waveforms, Address-Controlled
tAVAV
A0-A19
VALID
tAVQV
tAXQX
DQ0-DQ31
DATA VALID
DATA VALID
AI05607
9/26
M440T1MV
Figure 8. Clock READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
tAVAV
A0-A5
EC
VALID
tAVQV
tELQV
tAXQX
tEHQZ
tELQX
tGLQV
tGHQZ
GC
tGLQX
DQC0-DQC7
DATA OUT
AI04653
Figure 9. Clock READ Mode AC Waveforms, Address-Controlled
tAVAV
A0-A5
VALID
tAVQV
tAXQX
DQC0-DQC7
DATA VALID
DATA VALID
AI04654
Table 4. Memory/Clock READ Mode AC Characteristics
M440T1MV
Memory
–85
Clock
–15
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
t
READ Cycle Time
85
150
ns
ns
ns
ns
ns
ns
ns
RC
AVAV
t
t
t
t
Address Valid to Output Valid
70
85
45
150
150
70
ACC
AVQV
ELQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
CO
t
OE
GLQV
t
t
5
5
10
5
CEL
OEL
ELQX
GLQX
t
t
t
t
(2)
40
30
50
50
CEZ
t
EHQZ
(2)
Output Enable High to Output Hi-Z
ns
ns
OEZ
t
GHQZ
t
t
Address Transition to Output Transition
5
5
OH
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = –15 to 75°C; V = 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
10/26
M440T1MV
Memory WRITE Mode
Clock WRITE Mode
The M440T1MV is in the WRITE Mode whenever
any or all of W1-4 (WRITE Enable Byte 1 to 4) and
any corresponding E1-4 (Chip Enable Byte 1 to 4)
are in a low state after the address inputs are sta-
ble. Thus a Byte WRITE (8-bit), Word WRITE (16-
bit) or Long Word WRITE (32-bit) may be per-
formed. The start of a WRITE is referenced from
the latter occurring falling edge of W1-4 or E1-4. A
WRITE is terminated by the earlier rising edge of
W1-4 or E1-4. The addresses must be held valid
throughout the cycle. E1-4 or W1-4 must return
The clock is in the WRITE Mode whenever WC
(Clock WRITE Enable) and EC (Clock Chip En-
able) are in the low state after the address inputs
are stable. The start of a WRITE is referenced
from the latter occurring falling edge of WC or EC.
A WRITE is terminated by the earlier rising edge of
WC or EC. The addresses must be held valid
throughout the cycle. EC or WC must return high
for a minimum of t
from Chip Enable Clock or
EHAX
t
from WRITE Enable Clock prior to the initi-
WHAX
ation of another READ or WRITE cycle. Data-in
high for a minimum of t
from Chip Enable or
must be valid t prior to the end of WRITE and
EHAX
DVWH
t
from WRITE Enable prior to the initiation of
remain valid for t
afterward. GC should be
WHAX
WHDX
another READ or WRITE cycle. Data-in must be
valid t prior to the end of WRITE and remain
valid for t
kept high during WRITE cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on EC and GC a low on WC will
DVWH
afterward. G should be kept high
WHDX
during WRITE cycles to avoid bus contention; al-
though, if the output bus has been activated by a
low on E1-4 and G, a low on W1-4 will disable the
disable the outputs t
tion on Reading and Setting the Clock under
CLOCK OPERATION for more details.
after WC falls. See sec-
WLQZ
outputs t
after W1-4 falls.
WLQZ
Figure 10. Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled
tAVAV
A0-A19
E1 - E4
VALID
tAVWH
tAVEL
tAVWL
tWHAX
tWLWH
W1 - W4
tWLQZ
tWHQX
tWHDX
DQ0-DQ31
DATA INPUT
tDVWH
AI05608
Note: Output Enable (G) = Low
11/26
M440T1MV
Figure 11. Memory WRITE Mode AC Waveforms, Chip Enable-Controlled
tAVAV
A0-A19
VALID
tAVEH
tELEH
tAVEL
tEHAX
E1 - E4
W1 - W4
tAVWL
tWHDX
DQ0-DQ31
DATA INPUT
tDVWH
AI05609
Note: Output Enable (G) = High
Figure 12. Clock WRITE Mode AC Waveforms, WRITE Enable-Controlled
tAVAV
A0-A5
EC
VALID
tAVWH
tAVEL
tAVWL
tWHAX
tWLWH
WC
tWLQZ
tWHQX
tWHDX
DQC0-DQC7
DATA INPUT
tDVWH
AI04651
Note: Clock Output Enable (GC) = Low
12/26
M440T1MV
Figure 13. Clock WRITE Mode AC Waveforms, Chip Enable-Controlled
tAVAV
A0-A5
VALID
tAVEH
tELEH
tAVEL
tEHAX
EC
tAVWL
WC
tWHDX
DQC0-DQC7
DATA INPUT
tDVWH
AI04652
Note: Clock Output Enable (GC) = High
Table 5. Memory/Clock WRITE Mode AC Characteristics
M440T1MV
Memory
–85
Clock
–15
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
t
WRITE Cycle Time
85
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
WRITE Enable Pulse Width
AVWL
t
t
AW
t
0
0
AVEL
t
t
t
t
60
65
0
100
150
10
10
50
50
0
WP
WLWH
t
t
ELEH
Chip Enable Low to Chip Enable High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
CEW
WHAX
t
WR
t
15
35
35
0
EHAX
DVWH
t
DS
t
DVEH
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
WHDX
t
DH
t
15
0
EHDX
(2,3)
t
WLQZ
t
30
50
WEZ
t
70
70
5
150
150
5
AVWH
t
AVEH
(3)
WHQX
t
t
OEW
Note: 1. Valid for Ambient Operating Temperature: T = –15 to 75°C; V = 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
3. If E1 - E4 and EC goes low simultaneously with W1 - W4 and WC going low, the outputs remain in the high impedance state.
13/26
M440T1MV
CLOCK OPERATION
Clock Registers
Registers 00h, 01h, 02h, 04h, 06h, 08h, 09h, and
0Ah contain the time of day data in BCD. Eleven
bits within these eight registers are not used and
will always read '0' regardless of how they are writ-
ten. Bits 6 and 7 in the Months Register (09h) are
binary bits. When set to logic '0,' EOSC (Bit 7) en-
ables the Real Time Clock oscillator. This bit will
normally be turned on by the user during device
initialization. However, the oscillator can be turned
on and off as necessary by setting this bit to the
appropriate level. Bit 6 of the Hours Register is de-
fined as the 12- or 24-hour select bit. When set to
logic '1,' the 12-hour format is selected. In the 12-
hour format, Bit 5 is the AM/PM bit with logic '1' be-
ing PM. In the 24-hour mode, Bit 5 is the second
10-hour bit (20-23 hours). The Clock Registers are
updated every 0.01 seconds from the Real Time
Clock, except when the TE Bit (Bit 7 of Register
0Bh) is set low or the clock oscillator is not running.
ous results from READ and WRITE cycles has
been stated, it is worth noting that the probability
of an incorrect result is kept to a minimum due to
the redundant structure of the TIMEKEEPER.
Clock Alarm Registers
Registers 03h, 05h, and 07h contain the Clock
Alarm Registers. Bits 3, 4, 5, and 6 of Register 07h
will always read '0' regardless of how they are writ-
ten. Bit 7 of Registers 03h, 05h, and 07h are mask
bits (see Table 6., page 15). When all of the mask
bits are logic '0,' a Clock Alarm will only occur
when Registers 02h, 04h, and 06h match the val-
ues stored in Registers 03h, 05h, and 07h. An
alarm will be generated every day when Bit 7 of
Register 07h is set to a logic '1.' Similarly, an alarm
is generated every hour when Bit 7 of Registers
07h and 05h is set to a logic '1.' When Bit 7 of Reg-
isters 07h, 05h, and 03h is set to a logic '1,' an
alarm will occur every minute when Register 1
(seconds) rolls from “59” to “00.”
Reading and Setting the Clock
The preferred method of synchronizing data ac-
cess to and from the TIMEKEEPER is to access
Clock Alarm Registers are written and read in the
same format as the Clock Registers. The Clock
Alarm Flag and Interrupt are always cleared when
alarm Registers are read or written.
®
the Command Register by doing a WRITE cycle to
address location 0Bh and setting TE Bit (Transfer
Enable Bit) to a logic '0.' This will freeze the Exter-
nal Clock Registers at the present recorded time,
allowing access to occur without danger of simul-
taneous update. When the clock registers have
been read or written, a second WRITE cycle to lo-
cation 0Bh and setting the TE Bit to a logic '1' will
put the Clock Registers back to being updated ev-
ery 0.01 second. No time is lost in the Real Time
Clock because the internal copy of the Clock Reg-
ister buffers is continually incremented while the
external memory registers are frozen. An alternate
method of reading and writing the Clock Registers
is to ignore synchronization. However, any single
READ may give erroneous data as the Real Time
Clock may be in the process of updating the exter-
nal memory registers as data is being read. The in-
ternal copies of seconds through years are
incremented, and the time of day alarm is checked
during the period that hundreds of seconds reads
“99” to “00.” A way of making sure data is valid is
to do multiple READs and compare. Writing the
registers can also produce erroneous results for
the same reasons. A way of making sure that the
WRITE cycle has caused proper update is to do a
READ to verify and re-execute the WRITE cycle if
data is not correct. While the possibility of errone-
Watchdog Alarm Registers
Registers 0Ch and 0Dh contain the time for the
watchdog alarm. The two registers contain a time
count from 00.01 to 99.99 seconds in BCD. The
value written into the Watchdog Alarm Registers
can be written or read in any order. Any access to
Register 0Ch or 0Dh will cause the watchdog
alarm to re-initialize and clears the Watchdog Flag
Bit and the Watchdog Interrupt Output. When a
new value is entered or the Watchdog Registers
are read, the watchdog timer will start counting
down from the entered value to zero. When zero is
reached, the Watchdog Interrupt Output will go to
the active state. The watchdog timer countdown is
interrupted and re-initialized back to the entered
value every time either of the registers are access-
ed. In this manner, controlled periodic accesses to
the watchdog timer can prevent the watchdog
alarm from going to an active level. If access does
not occur, the countdown alarm will be repetitive.
The Watchdog Alarm Registers always read the
entered value. The actual countdown register is in-
ternal and is not readable. Writing registers 0Ch
and 0Dh to '0' will disable the watchdog alarm fea-
ture.
14/26
M440T1MV
Table 6. Register Map
RANGE
00-99
ADDRESS
0
BIT 0
BIT 7
0.1 SECONDS
0.01 SECONDS
SECONDS
MINUTES
MIN ALARM
HOURS
1
2
3
4
0
0
00-59
00-59
00-59
10 SECONDS
10 MINUTES
10 MIN ALARM
M
0
01-12+A/P
00-23
10
10
10
12/24
12/24
0
HR
HR
A/P
A/P
01-12+A/P
00-23
CLOCK
5
10
HOURS ALARM
DAYS
M
CALENDAR/
TIME OF DAY
ALARM
REGISTERS
01-07
01-07
01-31
0
M
0
0
0
0
0
6
0
0
7
8
9
DAY ALARM
DATE
0
0
10DATE
0
10MO
MONTHS
YEARS
01-12
00-99
EOSC
ESQW
A
10YEARS
IBH
COMMAND
REGISTER
PU
B
WAM
WAF
TE
IPSW
TDM
TDF
LO
LVL
C
0.1 SECONDS
10 SECONDS
0.01 SECONDS
SECONDS
00-99
00-99
WATCHDOG
ALARM
REGISTERS
D
USER
REGISTERS
E - 3F
SRAM ADDRESS SPACE
AI04208
Table 7. Time of Day Alarm Mask Bits
Register
(03h) Minutes
(05h) Hours
(07h) Days
1
0
0
0
1
1
0
0
1
1
1
0
Alarm once per minute
Alarm when minutes match
Alarm when hours and minutes match
Alarm when hours, minutes, and days match
Note: Any other bit combinations of mask bit settings produce an illegal operation.
15/26
M440T1MV
Command Register
Address location 0Bh is the Command Register
where mask bits, control bits, and flag bits reside.
The operation of each bit is as follows:
day alarm registers. This bit is reset to a logic '0'
state when any of the time of day registers are ac-
cessed.
TE - Bit 7 Transfer Enable. This bit, when set to
logic '0,' will disable the transfer of data between
internal and external clock registers. The contents
in the external clock registers are now frozen and
READs or WRITEs will not be affected with up-
dates. This bit must be set to a logic '1' to allow up-
dates.
IPSW - Bit 6 Interrupt Switch. When set to a
logic '1,' IRQ/(IRQ) is the Watchdog Alarm. When
set to a logic '0,' IRQ/(IRQ) is the time of day alarm
output.
When the interrupt is in the pulse mode (see PU/
LVL - Bit 4 Interrupt Pulse Mode or Level Mode),
this flag will be in the logic '1' state only during the
time the interrupt is active.
Battery Low
The M440T1MV automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of at least 24 hours.
The Battery Low (BL) signal will be asserted if the
battery voltage is found to be less than approxi-
mately 2.5V. The BL signal will remain asserted
until completion of battery replacement and sub-
sequent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval (see application note, “AN1540,
NVRAM PBGA Dual Battery Hat Mounting and
Removal” for more information).
IBH/LO - Bit 5 IRQ Sink or Source Current.
When this bit is set to a logic '1' and V is applied,
CC
IRQ/(IRQ) will source current (see Table
11., page 19, IOH). When this bit is set to a logic
'0,' IRQ will sink current (see Table 11., page 19,
I
OL
).
If a battery low is generated during a power-up se-
quence, this indicates that one of the batteries is
below 2.5V and may not be able to maintain data
integrity in the SRAM. Data should be considered
suspect, and verified as correct. Fresh batteries
should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
PU/LVL - Bit 4 Interrupt Pulse Mode or Level
Mode. This bit determines whether the interrupt
will output a pulse or level signal. When set to a
logic '0,' IRQ/(IRQ) will be in the level mode. When
this bit is set to a logic '1,' the pulse mode is select-
ed. IRQ/(IRQ) will either sink or source current, de-
pending on the condition of Bit 5, for a minimum of
3ms and then release. IRQ will only source current
when there is voltage present on V
.
CC
promised due to the fact that a nominal V
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
is
CC
WAM - Bit 3 Watchdog Alarm Mask. When this
bit is set to a logic '0,' the watchdog interrupt output
will be activated. The activated state is determined
by bits 1, 4, 5, and 6 of the Command Register.
when this bit is set to a logic '1,' the watchdog in-
terrupt output is deactivated.
®
batteries should be replaced. The SNAPHAT top
should be replaced with valid V
device.
applied to the
CC
The M440T1MV only monitors the batteries when
TDM - Bit 2 Time of Day Alarm Mask. When
this bit is set to a logic '0,' the time of day alarm in-
terrupt output will be activated. The activated state
is determined by bits 0, 4, 5, and 6 of the Com-
mand Register. When this bit is set to a logic '1,'
the time of day alarm interrupt output is deactivat-
ed.
WAF - Bit 1 Watchdog Alarm Flag. This bit is
set to a logic '1' when a watchdog alarm interrupt
occurs. This bit is “Read only.” The bit is reset
when any of the watchdog alarm registers are ac-
cessed.
a nominal V is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL signal is an open drain output
and an appropriate pull-up resistor should be cho-
sen to control the rise time.
Sleep Mode
Forcing the sleep pad more positive than +7.5V
above ground will cause the batteries to be isolat-
ed from the RAM, preserving the remaining battery
life. This mode may be used when device opera-
tion is not necessary for an extended period of
time.
When the interrupt is in the pulse mode (see PU/
LVL - Bit 4 Interrupt Pulse Mode or Level Mode),
this flag will be in the logic '1' state only during the
time the interrupt is active.
TDF - Bit 0 Time of Day Flag. This is a “Read
only” bit. This bit is set to a logic '1' when a time of
day alarm has occurred. the time the alarm oc-
curred can be determined by reading the time of
Note: Implementation of this Sleep Mode will re-
sult in complete loss of data.
16/26
M440T1MV
MAXIMUM RATINGS
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Operating Temperature
Value
–15 to 75
–40 to 85
260
Unit
°C
°C
°C
V
T
A
T
Storage Temperature (V , Oscillator Off)
STG
CC
T
Lead Solder Temperature for 10 seconds
Supply Voltage (on any pin relative to Ground)
Input or Output Voltages
SLD
V
CC
–0.3 to + 4.6
V
–0.3 to V + 0.3
V
IO
CC
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
CAUTION! Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up Mode
17/26
M440T1MV
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 9. DC and AC Measurement Conditions
Parameter
M440T1MV
3.0 to 3.6V
–15 to 75°C
30pF
V
Supply Voltage
CC
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 5ns
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 14. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
C = 30 pF
1.75V
AI05605
(1,2)
L
Table 10. Capacitance
M440T1MV
Unit
Symbol
Parameter
Min
Max
A0 - A5
50
pF
pF
pF
C
Input Capacitance
A6 - A19, G
All Other Inputs
40
IN
10
(3)
Output Capacitance (BL)
Input / Output Capacitance
10
10
pF
pF
C
OUT
(3)
C
IO
Note: 1. Effective capacitance measured with power supply at 3V; sampled only; not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs were deselected.
18/26
M440T1MV
Table 11. DC Characteristics
M440T1MV
Typ
(1)
Sym
Parameter
Unit
Test Condition
Min
Max
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±4
±4
µA
µA
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
I
210
mA
CC1
E1 - E4,
EC = V
I
Supply Current (TTL Standby)
5
2
12
mA
CC2
IH
E1 - E4,
EC = V – 0.2
I
V
Power Supply Current
CC
3
mA
V
CC3
CCI
(2)
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.3
2.2
0.6
V
V
IL
(2)
IH
V
+ 0.3
V
V
V
V
V
CC
I
= 2.0mA
= 10mA
OL
0.4
0.4
OL
V
OL
(3)
I
Output Low Voltage (Open drain)
Output High Voltage
V
I
= –1.0mA
2.2
OH
OH
(2)
Power Fail Deselect
2.80
2.97
V
PFD
(2)
Battery Back-up Switchover
2.5
V
V
SO
Note: 1. Valid for Ambient Operating Temperature: T = –15 to 75°C; V = 3.0 to 3.6V (except where noted).
A
CC
2. All voltages are referenced to Ground.
3. For BL and IRQ (Open drain); if pulled-up to supply other than V , this supply must be equal to, or less than 3.0V when V = 0V
CC
CC
(during battery back-up mode).
19/26
M440T1MV
Data Retention Mode
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
power supply lines is recommended. When V
CC
drops below V , the control circuit switches pow-
SO
V
falls between V
(max), V (min) win-
er to the internal battery, preserving data and pow-
ering the clock. The internal energy source will
maintain data in the M440T1MV for an accumulat-
ed period of 5 years at 45°C. As system power ris-
CC
PFD
PFD
dow. All outputs become high impedance and all
inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
es above V , the battery is disconnected, and the
SO
power supply is switched to external V . Write
CC
protection continues until V reaches V
(min)
CC
PFD
At voltages below V
in a write protected state, provided the V
(min), the memory will be
PFD
plus t (min). Normal RAM operation can resume
ER
fall
CC
t
after V exceeds V
(max). Refer to Appli-
ER
CC
PFD
time is not less than t . The M440T1MV may re-
F
cation Note (AN1012) on the ST Web Site for more
information on battery life.
spond to transient noise spikes on V
that cross
CC
into the deselect window during the time the de-
vice is sampling V .Therefore, decoupling of the
CC
Figure 15. Power Down/Up Mode AC Waveforms
V
V
CC
PFD
(max)
(min)
V
PFD
V
V
SO
SS
tF
tDR
tR
tFB
tRB
DON'T CARE
tREC
INPUTS
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
AI04792
Table 12. Power Down/Up Trip Points DC Characteristics
M440T1MV
(1,2)
Symbol
Unit
Parameter
Min
Typ
2.9
2.5
Max
2.97
V
PFD
Power-fail Deselect Voltage
2.8
V
V
V
SO
Battery Back-up Switchover Voltage
Expected Data Retention Time
(3)
5
YEARS
t
DR
Note: 1. Valid for Ambient Operating Temperature: T = –15 to 75°C; V = 3.0 to 3.6V (except where noted).
A
CC
2. All voltages referenced to V
.
SS
3. At 45°C, V = 0V.
CC
20/26
M440T1MV
Table 13. Power Down/Up AC Characteristics
(1)
Symbol
Min
Max
Unit
Parameter
(2)
V
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
(3)
V
Fall Time
10
10
1
µs
µs
µs
ms
t
PFD
PFD
SS CC
FB
t
V
V
(min) to V
(max) V Rise Time
PFD CC
R
t
to V (min) V Rise Time
PFD CC
RB
SS
t
Power-up Deselect Time
40
200
REC
Note: 1. Valid for Ambient Operating Temperature: T = –15 to 75°C; V = 3.0 to 3.6V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
PFD F CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
SS FB
PFD
21/26
M440T1MV
PACKAGE MECHANICAL INFORMATION
Figure 16. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Outline
A3
A1
A
A
B
E
A2
HE
B
D B
45˚
ddd C
GD
B3
B2
B1
GE
FD
SIDE VIEW
TOP VIEW
Non-plated
thru holes
E5
e
1
BALL 1
CORNER
eee
fff
S
S
A S B S
C
C
D3
b
b
D D1
D2
e
SOLDER BALL (Typ)
DETAIL A
Fiducial and
Soldermask
opening (3X)
e
E4
Detail A
E1
FE
E2
0.20 (4X)
E3
E
BOTTOM VIEW
PBGA-Z04
Note: Drawing is not to scale.
22/26
M440T1MV
Table 14. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
11.64
6.60
Max
12.04
6.90
Typ
Max
A
A1
A2
A3
B
11.24
6.30
0.458
0.260
0.059
0.364
1.748
1.441
1.112
0.909
0.030
1.752
1.100
1.575
0.809
0.050
1.752
0.900
1.118
1.575
0.620
0.566
0.326
0.426
0.033
0.039
0.052
0.443
0.248
0.055
0.354
1.744
1.437
1.108
0.906
0.028
1.744
0.474
0.272
0.063
0.374
1.752
1.445
1.116
0.913
0.032
1.760
1.50
1.40
1.60
9.25
9.00
9.50
44.40
36.60
28.25
23.10
0.76
44.30
36.50
28.15
23.00
0.71
44.50
36.70
28.35
23.20
0.81
B1
B2
B3
b
D
44.50
27.94
40.00
20.56
1.27
44.30
44.70
D1
D2
D3
e
39.80
20.46
40.20
20.66
1.567
0.806
1.583
0.813
E
44.50
22.86
28.40
40.00
15.75
14.38
8.28
44.30
44.70
1.744
1.760
E1
E2
E3
E4
E5
FD
FE
GD
GE
HE
n
39.80
15.65
14.28
8.08
40.20
15.85
14.48
8.48
1.567
0.616
0.562
0.318
0.422
0.026
1.583
0.624
0.570
0.334
0.430
0.041
10.82
0.85
10.72
0.65
10.92
1.05
1.00
1.32
1.12
168
1.52
0.044
168
0.060
Tolerance
0.15
Tolerance
0.006
ddd
eee
fff
0.25
0.010
0.10
0.004
23/26
M440T1MV
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M440T
1MV
–15
ZA
9
Device Type
M440T
Supply Voltage and Write Protect Voltage
1MV = V = 3.0 to 3.6V; V
= 2.8 to 2.97V
PFD
CC
Speed
–15 = 150ns
(1)
Package
ZA = 168-ball Ball Grid Array
Temperature Range
9 = –15 to 75 °C
Note: 1. Where “Z” is the symbol for PBGA packages and “A” denotes 1.27mm ball pitch
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
24/26
M440T1MV
REVISION HISTORY
Table 16. Document Revision History
Date
September 2002
16-Jan-03
Version
1.0
Revision Details
First issue
1.1
Modify mechanical data (Table 14)
31-Mar-03
11-Apr-03
1.2
Update test condition (Table 12)
2.0
Updated with template v2.2
05-Oct-04
3.0
Reformatted; update mechanical dimensions (Figure 16; Table 14)
25/26
M440T1MV
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
26/26
相关型号：
©2020 ICPDF网 联系我们和版权申明