M48T08Y [STMICROELECTRONICS]
5V, 64Kbit (8 Kb x 8) TIMEKEEPER㈢ SRAM; 5V ，为64Kbit （ 8 KB ×8 ） TIMEKEEPER㈢ SRAM
| 型号： | M48T08Y |
| 厂家： | 
ST |
| 描述： | 5V, 64Kbit (8 Kb x 8) TIMEKEEPER㈢ SRAM |
| 文件： | 总30页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T08
M48T08Y, M48T18
5V, 64Kbit (8 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated ultra low power sram, real time
clock, power-fail control circuit, and battery
■ BYTEWIDE™ RAM-like clock access
■ BCD coded year, month, day, date, hours,
28
minutes, and seconds
1
■ Typical clock accuracy of 1 minute a month, at
25°C
PCDIP28 (PC)
battery/crystal
CAPHAT
■ Automatic power-fail chip deselect and write
protection
■ Write protect
V
= Power-fail deselect voltage):
PFD
– M48T08: V = 4.75 to 5.5V
CC
4.5V ≤ V
≤ 4.75V
PFD
SNAPHAT (SH)
battery/crystal
– M48T18/T08Y: V = 4.5 to 5.5V
CC
4.2V ≤ V
≤ 4.5V
PFD
■ Software controlled clock calibration for high
accuracy applications
■ Self-contained battery and crystal in the
CAPHAT™ dip package
■ Packaging includes a 28-lead SOIC and
®
SNAPHAT top (to be ordered separately)
■ SOIC package provides direct connection for a
snaphat top which contains the battery and
crystal
28
1
■ Pin and function compatible with DS1643 and
JEDEC standard 8K x8 SRAMs
SOH28 (MH)
■ RoHS compliant
– Lead-free second level interconnect
July 2007
Rev 8
1/30
www.st.com
1
Contents
M48T08, M48T08Y, M48T18
Contents
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stopping and starting the oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30
M48T08, M48T08Y, M48T18
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 23
SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT, package mech. data. . . . . . . . 24
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data. . . . . . . 25
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech data.. . . . . . 26
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
List of figures
M48T08, M48T08Y, M48T18
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write enable controlled, write AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline. . . . . . . . . . . . . . . . . . . 23
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline. . . . 24
Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 25
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 26
4/30
M48T08, M48T08Y, M48T18
Summary description
Summary description
®
The M48T08/18/08Y TIMEKEEPER RAM is an 8K x 8 non-volatile static RAM and real
time clock which is pin and functional compatible with the DS1643. The monolithic chip is
available in two special packages to provide a highly integrated battery backed-up memory
and real time clock solution.
The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8K
x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal
and a long- life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
®
connection to a separate SNAPHAT housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (e.g., SNAPHAT)
part number is “M4T28-BR12SH” or “M4T32-BR12SH” (see Table 17 on page 28).
Figure 1.
Logic diagram
V
CC
13
8
A0-A12
DQ0-DQ7
INT
W
E1
E2
G
M48T08
M48T08Y
M48T18
V
SS
AI01020
5/30
Summary description
M48T08, M48T08Y, M48T18
Table 1.
Signal names
A0-A12
Address inputs
Data inputs / outputs
Power fail interrupt (open drain)
Chip enable 1
DQ0-DQ7
INT
E1
E2
Chip enable 2
G
Output enable
W
WRITE enable
VCC
VSS
Supply voltage
Ground
Figure 2.
DIP connections
INT
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
26 E2
25 A8
24 A9
23 A11
A6
A5
A4
A3
22
G
M48T08
M48T18
A2
21 A10
20 E1
A1
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
V
14
SS
AI01182
6/30
M48T08, M48T08Y, M48T18
Figure 3. SOIC connections
Summary description
INT
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
3
E2
A6
4
A8
A5
5
A9
A4
6
A11
G
A3
7
M48T08Y
A2
8
A10
E1
A1
9
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
SS
AI01021B
Figure 4.
Block diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A12
POWER
DQ0-DQ7
8184 x 8
SRAM ARRAY
LITHIUM
CELL
E1
E2
W
VOLTAGE SENSE
AND
V
PFD
SWITCHING
CIRCUITRY
G
V
INT
V
CC
SS
AI01333
7/30
Operation modes
M48T08, M48T08Y, M48T18
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own Power-fail Detect circuit. The control circuitry
constantly monitors the single 5V supply for an out of tolerance condition. When V is out
CC
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low V . As V falls below the
CC
CC
Battery Back-up Switchover Voltage (V ), the control circuitry connects the battery which
SO
maintains data and clock operation until valid power returns.
Table 2.
Mode
Operating modes
VCC
E1
E2
G
W
DQ0-DQ7
Power
Deselect
Deselect
WRITE
READ
VIH
X
X
X
X
X
High Z
High Z
DIN
Standby
Standby
Active
VIL
VIH
VIH
VIH
X
4.75 to 5.5V
or
VIL
VIL
VIL
X
VIL
VIH
VIH
4.5 to 5.5V
VIL
VIH
DOUT
High Z
Active
READ
Active
V
SO to
Deselect
Deselect
X
X
X
X
X
X
X
X
High Z
High Z
CMOS Standby
VPFD(min)(1)
Battery Back-up
Mode
(1)
≤ VSO
1. See Table 11 on page 22 for details.
Note:
X = V or V ; V = battery back-up switchover voltage.
IH IL SO
Read mode
The M48T08/18/08Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip
Enable 1) is low, and E2 (Chip Enable 2) is high. The device architecture allows ripple-
through access of data from eight of 65,536 locations in the static storage array. Thus, the
unique address specified by the 13 address inputs defines which one of the 8,192 bytes of
data is to be accessed. Valid data will be available at the Data I/O pins within address
access time (t
) after the last address input signal is stable, providing that the E1, E2,
AVQV
and G access times are also satisfied. If the E1, E2 and G access times are not met, valid
8/30
M48T08, M48T08Y, M48T18
data will be available after the latter of the Chip Enable Access times (t
Operation modes
or t ) or
E1LQV
E2HQV
Output Enable Access time (t
).
GLQV
The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the
outputs are activated before t , the data lines will be driven to an indeterminate state
AVQV
until t
. If the address inputs are changed while E1, E2 and G remain active, output data
AVQV
will remain valid for Output Data Hold time (t
address access.
) but will go indeterminate until the next
AXQX
Figure 5.
Read mode AC waveforms
tAVAV
A0-A12
VALID
tAVQV
tE1LQV
tAXQX
tE1HQZ
E1
tE1LQX
tE2HQV
tE2LQZ
E2
tE2HQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00962
Note:
WRITE Enable (W) = High.
9/30
Operation modes
Table 3. Read mode AC characteristics
M48T08, M48T08Y, M48T18
M48T08/M48T18/T08Y
–100/–10 (T08Y) –150/–15 (T08Y)
Symbol
Parameter(1)
Unit
Min
Max
Min
Max
tAVAV
tAVQV
READ Cycle Time
100
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Output Valid
100
100
100
50
150
150
150
75
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tE1HQZ
tE2LQZ
tGHQZ
tAXQX
Chip Enable 1 Low to Output Valid
Chip Enable 2 High to Output Valid
Output Enable Low to Output Valid
Chip Enable 1 Low to Output Transition
Chip Enable 2 High to Output Transition
Output Enable Low to Output Transition
Chip Enable 1 High to Output Hi-Z
Chip Enable 2 Low to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
10
10
5
10
10
5
50
50
40
75
75
60
5
5
Note:
Valid for ambient operating temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V
A CC
(except where noted).
Write mode
The M48T08/18/08Y is in the WRITE Mode whenever W, E1, and E2 are active. The start of
a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of
E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low
for a minimum of t
or t
from Chip Enable or t
from WRITE Enable prior to
E1HAX
E2LAX
WHAX
the initiation of another READ or WRITE Cycle. Data-in must be valid t
prior to the end
DVWH
of WRITE and remain valid for t
afterward. G should be kept high during WRITE
WHDX
Cycles to avoid bus contention; however, if the output bus has been activated by a low on
E1 and G and a high on E2, a low on W will disable the outputs t after W falls.
WLQZ
10/30
M48T08, M48T08Y, M48T18
Figure 6. Write enable controlled, write AC waveform
Operation modes
tAVAV
VALID
A0-A12
tAVWH
tAVE1L
tAVE2H
tWHAX
E1
E2
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00963
Figure 7.
Chip enable controlled, write AC waveforms
tAVAV
A0-A12
VALID
tAVE1H
tE1LE1H
tAVE1L
tE1HAX
tE2LAX
E1
tAVE2L
tE2HE2L
tAVE2H
E2
tAVWL
W
tE1HDX
tE2LDX
DQ0-DQ7
DATA INPUT
tDVE1H
tDVE2L
AI00964B
11/30
Operation modes
Table 4. Write mode AC characteristics
M48T08, M48T08Y, M48T18
M48T08/M48T18/T08Y
–100/–10 (T08Y) –150/–15 (T08Y)
Symbol
Parameter(1)
Unit
Min
Max
Min
Max
tAVAV
tAVWL
WRITE Cycle Time
100
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to WRITE Enable Low
Address Valid to Chip Enable 1 Low
Address Valid to Chip Enable 2 High
WRITE Enable Pulse Width
tAVE1L
tAVE2H
tWLWH
tE1LE1H
tE2HE2L
tWHAX
tE1HAX
tE2LAX
tDVWH
tDVE1H
tDVE2L
tWHDX
tE1HDX
tE2LDX
tWLQZ
tAVWH
tAVE1H
tAVE2L
tWHQX
0
0
0
0
80
80
80
10
10
10
50
50
50
5
100
130
130
10
10
10
70
70
70
5
Chip Enable 1 Low to Chip Enable 1 High
Chip Enable 2 High to Chip Enable 2 Low
WRITE Enable High to Address Transition
Chip Enable 1 High to Address Transition
Chip Enable 2 Low to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable 1 High
Input Valid to Chip Enable 2 Low
WRITE Enable High to Input Transition
Chip Enable 1 High to Input Transition
Chip Enable 2 Low to Input Transition
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable 1 High
Address Valid to Chip Enable 2 Low
WRITE Enable High to Output Transition
5
5
5
5
50
70
80
80
80
10
130
130
130
10
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
Data retention mode
With valid V applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static
CC
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V falls within the V
(max), V
(min) window. All outputs
CC
PFD
PFD
become high impedance, and all inputs are treated as “Don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the
PFD
user can be assured the memory will be in a write protected state, provided the V fall time
CC
is not less than t . The M48T08/18/08Y may respond to transient noise spikes on V that
F
CC
reach into the deselect window during the time the device is sampling V . Therefore,
CC
decoupling of the power supply lines is recommended.
12/30
M48T08, M48T08Y, M48T18
Operation modes
When V drops below V , the control circuit switches power to the internal battery which
CC
SO
preserves data and powers the clock. The internal button cell will maintain data in the
M48T08/18/08Y for an accumulated period of at least 10 years when V is less than V
.
CC
SO
®
Note:
Requires use of M4T32-BR12SH SNAPHAT top when using the SOH28 package.
As system power returns and V rises above V , the battery is disconnected and the
CC
SO
power supply is switched to external V
.
CC
Write protection continues until V reaches V
(min) plus t (min). E1 should be kept
rec
CC
PFD
high or E2 low as V rises past V
(min) to prevent inadvertent WRITE cycles prior to
CC
PFD
system stabilization. Normal RAM operation can resume t after V exceeds V (max).
rec
CC
PFD
For more information on Battery Storage Life refer to the Application Note AN1012.
Power-fail interrupt pin
The M48T08/18/08Y continuously monitors V . When V falls to the power-fail detect trip
CC
CC
point, an interrupt is immediately generated. An internal clock provides a delay of between
10µs and 40µs before automatically deselecting the M48T08/18/08Y. The INT pin is an
open drain output and requires an external pull up resistor, even if the interrupt output
function is not being used.
13/30
Clock operations
M48T08, M48T08Y, M48T18
Clock operations
Reading the clock
®
Updates to the TIMEKEEPER registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be
halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ Bit, the seventh bit in the control
register. As long as a '1' remains in that position, updating is halted. After a halt is issued,
the registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
Setting the clock
The eighth bit of the control register is the WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with
the correct day, date, and time data in 24 hour BCD format (on Table 5). Resetting the
WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits
marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation.
®
st
See the Application Note AN923, “TIMEKEEPER Rolling Into the 21 Century” for
information on Century Rollover.
14/30
M48T08, M48T08Y, M48T18
Clock operations
Table 5.
Address
Register map
Data
D4
Function/range
BCD format
D7
D6
D5
D3
D2
D1
Year
D0
1FFFh
1FFEh
1FFDh
1FFCh
1FFBh
1FFAh
1FF9h
1FF8h
10 Years
Year
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 M
0
Month
Date
Month
Date
10 Date
0
FT
0
0
0
Day
Day
0
10 Hours
10 Minutes
Hours
Minutes
Seconds
Hours
Minutes
Seconds
Control
0
ST
W
10 Seconds
S
R
Calibration
Note:
S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP Bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from
STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T08/18/08Y
oscillator starts within one second.
Note:
To guarantee oscillator start-up after initial power-up, first write the STOP Bit (ST) to '1,'
then reset to '0.'
Calibrating the clock
The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25°C without
calibration. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about 1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than
+1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature. Figure 8 on page 17 shows the
frequency error that can be expected at various temperatures. Most clock chips compensate
for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The
M48T08/18/08Y design, however, employs periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage,
as shown in Figure 9 on page 17. The number of times pulses are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded
15/30
Clock operations
M48T08, M48T08Y, M48T18
into the five-bit Calibration Byte found in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits in the Control register. This byte can
be set to represent any value between 0 and 31 in binary form. The sixth bit is the Sign Bit;
'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a
64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second
either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is
loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T08/18/08Y
may require. The first involves simply setting the clock, letting it run for a month and
comparing it to a known accurate reference (like WWV broadcasts). While that may seem
crude, it allows the designer to give the end user the ability to calibrate his clock as his
environment may require, even after the final product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a simple utility that accesses the Calibration
Byte.
The second approach is better suited to a manufacturing environment, and involves the use
of standard test equipment. When the Frequency Test (FT) Bit, the seventh-most significant
bit in the Day Register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB
(DQ0) of the Seconds Register will toggle at 512 Hz. Any deviation from 512 Hz indicates
the degree and direction of oscillator frequency shift at the test temperature. For example, a
reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –
10 (WR001010) to be loaded into the Calibration Byte for correction.
Note:
Setting or changing the Calibration Byte does not affect the Frequency Test output
frequency. The device must be selected and addresses must be stable at Address 1FF9h
when reading the 512 Hz on DQ0.
The LSB of the Seconds Register is monitored by holding the M48T08/18/08Y in an
extended READ of the Seconds Register, but without having the READ Bit set. The FT Bit
MUST be reset to '0' for normal clock operations to resume.
®
For more information on calibration, see the Application Note AN934, “TIMEKEEPER
Calibration.”
16/30
M48T08, M48T08Y, M48T18
Figure 8. Crystal accuracy across temperature
Clock operations
ppm
20
0
-20
-40
-60
-80
2
ΔF
F
ppm
C2
= -0.038
(T - T0) 10%
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 10) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from V to V (cathode connected to V , anode to V ). Schottky diode
CC
SS
CC
SS
17/30
Clock operations
M48T08, M48T08Y, M48T18
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 10. Supply voltage protection
V
CC
V
CC
0.1μF
DEVICE
V
SS
AI02169
18/30
M48T08, M48T08Y, M48T18
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
0 to 70
–40 to 85
260
°C
°C
°C
V
TSTG
(1) (2) (3)
TSLD
VIO
VCC
IO
–0.3 to 7
–0.3 to 7
20
Supply Voltage
V
Output Current
mA
W
PD
Power Dissipation
1
1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
Caution:
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
19/30
DC and AC parameters
M48T08, M48T08Y, M48T18
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter
Supply Voltage (VCC
M48T08
M48T18/T08Y
Unit
)
4.75 to 5.5
0 to 70
100
4.5 to 5.5
0 to 70
100
V
°C
pF
ns
V
Ambient Operating Temperature (TA)
Load Capacitance (CL)
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
1.5
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 11. AC testing load circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF
L
C
includes JIG capacitance
L
AI01019
Table 8.
Symbol
CIN
Capacitance
Parameter(1)(2)
Min
Max
Unit
Input Capacitance
10
10
pF
pF
(3)
CIO
Input / Output Capacitance
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
20/30
M48T08, M48T08Y, M48T18
DC and AC parameters
Table 9.
Symbol
ILI
DC characteristics
Parameter
M48T08/M48T18/T08Y
Test condition(1)
Unit
Min
Max
Input Leakage Current
Output Leakage Current
Supply Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
1
1
µA
µA
(2)
ILO
ICC
80
3
mA
mA
(3)
ICC1
Supply Current (Standby) TTL
E1 = VIH, E2 = VIL
E1 = VCC – 0.2V,
E2 = VSS + 0.2V
(3)
ICC2
Supply Current (Standby) CMOS
3
mA
VIL
VIH
Input Low Voltage
–0.3
2.2
0.8
VCC + 0.3
0.4
V
V
V
V
V
Input High Voltage
Output Low Voltage
Output Low Voltage (INT)(4)(4)
Output High Voltage
IOL = 2.1mA
IOL = 0.5mA
IOH = –1mA
VOL
VOH
0.4
2.4
1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. Outputs deselected.
3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
4. The INT pin is open drain.
Figure 12. Power down/up mode AC waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tPFX
tRB
tPFH
INT
trec
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00566
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high
or E2 low as V rises past V (min). Some systems may perform inadvertent WRITE
CC
PFD
cycles after V rises above V
(min) but before normal system operations begin. Even
CC
PFD
though a power on reset is being applied to the processor, a reset condition may not occur
until after the system clock is running.
21/30
DC and AC parameters
Table 10. Power down/up AC characteristics
M48T08, M48T08Y, M48T18
Symbol
Parameter(1)
Min
Max
Unit
E1 or W at VIH or E2 at VIL before Power
Down
tPD
0
µs
(2)
tF
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSS VCC Fall Time
VPFD (min) to VPFD (max) VCC Rise Time
VSS to VPFD (min) VCC Rise Time
E1 or W at VIH or E2 at VIL before Power Up
INT Low to Auto Deselect
300
10
0
µs
µs
µs
µs
ms
µs
µs
(3)
tFB
tR
tRB
1
trec
1
tPFX
tPFH
10
40
VPFD (max) to INT High
120
1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max
Unit
M48T08
4.5
4.2
4.6
4.3
3.0
4.75
4.5
V
VPFD
Power-fail Deselect Voltage
M48T18/T08Y
V
V
VSO
tDR
Battery Back-up Switchover Voltage
Expected Data Retention Time
10(3)
YEARS
1. All voltages referenced to VSS
.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except
where noted).
3. At 55°C, VCC = 0V; tDR = 8.5 years (typ) at 70°C. Requires use of M4T32-BR12SH SNAPHAT® top when
using the SOH28 package.
22/30
M48T08, M48T08Y, M48T18
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note:
Drawing is not to scale.
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
9.65
0.76
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
8.89
0.53
B1
C
1.78
0.31
D
39.88
18.34
2.79
E
e1
e3
eA
L
36.32
16.00
3.81
N
23/30
Package mechanical data
M48T08, M48T08Y, M48T18
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package
outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT, package mech. data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
28
28
CP
0.10
0.004
24/30
M48T08, M48T08Y, M48T18
Package mechanical data
Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note:
Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech.
data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
A2
A3
B
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
25/30
Package mechanical data
M48T08, M48T08Y, M48T18
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note:
Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech
data.
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
A2
A3
B
10.54
8.51
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
26/30
M48T08, M48T08Y, M48T18
Part numbering
Part numbering
Table 16. Ordering information scheme
Example:
M48T
18
–100
PC
1
E
Device type
M48T
Supply Voltage and Write Protect Voltage
08(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V
18/08Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed
–100 = 100ns
–150 = 150ns
–10 = 100ns (M48T08Y)
Package
PC(1) = PCDIP28
MH(2) = SOH28
Temperature Range
1 = 0 to 70°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = ECOPACK Package, Tubes
1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
2. The SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately
under the part number“M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see
Table 17). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only.
Caution:
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
27/30
Part numbering
Table 17. SNAPHAT battery table
M48T08, M48T08Y, M48T18
Package
Part Number
Description
M4T28-BR12SH
M4T32-BR12SH
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
SH
SH
28/30
M48T08, M48T08Y, M48T18
Revision history
Revision history
Table 18. Document revision history
Date
Revision
Changes
Dec-1999
1.0
First Issue
From Preliminary Data to Data Sheet; Battery Low Flag paragraph
changed; 100ns speed class identifier changed (Table 3, 4)
07-Feb-2000
11-Jul-2000
16-Jul-2001
2.0
2.1
3.0
tFB changed (Table 10); Watchdog Timer paragraph changed
Reformatted; SNAPHAT battery table added (Table 17); added
temp./voltage info. to tables (Table 8, 9, 3, 4, 10, 11).
01-Aug-2001
21-Dec-2001
06-Mar-2002
20-May-2002
29-Aug-2002
28-Mar-2003
10-Dec-2003
3.1
3.2
3.3
3.4
3.5
4.0
5.0
Reference to App. Note corrected in “Calibrating the Clock” section
Changes to text in document to reflect addition of M48T08Y option
Fix Ordering Information table and add to footnote (Table 16)
Modify reflow time and temperature footnotes (Table 6)
tDR specification temperature updated (Table 11)
v2.2 template applied; updated test conditions (Table 10)
Reformatted
Reformatted; Lead-free (Pb-free) information package update (Table 6,
16)
30-Mar-2004
13-Dec-2005
04-Jul-2007
6.0
7.0
8.0
Updated template, Lead-free information, removed footnote (Table 9, 16)
Reformatted; added lead-free second level interconnect information to
cover page and Section : Package mechanical data.
29/30
M48T08, M48T08Y, M48T18
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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