M48T12-70PC1TR [STMICROELECTRONICS]
5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER㈢ SRAM; 5.0V ， 16千位（ 2K位×8 ） TIMEKEEPER㈢ SRAM
| 型号： | M48T12-70PC1TR |
| 厂家： | 
ST |
| 描述： | 5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER㈢ SRAM |
| 文件： | 总19页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T02
M48T12
®
5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, and POWER-FAIL
CONTROL CIRCUIT
Figure 1. 24-pin PCDIP, CAPHAT™ Package
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■ TYPICAL CLOCK ACCURACY OF ±1 MINUTE
A MONTH, AT 25°C
24
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
1
PCDIP24 (PC)
Battery/Crystal
CAPHAT
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
– M48T02: V = 4.75 to 5.5V
CC
4.5V ≤ V
≤ 4.75V
PFD
– M48T12: V = 4.5 to 5.5V
CC
4.2V ≤ V
≤ 4.5V
PFD
■ SELF-CONTAINED BATTERY and CRYSTAL
IN THE CAPHAT™ DIP PACKAGE
■ PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2K x 8 SRAMs
March 2003
1/19
Rev. 3.0
M48T02, M48T12
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 5
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. WRITE Enable Controlled, WRITE AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Checking the BOK Flag Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M48T02, M48T12
SUMMARY DESCRIPTION
®
The M48T02/12 TIMEKEEPER RAM is a 2Kb x 8
non-volatile static RAM and real time clock which
is pin and functional compatible with the DS1642.
tionality for an accumulated time period of at least
10 years in the absence of power over the operat-
ing temperature range.
A special 24-pin, 600mil DIP CAPHAT™ package
houses the M48T02/12 silicon with a quartz crystal
and a long life lithium button cell to form a highly
integrated battery backed-up memory and real
time clock solution.
The M48T02/12 button cell has sufficient capacity
and storage life to maintain data and clock func-
The M48T02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2Kb x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A10
Address Inputs
Data Inputs / Outputs
Chip Enable
V
CC
DQ0-DQ7
11
8
E
A0-A10
DQ0-DQ7
G
W
Output Enable
WRITE Enable
Supply Voltage
Ground
W
E
M48T02
M48T12
V
CC
V
SS
G
V
SS
AI01027
Figure 3. DIP Connections
A7
A6
1
2
3
4
5
6
7
8
9
24
V
CC
23 A8
A5
22 A9
A4
21
20
W
G
A3
A2
M48T02 19 A10
M48T12
A1
18
E
A0
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
DQ0
DQ1 10
DQ2 11
V
12
SS
AI01028
3/19
M48T02, M48T12
Figure 4. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A10
POWER
DQ0-DQ7
2040 x 8
SRAM ARRAY
LITHIUM
CELL
E
V
PFD
VOLTAGE SENSE
AND
W
G
SWITCHING
CIRCUITRY
BOK
V
V
CC
SS
AI01329
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
A
Ambient Operating Temperature
T
Storage Temperature (V Off, Oscillator Off)
–40 to 85
°C
STG
CC
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
260
–0.3 to 7
–0.3 to 7
20
°C
V
T
SLD
V
IO
V
V
CC
I
Output Current
mA
W
O
P
Power Dissipation
1
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
4/19
M48T02, M48T12
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
Supply Voltage (V
M48T02
M48T12
4.5 to 5.5
0 to 70
100
Unit
V
)
4.75 to 5.5
0 to 70
100
CC
Ambient Operating Temperature (T )
°C
pF
ns
V
A
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
1.5
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF
L
C
includes JIG capacitance
L
AI01019
Table 4. Capacitance
Symbol
(1,2)
Min
Max
10
Unit
pF
Parameter
C
Input Capacitance
Input / Output Capacitance
IN
(3)
10
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
5/19
M48T02, M48T12
Table 5. DC Characteristics
(1)
Symbol
Parameter
Min
Max
±1
±1
80
3
Unit
µA
Test Condition
0V ≤ V ≤ V
Input Leakage Current
I
IN
CC
LI
(2)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
µA
I
OUT
LO
I
Outputs open
mA
mA
mA
CC
(3)
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
I
I
IH
CC1
(3)
E = V – 0.2V
3
CC
CC2
(4)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
V
V
V
V
V
IL
V
V
+ 0.3
IH
CC
V
V
I
= 2.1mA
= –1mA
OH
0.4
OL
OL
I
2.4
OH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
2. Outputs deselected.
3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
4. Negative spikes of –1V allowed for up to 10ns once per Cycle.
OPERATION MODES
As Figure 4, page 4 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T02/12 are integrated on one silicon chip. The
two circuits are interconnected at the upper eight
memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 7F8h-7FFh. The clock locations con-
tain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year - valid until 2100), 30, and 31 day
months are made automatically.
consisting of BiPORT™ READ/WRITE memory
cells. The M48T02/12 includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When V is out of tolerance, the circuit write
CC
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
operation brought on by low V . As V falls be-
CC
CC
low approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
Table 6. Operating Modes
V
Mode
Deselect
WRITE
READ
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.75 to 5.5V
or
4.5 to 5.5V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
Active
IL
OUT
V
IH
READ
High Z
High Z
High Z
Active
(1)
Deselect
X
X
X
CMOS Standby
V
SO
to V
(min)
PFD
(1)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
1. See Table 10, page 11 for details.
6/19
M48T02, M48T12
READ Mode
The M48T02/12 is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
available after the latter of the Chip Enable Access
time (t
) or Output Enable Access time
ELQV
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
, the data lines will be driven to an
AVQV
. If the Address In-
AVQV
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
within Address Access time (t
) after the last
AVQV
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
time (t
) but will go indeterminate until the next
AXQX
Address Access.
Figure 6. READ Mode AC Waveforms
tAVAV
VALID
A0-A10
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01330
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
M48T02/M48T12
–150
(1)
Symbol
–70
Max
–200
Unit
Parameter
Min
Min
Max
Min
Max
t
READ Cycle Time
70
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
35
150
150
75
200
200
80
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
ELQV
t
GLQV
t
5
5
10
5
10
5
ELQX
t
GLQX
t
25
25
35
35
40
40
EHQZ
t
GHQZ
t
10
5
5
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
7/19
M48T02, M48T12
WRITE Mode
The M48T02/12 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
er READ or WRITE cycle. Data-in must be valid t
D-
prior to the end of WRITE and remain valid for
VWH
t
afterward. G should be kept high during
WHDX
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WLQZ
a minimum of t
from Chip Enable or t
EHAX
WHAX
from WRITE Enable prior to the initiation of anoth-
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
A0-A10
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01331
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A10
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01332B
8/19
M48T02, M48T12
Table 8. WRITE Mode AC Characteristics
M48T02/M48T12
–150
(1)
Symbol
–70
–200
Unit
Parameter
Min Max Min Max Min Max
t
WRITE Cycle Time
70
0
150
0
200
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
WRITE Enable Pulse Width
AVWL
t
0
0
0
AVEL
t
50
55
0
90
90
10
10
40
40
5
120
120
10
10
60
60
5
WLWH
t
Chip Enable Low to Chip Enable High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
WHDX
t
5
5
5
EHDX
t
25
50
60
WLQZ
t
60
60
5
120
120
10
140
140
10
AVWH
t
AVEH
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
9/19
M48T02, M48T12
Data Retention Mode
Figure 9. Checking the BOK Flag Status
With valid V
applied, the M48T02/12 operates
CC
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
POWER-UP
READ DATA
AT ANY ADDRESS
self when V
falls within the V
(max), V
PFD PFD
CC
(min) window. All outputs become high imped-
ance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
tent. At voltages below V
(min), the user can be
PFD
assured the memory will be in a write protected
READ DATA
AT SAME
ADDRESS AGAIN
state, provided the V fall time is not less than t .
CC
F
The M48T02/12 may respond to transient noise
spikes on V that reach into the deselect window
CC
during the time the device is sampling V . There-
CC
fore, decoupling of the power supply lines is rec-
ommended.
IS DATA
The power switching circuit connects external V
to the RAM and disconnects the battery when V
NO (BATTERY LOW)
CC
CC
COMPLEMENT
OF FIRST
READ?
rises above V . As V rises, the battery voltage
SO
CC
is checked. If the voltage is too low, an internal
Battery Not OK (BOK) flag will be set. The BOK
flag can be checked after power up. If the BOK flag
is set, the first WRITE attempted will be blocked.
The flag is automatically cleared after the first
WRITE, and normal RAM operation resumes. Fig-
ure 9 illustrates how a BOK check routine could be
structured.
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
For more information on a Battery Storage Life re-
fer to the Application Note AN1012.
AI00607
10/19
M48T02, M48T12
Figure 10. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tRB
tREC
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as V rises past V
(min). Some systems
PFD
CC
may perform inadvertent WRITE cycles after V rises above V
(min) but before normal system operations begin. Even though a
CC
PFD
power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
Table 9. Power Down/Up AC Characteristics
(1)
Symbol
Min
0
Max
Unit
µs
Parameter
t
PD
E or W at V before Power Down
IH
(2)
V
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
(3)
V
Fall Time
10
0
µs
µs
µs
t
PFD
PFD
SS CC
FB
t
V
V
(min) to V
(max) V Rise Time
R
PFD CC
t
to V
(min) V Rise Time
PFD CC
1
RB
SS
E or W at V before Power Up
2
ms
t
IH
REC
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after V pass-
PFD CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
SS FB
PFD
Table 10. Power Down/Up Trip Points DC Characteristics
(1,2)
Symbol
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
V
Parameter
M48T02
M48T12
V
PFD
Power-fail Deselect Voltage
V
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
SO
(3)
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
3. At 25°C; V = 0V.
CC
11/19
M48T02, M48T12
CLOCK OPERATIONS
Reading the Clock
Setting the Clock
®
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, the seventh bit in the control register.
As long as a '1' remains in that position, updating
is halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
The eighth bit of the control register is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (on Ta-
ble 11). Resetting the WRITE Bit to a '0' then trans-
fers the values of all time registers (7F9-7FF) to
the actual TIMEKEEPER counters and allows nor-
mal operation to resume. The FT Bit and the bits
marked as '0' in Table 11 must be written to '0' to
allow for normal TIMEKEEPER and RAM opera-
tion.
®
See the Application Note AN923, “TIMEKEEPER
Rolling Into the 21 Century” for information on
st
Century Rollover.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Table 11. Register Map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
10 M
0
D3
D2
D1
D0
7FF
7FE
7FD
7FC
7FB
7FA
7F9
7F8
10 Years
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 Date
0
FT
0
0
0
Day
Hours
Day
0
10 Hours
Hours
Minutes
Seconds
Control
0
10 Minutes
10 Seconds
S
Minutes
ST
W
Seconds
R
Calibration
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
12/19
M48T02, M48T12
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T02/12 is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T02/12
oscillator starts within one second.
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration Byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T02/12 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
Calibrating the Clock
The M48T02/12 is driven by a quartz-controlled
oscillator with a nominal frequency of 32,768 Hz.
A typical M48T02/12 is accurate within 1 minute
per month at 25°C without calibration. The devices
are tested not to exceed ± 35 PPM (parts per mil-
lion) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) Bit, the seventh-most significant bit in the Day
Register, is set to a '1,' and the oscillator is running
at 32,768 Hz, the LSB (DQ0) of the Seconds Reg-
ister will toggle at 512 Hz. Any deviation from 512
Hz indicates the degree and direction of oscillator
frequency shift at the test temperature. For exam-
ple, a reading of 512.01024 Hz would indicate a
+20 PPM oscillator frequency error, requiring a –
10 (WR001010) to be loaded into the Calibration
Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency. The device must be selected and ad-
dresses must be stable at Address 7F9 when
reading the 512 Hz on DQ0.
The FT Bit must be set using the same method
used to set the clock: using the WRITE Bit. The
LSB of the Seconds Register is monitored by hold-
ing the M48T02/12 in an extended READ of the
Seconds Register, but without having the READ
Bit set. The FT Bit MUST be reset to '0' for normal
clock operations to resume.
The oscillation rate of any crystal changes with
temperature. Figure 11, page 14 shows the fre-
quency error that can be expected at various tem-
peratures. Most clock chips compensate for
crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T02/12
design, however, employs periodic counter cor-
rection. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure 12, page 14.
The number of times pulses are blanked (subtract-
ed, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five-bit Calibration Byte found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is the Sign Bit; '1' indicates pos-
itive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The
first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the Frequency Test Bit
(FT) or the Stop Bit (ST).
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or –2.034 PPM of adjustment per calibra-
For more information on calibration, see the Appli-
cation Note AN924, “TIMEKEEPER Calibration.”
®
13/19
M48T02, M48T12
Figure 11. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
-60
-80
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 12. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
14/19
M48T02, M48T12
V
Noise And Negative Going Transients
Figure 13. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
V
CC
V
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V
(cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
15/19
M48T02, M48T12
PACKAGE MECHANICAL INFORMATION
Figure 14. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note: Drawing is not to scale.
Table 12. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
34.80
18.34
2.79
30.73
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
34.29
17.83
2.29
25.15
15.24
3.05
24
0.350
0.015
0.330
0.015
0.045
0.008
1.350
0.702
0.090
0.990
0.600
0.120
24
0.380
0.030
0.350
0.021
0.070
0.012
1.370
0.722
0.110
1.210
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
16/19
M48T02, M48T12
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M48T
02
–70
PC
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
02 = V = 4.75 to 5.5V; V
= 4.5 to 4.75V
CC
PFD
12 = V = 4.5 to 5.5V; V
= 4.2 to 4.5V
PFD
CC
Speed
–70 = 100ns (M48T02/12)
–150 = 150ns (M48T02/12)
–200 = 200ns (M48T02/12)
Package
PC = PCDIP24
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest you.
17/19
M48T02, M48T12
REVISION HISTORY
Table 14. Document Revision History
Date
Rev. #
1.0
Revision Details
July 2000
13-Jul-00
07-May-01
14-May-01
16-Jul-01
20-May-02
26-Jun-02
28-Mar-03
First issue
change (Table 9)
t
1.1
REC
2.0
Reformatted; temp. / voltage info. added to tables (Tables 4, 5, 7, 8, 9, 10)
Note added to Clock Calibration section; table footnote correction (Table 6)
Basic formatting / content changes (Figure 1, Tables 4, 5, 10)
Add countries to disclaimer
2.1
2.2
2.3
2.4
Add footnote to table (Table 10)
3.0
v2.2 template applied; test conditions updated (Table 9)
18/19
M48T02, M48T12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2003 STMicroelectronics - All Rights Reserved
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19/19
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