M48T35AY-10PC1 [STMICROELECTRONICS]
256 Kbit 32Kb x8 TIMEKEEPER SRAM; 256千位32Kb的X8 TIMEKEEPER SRAM
| 型号： | M48T35AY-10PC1 |
| 厂家： | 
ST |
| 描述： | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| 文件： | 总19页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T35AY
M48T35AV
®
256 Kbit (32Kb x8) TIMEKEEPER SRAM
■ INTEGRATED ULTRA LOW POWER SRAM,
SNAPHAT (SH)
Battery/Crystal
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
■ BATTERY LOW FLAG (BOK)
28
■ FREQUENCY TEST OUTPUT for REAL TIME
1
CLOCK
28
PCDIP28 (PC)
Battery/Crystal
CAPHAT
1
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
SOH28 (MH)
■ WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48T35AY: 4.2V ≤ V
– M48T35AV: 2.7V ≤ V
≤ 4.5V
≤ 3.0V
PFD
PFD
Figure 1. Logic Diagram
■ SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT HOUSING
CONTAINING the BATTERY and CRYSTAL
V
CC
®
■ SNAPHAT HOUSING (BATTERY and
CRYSTAL) is REPLACEABLE
15
8
■ PIN and FUNCTION COMPATIBLE with
A0-A14
DQ0-DQ7
JEDEC STANDARD 32Kb x8 SRAMs
DESCRIPTION
The M48T35AY/35AV TIMEKEEPER RAM is a
32Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in two spe-
cial packages to provide a highly integrated bat-
tery backed-up memory and real time clock
solution.
W
E
M48T35AY
M48T35AV
®
G
The M48T35AY/35AV is a non-volatile pin and
function equivalent to any JEDEC standard 32Kb
x8 SRAM. It also easily fits into many ROM,
EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement
for special write timing or limitations on the number
of writes that can be performed.
V
SS
AI02797B
May 2000
1/19
M48T35AY, M48T35AV
Figure 2A. DIP Connections
Figure 2B. SOIC Connections
A14
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 A13
25 A8
24 A9
23 A11
3
A13
A8
A6
A6
4
A5
A5
5
A9
A4
A4
6
A11
G
A3
M48T35AY 22
G
A3
7
M48T35AY
M48T35AV
M48T35AV
A2
21 A10
A2
8
A10
E
A1
20
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
V
SS
SS
AI02798B
AI02799
Table 1. Signal Names
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28-
BR12SH1".
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T35AY/35AV are integrated on one silicon
chip. The two circuits are interconnected at the up-
per eight memory locations to provide user acces-
sible BYTEWIDE™ clock information in the bytes
with addresses 7FF8h-7FFFh.
A0-A14
Address Inputs
Data Inputs / Outputs
Chip Enable
DQ0-DQ7
E
G
W
Output Enable
Write Enable
Supply Voltage
Ground
V
CC
V
SS
The 28 pin 600mil DIP CAPHAT™ houses the
M48T35AY/35AV silicon with a quartz crystal and
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year), 30, and 31
day months are made automatically. Byte 7FF8h
is the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting.
2/19
M48T35AY, M48T35AV
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
Grade 1
0 to 70
T
A
Ambient Operating Temperature
Grade 6
–40 to 85
–40 to 85
°C
T
Storage Temperature (V Off, Oscillator Off)
°C
STG
CC
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
SLD
M48T35AY
M48T35AV
M48T35AY
M48T35AV
–0.3 to 7
–0.3 to 4.6
–0.3 to 7
–0.3 to 4.6
20
V
V
V
IO
V
V
Supply Voltage
CC
V
I
O
Output Current
mA
W
P
D
Power Dissipation
1
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
(1)
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
CC
V
X
High Z
IH
4.5V to 5.5V
or
3.0V to 3.6V
V
IL
V
IL
V
IL
V
D
Active
IL
IH
IH
IN
V
IL
V
V
D
Read
Active
OUT
V
IH
Read
High Z
High Z
High Z
Active
(2)
Deselect
Deselect
X
X
X
CMOS Standby
Battery Back-up Mode
V
to V
(min)
PFD
SO
≤ V
X
X
X
SO
Note: 1. X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
2. See Table 7 for details.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T35AY/35AV includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
itors the single 5V supply for an out of tolerance
condition. When V is out of tolerance, the circuit
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V . As V falls
CC
CC
below approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
The M48T35AY/35AV also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
3/19
M48T35AY, M48T35AV
Figure 3. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
DQ0-DQ7
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
V
CC
SS
AI01623
READ MODE
output data will remain valid for Output Data Hold
time (t ) but will go indeterminate until the next
Address Access.
AXQX
The M48T35AY/35AV is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
WRITE MODE
The M48T35AY/35AV is in the Write Mode when-
ever W and E are low. The start of a write is refer-
enced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
time (t
) after the last address input signal is
AVQV
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
a minimum of t
from Chip Enable or t
EHAX
WHAX
from Write Enable prior to the initiation of another
Access time (t
) or Output Enable Access time
ELQV
read or write cycle. Data-in must be valid t
DVWH
(t
).
GLQV
prior to the end of write and remain valid for t
WHDX
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
afterward. G should be kept high during write cy-
cles to avoid bus contention; although, if the output
bus has been activated by a low on E and G, a low
ed before t
, the data lines will be driven to an
AVQV
indeterminate state until t
puts are changed while E and G remain active,
. If the Address In-
AVQV
on W will disable the outputs t
after W falls.
WLQZ
4/19
M48T35AY, M48T35AV
Table 4. AC Measurement Conditions
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no longer
driven.
645Ω
DEVICE
UNDER
TEST
DATA RETENTION MODE
With valid V
applied, the M48T35AY/35AV op-
CC
C
= 100pF
(or 5pF)
1.75V
L
erates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when V
falls within the V
(max), VPFD
CC
PFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
C
includes JIG capacitance
L
AI02586
At voltages below V
(min), the user can be as-
PFD
sured the memory will be in a write protected state,
provided the V fall time is not less than t . The
CC
F
Figure 9 illustrates how a BOK check routine could
be structured.
For more information on Battery Storage Life refer
to the Application Note AN1012.
M48T35AY/35AV may respond to transient noise
spikes on V that reach into the deselect window
CC
during the time the device is sampling V . There-
CC
fore, decoupling of the power supply lines is rec-
ommended.
CLOCK OPERATIONS
Reading the Clock
When V
drops below V , the control circuit
SO
CC
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35AY/
35AV for an accumulated period of at least 7 years
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
when V
turns and V
is less than V . As system power re-
CC
SO
rises above V , the battery is dis-
SO
CC
connected, and the power supply is switched to
external V . Write protection continues until V
CC
CC
reaches V
kept high as V
inadvertent write cycles prior to processor stabili-
zation. Normal RAM operation can resume t
(min) plus t
(min). E should be
PFD
REC
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
rises past V
(min) to prevent
CC
PFD
REC
after V exceeds V
(max).
CC
PFD
Also, as V rises, the battery voltage is checked.
CC
If the voltage is less than approximately 2.5V, an
internal Battery Not OK (BOK) flag will be set. The
BOK flag can be checked after power up. If the
BOK flag is set, the first write attempted will be
blocked. The flag is automatically cleared after the
first write, and normal RAM operation resumes.
5/19
M48T35AY, M48T35AV
(1, 2)
Table 5. Capacitance
(T = 25°C)
A
Symbol
Parameter
Input Capacitance
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
10
pF
IN
IN
(3)
V
OUT
Input / Output Capacitance
10
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6A. DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
±1
µA
I
LI
IN
CC
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±5
50
3
µA
mA
mA
mA
V
I
OUT
LO
I
Outputs open
CC
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
CC1
IH
I
E = V – 0.2V
3
CC2
CC
(2)
–0.3
2.2
0.8
V
IL
V
V
V
+ 0.3
Input High Voltage
V
IH
CC
I
= 2.1mA
= –1mA
Output Low Voltage
0.4
V
OL
OH
OL
V
I
OH
Output High Voltage
2.4
V
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle.
Table 6B. DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 3.0V to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
±1
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±5
µA
I
OUT
LO
I
Outputs open
30
2
mA
mA
mA
CC
I
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC1
CC2
(2)
IH
E = V – 0.2V
2
CC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
V
V
V
V
V
IL
V
V
+ 0.3
IH
CC
V
I
= 2.1mA
= –1mA
0.4
OL
OH
OL
V
I
OH
2.4
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle.
6/19
M48T35AY, M48T35AV
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
Typ
Max
4.5
Unit
V
M48T35AY
M48T35AV
M48T35AY
M48T35AV
4.2
2.7
4.35
2.9
V
PFD
Power-fail Deselect Voltage
3.0
V
3.0
V
V
SO
Battery Back-up Switchover Voltage
V
–100mV
V
PFD
(2)
Grade 1
Grade 6
YEARS
YEARS
10
10
t
Expected Data Retention Time (at 25°C)
DR
(3)
Note: 1. All voltages referenced to V
.
SS
2. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top t = 7 years (typ).
DR
3. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
Max
Unit
t
E or W at V before Power Down
0
µs
PD
IH
(1)
V
V
(max) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
M48T35AY
M48T35AV
10
150
10
1
µs
µs
µs
µs
(2)
(min) to V
V
Fall Time
t
PFD
SS CC
FB
t
V
V
V
(min) to V
(max) V Rise Time
PFD CC
R
PFD
t
to V (min) V Rise Time
PFD CC
RB
SS
(3)
(max) to Inputs Recognized
40
200
ms
t
PFD
REC
Note: 1. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
F CC
PFD
PFD
es V
(min).
PFD
2. V
3. t
(min) to V fall time of less than t may cause corruption of RAM data.
(min) = 20ms for industrial temperature grade 6 device.
PFD
REC
SS FB
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
tDR
tREC
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
7/19
M48T35AY, M48T35AV
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48T35AY
-70
M48T35AV
-100
Symbol
Parameter
Unit
Min
Max
Min
Max
t
Read Cycle Time
70
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
(1)
Address Valid to Output Valid
70
70
35
100
100
50
t
t
AVQV
ELQV
GLQV
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
5
5
10
5
t
ELQX
GLQX
EHQZ
GHQZ
t
t
25
25
50
40
t
10
10
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
Figure 6. Read Mode AC Waveforms.
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: Write Enable (W) = High.
8/19
M48T35AY, M48T35AV
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48T35AY
-70
M48T35AV
Symbol
Parameter
-100
Unit
Min
Max
Min
100
0
Max
t
Write Cycle Time
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
0
80
80
10
10
50
50
5
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
WHDX
t
5
5
EHDX
(1, 2)
25
50
t
WLQZ
t
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
60
60
5
80
80
10
ns
ns
ns
AVWH
t
AVEH
(1, 2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Setting the Clock
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" on the for information
on Century Rollover.
Bit D7 of the Control Register 7FF8h is the WRITE
bit. Setting the WRITE bit to a '1', like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 11). Resetting the WRITE bit to a '0' then
transfers the values of all time registers 7FF9h-
7FFFh to the actual TIMEKEEPER counters and
allows normal operation to resume. The FT bit and
the bits marked as '0' in Table 11 must be written
to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next
clock update will occur within one second.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T35AY/35AV is
shipped from STMicroelectronics with the STOP
bit set to a '1'. When reset to a '0', the M48T35AY/
35AV oscillator starts within 1 second.
9/19
M48T35AY, M48T35AV
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
10/19
M48T35AY, M48T35AV
Calibrating the Clock
Figure 9. Checking the BOK Flag Status
The M48T35AY/35AV is driven by a quartz con-
trolled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency er-
ror at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T35AY/35AV improves
to better than ±4 ppm at 25°C.
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
The oscillation rate of any crystal changes with
temperature (see Figure 11). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T35AY/35AV design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
NO (BATTERY LOW)
READ?
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
AI00607
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T35AY/35AV may
require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register is set to a '1', and D7 of the Seconds Reg-
ister is a '0' (Oscillator Running), DQ0 will toggle at
512Hz during a read of the Seconds Register. Any
deviation from 512Hz indicates the degree and di-
rection of oscillator frequency shift at the test tem-
perature. For example, a reading of 512.01024Hz
would indicate a +20 ppm oscillator frequency er-
ror, requiring a –10 (WR001010) to be loaded into
the Calibration Byte for correction. Note that set-
ting or changing the Calibration Byte does not af-
fect the Frequency test output frequency.
The FT bit MUST be reset to '0' for normal clock
operations to resume. The FT bit is automatically
Reset on power-up.
For more information on calibration, see the Appli-
cation Note AN934 "TIMEKEEPER Calibration".
All the designer has to do is provide a simple utility
that accesses the Calibration byte.
11/19
M48T35AY, M48T35AV
Table 11. Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
10 Years
Year
Month
Date
Year
Month
Date
00-99
0
0
0
0
0
10 M.
01-12
01-31
10 Date
0
FT
0
CEB
CB
0
Day
Hours
Century/Day 00-01/01-07
0
10 Hours
Hour
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
Minutes
Minutes
Seconds
Control
ST
W
Seconds
R
Calibration
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to ‘0’ upon power for normal operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to ‘0’
CEB = Century Enable Bit
CB = Century Bit
Note: When CEB is set to ‘1’, CB will toggle from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of the century (dependent upon the initial value set).
When CEB is set to ‘0’, CB will not toggle.
The WRITE Bit does not need to be set to write to CEB and CB.
Figure 10. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
12/19
M48T35AY, M48T35AV
Figure 11. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
-60
-80
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
Figure 12. Supply Voltage Protection
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
V
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass ca-
pacitor value of 0.1µF (as shown in Figure 12) is
recommended in order to provide the needed fil-
tering.
CC
V
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
SS
CC
below V by as much as one Volt. These nega-
SS
tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V (cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
13/19
M48T35AY, M48T35AV
Table 12. Ordering Information Scheme
Example:
M48T35AY
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
35AY = V = 4.5V to 5.5V; V
= 4.2V to 4.5V
= 2.7V to 3.0V
CC
PFD
PFD
35AV = V = 3.0V to 3.6V; V
CC
Speed
-70 = 70ns (35AY)
-10 = 100ns (35AV)
Package
PC = PCDIP28
(1)
MH
= SOH28
Temperature Range
1 = 0 to 70 °C
(2)
6
= –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR00SH1" in plastic tube or "M4TXX-BR00SH1TR" in Tape & Reel form.
2. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery package "M4TXX-BR00SH1" in conductive foam since will drain the lithium button-cell bat-
tery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
November 1999 First Issue
04/21/00
05/29/00
From Preliminary Data to Data Sheet
change (Table 8)
t
FB
14/19
M48T35AY, M48T35AV
Table 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
Figure 13. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale.
15/19
M48T35AY, M48T35AV
Table 15. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
16/19
M48T35AY, M48T35AV
Table 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
3.20
0.018
0.835
0.560
0.126
0.080
D
E
eB
L
2.03
Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
17/19
M48T35AY, M48T35AV
Table 17. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
8.00
0.38
0.56
21.84
18.03
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
8.00
7.24
0.315
0.285
0.46
21.21
17.27
3.20
0.018
0.835
0.680
0.126
0.080
D
E
eB
L
2.03
Figure 16. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
18/19
M48T35AY, M48T35AV
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
19/19
相关型号：
©2020 ICPDF网 联系我们和版权申明