M48T37V-70MH1TR [STMICROELECTRONICS]
3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM; 3.3V - 5V 256 Kbit的32Kb的X8 TIMEKEEPER SRAM
| 型号： | M48T37V-70MH1TR |
| 厂家： | 
ST |
| 描述： | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| 文件： | 总20页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T37Y
M48T37V
3.3V-5V 256 Kbit (32Kb x8) TIMEKEEPER SRAM
■ INTEGRATED ULTRA-LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
SNAPHAT (SH)
Battery
■ FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
■ YEAR 2000 COMPLIANT
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ WATCHDOG TIMER
44
■ WRITE PROTECT VOLTAGE
1
(V
= Power-Fail Deselect Voltage):
PFD
SOH44 (MH)
– M48T37Y: 4.2V ≤ V
– M48T37V: 2.7V ≤ V
≤ 4.5V
≤ 3.0V
PFD
PFD
■ PACKAGING INCLUDES a44-LEAD SOIC and
SNAPHAT TOP (to be Ordered Separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
Figure 1. Logic Diagram
■ MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALARM OUTPUT ACTIVE
V
CC
in the BATTERY BACKED-UP
■ BATTERY LOW FLAG
15
8
A0-A14
DQ0-DQ7
Table 1. Signal Names
A0-A14
DQ0-DQ7
RST
Address Inputs
W
RST
M48T37Y
M48T37V
Data Inputs / Outputs
E
G
IRQ/FT
Power Fail Reset Output (Open Drain)
Interrupt / Frequency Test Output
(Open Drain)
IRQ/FT
WDI
WDI
E
Watchdog Input
Chip Enable
V
G
Output Enable
Write Enable
SS
AI02172
W
V
Supply Voltage
Ground
CC
V
SS
NC
Not connected Internally
February 2000
1/20
M48T37Y, M48T37V
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
Grade 1
Grade 6
SNAPHAT
SOIC
T
A
Ambient Operating Temperature
–40 to 85
–40 to 85
–55 to 125
°C
°C
T
Storage Temperature (V Off, Oscillator Off)
STG
CC
°C
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
SLD
M48T37Y
M48T37V
M48T37Y
M48T37V
–0.3 to 7
–0.3 to 4.6
–0.3 to 7
–0.3 to 4.6
10
V
V
V
IO
V
V
Supply Voltage
CC
V
I
Output Current
mA
W
O
P
Power Dissipation
1
D
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Figure 2. SOIC Connections
DESCRIPTION
The M48T37Y/37V TIMEKEEPER RAM is a
32Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in a special
package which provides a highly integrated bat-
tery backed-up memory and real time clock solu-
tion.
NC
RST
NC
NC
A14
A12
A7
1
44
43
42
41
40
39
38
37
36
35
34
V
CC
NC
2
3
NC
4
NC
The 44 lead 330mil SOIC package provides sock-
ets with gold-plated contacts at both ends for di-
rect connection to a separate SNAPHAT housing
containing the battery and crystal. The unique de-
sign allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
5
IRQ/FT
W
6
7
A13
A8
A6
8
A5
9
A9
A4
10
11
A11
G
A3
M48T37Y
NC
NC
WDI
A2
12 M48T37V 33
NC
13
14
15
16
17
18
19
20
21
22
32
31
NC
A10
E
30
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape &Reel
form. For the 44 lead SOIC, the battery/crystal
package (i.e. SNAPHAT) part number is ”M4T28-
BR12SH” or ”M4T32-BR12SH”.
A1
29
NC
A0
28
DQ7
DQ6
DQ5
DQ4
DQ3
NC
DQ0
DQ1
DQ2
NC
27
26
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
25
24
V
23
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T37Y/37V are integrated on one silicon chip.
SS
AI02174
2/20
M48T37Y, M48T37V
(1)
Table 3. Operating Modes
Mode
Deselect
Write
V
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.5V to 5.5V
(M48T37Y)
or
3.0V to 3.6V
(M48T37V)
V
V
V
V
D
IN
IL
IL
IL
IL
IH
IH
V
V
V
D
OUT
Read
Active
IL
V
Read
High Z
High Z
High Z
Active
IH
(2)
Deselect
Deselect
X
X
X
CMOS Standby
V
to V
(min)
PFD
SO
≤ V
X
X
X
Battery Back-up Mode
SO
Note: 1. X = V or V ; V = Battery Back-up Switchover Voltage.
SO
IH
IL
2. See Table 7 for details.
Figure 3. Block Diagram
IRQ/FT
WDI
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
POWER
A0-A14
LITHIUM
CELL
32,752 x
SRAM ARRAY
8
DQ0-DQ7
VOLTAGE SENSE
AND
V
E
PFD
SWITCHING
CIRCUITRY
W
G
V
RST
V
CC
SS
AI03253
3/20
M48T37Y, M48T37V
Table 4. AC Measurement Conditions
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no longer
driven.
645Ω
DEVICE
UNDER
TEST
The memory locations, to provide user accessible
BYTEWIDE clock information are in the bytes
with addresses 7FF1 and 7FF9h-7FFFh (located
in Table 11). The clock locations contain the cen-
tury, year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year-compliant until the year 2100), 30,
and 31 day months are made automatically.
1.75V
C
= 100pF
L
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
C
includes JIG capacitance
L
AI02325
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control mi-
croprocessor and provides a reset or interrupt to it.
Byte 7FF2h-7FF5h are reserved for clock alarm
programming.
Note: Excluding open-drain output pins.
These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin
when the alarm bytes match the date, hours, min-
utes and seconds of the clock. The eight clock
bytes are not the actual clock counters them-
selves; theyare memory locations consisting of Bi-
PORT read/write memory cells. The M48T37Y/
37V includes a clock control circuit which updates
the clock bytes with current information once per
second. The information can be accessed by the
user in the same manner as any other location in
the static memory array.
READ MODE
The M48T37Y/37V is in the Read Mode whenever
Write Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,752 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
) after the last address input signal is
AVQV
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
after the latter of the Chip Enable Access time
The M48T37Y/37V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
(t
) or Output Enable Access time (t
ELQV
).
GLQV
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
tors the single V
supply for an out of tolerance
CC
CC
condition. When V is out of tolerance, the circuit
ed before t
, the data lines will be driven to an
AVQV
writes protects the SRAM, providing a high degree
indeterminate state until t
.
AVQV
of data security in the midst of unpredictable sys-
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (t
nate until the next Address Access.
tem operation brought on by low V . As V falls
CC
CC
below the Battery Back-up Switchover Voltage
) but will be indetermi-
AXQX
(V ), the control circuitry connects the battery
SO
which maintains data and clock operation until val-
id power returns.
4/20
M48T37Y, M48T37V
(1, 2)
Table 5. Capacitance
A
(T = 25 °C)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
Input Capacitance
10
pF
IN
IN
(3)
V
Input / Output Capacitance
10
pF
C
IO
OUT
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
M48T37Y
M48T37V
= 3.0V to 3.6V
V
= 4.5V to 5.5V
V
Symbol
Parameter
Test Condition
Unit
CC
CC
Min
Max
Min
Max
(1)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±1
±1
µA
µA
mA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
±1
±1
I
OUT
LO
I
Outputs open
50
33
CC
Supply Current (Standby)
TTL
I
I
E = V
3
2
mA
mA
CC1
IH
Supply Current (Standby)
CMOS
E = V – 0.2V
3
2
CC2
(2)
CC
Input Low Voltage
Input High Voltage
–0.3
2.2
0.8
–0.3
0.8
V
V
V
IL
V
V
V
+ 0.3
V
+ 0.3
CC
2.2
IH
CC
Output Low Voltage
(standard)
I
= 2.1mA
OL
0.4
0.4
0.4
0.4
V
OL
Output Low Voltage
(open drain)
V
I
= 10mA
= –1mA
V
V
OL
OL
(2)
Output High Voltage
I
2.4
2.4
V
OH
OH
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
5/20
M48T37Y, M48T37V
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
A
(T = 0 to 70 °C or –40 to 85 °C)
Symbol
Parameter
Min
4.2
2.7
Typ
4.4
2.9
Max
4.5
Unit
V
M48T37Y
M48T37V
M48T37Y
M48T37V
Grade 1
V
Power-fail Deselect Voltage
PFD
3.0
V
V
V
BAT
V
Battery Back-up Switchover Voltage
SO
V
–100mV
V
PFD
7
YEARS
YEARS
5
t
Expected Data Retention Time (25°C)
DR
(2)
Grade 6
10
Note: 1. All voltages referenced to V
.
SS
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
Max
Unit
(1)
V
V
(max) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
PFD
CC
F
M48T37Y
M48T37V
10
150
10
1
µs
µs
µs
µs
(2)
(min) to V
(min) to V
V
Fall Time
t
FB
SS CC
t
V
V
V
(max) V
Rise Time
CC
R
PFD
t
to V
(min) V Rise Time
PFD CC
RB
SS
(3)
(max) to RST High
40
200
ms
t
PFD
REC
Note: 1. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after V
pass-
CC
PFD
PFD
es V
(min).
PFD
2. V
3. t
(min) to V fall time of less than t may cause corruption of RAM data.
(min) = 20ms for Industrial Temperature Range - grade 6 device.
PFD
REC
SS FB
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tDR
tREC
RST
VALID
INPUTS
DON’T CARE
HIGH-Z
VALID
OUTPUTS
VALID
VALID
AI03078
6/20
M48T37Y, M48T37V
Figure 6. Read Mode AC Waveforms.
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: Write Enable (W) = High.
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
M48T37Y
M48T37V
V
= 4.5V to 5.5V
-70
V
= 3.0V to 3.6V
CC
CC
Symbol
Parameter
Unit
-10
Min
Max
Min
Max
t
Read Cycle Time
70
100
ns
ns
AVAV
(1)
Address Valid to Output Valid
70
70
35
100
100
50
t
AVQV
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
ns
ns
ns
ns
ns
ns
ns
t
ELQV
t
GLQV
5
5
10
5
t
ELQX
t
t
GLQX
EHQZ
25
25
50
40
t
GHQZ
10
10
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
7/20
M48T37Y, M48T37V
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
WRITE MODE
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of theRAM’s content.
The M48T37Y/37V is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
At voltages below V
(min), the user can be as-
PFD
sured the memory willbe in a write protected state,
provided the V fall time is not less than t .
CC
F
The M48T37Y/37V may respond to transient noise
spikes on V that reach into the deselect window
of t
from Chip Enable or t
from Write En-
EHAX
WHAX
CC
able prior to the initiation of another read or write
cycle. Data-in must be valid t prior to the end
during the time the device is sampling V . There-
fore, decoupling of the power supply lines is rec-
ommended.
CC
DVWH
of write and remain valid for t
afterward. G
WHDX
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by alow on E and G a low on W will
When V
drops below V , the control circuit
SO
CC
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T37Y/37V
for an accumulated period of at least 7 years at
disable the outputs t
after W falls.
WLQZ
DATA RETENTION MODE
With valid V applied, the M48T37Y/37V oper-
room temperature when V is less than V . As
CC
SO
system power returns and V
rises above V
,
CC
CC
SO
ates as a conventional BYTEWIDE static RAM.
Should the Supply Voltage decay, the RAM will
automatically power-fail deselect, write protecting
the battery is disconnected, and the power supply
is switched to external V . Normal RAM opera-
CC
tion can resume t
(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
after V
reaches V
CC PFD
REC
itself when V falls within the V
(max), V
CC
PFD
PFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as ”don’t care”.
8/20
M48T37Y, M48T37V
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
M48T37Y
= 4.5V to 5.5V
-70
M48T37V
V
V
= 3.0V to 3.6V
CC
CC
Symbol
Parameter
Unit
-10
Min
70
0
Max
Min
100
0
Max
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
0
80
80
10
10
50
50
5
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
ELEH
t
t
t
WHAX
t
0
EHAX
30
30
5
DVWH
t
DVEH
WHDX
t
5
5
EHDX
(1, 2)
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
25
50
ns
ns
ns
ns
t
WLQZ
t
60
60
5
80
80
10
AVWH
t
AVEH
(1, 2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
9/20
M48T37Y, M48T37V
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
POWER-ON RESET
The M48T37Y/37V continuously monitors V
7FF6h and the Watchdog Steering (WDS) bit in
7FF7h allow the interrupt to activate the IRQ/FT
pin.
.
CC
When V
falls to the power fail detect trip point,
CC
the RST pulls low (open drain) and remains low on
power-up for 40ms to 200ms after V passes
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
condition reset will not occur unless the addresses
are stable at the flag location for at least 15ns
while the device is in the read mode as shown in
Figure 11.
CC
V
. RST is valid for all V conditions. The RST
PFD
CC
pin is an open drain output and an appropriate re-
sistor to V should be chosen to control rise time.
CC
PROGRAMMABLE INTERRUPTS
The IRQ/FT pin is an open drain output and re-
The M48T37Y/37V provides two programmable
interrupts; an alarm and a watchdog. When an in-
terrupt condition occurs, the M48T37Y/37V sets
the appropriate flag bit in the flag register 7FF0h.
The interrupt enable bits in (AFE and ABE) in
quires a pull-up resistor (10kΩ recommended) to
V
. The pin remains in the high impedance state
CC
unless an interrupt occurs or the frequency test
mode is enabled.
10/20
M48T37Y, M48T37V
Table 11. Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
10 M
0
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
10 Years
Year
Year
Month
00-99
01-12
01-31
01-7
0
0
0
0
0
Month
10 Date
Date: Day of Month
Day of Week
Hours
Date
0
FT
0
0
0
Day
0
10 Hours
Hour
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
Minutes
Min
ST
Seconds
Sec
W
R
Calibration
Control
Watchdog
Interrupts
Alarm Date
Alarm Hour
Alarm Min
Alarm Sec
Century
Flags
WDS
AFE
RPT4
RPT3
RPT2
RPT1
BMB4
BMB3
BMB2
0
BMB1
0
BMB0
0
RB1
0
RB0
0
0
0
0
ABE
AIarm 10 Date
AIarm 10 Hours
Alarm Date
01-31
00-23
00-59
00-59
00-99
Alarm Hours
Alarm Minutes
Alarm Seconds
100 Year
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
WDF
AF
Z
BL
Z
Z
Z
Z
Keys: S = Sign Bit
FT = Frequency Test Bit
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to ’0’
BL = Battery Low Flag
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
AF = Alarm Flag
BMB0-BMB4 = Watchdog Multiplier Bits
Z = ’0’ and are Read only
CLOCK OPERATIONS
Reading the Clock
progress. Updating will resumewithin a second af-
ter the bit is reset to a ’0’.
Setting the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ‘1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ‘1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
Bit D7 of the Control Register (7FF8h) is the
WRITE bit. Setting the WRITE bit to a ‘1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 11). Resetting the WRITE bit to
a ‘0’ then transfers the values of all time registers
(7FF1h, 7FF9h-7FFFh) to the actual TIMEKEEP-
ER counters and allows normal operation to re-
sume. After the WRITE bit is reset, the next clock
update will occur in approximately one second.
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
11/20
M48T37Y, M48T37V
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
= -0.038
(T - T0)2 ± 10%
∆F
F
ppm
C2
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Stopping and Starting the Oscillator
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ‘1’ stops the oscillator. When reset to a ’0’, the
M48T37Y/37V oscillator starts within one second.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ‘1’ indi-
cates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary ‘1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Calibrating the Clock
The M48T37Y/37V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 ppm
(parts per million) oscillator frequency error at
25 °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T37Y/37V improves to bet-
ter than +1/–2 ppm at 25 °C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T37Y/37V design, however, employs pe-
riodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 (64 minutes x 60 seconds/
minute x 32,768 cycles/second) actual oscillator
cycles, that is +4.068 or –2.034 ppm of adjustment
per calibration step in the calibration register. As-
suming that the oscillator is in fact running at ex-
actly 32,768 Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35
12/20
M48T37Y, M48T37V
Figure 11. Interrupt Reset Waveforms
A0-A14
ADDRESS 7FF0h
15ns Min
ACTIVE FLAG BIT
IRQ/FT
AI01677B
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month.
SETTING ALARM CLOCK
Registers 7FF5h-7FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
predetermined time on a specific day of the month
or repeat every day, hour, minute, or second. It
can also be programmed to go off while the
M48T37Y/37V is in the battery back-up mode of
operation to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 12 shows the possible configura-
tions. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Two methods are available for ascertaining how
much calibration a given M48T37Y/37V may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWW broad-
casts). While that may seem crude, it allows the
designer to give the end user the ability to calibrate
his clock as his environment may require, even af-
ter the final product is packaged in a non-user ser-
viceable enclosure. All the designer has to do is
provide a simple utility that accesses the Calibra-
tion byte.
Note: User must transition address (or toggle chip
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz when the
Stop bit (ST, D7 of 7FF9h) is ‘0’, the Frequency
Test Bit (FT, D6 of 7FFCh) is ‘1’, the Alarm Flag
Enable Bit (AFE, D7 of 7FF6h) is ‘0’, and the
Watchdog Steering bit (WDS, D7 of 7FF7h) is ‘1’
or the Watchdog Register is reset (7FF7h=0).
enable) to see Flag bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF is set. If AFE is also set, the
alarm condition activates the IRQ/FT pin. To dis-
able alarm, write ’0’ to the Alarm Date registers
and RPT1-4. The alarm flag and the IRQ/FT out-
put are cleared by a read to the Flags register.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. Forexample, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10(WR001010) to be loaded
into the Calibration Byte for correction. Note that
setting or changing the Calibration Byte does not
affect the Frequency test output frequency.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT bit is cleared on pow-
er-down.
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both Alarm in Battery Back-up
Mode Enable (ABE) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T37Y/37V was in the deselect mode
during power-up. Figure 12 illustrates the back-up
mode alarm timing.
For more information on calibration, see the Appli-
cation Note AN934 ”TIMEKEEPER Calibration”.
13/20
M48T37Y, M48T37V
Figure 12. Back-up Mode Alarm Waveforms
tREC
V
CC
V
V
(max)
(min)
PFD
PFD
V
SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03254B
Table 12. Alarm Repeat Mode
If the processor does not reset the timer within the
specified period, the M48T37Y/37V sets the
Watchdog Flag (WDF) and generates a watchdog
interrupt or a microprocessor reset. WDF is reset
by reading the Flags Register (Address 1FF0h).
RPT4 RPT3
RPT2
RPT1 Alarm Activated
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Once per Second
Once per Minute
Once per Hour
Once per Day
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a ‘0’, the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a ‘1’, the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40ms to 200ms. The Watchdog register and
the FT bit will reset to a ’0’ at the end of a Watch-
dog time-out when the WDS bit is set to a ‘1’.
Once per Month
The watchdog timer resets when the microproces-
sor performs a re-write of the Watchdog Register
or an edge transition, (low to high / high to low) on
the WDI pin occurs. The time-out period then
starts over.
The watchdog timer is disabled by writing a value
of 00000000 to the eight bits in the Watchdog Reg-
ister. Should the watchdog timer time out, a value
of 00h needs to be written to the Watchdog Regis-
ter in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied. The WDI
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight bit Watchdog Register, ad-
dress 7FF7h. The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1-
RB0) select the resolution, where 00 = 1/16 sec-
ond, 01 = 1/4second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five bit multi-
plier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3x1
or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
pin should be connected to V if not used.
SS
14/20
M48T37Y, M48T37V
Table 13. Default Values
Condition
WATCHDOG
W
R
FT
AFE
ABE
(1)
Register
Initial Power-up
0
0
0
0
0
0
(2)
(Battery Attach for SNAPHAT)
(3)
0
0
0
0
0
0
0
1
0
1
0
0
Subsequent Power-up / RESET
(4)
Power-down
Note: 1. WDS, BMB0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to ’1’ prior to power-down.
Figure 13. Supply Voltage Protection
applied to the device. Thus applications which re-
quire extensive durations in the battery back-up
mode should be powered-up periodically (at least
once every few months) in order for this technique
to be beneficial. Additionally, if a battery low is in-
dicated, data integrity should be verified upon
power-up via a checksum or other technique.
V
CC
V
CC
POWER-ON DEFAULTS
0.1µF
DEVICE
Upon application of power to the device, the fol-
lowing register bits are set to a ’0’ state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT.
V
SS
(See Table 13).
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
AI02169
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
BATTERY LOW FLAG
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
The M48T37Y/37V automatically performs period-
ic battery voltage monitoring upon power-up. The
Battery Low Flag (BL), Bit D4 of Flags Register
7FF0h, will be asserted high if the SNAPHAT bat-
tery is found to be less than approximately 2.5V.
The BL flag will remain active until completion of
battery replacement and subsequent battery low
monitoring tests, during the next power-up se-
quence.
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling cangenerate neg-
ative voltage spikes on V that drive it to values
CC
If a battery lowis generated during a power-up se-
quence, this indicates that the battery voltage is
below 2.5V (approximately), which may be insuffi-
cient to maintain data integrity. Data should be
considered suspect and verified as correct. A fresh
battery should be installed.
below V by as much as one Volt. These nega-
SS
tive spikes can cause data corruptionin the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
nect a schottky diode from V
to V (cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
Note: Battery monitoring is a useful technique only
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
when performed periodically. The M48T37Y/37V
only monitors the battery when a nominal V
is
CC
15/20
M48T37Y, M48T37V
Table 14. Ordering Information Scheme
Example:
M48T37Y
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
37Y = V = 4.5V to 5.5V; V
= 4.2V to 4.5V
= 2.7V to 3.0V
CC
PFD
PFD
37V = V = 3.0V to 3.6V; V
CC
Speed
-70 = 70ns
-10 = 100ns
Package
(1)
MH
= SOH44
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number
”M4TXX-BR12SH1” in plastic tube or ”M4TXX-BR12SH1TR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package ”M4TXX-BR12SH1” in conductive foam since will drain the lithium
button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Table 15. Revision History
Date
Revision Details
December 1999 First Issue
From Preliminary Data to Data Sheet
Battery Low Flag paragraph changed
100ns speed class identifier changed (Tables 9, 10 and 14)
02/07/00
16/20
M48T37Y, M48T37V
Table 16. SOH44 - 44 lead Plastic Small Outline, 4-socket SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
Figure 14. SOH44 - 44 lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
17/20
M48T37Y, M48T37V
Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
18/20
M48T37Y, M48T37V
Table 18. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 16. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
19/20
M48T37Y, M48T37V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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20/20
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