M48Z128V-85PM1 [STMICROELECTRONICS]
5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER? SRAM; 5.0 V或3.3 V ， 1兆位（ 128千位×8 ） ZEROPOWER ？ SRAM
| 型号： | M48Z128V-85PM1 |
| 厂家： | 
ST |
| 描述： | 5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER? SRAM |
| 文件： | 总20页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z128
M48Z128Y, M48Z128V
5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■ Conventional SRAM operation; unlimited
WRITE cycles
■ 10 years of data retention in the absence of
power
■ Battery internally isolated until power is first
applied
32
■ Automatic power-fail chip deselect and WRITE
1
protection
■ WRITE protect voltages:
(V
= power-fail deselect voltage)
PFD
PMDIP32 module (PM)
– M48Z128: V = 4.75 to 5.5 V
CC
4.5 V ≤ V
≤ 4.75 V
PFD
– M48Z128Y: V = 4.5 to 5.5 V
CC
4.2 V ≤ V
≤ 4.5 V
PFD
– M48Z128V: V = 3.0 to 3.6 V
CC
2.8 V ≤ V
≤ 3.0 V
PFD
(contact ST sales office for availability)
■ Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
July 2010
Doc ID 2426 Rev 5
1/20
www.st.com
1
Contents
M48Z128, M48Z128Y, M48Z128V
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
4
5
6
7
8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 16
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 2426 Rev 5
3/20
List of figures
M48Z128, M48Z128Y, M48Z128V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Description
1
Description
®
The M48Z128/Y/V ZEROPOWER RAM is a 128 Kbit x 8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM
and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated battery-
backed memory solution.
The M48Z128/Y/V is a non-volatile pin and function equivalent to any JEDEC standard
128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets,
providing the non-volatility of PROMs without any requirement for special WRITE timing or
limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP
module houses the M48Z128/Y/V silicon with a long-life lithium button cell in a single
package.
Figure 1.
Logic diagram
V
CC
17
8
A0-A16
DQ0-DQ7
M48Z128
M48Z128Y
M48Z128V
W
E
G
V
SS
AI01194
Table 1.
Signal names
A0-A16
Address inputs
DQ0-DQ7
Data inputs / outputs
Chip enable input
Output enable input
WRITE enable input
Supply voltage
E
G
W
VCC
VSS
NC
Ground
Not connected internally
Doc ID 2426 Rev 5
5/20
Description
M48Z128, M48Z128Y, M48Z128V
Figure 2.
DIP connections
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A15
30 NC
29
W
28 A13
27 A8
26 A9
25 A11
A6
A5
M48Z128
M48Z128Y
M48Z128V
A4
A3
24
23 A10
22
G
A2 10
A1 11
E
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
V
16
SS
AI01195
Figure 3.
Block diagram
V
CC
A0-A16
DQ0-DQ7
POWER
E
131,072 x 8
VOLTAGE SENSE
AND
SRAM ARRAY
E
SWITCHING
CIRCUITRY
W
G
INTERNAL
BATTERY
V
SS
AI01196
6/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Operating modes
2
Operating modes
The M48Z128/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single V supply for an out of tolerance condition. When V is out of
CC
CC
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V . As V falls below the
CC
CC
switchover voltage (V ), the control circuitry connects the battery which maintains data
SO
until valid power returns.
Table 2.
Mode
Operating modes
VCC
E
G
W
DQ0-DQ7
Power
Deselect
WRITE
READ
4.75 to 5.5 V
or
VIH
VIL
VIL
X
X
X
High Z
DIN
Standby
Active
VIL
VIH
4.5 to 5.5 V
or
VIL
DOUT
Active
READ
VIL
VIH
VIH
High Z
Active
3.0 to 3.6 V
Deselect
Deselect
V
SO to VPFD (min)(1)
X
X
X
X
X
X
High Z
High Z
CMOS standby
(1)
≤ VSO
Battery backup mode
1. See Table 10 on page 15 for details.
Note:
X = V or V ; V = battery backup switchover voltage.
IH IL SO
2.1
READ mode
The M48Z128/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
1,048,576 locations in the static storage array. Thus, the unique address specified by the 17
address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t
) after the last
AVQV
address input signal is stable, providing that the E and G (output enable) access times are
also satisfied. If the E and G access times are not met, valid data will be available after the
later of chip enable access time (t
) or output enable access time (t
). The state of
ELQV
GLQV
the eight three-state data I/O signals is controlled by E and G. If the outputs are activated
before t , the data lines will be driven to an indeterminate state until t . If the address
AVQV
AVQV
inputs are changed while E and G remain low, output data will remain valid for output data
hold time (t ) but will go indeterminate until the next address access.
AXQX
Doc ID 2426 Rev 5
7/20
Operating modes
Figure 4.
M48Z128, M48Z128Y, M48Z128V
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
A0-A16
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Note:
WRITE enable (W) = high.
Figure 5.
Address controlled, READ mode AC waveforms
tAVAV
VALID
A0-A16
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI01078
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.
Table 3.
Symbol
READ mode AC characteristics
Parameter(1)
M48Z128/Y M48Z128/Y/V M48Z128/Y/V
–70
–85
Max
–120
Unit
Min Max Min
Min
Max
tAVAV READ cycle time
70
85
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV Address valid to output valid
tELQV Chip enable low to output valid
70
70
35
85
85
45
120
120
60
tGLQV Output enable low to output valid
(2)
tELQX
tGLQX
tEHQZ
tGHQZ
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
5
3
5
3
5
3
(2)
(2)
(2)
30
20
35
25
45
35
tAXQX Address transition to output transition
5
5
10
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
2. CL = 5 pF.
8/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Operating modes
2.2
WRITE mode
The M48Z128/Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for
minimum of t
from E or t
from W prior to the initiation of another READ or WRITE
EHAX
WHAX
cycle. Data-in must be valid t
prior to the end of WRITE and remain valid for t
or
DVWH
WHDX
t
afterward. G should be kept high during WRITE cycles to avoid bus contention;
EHDX
although, if the output bus has been activated by a low on E and G, a low on W will disable
the outputs t
after W falls.
WLQZ
Figure 6.
WRITE enable controlled, WRITE AC waveforms
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DATA INPUT
tDVWH
DQ0-DQ7
AI01198
Note:
Output enable (G) = high.
Figure 7.
Chip enable controlled, WRITE AC waveforms
tAVAV
VALID
A0-A16
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01199
Note:
Output enable (G) = high.
Doc ID 2426 Rev 5
9/20
Operating modes
M48Z128, M48Z128Y, M48Z128V
Table 4.
Symbol
WRITE mode AC characteristics
M48Z128/Y M48Z128/Y/V M48Z128/Y/V
Parameter(1)
–70
–85
–120
Unit
Min Max
Min
Max
Min
Max
tAVAV
tAVWL
tAVEL
WRITE cycle time
70
0
85
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to WRITE enable Low
Address valid to chip enable low
WRITE enable pulse width
0
0
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
55
55
5
65
75
5
85
100
5
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
15
30
30
0
15
35
35
0
15
45
45
0
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
10
25
65
65
5
10
10
(2)(3)
tWLQZ
30
40
tAVWH
tAVEH
75
75
5
100
100
5
(2)(3)
tWHQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
™
With valid V applied, the M48Z128/Y/V operates as a conventional BYTEWIDE static
CC
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself t
after V falls below V
. All outputs become high impedance, and all
WP
CC
PFD
inputs are treated as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time t , write protection takes
WP
place. When V drops below V , the control circuit switches power to the internal energy
CC
SO
source which preserves data.
The internal coin cell will maintain data in the M48Z128/Y/V after the initial application of
for an accumulated period of at least 10 years when V is less than V . As system
V
CC
CC
SO
power returns and V rises above V , the battery is disconnected, and the power supply
CC
SO
is switched to external V . Write protection continues for t after V reaches V to
CC
ER
CC
PFD
allow for processor stabilization. After t , normal RAM operation can resume.
ER
For more information on battery storage life refer to the application note AN1012.
10/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Operating modes
2.4
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8)
is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from V to V (cathode connected to V , anode to V ). (Schottky diode 1N5817
CC
SS
CC
SS
is recommended for through hole and MBRS120T3 is recommended for surface-mount).
Figure 8.
Supply voltage protection
V
CC
V
V
CC
0.1µF
DEVICE
SS
AI02169
Doc ID 2426 Rev 5
11/20
Maximum ratings
M48Z128, M48Z128Y, M48Z128V
3
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Temperature under bias
0 to 70
–40 to 85
–10 to 70
260
°C
°C
°C
°C
V
TSTG
TBIAS
(1)
TSLD
Lead solder temperature for 10 seconds
Input or output voltages
VIO
–0.3 to 7
–0.3 to 7.0
–0.3 to 4.6
20
M48Z128/Y
M48Z128V
V
VCC
Supply voltage
V
IO
Output current
mA
W
PD
Power dissipation
1
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
12/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
DC and AC parameters
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
Supply voltage (VCC
M48Z128/Y
M48Z128V
Unit
)
4.75 to 5.5 V or 4.5 to 5.5
3.0 to 3.6
0 to 70
50
V
°C
pF
ns
V
Ambient operating temperature (TA)
Load capacitance (CL)
0 to 70
100
Input rise and fall times
≤ 5
≤ 5
Input pulse voltages
0 to 3
1.5
0 to 3
1.5
Input and output timing ref. voltages
V
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9. AC measurement load circuit
650Ω
DEVICE
UNDER
TEST
1.75V
C
= 100pF
L
or 50pF(1)
C
includes JIG capacitance
L
AI03630
1. 50 pF for M48Z128V (3.3 V).
Table 7.
Symbol
CIN
Capacitance
Parameter(1)(2)
Min
Max
Unit
Input capacitance
-
-
10
10
pF
pF
(3)
CIO
Input / output capacitance
1. Effective capacitance measured with power supply at 5 V (M48Z128/Y) or 3.3 V (M48Z128V); sampled
only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Doc ID 2426 Rev 5
13/20
DC and AC parameters
M48Z128, M48Z128Y, M48Z128V
Table 8.
Sym
DC characteristics
M48Z128/Y
–70 / –85 / –120
M48Z128V
–85 / –120
Parameter
Test condition(1)
Unit
Min
Max
Min
Max
ILI
Input leakage current
Output leakage current
0 V ≤ VIN ≤ VCC
1
1
1
1
µA
µA
(2)
ILO
0 V ≤ VOUT ≤ VCC
E = VIL
ICC
Supply current
105
50
mA
Outputs open
ICC1 Supply current (standby) TTL
ICC2 Supply current (standby) CMOS
E = VIH
7
4
4
3
mA
mA
V
E = VCC – 0.2 V
VIL
VIH
VOL
Input low voltage
Input high voltage
Output low voltage
–0.3
2.2
0.8
–0.3
2.2
0.6
VCC + 0.3
0.4
VCC + 0.3
0.4
V
IOL = 2.1 mA
IOH = –1 mA
V
VOH Output high voltage
2.4
2.2
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where
noted).
2. Outputs deselected.
14/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Figure 10. Power down/up mode AC waveforms
DC and AC parameters
V
V
CC
PFD
(max)
(min)
V
V
PFD
SO
tF
tDR
tR
tFB
tRB
tWP
tER
RECOGNIZED
RECOGNIZED
E
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01031
Table 9.
Symbol
Power down/up AC characteristics
Parameter(1)
Min
Max
Unit
(2)
tF
VPFD (max) to VPFD (min) VCC fall time
300
10
150
10
1
µs
M48Z128/Y
M48Z128V
(3)
tFB
VPFD (min) to VSS VCC fall time
µs
tR
VPFD (min) to VPFD (max) VCC rise time
VSS to VPFD (min) VCC rise time
µs
µs
tRB
M48Z128/Y
M48Z128V
40
40
40
150
250
120
tWP
tER
Write protect time
E recovery time
µs
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max
Unit
M48Z128
M48Z128Y
M48Z128V
M48Z128/Y
M48Z128V
4.5
4.2
2.8
4.6
4.3
2.9
3.0
2.5
4.75
4.5
V
VPFD
Power-fail deselect voltage
V
3.0
V
V
V
VSO
Battery backup switchover voltage
Expected data retention time
(3)
tDR
10
YEARS
1. All voltages referenced to VSS
.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
3. At 25 °C; VCC = 0 V.
Doc ID 2426 Rev 5
15/20
Package mechanical data
M48Z128, M48Z128Y, M48Z128V
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Note:
Drawing is not to scale.
Table 11. PMDIP32 – 32-pin plastic DIP module, package mechanical data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
B
9.27
0.38
9.52
–
0.365
0.015
0.017
0.008
1.670
0.710
0.090
0.375
–
0.43
0.59
0.33
43.18
18.80
2.79
0.023
0.013
1.700
0.740
0.110
C
0.20
D
42.42
18.03
2.29
E
e1
e3
eA
L
38.1
1.5
14.99
3.05
1.91
32
16.00
3.81
2.79
0.590
0.120
0.075
32
0.630
0.150
0.110
S
N
16/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Part numbering
6
Part numbering
Table 12. Ordering information scheme
Example:
M48Z
128Y
–70
PM
1
Device type
M48Z
Supply voltage and write protect voltage
128 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
128Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
128V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed
–70 = 70 ns (for M48Z128/Y)
–85 = 85 ns (for M48Z128/Y/V)
–120 = 120 ns (for M48Z128/Y/V)
Package
PM = PMDIP32
Temperature range
1 = 0 to 70 °C
Shipping method
blank = ECOPACK® package, tubes
1. Contact local ST sales office for availability
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 2426 Rev 5
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Environmental information
M48Z128, M48Z128Y, M48Z128V
7
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
18/20
Doc ID 2426 Rev 5
M48Z128, M48Z128Y, M48Z128V
Revision history
8
Revision history
Table 13. Revision history
Date
Revision
Changes
May-1999
13-Apr-2000
20-Jun-2000
19-Jul-2000
14-Sep-2001
07-Nov-2001
20-May-2002
18-Nov-2002
1
First issue
2
Document layout changed; surface-mount chip set solution added
tGLQX changed (Table 3)
2.1
2.2
3
M48Z128V added
Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10)
Remove chipset option from ordering Information (Table 12)
Modify reflow time and temperature footnotes (Table 5)
Modifying SMT solution text (Figure 2, 4;Table 2)
3.1
3.2
3.3
Remove references to M68ZXXX (obsolete) parts (Figure 4; Table 2);
update disclaimer
17-Sep-2003
22-Feb-2005
3.4
4
Reformatted; IR reflow, SO package updates (Table 5)
Reformatted document; updated Features, Section 3: Maximum ratings,
Table 11, 12; added ECOPACK® text to Section 5; added Section 7:
Environmental information; removed SOH28, SNAPHAT® housing and
all references from datasheet.
20-Jul-2010
5
Doc ID 2426 Rev 5
19/20
M48Z128, M48Z128Y, M48Z128V
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Doc ID 2426 Rev 5
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