M48Z2M1PL [STMICROELECTRONICS]
16 Mb 2Mb x 8 ZEROPOWER SRAM; 16兆的2Mb ×8 ZEROPOWER SRAM
| 型号： | M48Z2M1PL |
| 厂家： | 
ST |
| 描述： | 16 Mb 2Mb x 8 ZEROPOWER SRAM |
| 文件： | 总12页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z2M1
M48Z2M1Y
®
16 Mb (2Mb x 8) ZEROPOWER SRAM
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
36
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
1
PMLDIP36 (PL)
Module
– M48Z2M1: 4.5V ≤ VPFD ≤ 4.75V
– M48Z2M1Y: 4.2V ≤ VPFD ≤ 4.50V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Mb x 8 SRAMs
Figure 1. Logic Diagram
DESCRIPTION
The M48Z2M1/2M1Y ZEROPOWER® RAM is a
non-volatile 16,777,216 bit Static RAM organized
as 2,097,152 words by 8 bits. Thedevicecombines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36 pin DIP long Module.
V
CC
The ZEROPOWER RAM replaces industry stand-
ard SRAMs. It provides the nonvolatility of PROMs
without any requirement for special write timing or
limitations on the number of writes that can be
performed.
21
8
A0-A20
W
DQ0-DQ7
M48Z2M1
M48Z2M1Y
Table 1. Signal Names
E
A0-A20
Address Inputs
Data Inputs / Outputs
Chip Enable
G
DQ0-DQ7
E
V
SS
G
Output Enable
Write Enable
Supply Voltage
Ground
AI02048
W
VCC
VSS
January 1998
1/12
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M48Z2M1, M48Z2M1Y
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
0 to 70
Unit
°C
°C
°C
°C
V
Ambient Operating Temperature
Storage Temperature (VCC Off)
Temperature Under Bias
TSTG
TBIAS
–40 to 85
–40 to 85
260
(2)
TSLD
Lead Soldering Temperature for 10 seconds
Input or Output Voltages
VIO
–0.3 to 7
–0.3 to 7
VCC
Supply Voltage
V
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
Deselect
Write
VCC
E
VIH
VIL
VIL
VIL
X
G
X
W
X
DQ0-DQ7
High Z
DIN
Power
Standby
4.75V to 5.5V
or
4.5V to 5.5V
X
VIL
VIH
VIH
X
Active
Read
VIL
VIH
X
DOUT
Active
Read
High Z
High Z
High Z
Active
Deselect
Deselect
VSO to VPFD (min)
CMOS Standby
Battery Back-up Mode
≤ VSO
X
X
X
Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
DESCRIPTION (cont’d)
The M48Z2M1/2M1Yhas its own Power-fail Detect
Circuit. The controlcircuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a highdegree of data
security in the midst of unpredictable system op-
erations brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
batteries which sustain data until valid power re-
turns.
NC
A20
A18
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
36
V
CC
35 A19
34 NC
33 A15
32 A17
31
W
30 A13
29 A8
28 A9
27 A11
A6
M48Z2M1
M48Z2M1Y
A5
READ MODE
A4 10
A3 11
The M48Z2M1/2M1Y is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripple-
through access of data from eight of 16,777,216
locations in the static storage array. Thus, the
unique address specified by the 21 Address Inputs
defines which one of the 2,097,152 bytes of data is
to be accessed. Valid data will be available at the
26
25 A10
24
G
A2 12
A1 13
E
A0 14
23 DQ7
22 DQ6
21 DQ5
20 DQ4
19 DQ3
DQ0 15
DQ1 16
DQ2 17
Data I/O pins within Address Access time (tAVQV
)
V
18
SS
after the last address input signal is stable, provid-
ing that the E (Chip Enable) and G (Output Enable)
access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
AI02049
Warning: NC = Not Connected.
2/12
M48Z2M1, M48Z2M1Y
Figure 3. Block Diagram
V
CC
A0-A20
DQ0-DQ7
POWER
E
2048K x 8
SRAM ARRAY
VOLTAGE SENSE
AND
E
SWITCHING
CIRCUITRY
W
G
INTERNAL
BATTERIES
V
SS
AI02050
able after the later of Chip Enable Access time
(tELQV) or Output Enable Access Time (tGLQV). The
state of the eight three-state Data I/O signals is
controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain low, output
data will remain valid for Output Data Hold time
(tAXQX) but will go indeterminate until the next Ad-
dress Access.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
1.5V
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
WRITE MODE
The M48Z2M1/2M1Y is in the Write Mode when-
ever W and E are active. The start of a write is
referenced from the latter occurring falling edge of
W or E. A write is terminated by the earlier rising
edge of W or E.
1.9kΩ
DEVICE
UNDER
TEST
OUT
The addresses must be held valid throughout the
cycle. Eor W must return high for minimum of tEHAX
from E or tWHAX from W prior to the initiation of
another read or write cycle. Data-in must be valid
tDVEH or tDVWH prior to the end of write and remain
valid for tEHDX or tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs
tWLQZ after W falls.
1kΩ
C
= 100pF or 5pF
L
C
includes JIG capacitance
L
AI01030
3/12
M48Z2M1, M48Z2M1Y
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
VIN = 0V
Min
Max
40
Unit
pF
CIN
Input Capacitance
(3)
CIO
Input / Output Capacitance
VOUT = 0V
40
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
Table 6. DC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, Outputs open
E = VIH
Min
Max
Unit
µA
µA
mA
mA
mA
V
(1)
ILI
±4
±4
(1)
ILO
ICC
140
10
ICC1
ICC2
VIL
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
E ≥ VCC – 0.2V
8
–0.3
2.2
0.8
VIH
Input High Voltage
VCC + 0.3
0.4
V
VOL
VOH
Output Low Voltage
IOL = 2.1mA
IOH = –1mA
V
Output High Voltage
2.4
V
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70°C)
Symbol
VPFD
Parameter
Power-fail Deselect Voltage (M48Z2M1)
Power-fail Deselect Voltage (M48Z2M1Y)
Battery Back-up Switchover Voltage
Data Retention Time
Min
4.5
4.2
Typ
4.6
4.3
3
Max
4.75
4.5
Unit
V
VPFD
V
V
VSO
(2)
tDR
10
YEARS
Notes: 1. All voltages referenced to VSS
.
2. At 25°C
4/12
M48Z2M1, M48Z2M1Y
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C)
Symbol
Parameter
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
Write Protect Time from VCC = VPFD
VSO to VPFD (max) VCC Rise Time
E Recovery Time
Min
300
10
40
0
Max
Unit
µs
(1)
tF
(2)
tFB
µs
tWP
tR
150
120
µs
µs
tER
40
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tFB
tWP
tER
RECOGNIZED
RECOGNIZED
E
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01031
5/12
M48Z2M1, M48Z2M1Y
Table 9. Read Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z2M1 / M48Z2M1Y
-70
Symbol
Parameter
Unit
Min
Max
tAVAV
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAVQV
Address Valid to Output Valid
70
70
35
(1)
tELQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
(1)
tGLQV
(2)
tELQX
5
5
(2)
tGLQX
(2)
tEHQZ
30
25
(2)
tGHQZ
(1)
tAXQX
5
Notes: 1. CL = 100pF (see Figure 4).
2. CL = 5pF (see Figure 4)
Figure 6. Address Controlled, Read Mode AC Waveforms
A0-A20
tAVAV
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI02051
Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
6/12
M48Z2M1, M48Z2M1Y
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
VALID
A0-A20
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI02052
Note: Write Enable (W) = High.
DATA RETENTION MODE
low VSO, the control circuit switches power to the
internal energy source which preserves data.
With valid VCC applied, the M48Z2M1/2M1Y oper-
ates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as "don’t care."
If power fail detection occurs during a valid access,
the memory cycle continues to completion. If the
memory cycle fails to terminate within the time tWP
write protection takes place. When VCC drops be-
The internal coin cells will maintain data in the
M48Z2M1/2M1Y after the initial application of VCC
foran accumulated periodof at least 10years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the batteries are discon-
nected, and the power supply is switched to exter-
nal Vcc. Write protection continues for tER after VCC
reaches VPFD to allow for processor stabilization.
After tER, normal RAM operation can resume.
,
For more information on Battery Storage life refer
to the Application Note AN1012.
7/12
M48Z2M1, M48Z2M1Y
Table 10. Write Mode AC Characteristics
(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z2M1 / M48Z2M1Y
-70
Symbol
Parameter
Unit
Min
70
0
Max
tAVAV
tAVWL
tAVEL
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
55
55
5
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
15
30
30
0
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
10
(1,2)
tWLQZ
25
tAVWH
tAVEH
65
65
5
(1,2)
tWHQX
Notes: 1. CL = 5pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high-impedance state.
Figure 8. Supply Voltage Protection
POWER SUPPLY DECOUPLING and UNDER-
SHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A bypass capacitor value
of 0.1µF (as shown in Figure 8) is recommended
in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
V
CC
V
V
CC
0.1µF
DEVICE
SS
AI02169
8/12
M48Z2M1, M48Z2M1Y
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A20
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02053
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A20
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02054
Note: Output Enable (G) = High.
9/12
M48Z2M1, M48Z2M1Y
ORDERING INFORMATION SCHEME
Example:
M48Z2M1Y
-70
PL
1
Supply Voltage and Write
Protect Voltage
Speed
Package
Temp. Range
2M1
VCC = 4.75V to 5.5V
PFD = 4.5V to 4.75V
-70
70ns
PL
PMLDIP36
1
9 (1)
0 to 70°C
V
Extended
2M1Y VCC = 4.5V to 5.5V
PFD = 4.2V to 4.5V
Temperature
V
Note: 1. Contact Sales Offices for availability of Extended Temperature.
For a list of available options (Speed, Package, etc.) or for further information or any aspect of this device,
please contact the SGS-THOMSON Sales Office nearest to you.
10/12
M48Z2M1, M48Z2M1Y
PMLDIP36 - 36 pin Plastic DIP Long Module
mm
Min
inches
Min
Symb
Typ
Max
9.52
–
Typ
Max
0.375
–
A
A1
B
9.27
0.38
0.43
0.20
52.58
18.03
2.30
38.86
14.99
3.05
4.45
36
0.365
0.015
0.017
0.008
2.070
0.710
0.090
1.530
0.590
0.120
0.175
36
0.59
0.33
53.34
18.80
2.81
47.50
16.00
3.81
5.33
0.023
0.013
2.100
0.740
0.110
1.870
0.630
0.150
0.210
C
D
E
e1
e3
eA
L
S
N
PMLDIP36
A
L
A1
e1
C
eA
S
B
e3
D
N
1
E
PMDIP
Drawing is not to scale.
11/12
M48Z2M1, M48Z2M1Y
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1998 SGS-THOMSON Microelectronics - All Rights Reserved
® ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics
BYTEWIDE is a trademark of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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12/12
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