M48Z512ACS [STMICROELECTRONICS]
4 Mbit 512Kb x8 ZEROPOWER SRAM; 4兆位512KB X8 ZEROPOWER SRAM
| 型号： | M48Z512ACS |
| 厂家： | 
ST |
| 描述： | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| 文件： | 总17页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z512A
M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER SRAM
■ INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
32
1
■ 10 YEARS of DATA RETENTION in the
PMDIP32 (PM)
Module
ABSENCE of POWER
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
SNAPHAT (SH)
Battery
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
– M48Z512A: 4.50V ≤ V
≤ 4.75V
PFD
– M48Z512AY: 4.20V ≤ V
≤ 4.50V
PFD
32
■ BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
1
■ PIN and FUNCTION COMPATIBLE with
TSOP II 32
(10 x 20mm)
JEDEC STANDARD 512K x 8 SRAMs
■ SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
SOH28
Surface Mount Chip Set Solution (CS)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
Figure 1. Logic Diagram
V
CC
■ SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
19
8
Table 1. Signal Names
A0-A18
W
DQ0-DQ7
A0-A18
Address Inputs
Data Inputs / Outputs
Chip Enable
M48Z512A
M48Z512AY
DQ0-DQ7
E
E
G
G
W
Output Enable
Write Enable
Supply Voltage
Ground
V
V
SS
CC
AI02043
V
SS
March 2000
1/17
M48Z512A, M48Z512AY
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
A
Ambient Operating Temperature
T
T
Storage Temperature (V
Off)
CC
–40 to 70
–40 to 70
°C
STG
Temperature Under Bias
°C
BIAS
(2)
Lead Solder Temperature for 10 seconds
260
°C
T
SLD
V
Input or Output Voltages
Supply Voltage
–0.3 to 7
–0.3 to 7
V
V
IO
V
CC
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.75V to 5.5V
or
4.5V to 5.5V
V
V
V
V
D
IN
IL
IL
IL
IL
IH
IH
V
V
V
D
OUT
Read
Active
IL
Read
V
High Z
High Z
High Z
Active
IH
Deselect
Deselect
X
X
X
CMOS Standby
V
to V
(min)
PFD
SO
≤ V
X
X
X
Battery Back-up Mode
SO
Note: 1. X = V or V ; V
= Battery Back-up Switchover Voltage.
IH
IL
SO
Figure 2. DIP Connections
DESCRIPTION
The M48Z512A/512AY ZEROPOWER RAM is a
non-volatile 4,194,304 bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic 32 pin DIP Module.
For surface mount environments ST provides a
Chip Set solution consisting of a 28 pin 330mil
SOIC NVRAM Supervisor (M40Z300) and a 32 pin
TSOP Type II (10 x 20mm) LPSRAM (M68Z512)
packages.
A18
A16
A14
A12
A7
1
2
3
4
5
6
7
32
V
CC
31 A15
30 A17
29
W
28 A13
27 A8
26 A9
A6
A5
A4 8 M48Z512A 25 A11
M48Z512AY
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
A3
9
24
G
A2 10
A1 11
23 A10
22
E
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Zxx-BR00SH1”.
V
16
SS
AI02044
2/17
M48Z512A, M48Z512AY
Figure 3. Block Diagram
V
CC
A0-A18
DQ0-DQ7
POWER
E
512K x
SRAM ARRAY
8
VOLTAGE SENSE
AND
E
SWITCHING
CIRCUITRY
W
G
INTERNAL
BATTERY
V
SS
AI02045
The M48Z512A/512AY also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
timing or limitations on the number of writes that
can be performed.
The M48Z512A/512AY has its own Power-fail De-
tect Circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V is out of tolerance, the circuit
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
condition. When V is out of tolerance, the circuit
CC
tem operation brought on by low V . As V falls
CC
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
tem operations brought on by low V . As V
CC
CC
falls below approximately 3V, the control circuitry
connects the battery which sustains data until valid
power returns.
The ZEROPOWER RAM replaces industry stan-
dard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special write
3/17
M48Z512A, M48Z512AY
(1)
Figure 4. Hardware Hookup for SMT Chip Set
THS(2)
V
V
CC
OUT
SNAPHAT
E2
BATTERY(3)
M40Z300
E1
M68Z512
DQ0-DQ7
E
CON
E
E2
E3
E4
CON
CON
CON
A0-A18
A
B
RST
BL
W
V
V
SS
SS
AI03631
Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z512 at www.st.com.
2. Connect THS pin to V if 4.2V ≤ V ≤ 4.5V (M48Z512AY) or connect THS pin to V if 4.5V ≤ V ≤ 4.75V (M48Z512A).
PFD
OUT
PFD
SS
3. SNAPHAT top ordered separately.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Figure 5. AC Testing Load Circuit
≤ 5ns
0 to 3V
1.5V
5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
1.9kΩ
Note that Output Hi-Z is defined as the point where data is no longer
driven.
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF or 5pF
L
C
includes JIG capacitance
L
AI01030
4/17
M48Z512A, M48Z512AY
(1, 2)
Table 5. Capacitance
A
(T = 25 °C, f = 1MHz)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
Input Capacitance
10
pF
IN
(3)
IN
V
Input / Output Capacitance
10
pF
C
IO
OUT
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T = 0 to 70 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
±1
±1
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
µA
I
OUT
LO
I
Supply Current
E = V , Outputs open
115
10
5
mA
mA
mA
CC
IL
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC1
CC2
IH
I
E ≥ V – 0.2V
CC
Input Low Voltage
–0.3
2.2
0.8
V
V
IL
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
V
+ 0.3
CC
V
V
V
IH
I
= 2.1mA
= –1mA
OH
0.4
OL
OL
V
OH
I
2.4
Note: 1. Outputs deselected.
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
A
(T = 0 to 70 °C)
Symbol
Parameter
Power-fail Deselect Voltage
Min
4.5
4.2
Typ
4.6
4.3
3
Max
4.75
4.5
Unit
V
M48Z512A
V
PFD
M48Z512AY
V
V
Battery Back-up Switchover Voltage
Data Retention Time
V
SO
(2)
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. At 25 °C.
5/17
M48Z512A, M48Z512AY
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C)
A
Symbol
Parameter
Min
Max
Unit
(1)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
CC
F
(2)
V
V Fall Time
SO CC
10
40
0
µs
µs
µs
ms
t
FB
t
Write Protect Time from V
= V
CC PFD
150
120
WP
t
V
to V
(max) V Rise Time
PFD CC
R
SO
E Recovery Time
40
t
ER
Note: 1. V
(max) to V
(min) fall time of less than t may result indeselection/write protection not occurring until 200µs after V pass-
PFD F CC
PFD
es V
(min).
PFD
2. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SO FB
Figure 6. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tFB
tWP
tER
RECOGNIZED
RECOGNIZED
E
DON’T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01031
6/17
M48Z512A, M48Z512AY
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
M48Z512A/M48Z512AY
-70 -85
Symbol
Parameter
Unit
Min
Max
Min
Max
t
Read Cycle Time
70
85
ns
ns
ns
AVAV
(1)
Address Valid to Output Valid
Chip Enable Low to Output Valid
70
70
35
85
85
45
t
AVQV
(1)
(1)
(2)
(2)
(2)
(2)
(1)
t
ELQV
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
ns
ns
ns
ns
ns
ns
t
GLQV
5
5
5
5
t
ELQX
t
GLQX
30
20
35
25
t
EHQZ
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
GHQZ
5
5
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
Figure 7. Address Controlled, Read Mode AC Waveforms
A0-A18
tAVAV
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI01220
Note:
Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
7/17
M48Z512A, M48Z512AY
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
A0-A18
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01221
Note: Write Enable (W) = High.
READ MODE
available after the later of Chip Enable Access
time (t ) or Output Enable Access Time
ELQV
The M48Z512A/512AY is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripple-
through access of data from eight of 4,194,304 lo-
cations in the static storage array. Thus, the
unique address specified by the 19 Address Inputs
defines which one of the 524,288 bytes of data is
to be accessed. Valid data will be available at the
(t
). The state of the eight three-state Data I/O
GLQV
signals is controlled by E and G. If the outputs are
activated before t , the data lines will be driven
AVQV
to an indeterminate state until t
. If the Ad-
AVQV
dress Inputs are changed while E and G remain
low, output data will remain valid for Output Data
Hold time (t
) but will go indeterminate until the
AXQX
next Address Access.
Data I/O pins within Address Access time (t
)
AVQV
after the last address input signal is stable, provid-
ing that the E (Chip Enable) and G (Output En-
able) access times are also satisfied. If the E and
G access times are not met, valid data will be
8/17
M48Z512A, M48Z512AY
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
M48Z512A/M48Z512AY
-70 -85
Symbol
Parameter
Unit
Min
70
0
Max
Min
85
0
Max
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Validto Write Enable Low
Address Validto Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
55
55
5
65
75
5
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
ELEH
t
t
t
WHAX
t
15
30
30
0
15
35
35
0
EHAX
DVWH
t
DVEH
WHDX
t
10
10
EHDX
(1, 2)
Write Enable Low to Output Hi-Z
Address Validto Write Enable High
Address Validto Chip Enable High
Write Enable High to Output Transition
25
30
ns
ns
ns
ns
t
WLQZ
t
65
65
5
75
75
5
AVWH
t
AVEH
(1, 2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE MODE
from E or t
from W prior to the initiation
HAX
WHAX
of another read or write cycle. Data-in must be val-
The M48Z512A/512AY is in the Write Mode when-
ever W and E are active. The start of a write is ref-
erenced from the latter occurring falling edge of W
or E. A write is terminated by the earlier rising edge
of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of t
id t or t prior to the end of write and re-
DVEH
DVWH
main valid for t
or t
afterward. G should
WHDX
EHDX
be kept high during write cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G, a low on W will disable
the outputs t
after W falls.
WLQZ
E-
9/17
M48Z512A, M48Z512AY
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01222
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01223
Note: Output Enable (G) = High.
10/17
M48Z512A, M48Z512AY
Figure 11. Supply Voltage Protection
The internal coin cell will maintain data in the
M48Z512A/512AY after the initial application of
V
for an accumulated period of at least 10 years
CC
when V is less than V . As system power re-
CC
SO
turns and V rises above V , the battery is dis-
CC
SO
connected, and the power supply is switched to
external V . Write protection continues for t af-
CC
ER
V
CC
ter V reaches V
to allow for processor stabi-
CC
PFD
lization. After t , normal RAM operation can
ER
V
CC
resume.
For more information on Battery Storage Life refer
to the Application Note AN1012.
0.1µF
DEVICE
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
V
SS
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
AI02169
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
11) is recommended in order to provide the need-
ed filtering.
DATA RETENTION MODE
With valid V applied, the M48Z512A/512AY op-
CC
In addition to transients that are caused by normal
SRAM operation, power cycling cangenerate neg-
erates as a conventional BYTEWIDE
static
RAM. Should the supply voltage decay, the RAM
will automatically power-fail deselect, write pro-
ative voltage spikes on V that drive it to values
CC
below V by as much as one Volt. These nega-
SS
tecting itself t
after V
falls below V
. All
PFD
WP
CC
tive spikes can cause data corruptionin the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommeded to connect
outputs become high impedance, and all inputs
are treated as ”don’t care.”
If power fail detection occurs during a valid ac-
cess, thememory cycle continues to completion. If
the memory cycle fails to terminate within the time
a schottky diode from V
to V (cathode con-
SS
CC
SS
nected to V , anode to V ). Schottky diode
CC
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
t
, write protection takes place. When V drops
WP
CC
below V , the control circuit switches power to
SO
the internal energy source which preserves data.
11/17
M48Z512A, M48Z512AY
Table 11. Ordering Information Scheme
Example:
M48Z512AY
-85 PM
1
Device Type
M48Z
Supply Voltage and Write Protect Voltage
512A = V
= 4.75V to 5.5V; V
= 4.5V to 4.75V
= 4.2V to 4.5V
CC
PFD
PFD
512AY = V = 4.5V to 5.5V; V
CC
Speed
-70 = 70ns
-85 = 85ns
Package
PM = PMDIP32
(1)
CS
= Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z512 (TSOP II 32)
Temperature Range
1 = 0 to 70 °C
(2)
9
= Extended Temperature
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
”M4Zxx-BR00SH1” in plastic tube or ”M4Zxx-BR00SH1TR” in Tape & Reel form.
2. Contact Sales Offices for availability of Extended Temperature.
Caution: Do not place the SNAPHAT battery package ”M4Zxx-BR00SH1” in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
12/17
M48Z512A, M48Z512AY
Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.52
0.21
0.10
21.08
–
Typ
Max
0.047
0.006
0.041
0.020
0.008
0.004
0.830
–
A
A1
A2
b
0.05
0.95
0.30
0.12
0.002
0.037
0.012
0.005
C
CP
D
20.82
–
0.820
–
e
1.27
0.050
E
11.56
10.03
0.40
0°
11.96
10.29
0.60
5°
0.455
0.395
0.016
0°
0.471
0.405
0.024
5°
E1
L
α
N
32
32
Figure 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
D
16
1
E1
E
17
32
b
e
A2
A
C
α
A1
L
CP
TSOP-d
Drawing is not to scale.
13/17
M48Z512A, M48Z512AY
Table 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
14/17
M48Z512A, M48Z512AY
Table 14. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 14. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Drawing is not to scale.
15/17
M48Z512A, M48Z512AY
Table 15. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm
inches
Min
Symbol
Typ
Min
9.27
0.38
0.43
0.20
42.42
18.03
2.29
34.29
14.99
3.05
1.91
32
Max
9.52
–
Typ
Max
0.375
–
A
A1
B
0.365
0.015
0.017
0.008
1.670
0.710
0.090
1.350
0.590
0.120
0.075
32
0.59
0.33
43.18
18.80
2.79
41.91
16.00
3.81
2.79
0.023
0.013
1.700
0.740
0.110
1.650
0.630
0.150
0.110
C
D
E
e1
e3
eA
L
S
N
Figure 15. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Drawing is not to scale.
16/17
M48Z512A, M48Z512AY
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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17/17
相关型号：
M48Z512AV-70PM9
512KX8 NON-VOLATILE SRAM MODULE, 70ns, PDIP32, PLASTIC, MODULE, DIP-32
STMICROELECTR
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