M50FLW040BN5G [STMICROELECTRONICS]
4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory; 4兆位（ 5 】 64字节块+ 3 】 16 】 4千字节扇区） 3 -V供应固件集线器/低引脚数闪存
| 型号： | M50FLW040BN5G |
| 厂家： | 
ST |
| 描述： | 4-Mbit (5 】 64 Kbyte blocks + 3 】 16 】 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory |
| 文件： | 总64页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M50FLW040A
M50FLW040B
4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors)
3-V supply Firmware Hub / low-pin count Flash memory
Feature summary
■ Flash memory
– Compatible with either the LPC interface or
the FWH interface (Intel Spec rev1.1) used
in PC BIOS applications
PLCC32 (K)
– 5 Signal Communication Interface
supporting Read and Write Operations
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
■ 8 blocks of 64 Kbytes
– 5 blocks of 64 KBytes each
– 3 blocks, subdivided into 16 uniform
sectors of 4 KBytes each
TSOP32 (NB)
8 x 14mm
Two blocks at the top and one at the bottom
(M50FLW040A)
One block at the top and two at the bottom
(M50FLW040B)
■ Enhanced security
– Hardware Write Protect Pins for Block
Protection
TSOP40 (N)
10 x 20mm
– Register-based Read and Write Protection
■ Supply voltage
■ Program/Erase Suspend
– V = 3 to 3.6V for Program, Erase and
CC
– Read other Blocks/Sectors during Program
Suspend
Read Operations
– V = 12V for Fast Program and Erase
PP
– Program other Blocks/Sectors during Erase
Suspend
■ Two interfaces
– Auto Detection of Firmware Hub (FWH) or
Low Pin Count (LPC) Memory Cycles for
Embedded Operation with PC Chipsets
■ Electronic signature
– Manufacturer Code: 20h
– Device Code (M50FLW040A): 08h
– Device Code (M50FLW040B): 28h
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
■ Packages
■ Programming time: 10 µs typical
– ECOPACK® (RoHS compliant)
■ Program/Erase Controller
– Embedded Program and Erase algorithms
– Status Register Bits
October 2006
Rev 6
1/64
www.st.com
1
Contents
M50FLW040A, M50FLW040B
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Firmware Hub/low-pin count (FWH/LPC) signal descriptions . . . . . . . . . 13
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
Input/Output communications (FWH0/LAD0-FWH3/LAD3) . . . . . . . . . . 13
Input communication frame (FWH4/LFRAME) . . . . . . . . . . . . . . . . . . . 13
Identification inputs (ID0-ID3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General-purpose inputs (GPI0-GPI4) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interface Configuration (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interface Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CPU Reset (INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Top Block Lock (TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.10 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.11 Reserved for Future Use (RFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2
Address/Address Multiplexed (A/A Mux) signal descriptions . . . . . . . . . . 15
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Address inputs (A0-A10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Row/Column Address Select (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3
Supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1
2.3.2
2.3.3
V
V
V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
optional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
PP
SS
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Firmware hub/low-pin count (FWH/LPC) bus operations . . . . . . . . . . . . . 18
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/64
M50FLW040A, M50FLW040B
Contents
3.1.6
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Address/Address Multiplexed (A/A Mux) bus operations . . . . . . . . . . . . . 20
3.2.1
3.2.2
3.2.3
3.2.4
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.0.1
4.0.2
4.0.3
4.0.4
4.0.5
4.0.6
4.0.7
4.0.8
4.0.9
Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Quadruple Byte Program command (A/A Mux interface) . . . . . . . . . . . . 28
Double/Quadruple Byte Program command (FWH mode) . . . . . . . . . . 28
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sector Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.0.10 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.0.11 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.0.12 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
5.2
5.3
Program/Erase Controller status (Bit SR7) . . . . . . . . . . . . . . . . . . . . . . . 32
Erase Suspend status (Bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Erase status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Program status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
V
PP
Program Suspend status (Bit SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Block Protection status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Firmware hub/low pin count (FWH/LPC) interface Configuration
Registers 35
6.1
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1
6.1.2
6.1.3
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/64
Contents
M50FLW040A, M50FLW040B
6.2
6.3
Firmware hub/low-pin count (FWH/LPC) General-Purpose
Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
Program and Erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8
9
10
11
Appendix A Block and sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix B Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4/64
M50FLW040A, M50FLW040B
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal names (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Addresses (M50FLW040A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Addresses (M50FLW040B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory identification input configuration (LPC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FWH bus read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FWH bus write field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LPC bus read field definitions (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LPC bus write field definitions (1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
A/A Mux bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Configuration Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Lock Register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
General-Purpose Input Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FWH/LPC interface AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
A/A Mux interface AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FWH/LPC interface clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
FWH/LPC interface AC signal timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A/A Mux interface Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A/A Mux interface Write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package mechanical data . . 48
TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package
Table 32.
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
M50FLW040A block and sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
M50FLW040B block and sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 33.
Table 34.
Table 35.
Table 36.
5/64
List of figures
M50FLW040A, M50FLW040B
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram (FWH/LPC interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic diagram (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PLCC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TSOP32 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TSOP40 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FWH bus read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FWH bus write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LPC bus read waveforms (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LPC bus write waveforms (1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. FWH/LPC interface AC measurement I/O waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. A/A Mux interface AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. FWH/LPC interface clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. FWH/LPC interface AC signal timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 16. A/A Mux interface Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. A/A Mux interface Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package outline . . . . . . . . . . 48
Figure 19. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline . . . . . . . . . . . . 49
Figure 20. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package outline . . . . . . . . . . . 50
Figure 21. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Double/Quadruple Byte Program flowchart and pseudo code (FWH mode only). . . . . . . . 57
Figure 23. Quadruple Byte Program flowchart and pseudo code (A/A Mux interface only). . . . . . . . . 58
Figure 24. Program Suspend and Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25. Chip Erase flowchart and pseudo code (A/A Mux interface only). . . . . . . . . . . . . . . . . . . . 60
Figure 26. Sector/Block Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 27. Erase Suspend and Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 62
6/64
M50FLW040A, M50FLW040B
Summary description
1
Summary description
The M50FLW040 is a 4 Mbit (512 Kb x8) non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in production lines, an optional 12 V power
supply can be used to reduce the erasing and programming time.
The memory is divided into 8 Uniform Blocks of 64 KBytes each, three of which are divided
into 16 uniform sectors of 4 KBytes each (see Appendix A for details). All blocks and sectors
can be erased independently. So, it is possible to preserve valid data while old data is
erased. Blocks can be protected individually to prevent accidental program or erase
commands from modifying their contents.
Program and erase commands are written to the Command Interface of the memory. An on-
chip Program/Erase Controller simplifies the process of programming or erasing the
memory by taking care of all of the special operations that are required to update the
memory contents. The end of a program or erase operation can be detected and any error
conditions identified. The command set to control the memory is consistent with the JEDEC
standards.
Two different bus interfaces are supported by the memory:
■
The primary interface, the FWH/LPC Interface, uses Intel’s proprietary Firmware Hub
(FWH) and Low Pin Count (LPC) protocol. This has been designed to remove the need
for the ISA bus in current PC Chipsets. The M50FLW040 acts as the PC BIOS on the
Low Pin Count bus for these PC Chipsets.
■
The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is
designed to be compatible with current Flash Programmers, for production line
programming prior to fitting the device in a PC Motherboard.
The memory is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, ST offers the M50FLW040A and
M50FLW040B in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS
compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
7/64
Summary description
Figure 1.
M50FLW040A, M50FLW040B
Logic diagram (FWH/LPC interface)
V
V
CC PP
4
5
4
FWH0/LAD0
FWH3/LAD3
1
ID0-ID3
GPI0-GPI4
WP
M50FLW040A
M50FLW040B
FWH4/LFRAME
TBL
CLK
IC
RP
INIT
V
SS
AI08417B
1. ID3 is Reserved for Future Use (RFU) in LPC mode.
Table 1.
Signal names (FWH/LPC Interface)
FWH0/LAD0-FWH3/LAD3
Input/Output Communications
FWH4/LFRAME
Input Communication Frame
Identification Inputs
General Purpose Inputs
Interface Configuration
Interface Reset
ID0-ID3
GPI0-GPI4
IC
RP
INIT
CLK
TBL
CPU Reset
Clock
Top Block Lock
WP
Write Protect
RFU
VCC
Reserved for Future Use. Leave disconnected
Supply Voltage
VPP
Optional Supply Voltage for Fast Program and Erase Operations
VSS
Ground
NC
Not Connected Internally
8/64
M50FLW040A, M50FLW040B
Summary description
Figure 2.
Logic diagram (A/A Mux interface)
V
V
CC PP
11
8
DQ0-DQ7
A0-A10
RC
IC
M50FLW040A
M50FLW040B
RB
G
W
RP
V
SS
AI08418B
Table 2.
Signal names (A/A Mux interface)
IC
Interface Configuration
A0-A10
DQ0-DQ7
G
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
W
RC
Row/Column Address Select
Ready/Busy Output
Interface Reset
RB
RP
VCC
VPP
VSS
NC
Supply Voltage
Optional Supply Voltage for Fast Program and Erase Operations
Ground
Not Connected Internally
9/64
Summary description
Figure 3.
M50FLW040A, M50FLW040B
PLCC connections
A/A Mux
A/A Mux
1 32
A7
GPI1
GPI0
WP
IC (V )
IL
NC
IC (V
NC
)
IH
A6
A5
A4
A3
A2
A1
A0
NC
NC
TBL
V
V
V
V
SS
CC
SS
CC
M50FLW040A
M50FLW040B
ID3/RFU
ID2
9
25
INIT
G
ID1
FWH4/LFRAME
RFU
W
RB
DQ7
ID0
RFU
DQ0 FWH0/LAD0
17
A/A Mux
A/A Mux
AI08419B
1. Pins 27 and 28 are not internally connected.
Figure 4.
TSOP32 connections
NC
NC
NC
NC
NC
NC
NC
1
32
INIT
G
FWH4/LFRAME
NC
W
NC
V
RFU
RFU
RFU
RFU
DQ7
DQ6
DQ5
DQ4
SS
IC
IC (V
)
IH
A10
RC
GPI4
CLK
V
V
8
9
25
24
M50FLW040A
M50FLW040B
FWH3/LAD3
DQ3
CC
CC
V
V
V
V
PP
RP
PP
SS
SS
RP
GPI3
GPI2
GPI1
GPI0
WP
FWH2/LAD2
FWH1/LAD1
FWH0/LAD0
ID0
DQ2
DQ1
DQ0
A0
A9
A8
A7
A6
A5
A4
ID1
A1
ID2
A2
TBL
16
17
ID3/RFU
A3
AI09742B
10/64
M50FLW040A, M50FLW040B
Summary description
Figure 5.
TSOP40 connections
NC
IC (V
NC
1
40
V
V
V
V
SS
SS
CC
)
IC (V )
IL
IH
CC
NC
NC
NC
NC
A10
NC
RC
NC
FWH4/LFRAME
W
NC
INIT
RFU
RFU
RFU
RFU
RFU
G
NC
RB
NC
DQ7
DQ6
DQ5
DQ4
GPI4
NC
CLK
V
V
10
11
31
30
V
V
M50FLW040A
M50FLW040B
CC
CC
CC
CC
V
V
V
V
V
V
PP
RP
PP
RP
NC
SS
SS
SS
SS
NC
NC
A9
A8
A7
A6
A5
A4
FWH3/LAD3
FWH2/LAD2
FWH1/LAD1
FWH0/LAD0
ID0
DQ3
DQ2
DQ1
DQ0
A0
NC
GPI3
GPI2
GPI1
GPI0
WP
ID1
A1
ID2
A2
TBL
20
21
ID3/RFU
A3
AI08420B
Table 3.
Addresses (M50FLW040A)
Address Range
Block Size
(KByte)
Sector Size (KByte)
64
64
64
64
64
64
64
64
70000h-7FFFFh
60000h-6FFFFh
50000h- 5FFFFh
40000h- 4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
16 x 4KBytes
16 x 4KBytes
5 x 64KBytes
16 x 4KBytes
11/64
Summary description
Table 4.
M50FLW040A, M50FLW040B
Addresses (M50FLW040B)
Address Range
Block Size
(KByte)
Sector Size (KByte)
64
64
64
64
64
64
64
64
70000h-7FFFFh
60000h- 6FFFFh
50000h- 5FFFFh
40000h- 4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
16 x 4KBytes
5 x 64KBytes
16 x 4KBytes
16 x 4KBytes
1. Also see Appendix A, Table 34 and Table 35 for a full listing of the Block Addresses.
12/64
M50FLW040A, M50FLW040B
Signal descriptions
2
Signal descriptions
There are two distinct bus interfaces available on this device. The active interface is selected
before power-up, or during Reset, using the Interface Configuration Pin, IC.
The signals for each interface are discussed in the Firmware Hub/low-pin count (FWH/LPC)
signal descriptions section and the Address/Address Multiplexed (A/A Mux) signal
descriptions section, respectively, while the supply signals are discussed in the Supply
signal descriptions section.
2.1
Firmware Hub/low-pin count (FWH/LPC) signal descriptions
Please see Figure 1 and Table 1.
2.1.1
Input/Output communications (FWH0/LAD0-FWH3/LAD3)
All Input and Output Communications with the memory take place on these pins. Addresses
and Data for Bus Read and Bus Write operations are encoded on these pins.
2.1.2
2.1.3
Input communication frame (FWH4/LFRAME)
The Input Communication Frame (FWH4/LFRAME) signal indicates the start of a bus
operation. When Input Communication Frame is Low, V , on the rising edge of the Clock, a
IL
new bus operation is initiated. If Input Communication Frame is Low, V , during a bus
operation then the operation is aborted. When Input Communication Frame is High, V , the
current bus operation is either proceeding or the bus is idle.
IL
IH
Identification inputs (ID0-ID3)
Up to 16 memories can be addressed on a bus, in the Firmware Hub (FWH) mode. The
Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified
on a pin by driving it Low, V , or leaving it floating (since there is an internal pull-down
IL
resistor, with a value of R ). A ‘1’ is signified on a pin by driving it High, V (and there will
IL
IH
be a leakage current of I through the pin).
LI2
By convention, the boot memory must have address ‘0000’, and all additional memories are
given addresses, allocated sequentially, from ‘0001’.
In the Low Pin Count (LPC) mode, the identification Inputs (ID0-ID2) can address up to 8
memories on a bus. In the LPC mode, the ID3 pin is Reserved for Future Use (RFU). The
value on address A19-A21 is compared to the hardware strapping on the ID0-ID2 pins to
select the memory that is being addressed. For an address bit to be ‘1’, the corresponding
ID pin can be left floating or driven Low, V (again, with the internal pull-down resistor, with
IL
a value of R ). For an address bit to be ‘0’, the corresponding ID pin must be driven High,
IL
V
(and there will be a leakage current of I through the pin, as specified in Table 24). For
IH
LI2
details, see Table 5.
13/64
Signal descriptions
M50FLW040A, M50FLW040B
2.1.4
General-purpose inputs (GPI0-GPI4)
The General Purpose Inputs can be used as digital inputs for the CPU to read, with their
contents being available in the General Purpose Inputs Register. The pins must have stable
data throughout the entire cycle that reads the General Purpose Input Register. These pins
should be driven Low, V or High, V , and must not be left floating.
IL,
IH
2.1.5
Interface Configuration (IC)
The Interface Configuration input selects whether the FWH/LPC interface or the
Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during operation of the memory device, except for
selecting the desired interface in the period before power-up or during a Reset.
To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or
driven Low, V . To select the Address/Address Multiplexed (A/A Mux) Interface, the pin
IL
should be driven High, V . An internal pull-down resistor is included with a value of R ;
IH
IL
there will be a leakage current of I through each pin when pulled to V .
LI2
IH
2.1.6
Interface Reset (RP)
The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is
driven Low, V , the memory is in Reset mode (the outputs go to high impedance, and the
IL
current consumption is minimized). When RP is driven High, V , the device is in normal
IH
operation. After exiting Reset mode, the memory enters Read mode.
2.1.7
2.1.8
2.1.9
CPU Reset (INIT)
The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves
identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK)
The Clock, CLK, input is used to clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI
specification.
Top Block Lock (TBL)
The Top Block Lock input is used to prevent the Top Block (Block 7) from being changed.
When Top Block Lock, TBL, is driven Low, V , program and erase operations in the Top
IL
Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,
TBL, is driven High, V , the protection of the Block is determined by the Lock Register. The
IH
state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to
6). For details, see Appendix A.
Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and
must not be changed until the operation has completed, otherwise unpredictable results
may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
14/64
M50FLW040A, M50FLW040B
Signal descriptions
2.1.10
Write Protect (WP)
The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 6) from being
changed. When Write Protect, WP, is driven Low, V , Program and Erase operations in the
IL
Main Blocks have no effect, regardless of the state of the Lock Register. When Write
Protect, WP, is driven High, V , the protection of the Block is determined by the Lock
IH
Register. The state of Write Protect, WP, does not affect the protection of the Top Block
(Block 7). For details, see Appendix A.
Write Protect, WP, must be set prior to a Program or Erase operation is initiated, and must
not be changed until the operation has completed otherwise unpredictable results may
occur. Similarly, unpredictable behavior is possible if WP is changed during Program or
Erase Suspend, and care should be taken to avoid this.
2.1.11
Reserved for Future Use (RFU)
These pins do not presently have assigned functions. They must be left disconnected,
except for ID3 (when in LPC mode) which can be left connected. The electrical
characteristics for this signal are as described in the “Identification inputs (ID0-ID3)” section.
2.2
Address/Address Multiplexed (A/A Mux) signal descriptions
Please see Figure 2 and Table 2.
2.2.1
Address inputs (A0-A10)
The Address Inputs are used to set the Row Address bits (A0-A10) and the Column
Address bits (A11-A18). They are latched during any bus operation by the Row/Column
Address Select input, RC.
2.2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs hold the data that is to be written to or read from the memory. They
output the data stored at the selected address during a Bus Read operation. During Bus
Write operations they carry the commands that are sent to the Command Interface of the
internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
2.2.3
2.2.4
2.2.5
Output Enable (G)
The Output Enable signal, G, controls the output buffers during a Bus Read operation.
Write Enable (W)
The Write Enable signal, W, controls the Bus Write operation of the Command Interface.
Row/Column Address Select (RC)
The Row/Column Address Select input selects whether the Address Inputs are to be latched
into the Row Address bits (A0-A10) or the Column Address bits (A11-A18). The Row
Address bits are latched on the falling edge of RC whereas the Column Address bits are
latched on its rising edge.
15/64
Signal descriptions
M50FLW040A, M50FLW040B
2.2.6
Ready/Busy output (RB)
The Ready/Busy pin gives the status of the device’s Program/Erase Controller. When
Ready/Busy is Low, V , the device is busy with a program or erase operation, and it will not
OL
accept any additional program or erase command (except for the Program/Erase Suspend
command). When Ready/Busy is High, V , the memory is ready for any read, program or
OH
erase operation.
2.3
Supply signal descriptions
The Supply Signals are the same for both interfaces.
2.3.1
V
supply voltage
CC
The V Supply Voltage supplies the power for all operations (read, program, erase, etc.).
CC
The Command Interface is disabled when the V Supply Voltage is less than the Lockout
CC
Voltage, V
. This is to prevent Bus Write operations from accidentally damaging the data
LKO
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time, the operation aborts, and the memory contents
that were being altered will be invalid. After V becomes valid, the Command Interface is
CC
reset to Read mode.
A 0.1µF capacitor should be connected between the V Supply Voltage pins and the V
CC
SS
Ground pin to decouple the current surges from the power supply. Both V Supply Voltage
CC
pins must be connected to the power supply. The PCB track widths must be sufficient to
carry the currents required during program and erase operations.
2.3.2
V
optional supply voltage
PP
The V Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple
PP
Byte Program command description in A/A Mux interface and the Double/Quadruple Byte
Program command description in FWH mode) and Fast Erase options of the memory.
When V = V , program and erase operations take place as normal. When V = V ,
PPH
PP
CC
PP
Fast Program and Erase operations are used. Any other voltage input to V will result in
PP
undefined behavior, and should not be used.
V
should not be set to V
for more than 80 hours during the life of the memory.
PPH
PP
2.3.3
V
ground
SS
V
is the reference for all the voltage measurements.
SS
16/64
M50FLW040A, M50FLW040B
Signal descriptions
Table 5.
Memory identification input configuration (LPC mode)
Memory number
ID2
ID1
ID0
A21
A20
A19
1 (Boot memory)
V
IL or float
VIL or float
VIL or float
VIH
VIL or float
VIH
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
2
3
4
5
6
7
8
VIL or float
VIL or float
VIL or float
VIH
V
IL or float
VIH
VIH
VIL or float
VIL or float
VIH
VIL or float
VIH
VIH
VIH
VIL or float
VIH
VIH
VIH
17/64
Bus operations
M50FLW040A, M50FLW040B
3
Bus operations
The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with different
bus signals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full
functionality, while the Address/Address Multiplexed (A/A Mux) Interface is orientated for
erase and program operations.
See the sections below, The Firmware hub/low-pin count (FWH/LPC) bus operations and
Address/Address Multiplexed (A/A Mux) bus operations, for details of the bus operations on
each interface.
3.1
Firmware hub/low-pin count (FWH/LPC) bus operations
The M50FLW040 automatically identifies the type of FWH/LPC protocol from the first
received nibble (START nibble) and decodes the data that it receives afterwards, according
to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface
consists of four data signals (FWH0/LAD0-FWH3/LAD3), one control line (FWH4/LFRAME)
and a clock (CLK).
Protection against accidental or malicious data corruption is achieved using two additional
signals (TBL and WP). And two reset signals (RP and INIT) are available to put the memory
into a known state.
The data, control and clock signals are designed to be compatible with PCI electrical
specifications. The interface operates with clock speeds of up to 33MHz.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Standby, Reset and Block Protection.
3.1.1
Bus Read
Bus Read operations are used to read from the memory cells, specific registers in the
Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when the Input Communication Frame,
FWH4/LFRAME, is Low, V , and the correct Start cycle is present on FWH0/LAD0-
IL
FWH3/LAD3. On subsequent clock cycles the Host will send to the memory:
■
■
ID Select, Address and other control bits on FWH0-FWH3 in FWH mode.
Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode.
The device responds by outputting Sync data until the wait states have elapsed, followed by
Data0-Data3 and Data4-Data7.
See Table 6 and Table 8, and Figure 6 and Figure 8, for a description of the Field definitions
for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of
the signals.
18/64
M50FLW040A, M50FLW040B
Bus operations
3.1.2
Bus Write
Bus Write operations are used to write to the Command Interface or Firmware Hub/Low Pin
Count Registers. A valid Bus Write operation starts on the rising edge of the Clock signal
when Input Communication Frame, FWH4/LFRAME, is Low, V , and the correct Start cycle
IL
is present on FWH0/LAD0-FWH3/LAD3. On subsequent Clock cycles the Host will send to
the memory:
■
ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-FWH3
in FWH mode.
■
Cycle Type + Dir, Address, other control bits, Data0-Data3 and Data4-Data7 on LAD0-
LAD3.
The device responds by outputting Sync data until the wait states have elapsed.
See Table 7 and Table 9, and Figure 7 and Figure 9, for a description of the Field definitions
for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of
the signals.
3.1.3
Bus Abort
The Bus Abort operation can be used to abort the current bus operation immediately. A Bus
Abort occurs when FWH4/LFRAME is driven Low, V , during the bus operation. The device
IL
puts the Input/Output Communication pins, FWH0/LAD0-FWH3/LAD3, to high impedance.
Note that, during a Bus Write operation, the Command Interface starts executing the
command as soon as the data is fully received. A Bus Abort during the final TAR cycles is
not guaranteed to abort the command. The bus, however, will be released immediately.
3.1.4
3.1.5
Standby
When FWH4/LFRAME is High, V , the device is put into Standby mode, where
FWH0/LAD0-FWH3/LAD3 are put into a high-impedance state and the Supply Current is
reduced to the Standby level, I
IH
.
CC1
Reset
During the Reset mode, all internal circuits are switched off, the device is deselected, and
the outputs are put to high-impedance. The device is in the Reset mode when Interface
Reset, RP, or CPU Reset, INIT, is driven Low, V . RP or INIT must be held Low, V , for
IL
IL
t
. The memory reverts to the Read mode upon return from the Reset mode, and the
PLPH
Lock Registers return to their default states regardless of their states before Reset. If RP or
INIT goes Low, V , during a Program or Erase operation, the operation is aborted and the
IL
affected memory cells no longer contain valid data. The device can take up to t
a Program or Erase operation.
to abort
PLRH
3.1.6
Block Protection
Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect,
WP, regardless of the state of the Lock Registers.
19/64
Bus operations
M50FLW040A, M50FLW040B
3.2
Address/Address Multiplexed (A/A Mux) bus operations
The Address/Address Multiplexed (A/A Mux) Interface has a more traditional-style interface.
The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash
Programming equipment for faster factory programming. Only a subset of the features
available to the Firmware Hub (FWH)/Low Pin Count (LPC) Interface are available; these
include all the Commands but exclude the Security features and other registers.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux) Interface is selected, all the blocks are
unprotected. It is not possible to protect any blocks through this interface.
3.2.1
3.2.2
Bus Read
Bus Read operations are used to read the contents of the Memory Array, the Electronic
Signature or the Status Register. A valid Bus Read operation begins by latching the Row
Address and Column Address signals into the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Write Enable (W) and Interface Reset (RP) must
be High, V , and Output Enable, G, Low, V . The Data Inputs/Outputs will output the value,
IH
IL
according to the timing constraints specified in Figure 16, and Table 28.
Bus Write
Bus Write operations are used to write to the Command Interface. A valid Bus Write
operation begins by latching the Row Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The
data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset,
RP, must be High, V ; and Write Enable, W, must be Low, V . The Data Inputs/Outputs are
IH
IL
latched on the rising edge of Write Enable, W. See Figure 17, and Table 29, for details of the
timing requirements.
3.2.3
3.2.4
Output Disable
The data outputs are high-impedance when the Output Enable, G, is at V .
IH
Reset
During the Reset mode, all internal circuits are switched off, the device is deselected, and
the outputs are put at high-impedance. The device is in the Reset mode when RP is Low,
V . RP must be held Low, V for t
. If RP goes Low, V , during a Program or Erase
IL
IL
PLPH
IL
operation, the operation is aborted, and the affected memory cells no longer contain valid
data. The memory can take up to t to abort a Program or Erase operation.
PLRH
20/64
M50FLW040A, M50FLW040B
Bus operations
Table 6.
FWH bus read field definitions
Clock Clock
Cycle Cycle Field
Number Count
FWH0- Memory
Description
FWH3
I/O
On the rising edge of CLK with FWH4 Low, the contents
of FWH0-FWH3 indicate the start of a FWH Read cycle.
1
1
START 1101b
IDSEL XXXX
I
Indicates which FWH Flash Memory is selected. The
value on FWH0-FWH3 is compared to the IDSEL
strapping on the FWH Flash Memory pins to select
which FWH Flash Memory is being addressed.
2
1
I
I
A 28-bit address is transferred, with the most significant
nibble first. For the multi-byte read operation, the least
significant bits (MSIZE of them) are treated as Don't
Care, and the read operation is started with each of
these bits reset to 0. Address lines A19-21 and A23-27
are treated as Don’t Care during a normal memory
array access, with A22=1, but are taken into account for
a register access, with A22=0. (See Table 15)
3-9
10
7
1
ADDR XXXX
This one clock cycle is driven by the host to determine
the number of Bytes that will be transferred.
M50FLW040 supports: single Byte transfer (0000b), 2-
Byte transfer (0001b), 4-Byte transfer (0010b), 16-Byte
transfer (0100b) and 128-Byte transfer (0111b).
MSIZE XXXX
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
11
12
1
1
TAR
TAR
1111b
I
1111b
(float)
The FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
O
The FWH Flash Memory drives FWH0-FWH3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
13-14
15
2
1
WSYNC 0101b
RSYNC 0000b
O
O
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating that data will be available during the next
clock cycle.
Data transfer is two CLK cycles, starting with the least
significant nibble. If multi-Byte read operation is
enabled, repeat cycle-16 and cycle-17 n times, where
16-17 M=2n DATA XXXX
previous
n = 2MSIZE
.
The FWH Flash Memory drives FWH0-FWH3 to 1111b
to indicate a turnaround cycle.
1
TAR
1111b
O
+1
previous
+1
1111b
(float)
The FWH Flash Memory floats its outputs, the host
takes control of FWH0-FWH3.
1
TAR
N/A
21/64
Bus operations
M50FLW040A, M50FLW040B
Figure 6.
FWH bus read waveforms
CLK
FWH4
FWH0-FWH3
START
1
IDSEL
1
ADDR
7
MSIZE
1
TAR
2
SYNC
3
DATA
M
TAR
2
Number of
clock cycles
AI08433B
22/64
M50FLW040A, M50FLW040B
Bus operations
Table 7.
FWH bus write field definitions
Clock Clock
Cycle Cycle Field
Number Count
FWH0- Memory
Description
FWH3
I/O
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
1
1
START 1110b
IDSEL XXXX
I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on
the FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
2
1
I
A 28-bit address is transferred, with the most significant
nibble first. Address lines A19-21 and A23-27 are treated
as Don’t Care during a normal memory array access, with
A22=1, but are taken into account for a register access,
with A22=0. (See Table 15)
3-9
10
7
1
ADDR XXXX
MSIZE XXXX
I
I
0000(Single Byte Transfer) 0001 (Double Byte Transfer)
0010b (Quadruple Byte Transfer).
Data transfer is two cycles, starting with the least significant
nibble. (The first pair of nibbles is that at the address with
A1-
A0 set to 00, the second pair with A1-A0 set to 01, the third
pair with A1-A0 set to 10, and the fourth pair with A1-A0 set
11-18 M=2/4/8 DATA XXXX
I
to 11. In Double Byte Program the first pair of nibbles is that
at the address with A0 set to 0, the second pair with A0 set
to 1)
previous
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
1
1
1
1
1
TAR 1111b
I
O
+1
previous
+1
1111b
TAR
The FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
(float)
previous
+1
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
SYNC 0000b
TAR 1111b
O
previous
+1
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
O
previous
+1
1111b
TAR
The FWH Flash Memory floats its outputs and the host
takes control of FWH0-FWH3.
N/A
(float)
Figure 7.
FWH bus write waveforms
CLK
FWH4
FWH0-FWH3
START
1
IDSEL
1
ADDR
7
MSIZE
1
DATA
M
TAR
2
SYNC
1
TAR
2
Number of
clock cycles
AI08434B
23/64
Bus operations
M50FLW040A, M50FLW040B
Description
Table 8.
LPC bus read field definitions (1-byte)
Clock
Cycle
Number Count
Clock
Cycle
LAD0- Memory
Field
LAD3
I/O
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
1
2
1
1
START
0000b
I
Indicates the type of cycle and selects 1-byte
reading. Bits 3:2 must be 01b. Bit 1 indicates
the direction of transfer: 0b for read. Bit 0 is
Don’t Care.
CYCTYPE
+ DIR
0100b
I
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to
1. A22=1 for memory access, and A22=0 for
register access. Table 5 shows the appropriate
values for A21-A19.
3-10
8
ADDR
XXXX
1111b
The host drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
11
12
1
1
TAR
TAR
I
1111b
(float)
The LPC Flash Memory takes control of
LAD0-LAD3 during this cycle.
O
The LPC Flash Memory drives LAD0-LAD3 to
0101b (short wait-sync) for two clock cycles,
indicating that the data is not yet available.
Two wait-states are always included.
13-14
15
2
1
WSYNC 0101b
O
O
The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating that data will be available
during the next clock cycle.
RSYNC
0000b
Data transfer is two CLK cycles, starting with
the least significant nibble.
16-17
18
2
1
1
DATA
TAR
TAR
XXXX
1111b
O
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b to indicate a turnaround cycle.
1111b
(float)
The LPC Flash Memory floats its outputs, the
host takes control of LAD0-LAD3.
19
N/A
Figure 8.
LPC bus read waveforms (1-byte)
CLK
LFRAME
LAD0-LAD3
CYCTYPE
+ DIR
START
1
ADDR
8
TAR
2
SYNC
3
DATA
2
TAR
2
Number of
clock cycles
1
AI04429
24/64
M50FLW040A, M50FLW040B
Bus operations
Table 9.
LPC bus write field definitions (1 byte)
Clock Clock
Cycle Cycle
Number Count
LAD0- Memory
Field
Description
LAD3
I/O
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
1
2
1
1
START
0000b
I
Indicates the type of cycle. Bits 3:2 must be 01b.
Bit 1 indicates the direction of transfer: 1b for
write. Bit 0 is don’t care (X).
CYCTYPE
+ DIR
011Xb
XXXX
I
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to 1.
A22=1 for memory access, and A22=0 for
register access. Table 5 shows the appropriate
values for A21-A19.
3-10
8
ADDR
Data transfer is two cycles, starting with the
least significant nibble.
11-12
13
2
1
1
DATA
TAR
TAR
XXXX
1111b
I
I
The host drives LAD0-LAD3 to 1111b to indicate
a turnaround cycle.
1111b
(float)
The LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
14
O
The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating it has received data or a
command.
15
1
SYNC
0000b
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
16
17
1
1
TAR
TAR
O
1111b
(float)
The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
N/A
Figure 9.
LPC bus write waveforms (1 byte)
CLK
LFRAME
LAD0-LAD3
CYCTYPE
+ DIR
START
1
ADDR
8
DATA
2
TAR
2
SYNC
1
TAR
2
Number of
clock cycles
1
AI04430
Table 10. A/A Mux bus operations
Operation
Bus Read
G
W
RP
VPP
DQ7-DQ0
VIL
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIL
Don't Care
VCC or VPPH
Don't Care
Don't Care
Data Output
Data Input
Hi-Z
Bus Write
Output Disable
Reset
VIH
V
IL or VIH
VIL or VIH
Hi-Z
25/64
Command interface
M50FLW040A, M50FLW040B
4
Command interface
All Bus Write operations to the device are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings, and verifies the correct execution of the
Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor the progress or the result of the operation.
The Command Interface reverts to the Read mode when power is first applied, or when
exiting from Reset. Command sequences must be followed exactly. Any invalid combination
of commands will be ignored. See Table 11 for the available Command Codes.
Table 11. Command codes
Hexadecimal
Command
Alternative Program Setup, Double/Quadruple Byte Program Setup, Chip Erase
Confirm
10h
20h
32h
40h
50h
70h
80h
90h
B0h
D0h
FFh
Block Erase Setup
Sector Erase Setup
Program, Double/Quadruple Byte Program Setup
Clear Status Register
Read Status Register
Chip Erase Setup
Read Electronic Signature
Program/Erase Suspend
Program/Erase Resume, Block Erase Confirm, Sector Erase Confirm
Read Memory Array
The following commands are the basic commands used to read from, write to, and configure
the device. The following text descriptions should be read in conjunction with Table 13.
4.0.1
Read Memory Array command
The Read Memory Array command returns the device to its Read mode, where it behaves
like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array
command and return the device to Read mode. Once the command is issued, the device
remains in Read mode until another command is issued. From Read mode, Bus Read
operations access the memory array.
If the Program/Erase Controller is executing a Program or Erase operation, the device will
not accept any Read Memory Array commands until the operation has completed.
For a multibyte read, in the FWH mode, the address, that was transmitted with the
command, will be automatically aligned, according to the MSIZE granularity. For example, if
MSIZE=7, regardless of any values that are provided for A6-A0, the first output will be from
the location for which A6-A0 are all ‘0’s.
26/64
M50FLW040A, M50FLW040B
Command interface
4.0.2
Read Status Register command
The Read Status Register command is used to read the Status Register. One Bus Write
cycle is required to issue the Read Status Register command. Once the command is issued,
subsequent Bus Read operations read the Status Register until another command is issued.
See the section on the Status Register for details on the definitions of the Status Register
bits.
4.0.3
Read Electronic Signature command
The Read Electronic Signature command is used to read the Manufacturer Code and the
Device Code. One Bus Write cycle is required to issue the Read Electronic Signature
command. Once the command is issued, the Manufacturer Code and Device Code can be
read using conventional Bus Read operations, and the addresses shown in Table 12.
Table 12. Electronic signature codes
Code
Address(1)
Data
Manufacturer Code
Device Code
...00000h
20h
M50FLW040A
M50FLW040B
08h
28h
...00001h
1. A22 should be ‘1’, and the ID lines and upper address bits should be set according to the rules illustrated in
Table 5, Table 6 and Table 8.
The device remains in this mode until another command is issued. That is, subsequent Bus
Read operations continue to read the Manufacturer Code, or the Device Code, and not the
Memory Array.
4.0.4
Program command
The Program command can be used to program a value to one address in the memory array
at a time.
The Program command works by changing appropriate bits from ‘1’ to ‘0’. (It cannot change
a bit from ‘0’ back to ‘1’. Attempting to do so will not modify the value of the bit. Only the
Erase command can set bits back to ‘1’. and does so for all of the bits in the block.)
Two Bus Write operations are required to issue the Program command. The second Bus
Write cycle latches the address and data, and starts the Program/Erase Controller.
Once the command is issued, subsequent Bus Read operations read the value in the Status
Register. (See the section on the Status Register for details on the definitions of the Status
Register bits.)
If the address falls in a protected block, the Program operation will abort, the data in the
memory array will not be changed, and the Status Register will indicate the error.
During the Program operation, the memory will only accept the Read Status Register
command and the Program/Erase Suspend command. All other commands are ignored.
See Figure 21, for a suggested flowchart on using the Program command. Typical Program
times are given in Table 18.
27/64
Command interface
M50FLW040A, M50FLW040B
4.0.5
Quadruple Byte Program command (A/A Mux interface)
The Quadruple Byte Program Command is used to program four adjacent Bytes in the
memory array at a time. The four Bytes must differ only for addresses A0 and A1.
Programming should not be attempted when V is not at V
.
PP
PPH
Five Bus Write operations are required to issue the command. The second, third and fourth
Bus Write cycles latch the respective addresses and data of the first, second and third Bytes
in the Program/Erase Controller. The fifth Bus Write cycle latches the address and data of
the fourth Byte and starts the Program/Erase Controller. Once the command is issued,
subsequent Bus Read operations read the value in the Status Register. (See the section on
the Status Register for details on the definitions of the Status Register bits.)
During the Quadruple Byte Program operation, the memory will only accept the Read Status
Register and Program/Erase Suspend commands. All other commands are ignored.
Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’
and attempting to do so will not modify its value. One of the erase commands must be used
to set all of the bits in the block to ‘1’.
See Figure 23, for a suggested flowchart on using the Quadruple Byte Program command.
Typical Quadruple Byte Program times are given in Table 18.
4.0.6
Double/Quadruple Byte Program command (FWH mode)
The Double/Quadruple Byte Program Command can be used to program two/four adjacent
Bytes to the memory array at a time. The two Bytes must differ only for address A0; the four
Bytes must differ only for addresses A0 and A1.
Two Bus Write operations are required to issue the command. The second Bus Write cycle
latches the start address and two/four data Bytes and starts the Program/Erase Controller.
Once the command is issued, subsequent Bus Read operations read the contents of the
Status Register. (See the section on the Status Register for details on the definitions of the
Status Register bits.)
During the Double/Quadruple Byte Program operation the memory will only accept the Read
Status register and Program/Erase Suspend commands. All other commands are ignored.
Note that the Double/Quadruple Byte Program command cannot change a bit set to ‘0’ back
to ‘1’ and attempting to do so will not modify its value. One of the erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 22, for a suggested flowchart on using the Double/Quadruple Byte Program
command. Typical Double/Quadruple Byte Program times are given in Table 18.
28/64
M50FLW040A, M50FLW040B
Command interface
4.0.7
4.0.8
4.0.9
Chip Erase command
The Chip Erase Command erases the entire memory array, setting all of the bits to ‘1’. All
previous data in the memory array are lost. This command, though, is only available under
the A/A Mux interface.
Two Bus Write operations are required to issue the command, and to start the
Program/Erase Controller. Once the command is issued, subsequent Bus Read operations
read the contents of the Status Register. (See the section on the Status Register for details
on the definitions of the Status Register bits.)
Erasing should not be attempted when V is not at V
, otherwise the result is uncertain.
PPH
PP
During the Chip Erase operation, the memory will only accept the Read Status Register
command. All other commands are ignored.
See Figure 25, for a suggested flowchart on using the Chip Erase command. Typical Chip
Erase times are given in Table 18.
Block Erase command
The Block Erase command is used to erase a block, setting all of the bits to ‘1’. All previous
data in the block are lost.
Two Bus Write operations are required to issue the command. The second Bus Write cycle
latches the block address and starts the Program/Erase Controller. Once the command is
issued, subsequent Bus Read operations read the contents of the Status Register. (See the
section on the Status Register for details on the definitions of the Status Register bits.)
If the block is protected (FWH/LPC only) then the Block Erase operation will abort, the data
in the block will not be changed, and the Status Register will indicate the error.
During the Block Erase operation the memory will only accept the Read Status Register and
Program/Erase Suspend commands. All other commands are ignored.
See Figure 26, for a suggested flowchart on using the Block Erase command. Typical Block
Erase times are given in Table 18.
Sector Erase command
The Sector Erase command is used to erase a Uniform 4-KByte Sector, setting all of the bits
to ‘1’. All previous data in the sector are lost.
Two Bus Write operations are required to issue the command. The second Bus Write cycle
latches the Sector address and starts the Program/Erase Controller. Once the command is
issued, subsequent Bus Read operations read the contents of the Status Register. (See the
section on the Status Register for details on the definitions of the Status Register bits.)
If the Block to which the Sector belongs is protected (FWH/LPC only) then the Sector Erase
operation will abort, the data in the Sector will not be changed, and the Status Register will
indicate the error.
During the Sector Erase operation the memory will only accept the Read Status Register
and Program/Erase Suspend commands. All other commands are ignored.
See Figure 26, for a suggested flowchart on using the Sector Erase Command. Typical
Sector Erase times are given in Table 18.
29/64
Command interface
M50FLW040A, M50FLW040B
4.0.10
Clear Status Register command
The Clear Status Register command is used to reset Status Register bits SR1, SR3, SR4
and SR5 to ‘0’. One Bus Write is required to issue the command. Once the command is
issued, the device returns to its previous mode, subsequent Bus Read operations continue
to output the data from the same area, as before.
Once set, these Status Register bits remain set. They do not automatically return to ‘0’, for
example, when a new program or erase command is issued. If an error has occurred, it is
essential that any error bits in the Status Register are cleared, by issuing the Clear Status
Register command, before attempting a new program or erase command.
4.0.11
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause the Program/Erase Controller
during a program or Sector/Block Erase operation. One Bus Write cycle is required to issue
the command.
Once the command has been issued, it is necessary to poll the Program/Erase Controller
Status bit until the Program/Erase Controller has paused. No other commands are accepted
until the Program/Erase Controller has paused. After the Program/Erase Controller has
paused, the device continues to output the contents of the Status Register until another
command is issued.
During the polling period, between issuing the Program/Erase Suspend command and the
Program/Erase Controller pausing, it is possible for the operation to complete. Once the
Program/Erase Controller Status bit indicates that the Program/Erase Controller is no longer
active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to
determine if the operation has completed or is suspended.
During Program/Erase Suspend, the Read Memory Array, Read Status Register, Read
Electronic Signature and Program/Erase Resume commands will be accepted by the
Command Interface. Additionally, if the suspended operation was Sector Erase or Block
Erase then the program command will also be accepted. However, it should be noted that
only the Sectors/Blocks not being erased may be read or programmed correctly.
See Figure 24, and Figure 27, for suggested flowcharts on using the Program/Erase
Suspend command. Typical times and delay durations are given in Table 18.
4.0.12
Program/Erase Resume command
The Program/Erase Resume command can be used to restart the Program/Erase Controller
after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the
command. Once the command is issued, subsequent Bus Read operations read the
contents of the Status Register.
30/64
M50FLW040A, M50FLW040B
Table 13. Commands
Command interface
Bus operations(1)
3rd
Command
1st
2nd
Data
4th
5th
Addr Data Addr
Addr Data Addr Data Addr Data
Read
Addr
Read
Data
(Read (Read (Read (Read (Read (Read
Addr2) Data2) Addr3) Data3) Addr4) Data4)
Read Memory Array(2),(3),(4) 1+
X
X
X
X
X
FFh
70h
Status
Reg
(Status
Reg)
(Status
Reg)
(Status
Reg)
Read Status Register(5),(3)
1+
X
(X)
(X)
(X)
90h or Sig
98h Addr
(Sig (Signat (Sig (Signat (Sig (Signat
Read Electronic Signature(3) 1+
Signature
Addr)
ure)
Addr)
ure) Addr) ure)
Program / Multiple Byte
40h or Prog
10h Addr
Prog
Data
2
program (FWH)(6),(7),(4)
Quadruple Byte Program
Prog
Data1
Prog
Data2
Prog
Data3
Prog
Data4
5
30h
A1
A2
A3
A4
(A/A Mux)(6),(8)
Chip Erase(6)
2
2
2
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
80h
20h
32h
50h
B0h
D0h
00h
01h
60h
2Fh
C0h
X
10h
D0h
D0h
Block Erase(6)
BA
SA
Sector Erase(6)
Clear Status Register(9)
Program/Erase suspend(10)
Program/Erase resume(11)
Invalid reserved(12)
1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read
Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles
are WRITE.
BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC
mode), and A21, A20 and A19 are set according to the rules shown in Table 5 (for LPC mode)
2. After a Read Memory Array command, read the memory as normal until another command is issued.
3. “1+” indicates that there is one write cycle, followed by any number of read cycles.
4. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read
Operation is all that is needed.
5. After a Read Status Register command, read the Status Register as normal until another command is issued.
6. After the erase and program commands read the Status Register until the command completes and another command is
issued.
7. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t
Care. PD is two or four Bytes depending on Msize code.
8. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
9. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.
10. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during
Erase Suspend) and Program/Erase Resume commands can be issued.
11. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status
Register until the Program/Erase Controller completes and the memory returns to Read Mode.
12. Do not use Invalid or Reserved commands.
31/64
Status Register
M50FLW040A, M50FLW040B
5
Status Register
The Status Register provides information on the current or previous Program or Erase
operation. The bits in the Status Register convey specific information about the progress of
the operation.
To read the Status Register, the Read Status Register command can be issued. The Status
Register is automatically read after Program, Erase and Program/Erase Resume
commands are issued. The Status Register can be read from any address.
The text descriptions, below, should be read in conjunction with Table 14, where the
meanings of the Status Register bits are summarized.
5.1
Program/Erase Controller status (Bit SR7)
This bit indicates whether the Program/Erase Controller is active or inactive. When the
Program/Erase Controller Status bit is ‘0’, the Program/Erase Controller is active; when the
bit is ‘1’, the Program/Erase Controller is inactive.
The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend
command is issued, until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses, the bit is ‘1’.
The end of a Program and Erase operation can be found by polling the Program/Erase
Controller Status bit can be polled. The other bits in the Status Register should not be tested
until the Program/Erase Controller has completed the operation (and the Program/Erase
Controller Status bit is ‘1’).
After the Program/Erase Controller has completed its operation, the Erase Status, Program
Status, V Status and Block Protection Status bits should be tested for errors.
PP
5.2
Erase Suspend status (Bit SR6)
This bit indicates that an Erase operation has been suspended, and that it is waiting to be
resumed. The Erase Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). After a
Program/Erase Suspend command is issued, the memory may still complete the operation
rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’, the Program/Erase Controller is active or has
completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been
issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued, the Erase Suspend Status bit returns
to ‘0’.
32/64
M50FLW040A, M50FLW040B
Status Register
5.3
Erase status (Bit SR5)
This bit indicates if a problem has occurred during the erasing of a Sector or Block. The
Erase Status bit should be read once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’, the memory has successfully verified that the Sector/Block
has been erased correctly. When the Erase Status bit is ‘1’, the Program/Erase Controller
has applied the maximum number of pulses to the Sector/Block and still failed to verify that
the Sector/Block has been erased correctly.
Once the Erase Status bit is set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register
command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to have failed, too.
5.3.1
Program status (Bit SR4)
This bit indicates if a problem has occurred during the programming of a byte. The Program
Status bit should be read once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Program Status bit is ‘0’, the memory has successfully verified that the byte has
been programmed correctly. When the Program Status bit is ‘1’, the Program/Erase
Controller has applied the maximum number of pulses to the byte and still failed to verify
that the byte has been programmed correctly.
Once the Program Status bit is set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register
command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to have failed, too.
5.3.2
V
status (Bit SR3)
PP
This bit indicates whether an invalid voltage was detected on the V pin at the beginning of
PP
a Program or Erase operation. The V pin is only sampled at the beginning of the
PP
operation. Indeterminate results can occur if V becomes invalid during a Program or
PP
Erase operation.
Once the V Status bit set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register
PP
command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to have failed, too.
5.3.3
Program Suspend status (Bit SR2)
This bit indicates that a Program operation has been suspended, and that it is waiting to be
resumed. The Program Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). After a
Program/Erase Suspend command is issued, the memory may still complete the operation
instead of entering the Suspend mode.
When the Program Suspend Status bit is ‘0’, the Program/Erase Controller is active, or has
completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been
issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued, the Program Suspend Status bit
returns to ‘0’.
33/64
Status Register
M50FLW040A, M50FLW040B
5.3.4
Block Protection status (Bit SR1)
The Block Protection Status bit can be used to identify if the Program or Erase operation has
tried to modify the contents of a protected block. When the Block Protection Status bit is to
‘0’, no Program or Erase operations have been attempted to protected blocks since the last
Clear Status Register command or hardware reset. When the Block Protection Status bit is
‘1’, a Program or Erase operation has been attempted on a protected block.
Once it is set to ‘1’, the Block Protection Status bit can only be reset to ‘0’ by a Clear Status
Register command or by a hardware reset. If it is set to ‘1’, it should be reset before a new
Program or Erase command is issued, otherwise the new command will appear to have
failed, too.
Using the A/A Mux Interface, the Block Protection Status bit is always ‘0’.
5.3.5
Reserved (Bit SR0)
Bit 0 of the Status Register is reserved. Its value should be masked.
Table 14. Status Register bits
Operation
SR7 SR6 SR5 SR4 SR3 SR2 SR1
Program active
‘0’
‘1
X(1)
X(1)
X(1)
X(1)
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘1’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Program suspended
Program completed successfully
Program failure due to VPP Error
‘1’
‘1’
Program failure due to Block Protection (FWH/LPC
Interface only)
‘1’
X(1)
‘0’
‘1’
‘0’
‘0’
‘1’
Program failure due to cell failure
Erase active
‘1’
‘0’
‘1’
‘1’
‘1’
X(1)
‘0’
)
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Erase suspended
‘1’
Erase completed successfully
Erase failure due to VPP Error
‘0’
‘0’
Erase failure due to Block Protection (FWH/LPC
Interface only)
‘1’
‘1’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
Erase failure due to failed cell(s) in block
1. For Program operations during Erase Suspend Bit SR6 is ‘1’, otherwise Bit SR6 is ‘0’.
34/64
M50FLW040A, M50FLW040BFirmware hub/low pin count (FWH/LPC) interface Configuration Reg-
6
Firmware hub/low pin count (FWH/LPC) interface
Configuration Registers
When the Firmware Hub Interface/Low Pin Count is selected, several additional registers
can be accessed. These registers control the protection status of the Blocks, read the
General Purpose Input pins and identify the memory using the manufacturer code. See
Table 15 for the memory map of the Configuration Registers. The Configuration registers
are accessed directly without using any specific command code. A single Bus Write or Bus
Read Operation, with the appropriate address (including A22=0), is all that is needed.
6.1
Lock Registers
The Lock Registers control the protection status of the Blocks. Each Block has its own Lock
Register. Three bits within each Lock Register control the protection of each block: the Write
Lock Bit, the Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written. Care should be taken, though, when writing.
Once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be
made until it is cleared again by a reset or power-up.
See Table 16 for details on the bit definitions of the Lock Registers.
6.1.1
Write Lock
The Write Lock Bit determines whether the contents of the Block can be modified (using the
Program or Erase Command). When the Write Lock Bit is set, ‘1’, the block is write
protected – any operations that attempt to change the data in the block will fail, and the
Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the block is not
write protected by the Lock Register, and may be modified, unless it is write protected by
some other means.
If the Top Block Lock signal, TBL, is Low, V , then the Top Block (Block 7) is write protected,
IL
and cannot be modified. Similarly, if the Write Protect signal, WP, is Low, V , then the Main
IL
Blocks (Blocks 0 to 6) are write protected, and cannot be modified.
After power-up, or reset, the Write Lock Bit is always set to ‘1’ (write-protected).
6.1.2
Read Lock
The Read Lock bit determines whether the contents of the Block can be read (in Read
mode). When the Read Lock Bit is set, ‘1’, the block is read protected – any operation that
attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is
reset, ‘0’, read operations are allowed in the Block, and return the value of the data that had
been programmed in the block.
After power-up, or reset, the Read Lock Bit is always reset to ‘0’ (not read-protected).
35/64
Firmware hub/low pin count (FWH/LPC) interface Configuration Registers
M50FLW040A,
6.1.3
Lock Down
The Lock Down Bit provides a mechanism for protecting software data from simple hacking
and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write
Lock, Read Lock and Lock Down Bits cannot be performed. A reset, or power-up, is required
before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write
Lock, Read Lock and Lock Down Bits can be changed.
Table 15. Configuration Register map
Memory
Address
Default
Value
Mnemonic
Register Name
Access
Lock Registers (For details, see Appendix A)
Firmware Hub/Low Pin Count (FWH/LPC)
GPI_REG
FBC0100h
FBC0000h
N/A
20h
R
R
General Purpose Input Register
MANU_REG Manufacturer Code Register
1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0,
and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to
Table 9.
Table 16. Lock Register bit definitions
Bit
Bit Name
Value
Function(1)
7-3
Reserved
‘1’
‘0’
Bus Read operations in this Block always return 00h.
2
1
Read-Lock
Bus read operations in this Block return the Memory Array contents.
(Default value).
Changes to the Read-Lock bit and the Write-Lock bit cannot be
performed. Once a ‘1’ is written to the Lock-Down bit it cannot be
cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP
or INIT) or after power-up.
‘1’
Lock-Down
Write-Lock
Read-Lock and Write-Lock can be changed by writing new values to
them. (Default value).
‘0’
‘1’
‘0’
Program and Erase operations in this Block will set an error in the
Status Register. The memory contents will not be changed. (Default
value).
0
Program and Erase operations in this Block are executed and will
modify the Block contents.
1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to
Top Block [-7] Lock Register (T_MINUS07_LK).
36/64
M50FLW040A, M50FLW040BFirmware hub/low pin count (FWH/LPC) interface Configuration Reg-
Table 17. General-Purpose Input Register definition
Bit
Bit Name
Value
Function(1)
7-5
Reserved
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
Input Pin GPI4 is at VIH
Input Pin GPI4 is at VIL
Input Pin GPI3 is at VIH
Input Pin GPI3 is at VIL
Input Pin GPI2 is at VIH
Input Pin GPI2 is at VIL
Input Pin GPI1 is at VIH
Input Pin GPI1 is at VIL
Input Pin GPI0 is at VIH
Input Pin GPI0 is at VIL
4
3
2
1
0
GPI4
GPI3
GPI2
GPI1
GPI0
1. Applies to the General Purpose Inputs Register (GPI-REG).
6.2
6.3
Firmware hub/low-pin count (FWH/LPC) General-Purpose
Input Register
The FWH/LPC General Purpose Input Register holds the state of the General Purpose
Input pins, GPI0-GPI4. When this register is read, the state of these pins is returned. This
register is read-only. Writing to it has no effect.
The signals on the FWH/LPC Interface General Purpose Input pins should remain constant
throughout the whole Bus Read cycle.
Manufacturer Code Register
Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer
Code for STMicroelectronics. This register is read-only. Writing to it has no effect.
37/64
Program and Erase times
M50FLW040A, M50FLW040B
7
Program and Erase times
The Program and Erase times are shown in Table 18.
Table 18. Program and Erase times
Parameter
Byte Program
Interface
Test Condition Min Typ(1) Max Unit
10
200
µs
µs
Double Byte Program
FWH
VPP = 12 V ± 5%
PP = 12 V ± 5%
10(2) 200
A/A Multiplexed
FWH
Quadruple Byte Program
V
10(3) 200
µs
s
VPP = 12 V ± 5%
VPP = VCC
0.1(4)
0.4
0.4
0.5
0.75
1
5
5
Block Program
VPP = 12 V ± 5%
VPP = VCC
4
Sector Erase (4 KBytes)(5)
s
s
5
V
PP = 12 V ± 5%
VPP = VCC
8
Block Erase (64 KBytes)
Chip Erase
10
A/A Multiplexed
VPP = 12 V ± 5%
5
s
Program/Erase Suspend to
Program pause(5)
5
µs
Program/Erase Suspend to
Block Erase/Sector Erase
pause(5)
30
µs
1. TA = 25°C, VCC = 3.3V
2. Time to program two Bytes.
3. Time to program four Bytes.
4. Time obtained executing the Quadruple Byte Program command.
5. Sampled only, not 100% tested.
38/64
M50FLW040A, M50FLW040B
Maximum rating
8
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 19. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
TSTG
VIO
Storage Temperature
–65
–0.50
–0.50
–0.6
150
°C
V
Input or Output range (1)
Supply Voltage
VCC + 0.6
VCC
VPP
4
V
Program Voltage
13
V
Electrostatic Discharge Voltage (Human Body
model)(2)
VESD
–2000
2000
V
1. Minimum voltage may undershoot to –2 V for less than 20ns during transitions. Maximum voltage may
overshoot to VCC + 2 V for less than 20 ns during transitions.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
39/64
DC and AC parameters
M50FLW040A, M50FLW040B
9
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 20, Table 21 and Table 22. Designers should check that the operating conditions in
their circuit match the operating conditions when relying on the quoted parameters.
Table 20. Operating conditions
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply Voltage
Ambient Operating Temperature (Device Grade 5)
3.0
3.6
85
V
–20
°C
Table 21. FWH/LPC interface AC measurement conditions
Parameter
Value
Unit
Load Capacitance (CL)
10
pF
ns
V
Input Rise and Fall Times
≤1.4
Input Pulse Voltages
0.2 VCC and 0.6 VCC
0.4 VCC
Input and Output Timing Ref. Voltages
V
Table 22. A/A Mux interface AC measurement conditions
Parameter
Value
Unit
Load Capacitance (CL)
30
≤10
pF
ns
V
Input Rise and Fall Times
Input Pulse Voltages
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Figure 10. FWH/LPC interface AC measurement I/O waveforms
0.6 V
CC
0.4 V
CC
0.2 V
CC
Input and Output AC Testing Waveform
I
< I
I
> I
I
< I
O LO
O
LO
O
LO
Output AC Tri-state Testing Waveform
AI03404
40/64
M50FLW040A, M50FLW040B
DC and AC parameters
Figure 11. A/A Mux interface AC measurement I/O waveform
3V
0V
1.5V
AI01417
Figure 12. AC measurement load circuit
V
DD
V
PP
V
DD
16.7kΩ
DEVICE
UNDER
TEST
C
L
16.7kΩ
0.1µF
0.1µF
C
includes JIG capacitance
L
AI08430
(1)
Table 23. Impedance
Symbol
Parameter
Test Condition
Min
Max
Unit
(2)
CIN
Input Capacitance
Clock Capacitance
VIN = 0V
VIN = 0V
13
12
pF
pF
(2)
CCLK
3
Recommended Pin
Inductance
(3)
LPIN
20
nH
1. TA = 25°C, f = 1MHz.
2. Sampled only, not 100% tested.
3. See PCI Specification.
41/64
DC and AC parameters
M50FLW040A, M50FLW040B
Table 24. DC characteristics
Symbol
Parameter
Interface
Test Condition
Min
Max
Unit
FWH
0.5 VCC VCC + 0.5
0.7 VCC VCC + 0.3
V
V
VIH
Input High Voltage
A/A Mux
FWH/LPC
A/A Mux
–0.5
-0.5
1.1
0.3 VCC
0.8
V
VIL
Input Low Voltage
V
VIH(INIT) INIT Input High Voltage FWH/LPC
VCC + 0.5
0.2 VCC
±10
V
VIL(INIT) INIT Input Low Voltage FWH/LPC
–0.5
V
(1)
ILI
Input Leakage Current
0 V ≤VIN ≤VCC
µA
IC, IDx Input Leakage
Current
IC, ID0, ID1, ID2, ID3(2)
= VCC
ILI2
200
100
µA
IC, IDx Input Pull Low
Resistor
RIL
20
kΩ
FWH/LPC
A/A Mux
FWH/LPC
A/A Mux
IOH = –500 µA
IOH = –100 µA
0.9 VCC
V
V
V
V
VOH
Output High Voltage
Output Low Voltage
VCC – 0.4
I
OL = 1.5 mA
OL = 1.8 mA
0.1 VCC
0.45
VOL
I
Output Leakage
Current
ILO
0V ≤VOUT ≤VCC
±10
3.6
µA
V
VPP1
VPPH
VPP Voltage
3
VPP Voltage (Fast
Erase)
11.4
1.8
12.6
2.3
V
(3)
VLKO
VCC Lockout Voltage
V
FWH4/LFRAME =
0.9VCC
VPP = VCC
Supply Current
(Standby)
ICC1
FWH/LPC
100
µA
All other inputs 0.9VCC
to 0.1VCC
VCC = 3.6 V, f(CLK) =
33 MHz
FWH4/LFRAME = 0.1
VCC, VPP = VCC
All other inputs 0.9 VCC
to 0.1 VCC
VCC = 3.6 V, f(CLK) =
33 MHz
Supply Current
(Standby)
ICC2
FWH/LPC
FWH/LPC
10
60
mA
mA
VCC = VCC max,
VPP = VCC
f(CLK) = 33 MHz
IOUT = 0 mA
Supply Current
ICC3
(Any internal operation
active)
ICC4
Supply Current (Read) A/A Mux
G = VIH, f = 6 MHz
20
20
mA
mA
Supply Current
A/A Mux
Program/Erase
Controller Active
(3)
ICC5
(Program/Erase)
42/64
M50FLW040A, M50FLW040B
DC and AC parameters
Table 24. DC characteristics (continued)
Symbol
Parameter
Interface
Test Condition
PP > VCC
Min
Max
Unit
VPP Supply Current
(Read/Standby)
IPP
V
400
µA
VPP = VCC
40
15
mA
mA
VPP Supply Current
(Program/Erase active)
(3)
IPP1
VPP = 12 V ± 5%
1. Input leakage currents include High-Z output leakage for all bidirectional buffers with three-state outputs.
2. ID3 pin is RFU in LPC mode.
3. Sampled only, not 100% tested.
Figure 13. FWH/LPC interface clock waveform
tCYC
tHIGH
tLOW
0.6 V
0.5 V
0.4 V
0.3 V
0.2 V
CC
CC
CC
CC
CC
0.4 V
,
CC p-to-p
(minimum)
AI03403
Table 25. FWH/LPC interface clock characteristics
Symbol
Parameter
Test Condition
Value
Unit
tCYC
tHIGH
tLOW
CLK Cycle Time(1)
CLK High Time
CLK Low Time
Min
Min
Min
Min
Max
30
11
11
1
ns
ns
ns
V/ns
V/ns
CLK Slew Rate
peak to peak
4
1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz
devices may be guaranteed by design rather than tested. Refer to PCI Specification.
43/64
DC and AC parameters
M50FLW040A, M50FLW040B
Figure 14. FWH/LPC interface AC signal timing waveforms
CLK
tCHQV
tCHQZ
tDVCH
tCHDX
tCHQX
FWH0-FWH3/
LAD0-LAD3
VALID
tCHFH
tFLCH
FWH4
VALID
OUTPUT DATA
START CYCLE
FLOAT OUTPUT DATA
VALID INPUT DATA
AI09700
Table 26. FWH/LPC interface AC signal timing characteristics
Symbol
PCI Symbol
Parameter
Value
Unit
Min
2
ns
ns
tCHQV
tval
CLK to Data Out
CLK to Active
Max
11
(1)
tCHQX
ton
toff
tsu
th
Min
Max
Min
Min
2
28
7
ns
ns
ns
ns
(Float to Active Delay)
CLK to Inactive
tCHQZ
(Active to Float Delay)
tAVCH
tDVCH
tCHAX
tCHDX
tFLCH
tCHFH
Input Set-up Time(2)
Input Hold Time(2)
0
Input Set-up time on FWH4
Input Hold time on FWH4
Min
Min
10
5
ns
ns
1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage
current specification.
2. Applies to all inputs except CLK and FWH4.
44/64
M50FLW040A, M50FLW040B
DC and AC parameters
Figure 15. Reset AC waveforms
RP, INT
tPLPH
tPHWL, tPHGL, tPHFL
W, G, FWH4/LFRAME
tPLRH
RB
ai08422
Table 27. Reset AC characteristics
Symbol
Parameter
Test Condition
Value
Unit
tPLPH
RP or INIT Reset Pulse Width
Min
Max
Max
Min
100
100
30
ns
ns
Program/Erase Inactive
Program/Erase Active
Rising edge only
tPLRH RP or INIT Low to Reset
RP or INIT Slew Rate(1)
µs
50
mV/ns
RP or INIT High to
tPHFL
FWH/LPC Interface only
A/A Mux Interface only
Min
Min
30
50
µs
µs
FWH4/LFRAME Low
tPHWL
tPHGL
RP High to Write Enable or
Output Enable Low
1. See Chapter 4 of the PCI Specification.
45/64
DC and AC parameters
M50FLW040A, M50FLW040B
Figure 16. A/A Mux interface Read AC waveforms
tAVAV
A0-A10
ROW ADDR VALID COLUMN ADDR VALID
NEXT ADDR VALID
tAVCL
tAVCH
tCLAX
tCHAX
RC
G
tCHQV
tGLQV
tGLQX
tGHQZ
tGHQX
VALID
DQ0-DQ7
W
tPHAV
RP
AI03406
Table 28. A/A Mux interface Read AC characteristics
Symbol
Parameter
Test Condition
Value
Unit
tAVAV
tAVCL
tCLAX
tAVCH
tCHAX
Read Cycle Time
Min
Min
Min
Min
Min
250
50
50
50
50
150
50
1
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Row Address Valid to RC Low
RC Low to Row Address Transition
Column Address Valid to RC high
RC High to Column Address Transition
RC High to Output Valid
(1)
tCHQV
Max
Max
Min
Min
Max
Min
(1)
tGLQV
Output Enable Low to Output Valid
RP High to Row Address Valid
tPHAV
tGLQX
tGHQZ
tGHQX
Output Enable Low to Output Transition
Output Enable High to Output Hi-Z
Output Hold from Output Enable High
0
50
0
1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV
.
46/64
M50FLW040A, M50FLW040B
DC and AC parameters
Figure 17. A/A Mux interface Write AC waveforms
Write erase or
program setup
Write erase confirm or Automated erase
valid address and data or program delay
Read Status
Register Data
Ready to write
another command
A0-A10
RC
R1
C1
R2
C2
tCLAX
tAVCH
tAVCL
tCHAX
tWHWL
tWLWH
tCHWH
W
G
tVPHWH
tWHGL
tWHRL
RB
tQVVPL
V
PP
tDVWH
tWHDX
DQ0-DQ7
D
D
VALID SRD
IN1
IN2
AI04185
Table 29. A/A Mux interface Write AC characteristics
Symbol
Parameter
Test Condition
Value
Unit
tWLWH
tDVWH
tWHDX
tAVCL
Write Enable Low to Write Enable High
Data Valid to Write Enable High
Write Enable High to Data Transition
Row Address Valid to RC Low
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
100
50
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
50
50
100
50
100
30
0
tCLAX
tAVCH
tCHAX
tWHWL
tCHWH
RC Low to Row Address Transition
Column Address Valid to RC High
RC High to Column Address Transition
Write Enable High to Write Enable Low
RC High to Write Enable High
(1)
tVPHWH
tWHGL
tWHRL
VPP High to Write Enable High
Write Enable High to Output Enable Low
Write Enable High to RB Low
(1),(2)
tQVVPL
Output Valid, RB High to VPP Low
0
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
47/64
Package mechanical
M50FLW040A, M50FLW040B
10
Package mechanical
Figure 18. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package
outline
D
A1
D1
A2
1
N
B1
e
E2
E2
E3
E1 E
F
B
0.51 (.020)
1.14 (.045)
D3
A
R
CP
D2
D2
PLCC-A
1. Drawing is not to scale.
Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
3.18
1.53
0.38
0.33
0.66
3.56
2.41
–
0.125
0.060
0.015
0.013
0.026
0.140
0.095
–
0.53
0.81
0.10
12.57
11.51
5.66
–
0.021
0.032
0.004
0.495
0.453
0.223
–
B1
CP
D
12.32
11.35
4.78
–
0.485
0.447
0.188
–
D1
D2
D3
E
7.62
0.300
14.86
13.89
6.05
–
15.11
14.05
6.93
–
0.585
0.547
0.238
–
0.595
0.553
0.273
–
E1
E2
E3
e
10.16
1.27
0.400
0.050
–
–
–
–
F
0.00
–
0.13
–
0.000
–
0.005
–
R
0.89
0.035
N
32
32
48/64
M50FLW040A, M50FLW040B
Package mechanical
Figure 19. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
1. Drawing is not to scale.
Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
α
1.200
0.150
1.050
5°
0.0472
0.0059
0.0413
5°
0.050
0.950
0°
0.0020
0.0374
0°
B
0.170
0.100
0.270
0.210
0.100
14.200
12.500
–
0.0067
0.0039
0.0106
0.0083
0.0039
0.5591
0.4921
–
C
CP
D
13.800
12.300
–
0.5433
0.4843
–
D1
e
0.500
0.0197
E
7.900
0.500
32
8.100
0.700
0.3110
0.0197
32
0.3189
0.0276
L
N
49/64
Package mechanical
M50FLW040A, M50FLW040B
Figure 20. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.200
0.150
1.050
0.270
0.210
0.100
20.200
18.500
–
0
0
0
0
0
0
1
1
–
0
0
5°
0.050
0.950
0.170
0.100
0
0
0
0
C
CP
D
19.800
18.300
–
1
1
D1
e
0.500
0
–
E
9.900
0.500
0°
10.100
0.700
5°
0
L
0
α
0°
40
N
40
50/64
M50FLW040A, M50FLW040B
Part numbering
11
Part numbering
Table 33. Ordering information scheme
Example:
M50FLW040
A
K
5
T
P
Device Type
M50 = Flash Memory for PC BIOS
Architecture
FL = Firmware Hub/Low Pin Count Interface
Operating Voltage
W = VCC = 3.0 to 3.6V
Device Function
040 = 4 Mbit (x8), Uniform Blocks and Sectors
Array Matrix
A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors
B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors(1)
Package
K = PLCC32
NB = TSOP32: 8 x 14mm(2)
N = TSOP40: 10 x 20 mm(2)
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHs compliant)
1. Devices with this architecture are Not Recommended for New Design.
2. Devices delivered in this package are Not Recommended for New Design.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
51/64
Block and sector address table
M50FLW040A, M50FLW040B
Appendix A Block and sector address table
(1)
Table 34. M50FLW040A block and sector addresses
Block Size
(KByte)
Block No
and Type
Sector Size
(KByte)
Register
Address
Address Range
Sector No
7F000h-7FFFFh
7E000h-7EFFFh
7D000h-7DFFFh
7C000h-7CFFFh
7B000h-7BFFFh
7A000h-7AFFFh
79000h-79FFFh
78000h-78FFFh
77000h-77FFFh
76000h-76FFFh
75000h-75FFFh
74000h-74FFFh
73000h-73FFFh
72000h-72FFFh
71000h-71FFFh
70000h-70FFFh
6F000h-6FFFFh
6E000h-6EFFFh
6D000h-6DFFFh
6C000h-6CFFFh
6B000h-6BFFFh
6A000h-6AFFFh
69000h-69FFFh
68000h-68FFFh
67000h-67FFFh
66000h-66FFFh
65000h-65FFFh
64000h-64FFFh
63000h-63FFFh
62000h-62FFFh
61000h-61FFFh
60000h-60FFFh
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
7
64
FBF0002
(Top)
6
64
FBE0002
(Main)
52/64
M50FLW040A, M50FLW040B
Block and sector address table
(1)
Table 34. M50FLW040A block and sector addresses (continued)
Block Size
(KByte)
Block No
and Type
Sector Size
(KByte)
Register
Address
Address Range
50000h- 5FFFFh
40000h- 4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
Sector No
5
64
64
64
64
64
FBD0002
FBC0002
FBB0002
FBA0002
FB90002
(Main)
4
(Main)
3
(Main)
2
(Main)
1
(Main)
0F000h-0FFFFh
0E000h-0EFFFh
0D000h-0DFFFh
0C000h-0CFFFh
0B000h-0BFFFh
0A000h-0AFFFh
09000h-09FFFh
08000h-08FFFh
07000h-07FFFh
06000h-06FFFh
05000h-05FFFh
04000h-04FFFh
03000h-03FFFh
02000h-02FFFh
01000h-01FFFh
00000h-00FFFh
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
15
14
13
12
11
10
9
8
0
64
FB80002
(Main)
7
6
5
4
3
2
1
0
1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0,
and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to
Table 9.
53/64
Block and sector address table
M50FLW040A, M50FLW040B
(1)
Table 35. M50FLW040B block and sector addresses
Block Size
(KByte)
Block No
and Type
Sector Size
(KByte)
Register
Sector No
Address Range
Address
7F000h-7FFFFh
7E000h-7EFFFh
7D000h-7DFFFh
7C000h-7CFFFh
7B000h-7BFFFh
7A000h-7AFFFh
79000h-79FFFh
78000h-78FFFh
77000h-77FFFh
76000h-76FFFh
75000h-75FFFh
74000h-74FFFh
73000h-73FFFh
72000h-72FFFh
71000h-71FFFh
70000h-70FFFh
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
47
46
45
44
43
42
41
40
7
64
FBF0002
39
(Top)
38
37
36
35
34
33
32
6
64
64
64
64
64
60000h- 6FFFFh
50000h- 5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
FBE0002
FBD0002
FBC0002
FBB0002
FBA0002
(Main)
5
(Main)
4
(Main)
3
(Main)
2
(Main)
54/64
M50FLW040A, M50FLW040B
Block and sector address table
(1)
Table 35. M50FLW040B block and sector addresses (continued)
Block Size
(KByte)
Block No
and Type
Sector Size
(KByte)
Register
Address
Address Range
Sector No
1F000h-1FFFFh
1E000h-1EFFFh
1D000h-1DFFFh
1C000h-1CFFFh
1B000h-1BFFFh
1A000h-1AFFFh
19000h-19FFFh
18000h-18FFFh
17000h-17FFFh
16000h-16FFFh
15000h-15FFFh
14000h-14FFFh
13000h-13FFFh
12000h-12FFFh
11000h-11FFFh
10000h-10FFFh
0F000h-0FFFFh
0E000h-0EFFFh
0D000h-0DFFFh
0C000h-0CFFFh
0B000h-0BFFFh
0A000h-0AFFFh
09000h-09FFFh
08000h-08FFFh
07000h-07FFFh
06000h-06FFFh
05000h-05FFFh
04000h-04FFFh
03000h-03FFFh
02000h-02FFFh
01000h-01FFFh
00000h-00FFFh
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
1
64
FB90002
(Main)
8
0
64
FB80002
(Main)
7
6
5
4
3
2
1
0
1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0,
and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to
Table 9.
55/64
Flowcharts and pseudo codes
M50FLW040A, M50FLW040B
Appendix B Flowcharts and pseudo codes
Figure 21. Program flowchart and pseudo code
Start
Program command:
– Write 40h or 10h
Write 40h or 10h
– Write Address and Data
(memory enters read status state after
the Program command)
Write Address
and Data
do:
NO
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
Read Status
Register
Suspend
YES
– Enter suspend program loop
NO
NO
NO
NO
Suspend
Loop
SR7 = 1
YES
V
Invalid
Error (1, 2)
If SR3 = 1,
– Enter the "V
PP
SR3 = 0
YES
invalid" error handler
PP
Program
Error (1, 2)
If SR4 = 1,
– Enter the "Program error" error handler
SR4 = 0
YES
FWH/LPC
Interface
Only
If SR1 = 1,
– Enter the "Program to protected
block" error handler
Program to Protected
Block Error (1, 2)
SR1 = 0
YES
End
AI08425B
1. A Status check of SR1 (Protected Block), SR3 (VPP invalid) and SR4 (Program Error) can be made after
each Program operation by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
56/64
M50FLW040A, M50FLW040B
Flowcharts and pseudo codes
Figure 22. Double/Quadruple Byte Program flowchart and pseudo code (FWH mode
only)
Start
Write 40h or 10h
Write Start Address
and 2/4 Data Bytes (3)
Double/Quadruple Byte Program command:
– write 40h or 10h
– write Start Address and 2/4 Data Bytes (3)
(memory enters read status state after
the Double/Quadruple Byte Program command)
do:
NO
– Read Status Register
Read Status
– If SR7=0 and a Program/Erase Suspend
Register
command has been executed
– SR7 is set to 1
Suspend
YES
– Enter suspend program loop
NO
NO
NO
NO
Suspend
Loop
SR7 = 1
YES
V
Invalid
Error (1, 2)
If SR3 = 1, V invalid error:
PP
PP
SR3 = 0
YES
– error handler
Program
Error (1, 2)
If SR4 = 1, Program error:
– error handler
SR4 = 0
YES
Program to Protected
Block Error (1, 2)
If SR1 = 1,
Program to protected block error:
– error handler
SR1 = 0
YES
End
AI08423B
1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation
by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. A0 and/or A1 are treated as Don’t Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte
Program).
For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even
address, and the second at the odd address.
For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the
address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that
has A1-A0 at 10, and the fourth at the address that has A1-A0 at 11.
57/64
Flowcharts and pseudo codes
M50FLW040A, M50FLW040B
Figure 23. Quadruple Byte Program flowchart and pseudo code (A/A Mux interface
only)
Start
Write 30h
Write Address 1
& Data 1 (3)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1 (3)
– write Address 2 & Data 2 (3)
– write Address 3 & Data 3 (3)
Write Address 2
& Data 2 (3)
– write Address 4 & Data 4 (3)
(memory enters read status state after
the Quadruple Byte Program command)
Write Address 3
& Data 3 (3)
Write Address 4
& Data 4 (3)
do:
NO
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
Read Status
Register
Suspend
YES
– Enter suspend program loop
NO
NO
NO
Suspend
Loop
SR7 = 1
YES
V
Invalid
Error (1, 2)
If SR3 = 1, V invalid error:
PP
PP
SR3 = 0
YES
– error handler
Program
Error (1, 2)
If SR4 = 1, Program error:
– error handler
SR4 = 0
YES
End
AI08437B
1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation
by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address
bits A0 and A1.
58/64
M50FLW040A, M50FLW040B
Flowcharts and pseudo codes
Figure 24. Program Suspend and Resume flowchart and pseudo code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
Write 70h
– write 70h
do:
– read Status Register
Read Status
Register
NO
NO
SR7 = 1
YES
while SR7 = 0
SR2 = 1
YES
Program Complete
If SR2 = 0 Program completed
Write a read
Command
Read data from
another address
Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Write D0h
Write FFh
Read Data
Program Continues
AI08426B
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
59/64
Flowcharts and pseudo codes
M50FLW040A, M50FLW040B
Figure 25. Chip Erase flowchart and pseudo code (A/A Mux interface only)
Start
Chip Erase command:
– write 80h
Write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
Write 10h
do:
– read Status Register
Read Status
Register
NO
while SR7 = 0
SR7 = 1
YES
NO
NO
NO
V
Invalid
If SR3 = 1, V invalid error:
PP
PP
Error (1)
SR3 = 0
YES
– error handler
Command
Sequence Error (1)
If SR4, SR5 = 1, Command sequence error:
– error handler
SR4, SR5 = 0
YES
If SR5 = 1, Erase error:
– error handler
SR5 = 0
Erase Error (1)
YES
End
AI08428B
1. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
60/64
M50FLW040A, M50FLW040B
Flowcharts and pseudo codes
Figure 26. Sector/Block Erase flowchart and pseudo code
Start
Block Erase command:
– Write 20h/32h
Write 20h/32h
– Write block Address and D0h
(memory enters read Status Register after
the Block Erase command)
Write Block
Address and D0h
do:
– Read Status Register
– If SR7=0 and a Program/Erase Suspend
command has been executed
– SR7 is set to 1
NO
Read Status
Register
Suspend
YES
– Enter suspend program loop
NO
Suspend
Loop
SR7 = 1
YES
NO
NO
NO
NO
V
Invalid
Error (1)
If SR3 = 1,
– Enter the "V invalid" error handler
PP
SR3 = 0
YES
PP
Command
Sequence Error (1)
If SR4, SR5 = 1,
– Enter the "Command sequence"error handler
SR4, SR5 = 0
YES
If SR5 = 1,
– Enter the "Erase Error" error handler
SR5 = 0
YES
Erase Error (1)
FWH/LPC
Interface
Only
If SR1 = 1,
– Enter the "Erase to protected block"
error handler
Erase to Protected
Block Error (1)
SR1 = 0
YES
End
AI08424B
1. If an error is found, the Status Register must be cleared before further Program/Erase Controller
operations.
61/64
Flowcharts and pseudo codes
M50FLW040A, M50FLW040B
Figure 27. Erase Suspend and Resume flowchart and pseudo code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
Write 70h
– write 70h
do:
Read Status
Register
– read Status Register
NO
NO
SR7 = 1
YES
while SR7 = 0
SR6 = 1
YES
Erase Complete
If SR6 = 0, Erase completed
Read data from
another block/sector
or
Program
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Write D0h
Write FFh
Read Data
Erase Continues
AI08429B
62/64
M50FLW040A, M50FLW040B
Revision history
Revision history
Table 36. Document revision history
Date
Version
Changes
23-Jun-2003
1.0
First Issue
VIH(INIT) min parameter modified in Table 24: DC characteristics.
04-Jul-2003
2.0
Document status promoted from Target Specification to Product Preview
28-Jul-2003
08-Oct-2003
07-Nov-2003
18-Feb-2004
2.1
2.2
2.3
3.0
Document renamed to M50FLW040A, M50FLW040B
Block types removed from the Block and Sector Address tables
Document promoted to Preliminary Data
Wording in the textual descriptions revised throughout the document.
TSOP32 package added. Updates to Tables 8, 9, 12, 13, 14, 15, 19, 26, 34
and 35; and to Figures 14, and 21 to 27
18-May-2004
18-Aug-2004
4.0
5.0
Pins 2 and 5 of the TSOP32 Connections illustration corrected
Document converted to new ST template.
Packages are ECOPACK® compliant. TLEAD removed from Table 19:
Absolute maximum ratings.
24-Oct-2006
6
Device grade 1 removed. Blank Plating Technology option removed from
Table 33: Ordering information scheme.
63/64
M50FLW040A, M50FLW040B
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