M50LPW012K [STMICROELECTRONICS]
2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory; 2兆位256Kb的X8 ，引导块3V电源低引脚数闪存
| 型号： | M50LPW012K |
| 厂家： | 
ST |
| 描述： | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 文件： | 总35页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M50LPW012
2 Mbit (256Kb x8, Boot Block)
3V Supply Low Pin Count Flash Memory
PRELIMINARY DATA
■ SUPPLY VOLTAGE
– V = 3V to 3.6V for Program, Erase and
CC
Read Operations
– V = 12V for Fast Program and Fast Erase
PP
■ LOW PIN COUNT (LPC)
– Standard Interface for embedded operation
with PC Chipsets that are without automap-
ping memory features
■ ADDRESS/ADDRESS MULTIPLEXED (A/A
PLCC32 (K)
MUX)
– Interface for programming equipment com-
patibility
■ LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
Figure 1. Logic Diagram (LPC Interface)
– Hardware Write Protect Pins for Block Pro-
tection
V
V
CC PP
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for plat-
form design flexibility
4
5
4
LAD0-
LAD3
ID0-ID3
– Synchronized with 33MHz PCI clock
■ BYTE PROGRAMMING TIME
– Single Byte Mode 10µs typical
– Quadruple Byte Mode 2.5µs typical
■ 7 MEMORY BLOCKS
GPI0-
GPI4
WP
LFRAME
CLK
IC
TBL
M50LPW012
– 1 Boot Block
– 4 Main Blocks and 2 Parameter Blocks
■ PROGRAM/ERASE CONTROLLER
RP
– Embedded Byte Program and Block/Chip
Erase algorithms
INIT
– Status Register Bits
■ PROGRAM and ERASE SUSPEND
■ FOR USE in PC BIOS APPLICATIONS
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
V
SS
AI06949
– Device Code: 3Bh
September 2002
1/35
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M50LPW012
Figure 2. Logic Diagram (A/A Mux Interface)
DESCRIPTION
The M50LPW012 is a 2Mbit (256Kb x8) non-
volatile memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
V
V
CC PP
11
8
DQ0-DQ7
A0-A10
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
RC
IC
M50LPW012
RB
G
W
RP
V
SS
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
AI06950
Figure 3. PLCC Connections
A/A Mux
A/A Mux
1 32
A7
A6
GPI1
GPI0
WP
IC (V )
IL
NC
IC (V
NC
)
IH
A5
NC
NC
A4
TBL
ID3
V
V
V
V
SS
CC
SS
CC
A3
9
M50LPW012
25
A2
ID2
INIT
G
A1
ID1
LFRAME
RFU
W
A0
ID0
RB
DQ7
DQ0
LAD0
RFU
17
A/A Mux
A/A Mux
AI06951
Note: Pins 27 and 28 are not internally connected.
2/35
M50LPW012
current PC Chipsets; the M50LPW012 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
Table 1. Signal Names (LPC Interface) Memory
LAD0-LAD3
LFRAME
ID0-ID3
GPI0-GPI4
IC
Input/Output Communications
Input Communication Frame
Identification Inputs
General Purpose Inputs
Interface Configuration
Interface Reset
The memory is offered in a PLCC32 package and
is supplied with all the bits erased (set to 1).
RP
System Memory Mapping
INIT
CPU Reset
The LPC address sequence is 32 bits long. The
M50LPW012 responds to addresses mapped to
the top of the 4 GByte memory space, from
FFFF FFFFh. Address bits A31-A24, A22 must be
set to 1. A23 is set to 1 for array access, and to 0
for register access.
The M50LPW012 also responds to addresses
mapped to the bottom of the 4 GByte memory
space, from 0000 0000h. Address bits A31-A24,
A22 must be set to 0. A23 is set to 0 for array
access, and to 1 for register access.
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
Reserved for Future Use. Leave
disconnected or set at V or V .
RFU
IL
IH
V
CC
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
V
PP
V
SS
For A21-A18, see Table 2. A17-A0 are for array
addresses.
Ground
NC
Not Connected Internally
Table 2. Memory Identification Input Configuration
Memory
Top
Bottom
ID2
ID2
ID1
ID0
A
A
A
A
A
A
A
A
Number
21 20 19 18 21 20 19 18
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
or floating
or floating
or floating
or floating
or floating
or floating
or floating
or floating
V
V
V
V
or floating
or floating
or floating
or floating
V
V
or floating
or floating
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
or floating
1 (Boot)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
IL
IL
IL
IL
IL
IL
V
IH
2
3
V
or floating
IH
V
V
IH
4
IH
V
IH
V
V
or floating
or floating
or floating
5
IL
IL
V
IH
V
IH
6
V
IH
V
or floating
7
IH
V
IH
V
V
IH
8
IH
V
IH
V
IL
V
IL
V
IL
V
IL
or floating
or floating
or floating
or floating
V
V
or floating
or floating
or floating
9
IL
IL
V
IH
V
IH
10
11
12
13
14
15
16
V
IH
V
or floating
IH
V
IH
V
V
IH
IH
V
IH
V
IH
V
V
or floating
or floating
or floating
IL
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
or floating
IH
V
IH
V
IH
V
V
IH
IH
3/35
M50LPW012
Table 3. System Memory Map
A31:24, A22
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
A23
Register
Array
Top
FFh, 1b
00h, 0b
1
0
0
1
driven Low, V ; to select the Address/Address
IL
Bottom
Multiplexed (A/A Mux) Interface the pin should be
driven High, V . An internal pull-down resistor is
IH
included with a value of R ; there will be a leakage
IL
current of I through each pin when pulled to V ;
see Table 21.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
SIGNAL DESCRIPTIONS
LI2
IH
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Reset (RP) is set Low, V , the memory is in Reset
IL
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V , the memory is in normal operation.
IH
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Input/Output Communications (LAD0-LAD3). All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (LFRAME). The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock
input is used to prevent the Top Block (Block 6)
from being changed. When Top Block Lock, TBL,
is set Low, V , Program and Block Erase
IL
nication Frame is Low, V , on the rising edge of
IL
operations in the Top Block have no effect,
regardless of the state of the Lock Register. When
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, V , during a bus
IL
Top Block Lock, TBL, is set High, V , the
IH
operation then the operation is aborted. When In-
protection of the Block is determined by the Lock
Register. The state of Top Block Lock, TBL, does
not affect the protection of the Main Blocks (Blocks
0 to 5).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
put Communication Frame is High, V , the cur-
IH
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identification
Inputs (ID0-ID3) allow to address up to 16
memories on a bus. The value on addresses A18-
A21 is compared to the hardware strapping on the
ID0-ID3 pins to select which memory is being
addressed, as shown in Table 2.
General Purpose Inputs (GPI0-GPI4). The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 5)
from being changed. When Write Protect, WP, is
set Low, V , Program and Block Erase operations
IL
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
be left to float, they should be driven Low, V or
IL,
WP, is set High, V , the protection of the Block is
IH
High, V .
IH
determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 6).
Write Protect, WP, must be set prior to a Program
or Block Erase operation is initiated and must not
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
4/35
M50LPW012
be changed until the operation completes or un-
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
WP during Program or Erase Suspend.
Table 4. Signal Names (A/A Mux Interface)
IC
Interface Configuration
A0-A10
Address Inputs
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They may be left disconnected or driven Low,
DQ0-DQ7
Data Inputs/Outputs
Output Enable
G
V , or High, V .
IL
IH
W
Write Enable
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2, Logic Diagram, and Table
4, Signal Names.
RC
RB
RP
Row/Column Address Select
Ready/Busy Output
Interface Reset
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A17). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
V
Supply Voltage
CC
Optional Supply Voltage for Fast
Program and Fast Erase
Operations
V
PP
V
Ground
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
SS
NC
Not Connected Internally
V
. This prevents Bus Write operations from
LKO
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the
memory contents being altered will be invalid.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
After V
becomes valid the Command Interface
CC
is reset to Read mode.
A 0.1µF capacitor should be connected between
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
the V Supply Voltage pins and the V Ground
CC
SS
pin to decouple the current surges from the power
supply. Both V Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents
required during program and erase operations.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row
Address bits (A0-A10) or the Column Address bits
(A11-A17). The Row Address bits are latched on
the falling edge of RC whereas the Column
Address bits are latched on the rising edge.
CC
V
Optional Supply Voltage. The V Optional
PP
PP
Supply Voltage pin is used to select the Fast
Program (see the Quadruple Byte Program
Command description) and Fast Erase options of
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
the memory. V can be left floating. When V
=
PP
PP
Controller. When Ready/Busy is Low, V , the
OL
V
Fast Program (if a Quadruple Byte Program
PPH
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase
Suspend command. When Ready/Busy is High,
Command is performed) and Fast Erase
operations are used.
V
should not be set to V
for more than 80
PPH
PP
V
, the memory is ready for any Read, Program
hours during the life of the memory.
OH
or Erase operation.
Supply Signal Descriptions
V
Ground. V is the reference for all the volt-
SS
SS
age measurements.
The Supply Signals are the same for both interfac-
es.
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
5/35
M50LPW012
(1)
Table 5. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
A
T
–50 to 125
–65 to 150
°C
BIAS
T
°C
STG
(2)
–0.6 to V + 0.6
V
V
V
V
CC
IO
V
CC
–0.6 to 4
V
Program Voltage
–0.6 to 13
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to -2V and for less than 20ns during transitions. Maximum Voltage may overshoot to V
and for less than 20ns during transitions.
+2V
CC
BUS OPERATIONS
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 7, LPC Bus Read Field Definitions,
and Figure 4, LPC Bus Read Waveforms, for a de-
scription of the Field definitions for each clock cy-
cle of the transfer. See Table 23, LPC Interface AC
Signal Timing Characteristics and Figure 9, LPC
Interface AC Signal Timing Waveforms, for details
on the timings of the signals.
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Low Pin Count (LPC) Interface is the usual
interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/
Address Multiplexed (A/A Mux) Interface.
Follow the section Low Pin Count (LPC) Bus
Operations below and the section Address/
Address Multiplexed (A/A Mux) Interface Bus
Operations below for a description of the bus
operations on each interface.
Bus Write. Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input
Low Pin Count (LPC) Bus Operations
The Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME) and a clock (CLK). In addition
protection against accidental or malicious data
corruption can be achieved using two further
signals (TBL and WP). Finally two reset signals
(RP and INIT) are available to put the memory into
a known state.
Communication Frame, LFRAME, is Low, V , as
IL
Clock rises and the correct Start cycle is on LAD0-
LAD3. On the following Clock cycles the Host will
send the Cycle Type + Dir, Address, other control
bits, Data0-Data3 and Data4-Data7 on LAD0-
LAD3. The memory outputs Sync data until the
wait-states have elapsed.
Refer to Table 8, LPC Bus Write Field Definitions,
and Figure 5, LPC Bus Write Waveforms, for a
description of the Field definitions for each clock
cycle of the transfer. See Table 23, LPC Interface
AC Signal Timing Characteristics and Figure 9,
LPC Interface AC Signal Timing Waveforms, for
details on the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
The data signals, control signal and clock are
designed to be compatible with PCI electrical
specifications. The interface operates with clock
speeds up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
V , during the bus operation; the memory will tri-
IL
state the Input/Output Communication pins,
LAD0-LAD3.
Frame, LFRAME, is Low, V , as Clock rises and
IL
the correct Start cycle is on LAD0-LAD3. On the
6/35
M50LPW012
Table 6. Block Addresses
The Address/Address Multiplexed (A/A Mux)
Interface is included for use by Flash
Programming equipment for faster factory
programming. Only a subset of the features
available to the Low Pin Count (LPC) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
Size
Block
Number
Address Range
(KBytes)
Block Type
16
8
3C000h-3FFFFh
3A000h-3BFFFh
6
5
Boot Block
Parameter
Block
Parameter
Block
8
38000h-39FFFh
4
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read. Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then
Write Enable (W) and Interface Reset (RP) must
32
64
64
64
30000h-37FFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
3
2
1
0
Main Block
Main Block
Main Block
Main Block
Note: For A19:18 values, refer to Table 2.
Note that, during a Bus Write operation, the
Command Interface starts executing the
command as soon as the data is fully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.
be High, V , and Output Enable, G, Low, V , in
IH
IL
order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
11, A/A Mux Interface Read AC Waveforms, and
Table 25, A/A Mux Interface Read AC
Characteristics, for details of when the output
becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC. The data should be set up on
the Data Inputs/Outputs; Output Enable, G, and
Standby. When LFRAME is High, V , the
IH
memory is put into Standby mode where LAD0-
LAD3 are put into a high-impedance state and the
Supply Current is reduced to the Standby level,
I
.
CC1
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, V . RP or INIT must be held
Low, V , for t
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 16. If RP or
INIT goes Low, V , during a Program or Erase
operation, the operation is aborted and the
memory cells affected no longer contain valid
data; the memory can take up to t
Program or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
IL
. The memory resets to Read
IL
PLPH
Interface Reset, RP, must be High, V and Write
IH
Enable, W, must be Low, V . The Data Inputs/
IL
Outputs are latched on the rising edge of Write
Enable, W. See Figure 12, A/A Mux Interface
Write AC Waveforms, and Table 26, A/A Mux
Interface Write AC Characteristics, for details of
the timing requirements.
IL
to abort a
PLRH
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at V .
IH
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
Address/Address Multiplexed (A/A Mux) Bus
Operations
in Reset mode when RP is Low, V . RP must be
IL
held Low, V for t
. If RP is goes Low, V ,
IL
PLPH
IL
during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
The Address/Address Multiplexed (A/A Mux)
Interface has a more traditional style interface.
The signals consist of a multiplexed address
signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional
signal, RP, can be used to reset the memory.
up to t
to abort a Program or Erase operation.
PLRH
7/35
M50LPW012
Table 7. LPC Bus Read Field Definitions
Clock
Cycle
Number Count
Clock
Cycle
LAD0-
LAD3
Memory
I/O
Field
Description
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
1
2
1
1
8
START
0000b
0100b
I
I
I
CYCTY
PE +
DIR
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 0b for read. Bit 0 is ‘0’.
A 32-bit address phase is transferred starting with the most
significant nibble first. See Tables 3, 2 and 6 for the field
description.
3-10
ADDR
XXXX
1111b
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
11
12
1
1
TAR
TAR
I
1111b
(float)
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
O
The LPC Flash Memory drives LAD0-LAD3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not
yet available. Two wait-states are always included.
13-14
15
2
1
WSYNC
RSYNC
0101b
0000b
O
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
Data transfer is two CLK cycles, starting with the least
significant nibble.
16-17
18
2
1
1
DATA
TAR
TAR
XXXX
1111b
O
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
1111b
(float)
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
19
N/A
Figure 4. LPC Bus Read Waveforms
CLK
LFRAME
CYCTYPE
+ DIR
LAD0-LAD3
START
1
ADDR
8
TAR
2
SYNC
3
DATA
2
TAR
2
Number of
clock cycles
1
AI04429
8/35
M50LPW012
Table 8. LPC Bus Write Field Definitions
Clock
Cycle
Number Count
Clock
Cycle
LAD0-
LAD3
Memory
I/O
Field
Description
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
1
2
1
1
8
START
0000b
011Xb
XXXX
I
I
I
CYCTY
PE +
DIR
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 1b for write. Bit 0 is don’t
care (X).
A 32-bit address phase is transferred starting with the most
significant nibble first. See Tables 3, 2 and 6 for the field
description.
3-10
ADDR
Data transfer is two cycles, starting with the least significant
nibble.
11-12
13
2
1
1
1
1
1
DATA
TAR
XXXX
1111b
I
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
1111b
(float)
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
14
TAR
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
15
SYNC
TAR
0000b
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
16
O
1111b
(float)
The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
17
TAR
N/A
Figure 5. LPC Bus Write Waveforms
CLK
LFRAME
CYCTYPE
+ DIR
LAD0-LAD3
START
1
ADDR
8
DATA
2
TAR
2
SYNC
1
TAR
2
Number of
clock cycles
1
AI04430
9/35
M50LPW012
Table 9. A/A Mux Bus Operations
V
Operation
Bus Read
G
W
RP
DQ7-DQ0
Data Output
Data Input
Hi-Z
PP
V
V
IH
V
IH
Don’t Care
IL
IH
IH
V
V
V
V
V
IH
Float or V or V
PPH
Bus Write
Output Disable
Reset
IL
CC
V
IH
Don’t Care
Don’t Care
IH
V
or V
V
IL
or V
V
Hi-Z
IL
IH
IH
IL
Table 10. Manufacturer and Device Codes
Operation
Manufacturer Code
Device Code
G
W
RP
A18-A1
A0
DQ7-DQ0
20h
V
IL
V
IH
V
IH
V
V
V
IL
IL
V
V
IH
V
IH
V
3Bh
IL
IL
IH
COMMAND INTERFACE
All Bus Write operations to the memory are
interpreted by the Command Interface.
command is issued subsequent Bus Read
operations read the Manufacturer Code or the
Device Code until another command is issued.
Commands consist of one or more sequential Bus
Write operations.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the
addresses in Table 11.
After power-up or a Reset operation the memory
enters Read mode.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the address and
data in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the
memory array will not be changed and the Status
Register will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 13.
The commands are summarized in Table 12,
Commands. Refer to Table 12 in conjunction with
the text descriptions below.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. One of the
Erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 13, Program Flowchart and Pseudo
Code, for a suggested flowchart on using the
Program command.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read
Electronic Signature command. Once the
10/35
M50LPW012
Quadruple Byte Program Command. The Qua-
druple Byte Program Command can be only used
in A/A Mux mode to program four adjacent Bytes
in the memory array at a time. The four Bytes must
differ only for the addresses A0 and A1.
Table 11. Read Electronic Signature
Code
Address
00000h
00001h
Data
20h
Manufacturer Code
Device Code
3Bh
Programming should not be attempted when V
PP
Note: For A19:18 values, see Table 2.
is not at V
. The operation can also be executed
PPH
if V is below V
, but result could be uncertain.
PPH
PP
Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third Byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
Byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Read Status register
command and the Program/Erase Suspend com-
mand. All other commands will be ignored. Typical
Quadruple Byte Program times are given in Table
13.
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase
operation will abort, the data in the block will not be
changed and the Status Register will output the
error.
During the Block Erase operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 13.
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and
attempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 14, Quadruple Byte Program Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Quadruple Byte Program command.
See Figure 17, Block Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
Block Erase command.
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the mem-
ory returns to its previous mode, subsequent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
Chip Erase Command. The Chip Erase Com-
mand can be only used in A/A Mux mode to erase
the entire chip at a time. Erasing should not be at-
tempted when V is not at V
. The operation
PP
PPH
can also be executed if V is below V
, but re-
PPH
PP
sult could be uncertain. Two Bus Write operations
are required to issue the command and start the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits. During the Chip Erase operation the
memory will only accept the Read Status Register
command. All other commands will be ignored.
Typical Chip Erase times are given in Table 13.
The Chip Erase command sets all of the bits in the
memory to ‘1’. See Figure 16, Chip Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Chip Erase command.
Program/Erase Suspend Command. The
Pro-
gram/Erase Suspend command can be used to
pause a Program or Block Erase operation. One
Bus Write cycle is required to issue the Program/
Erase Suspend command and pause the Pro-
gram/Erase Controller. Once the command is is-
sued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/
Erase Controller has paused; no other commands
will be accepted until the Program/Erase Control-
ler has paused. After the Program/Erase Control-
ler has paused, the memory will continue to output
the Status Register until another command is is-
sued.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal state machine and starts the Pro-
11/35
M50LPW012
Table 12. Commands
Bus Write Operations
3rd
Command
1st
2nd
4th
5th
Addr Data Addr Data Addr Data Addr Data Addr Data
Read Memory Array
Read Status Register
1
1
1
1
2
2
5
2
2
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FFh
70h
90h
98h
40h
10h
30h
80h
20h
50h
B0h
D0h
00h
01h
60h
2Fh
C0h
Read Electronic Signature
Program
PA
PA
PD
PD
A
1
A
A
A
4
Quadruple Byte Program
Chip Erase
PD
PD
PD
PD
2
3
X
10h
D0h
Block Erase
BA
Clear Status Register
Program/Erase Suspend
Program/Erase Resume
Invalid/Reserved
Note: X Don’t Care, PA Program Address, PD Program Data, A
Consecutive Addresses, BA Any address in the Block.
1,2,3,4
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-
mand is issued.
Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-
sued.
Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A , A , A and A must be consecutive addresses
1
2
3
4
differing only for address bit A0 and A1. After this command read the Status Register until the command completes and another com-
mand is issued.
Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes
and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.
12/35
M50LPW012
Table 13. Program and Erase Times
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
(1)
Parameter
Interface
Test Condition
Min
Max
200
200
Unit
µs
Typ
10
Byte Program
(4)
V
PP
V
PP
V
PP
V
PP
V
PP
V
PP
= 12V ± 5%
= 12V ± 5%
= 12V ± 5%
< 12V – 5%
= 12V ± 5%
< 12V – 5%
Quadruple Byte Program
A/A Mux
A/A Mux
A/A Mux
µs
10
Chip Erase
3
sec
sec
sec
sec
sec
µs
(2)
0.1
5
5
Block Program (64 KBytes)
0.4
0.75
1
8
Block Erase (64 KBytes)
10
5
(3)
Program/Erase Suspend to Program pause
(3)
30
µs
Program/Erase Suspend to Block Erase pause
Note: 1. T = 25°C, V = 3.3V
A
CC
2. This time is obtained executing the Quadruple Byte Program Command.
3. Sampled only, not 100% tested.
4. 10µs to program 4 Bytes.
During the polling period between issuing the
Program/Erase Suspend command and the
Program/Erase Controller pausing it is possible for
the operation to complete. Once Program/Erase
Controller Status bit indicates that the Program/
Erase Controller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to determine if the operation has
completed or is suspended. For timing on the
delay between issuing the Program/Erase
Suspend command and the Program/Erase
Controller pausing see Table 13.
During Program/Erase Suspend the Read
Memory Array, Read Status Register, Read
Electronic Signature and Program/Erase Resume
commands will be accepted by the Command
Interface. Additionally, if the suspended operation
was Block Erase then the Program command will
also be accepted; only the blocks not being erased
may be read or programmed correctly.
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.
To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. The Status Register can be read from
any address.
The Status Register bits are summarized in Table
14, Status Register Bits. Refer to Table 14 in con-
junction with the text descriptions below.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
See Figures 15, Program Suspend & Resume
Flowchart and Pseudo Code, and 18, Erase
Suspend & Resume Flowchart and Pseudo Code,
for suggested flowcharts on using the Program/
Erase Suspend command.
Program/Erase Resume Command. The
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after
Pro-
a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. Once the command is issued
subsequent Bus Read operations read the Status
Register.
13/35
M50LPW012
Table 14. Status Register Bits
Operation
Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1
(1)
Program active
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
X
X
X
X
X
(1)
(1)
(1)
(1)
Program suspended
Program completed successfully
Program failure due to Block Protection (LPC Interface only)
Program failure due to cell failure
Erase active
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
Block Erase suspended
Erase completed successfully
Block Erase failure due to Block Protection (LPC Interface only)
Erase failure due to failed cell(s)
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that a Block Erase oper-
ation has been suspended and is waiting to be
resumed. The Erase Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Pro-
gram/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
Byte and still failed to verify that the Byte has pro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the Byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the Byte and still
failed to verify that the Byte has programmed cor-
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
Reserved (Bit 3). This status bit is reserved for
future use. Its value should be masked out when-
ever the status register is read.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block(s) and still failed to
verify that the block(s) has erased correctly.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
14/35
M50LPW012
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection Status bit is to ‘0’ no Program or Block
Erase operations have been attempted to protect-
ed blocks since the last Clear Status Register
command or hardware reset; when the Block Pro-
tection Status bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
If Top Block Lock, TBL, is Low, V , then the Boot
IL
Block (Block 6) is write protected and cannot be
modified. Similarly, if Write Protect, WP, is Low,
V , then the Main Blocks (Blocks 0 to 5) are write
IL
protected and cannot be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
LOW PIN COUNT (LPC) INTERFACE
CONFIGURATION REGISTERS
When the Low Pin Count Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the Blocks
and read the General Purpose Input pins. See Ta-
ble 15 for an example of the Register Configura-
tion map, valid for the boot memory, that is, ID0-
General Purpose Input Register
The General Purpose Input Register holds the
state of the General Purpose Input pins, GPI0-
GPI4. When this register is read, the state of these
pins is returned. This register is read-only and writ-
ing to it has no effect.
The signals on the General Purpose Input pins
should remain constant throughout the whole Bus
Read cycle in order to guarantee that the correct
data is read.
ID3 can be left floating or driven Low, V .
IL
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bit is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 16 for details on the bit definitions of the
Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
15/35
M50LPW012
(1)
Table 15. Low Pin Count Register Configuration Map
Memory Address
Default
Value
Mnemonic
Register Name
Access
Top
Bottom
T_BLOCK_LK
Top Block Lock Register (Block 6)
FF7FC002h
FF7FA002h
FF7F8002h
FF7F0002h
FF7E0002h
FF7D0002h
FF7C0002h
FF7C0100h
008FC002h
008FA002h
008F8002h
008F0002h
008E0002h
008D0002h
008C0002h
008C0100h
01h
01h
01h
01h
01h
01h
01h
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
T_MINUS01_LK Top Block [-1] Lock Register (Block 5)
T_MINUS02_LK Top Block [-2] Lock Register (Block 4)
T_MINUS03_LK Top Block [-3] Lock Register (Block 3)
T_MINUS04_LK Top Block [-4] Lock Register (Block 2)
T_MINUS05_LK Top Block [-5] Lock Register (Block 1)
T_MINUS06_LK Top Block [-6] Lock Register (Block 0)
GPI_REG
General Purpose Input Register
Note: 1. This map is referred to the boot memory (ID0-ID3 floating or driven, Low).
16/35
M50LPW012
(1)
Table 16. Lock Register Bit Definitions
Bit
Bit Name
Value
Function
7-3
Reserved
Bus Read operations in this Block always return 00h.
‘1’
‘0’
2
Read-Lock
Bus read operations in this Block return the Memory Array contents. (Default
value).
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘1’
1
Lock-Down
Write-Lock
Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
‘0’
‘1’
‘0’
Program and Block Erase operations in this Block will set an error in the Status
Register. The memory contents will not be changed. (Default value).
0
Program and Block Erase operations in this Block are executed and will modify the
Block contents.
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-6] Lock Reg-
ister (T_MINUS06_LK).
(1)
Table 17. General Purpose Input Register Definition
Bit
Bit Name
Value
Function
7-5
Reserved
Input Pin GPI4 is at V
Input Pin GPI4 is at V
Input Pin GPI3 is at V
Input Pin GPI3 is at V
Input Pin GPI2 is at V
Input Pin GPI2 is at V
Input Pin GPI1 is at V
Input Pin GPI1 is at V
Input Pin GPI0 is at V
Input Pin GPI0 is at V
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
4
3
2
1
0
GPI4
GPI3
GPI2
GPI1
GPI0
Note: 1. Applies to the General Purpose Input Register (GPI_REG).
17/35
M50LPW012
Table 18. LPC Interface AC Measurement Conditions
Parameter
Value
3.0 to 3.6
10
Unit
V
V
Supply Voltage
CC
Load Capacitance (C )
pF
ns
V
L
Input Rise and Fall Times
≤ 1.4
0.2 V and 0.6 V
Input Pulse Voltages
CC
CC
0.4 V
Input and Output Timing Ref. Voltages
V
CC
Figure 6. LPC Interface AC Testing Input Output Waveforms
0.6 V
CC
0.4 V
CC
0.2 V
CC
Input and Output AC Testing Waveform
I
< I
I
> I
I
< I
O LO
O
LO
O
LO
Output AC Tri-state Testing Waveform
AI03404
18/35
M50LPW012
Table 19. A/A Mux Interface AC Measurement Conditions
Parameter
Value
3.0 to 3.6
30
Unit
V
V
CC
Supply Voltage
Load Capacitance (C )
pF
ns
V
L
Input Rise and Fall Times
≤ 10
Input Pulse Voltages
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Figure 7. A/A Mux Interface AC Testing Input Output Waveform
3V
0V
1.5V
AI01417
Table 20. Impedance
(T = 25 °C, f = 1 MHz)
A
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
V
V
= 0V
= 0V
Input Capacitance
Clock Capacitance
13
12
pF
C
IN
IN
IN
(1)
CLK
3
pF
nH
C
L
Recommended Pin
Inductance
(2)
20
PIN
Note: 1. Sampled only, not 100% tested.
2. See PCI Specification.
19/35
M50LPW012
Table 21. DC Characteristics
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
Symbol
Parameter
Interface
LPC
Test Condition
Min
Max
Unit
V
0.5 V
V
V
+ 0.5
CC
CC
V
IH
Input High Voltage
Input Low Voltage
0.7 V
+ 0.3
A/A Mux
LPC
V
CC
CC
0.3 V
–0.5
-0.5
1.35
–0.5
V
CC
V
IL
A/A Mux
LPC
0.8
+ 0.5
V
V
IH
(INIT)
V
CC
INIT Input High Voltage
INIT Input Low Voltage
Input Leakage Current
V
V (INIT)
IL
0.2 V
CC
LPC
V
(2)
0V ≤ V ≤ V
±10
µA
µA
I
LI
IN
CC
IC, IDx Input Leakage
Current
I
IC, ID0, ID1, ID2, ID3 = V
CC
200
LI2
IC, IDx Input Pull Low
Resistor
R
20
100
kΩ
IL
0.9 V
LPC
A/A Mux
LPC
I
I
= –500µA
= –100µA
= 1.5mA
= 1.8mA
V
V
CC
OH
V
Output High Voltage
OH
V
CC
– 0.4
OH
I
OL
0.1 V
V
CC
V
Output Low Voltage
OL
I
A/A Mux
0.45
±10
V
OL
I
0V ≤ V
≤ V
OUT CC
Output Leakage Current
µA
LO
V
Voltage (Fast
PP
V
11.4
1.8
12.6
2.3
V
V
PPH
Program/Fast Erase)
(1)
V
CC
Lockout Voltage
V
LKO
LFRAME = 0.9 V
CC
I
All other inputs 0.9 V to 0.1 V
CC
Supply Current (Standby)
Supply Current (Standby)
LPC
LPC
LPC
100
10
µA
mA
mA
CC1
CC
CC
V
CC
= 3.6V, f(CLK) = 33MHz
LFRAME = 0.1 V
CC
I
All other inputs 0.9 V to 0.1 V
CC
CC2
V
CC
= 3.6V, f(CLK) = 33MHz
V
CC
= V max
CC
Supply Current
(Any internal operation
active)
f(CLK) = 33MHz
= 0mA
60
I
I
CC3
I
OUT
G = V , f = 6MHz
Supply Current (Read)
A/A Mux
A/A Mux
20
20
mA
mA
CC4
IH
Supply Current
(Program/Erase)
(1)
Program/Erase Controller Active
I
I
CC5
V
Supply Current
PP
I
V
V
> V
400
µA
PP
PP
CC
(Read/Standby)
= V
5
µA
PP
CC
V
PP
Supply Current
(1)
PP1
(Program/Erase active)
V
= 12V ± 5%
15
mA
PP
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
20/35
M50LPW012
Table 22. LPC Interface Clock Characteristics
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Value
Unit
(1)
t
Min
30
ns
CYC
CLK Cycle Time
CLK High Time
CLK Low Time
t
Min
Min
Min
Max
11
11
1
ns
ns
HIGH
t
LOW
V/ns
V/ns
CLK Slew Rate
peak to peak
4
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.
Figure 8. LPC Interface Clock Waveform
tCYC
tHIGH
tLOW
0.6 V
0.5 V
0.4 V
0.3 V
0.2 V
CC
CC
CC
CC
CC
0.4 V
,
CC p-to-p
(minimum)
AI03403
21/35
M50LPW012
Table 23. LPC Interface AC Signal Timing Characteristics
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
PCI
Symbol
Symbol
Parameter
Test Condition
Value
Unit
Min
2
ns
ns
t
t
val
CLK to Data Out
CHQV
Max
11
CLK to Active
(Float to Active Delay)
(1)
t
Min
Max
Min
2
28
7
ns
ns
ns
t
on
CHQX
CLK to Inactive
(Active to Float Delay)
t
t
off
CHQZ
t
t
AVCH
DVCH
(2)
t
su
Input Set-up Time
t
t
CHAX
CHDX
(2)
t
h
Min
0
ns
Input Hold Time
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-
ification.
2. Applies to all inputs except CLK.
Figure 9. LPC Interface AC Signal Timing Waveforms
CLK
tCHQV
tCHQZ
tCHQX
tDVCH
tCHDX
VALID
LAD0-LAD3
VALID OUTPUT DATA
FLOAT OUTPUT DATA
VALID INPUT DATA
AI04431
22/35
M50LPW012
Table 24. Reset AC Characteristics
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Value
100
100
30
Unit
ns
t
RP or INIT Reset Pulse Width
Min
Max
Max
Min
PLPH
Program/Erase Inactive
Program/Erase Active
Rising edge only
ns
t
RP or INIT Low to Reset
PLRH
µs
(1)
50
mV/ns
RP or INIT Slew Rate
t
RP or INIT High to LFRAME Low
LPC Interface only
Min
Min
30
50
µs
µs
PHFL
t
RP High to Write Enable or Output
Enable Low
PHWL
A/A Mux Interface only
t
PHGL
Note: 1. See Chapter 4 of the PCI Specification.
Figure 10. Reset AC Waveforms
RP, INIT
tPHWL, tPHGL, tPHFL
tPLPH
W, G, LFRAME
RB
tPLRH
AI04432
23/35
M50LPW012
Table 25. A/A Mux Interface Read AC Characteristics
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Value
250
50
Unit
ns
t
Read Cycle Time
Min
Min
Min
Min
Min
AVAV
t
Row Address Valid to RC Low
RC Low to Row Address Transition
Column Address Valid to RC high
RC High to Column Address Transition
ns
AVCL
t
50
ns
CLAX
t
50
ns
AVCH
t
50
ns
CHAX
(1)
RC High to Output Valid
Max
150
ns
ns
t
CHQV
(1)
Output Enable Low to Output Valid
RP High to Row Address Valid
Max
Min
Min
Max
Min
50
1
t
GLQV
t
µs
ns
ns
ns
PHAV
t
t
Output Enable Low to Output Transition
Output Enable High to Output Hi-Z
Output Hold from Output Enable High
0
GLQX
50
0
GHQZ
GHQX
t
Note: 1. G may be delayed up to t
– t
after the rising edge of RC without impact on t
.
CHQV
CHQV
GLQV
Figure 11. A/A Mux Interface Read AC Waveforms
tAVAV
A0-A10
ROW ADDR VALID COLUMN ADDR VALID
NEXT ADDR VALID
tAVCL
tAVCH
tCLAX
tCHAX
RC
G
tCHQV
tGLQV
tGLQX
tGHQZ
tGHQX
VALID
DQ0-DQ7
W
tPHAV
RP
AI03406
24/35
M50LPW012
Table 26. A/A Mux Interface Write AC Characteristics
(T = 0 to 70°C; V = 3.0 to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Value
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Write Enable Low to Write Enable High
Data Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
100
50
5
WLWH
t
DVWH
t
Write Enable High to Data Transition
Row Address Valid to RC Low
WHDX
t
50
50
50
50
100
50
30
0
AVCL
t
RC Low to Row Address Transition
Column Address Valid to RC High
RC High to Column Address Transition
Write Enable High to Write Enable Low
RC High to Write Enable High
CLAX
t
AVCH
t
CHAX
t
WHWL
t
CHWH
t
Write Enable High to Output Enable Low
Write Enable High to RB Low
WHGL
t
WHRL
25/35
M50LPW012
Figure 12. A/A Mux Interface Write AC Waveforms
Write erase or
program setup
Write erase confirm or Automated erase
valid address and data or program delay
Read Status
Register Data
Ready to write
another command
A0-A10
RC
R1
C1
R2
C2
tCLAX
tAVCH
tAVCL
tCHAX
tWHWL
tWLWH
tCHWH
W
G
tWHGL
tWHRL
RB
tDVWH
tWHDX
DQ0-DQ7
D
D
VALID SRD
IN1
IN2
AI06817
26/35
M50LPW012
Figure 13. Program Flowchart and Pseudo Code
Start
Program command:
– write 40h or 10h
Write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)
Write Address
& Data
do:
NO
Read Status
–read Status Register if Program/Erase
Suspend command given execute
suspend program loop
Register
Suspend
YES
NO
Suspend
Loop
b7 = 1
YES
while b7 = 1
NO
NO
Program
Error (1, 2)
If b4 = 1, Program error:
– error handler
b4 = 0
YES
LPC
Interface
Only
Program to Protected
Block Error (1, 2)
If b1 = 1, Program to protected block error:
– error handler
b1 = 0
YES
End
AI06818
Note: 1. A Status check of b1 (Protected Block) and b4 (Program Error) can be made after each Program operation by following the correct
command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
27/35
M50LPW012
Figure 14. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 30h
Write Address 1
& Data 1 (3)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1 (3)
– write Address 2 & Data 2 (3)
– write Address 3 & Data 3 (3)
Write Address 2
& Data 2 (3)
– write Address 4 & Data 4 (3)
(memory enters read status state after
the Quadruple Byte Program command)
Write Address 3
& Data 3 (3)
Write Address 4
& Data 4 (3)
do:
NO
– read Status Register if Program/Erase
Suspend command given execute
suspend program loop
Read Status
Register
Suspend
YES
NO
NO
Suspend
Loop
b7 = 1
YES
while b7 = 1
Program
Error (1, 2)
If b4 = 1, Program error:
– error handler
b4 = 0
YES
End
AI06819
Note: 1. A Status check of b4 (Program Error) can be made after each Program operation by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.
28/35
M50LPW012
Figure 15. Program Suspend and Resume Flowchart, and Pseudo Code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
– write 70h
Write 70h
do:
– read Status Register
Read Status
Register
NO
NO
b7 = 1
YES
while b7 = 1
b2 = 1
YES
Program Complete
If b2 = 0 Program completed
Write a read
Command
Read data from
another address
Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Write D0h
Write FFh
Read Data
Program Continues
AI03408
29/35
M50LPW012
Figure 16. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Chip Erase command:
Write 80h
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
Write 10h
do:
– read Status Register
Read Status
Register
NO
b7 = 1
YES
while b7 = 1
NO
NO
Command
Sequence Error (1)
If b4, b5 = 1, Command sequence error:
– error handler
b4, b5 = 0
YES
If b5 = 1, Erase error:
– error handler
b5 = 0
Erase Error (1)
YES
End
AI06820
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
30/35
M50LPW012
Figure 17. Block Erase Flowchart and Pseudo Code
Start
Block Erase command:
– write 20h
Write 20h
– write Block Address & D0h
(memory enters read Status Register after
the Block Erase command)
Write Block Address
& D0h
do:
– read Status Register
– if Program/Erase Suspend command
given execute suspend erase loop
NO
Read Status
Register
Suspend
YES
NO
Suspend
Loop
b7 = 1
while b7 = 1
YES
NO
NO
NO
Command
Sequence Error (1)
If b4, b5 = 1, Command sequence error:
– error handler
b4, b5 = 0
YES
If b5 = 1, Erase error:
– error handler
b5 = 0
YES
Erase Error (1)
LPC
Interface
Only
Erase to Protected
Block Error (1)
If b1 = 1, Erase to protected block error:
– error handler
b1 = 0
YES
End
AI04434
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
31/35
M50LPW012
Figure 18. Erase Suspend and Resume Flowchart, and Pseudo Code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read Status Register
NO
NO
b7 = 1
YES
while b7 = 1
b6 = 1
YES
Erase Complete
If b6 = 0, Erase completed
Read data from
another block
or
Program
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
Write D0h
Write FFh
Read Data
Erase Continues
AI03410
32/35
M50LPW012
Table 27. Ordering Information Scheme
Example:
M50LPW012
K
1
T
Device Type
M50
Architecture
LP = Low Pin Count Interface
Operating Voltage
W = 3.0 to 3.6V
Device Function
012 = 2 Mbit (256Kb x8), Boot Block
Package
K = PLCC32
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
For a list of available options or for further information on any aspect of this device, please contact the ST
Sales Office nearest to you.
Table 28. Revision History
Date
Version
-01
Revision Details
17-Jun-2002
29-Aug-2002
First Issue
1.1
PC Chipsets without automapping memory features mentioned on page 1
Value of A inverted for Memory Identification Input Configuration (and
Register Configuration Map) for Bottom Boot Block devices
19
16-Sep-2002
1.2
33/35
M50LPW012
PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
A2
D1
1
N
B1
e
E2
E2
E3
E1 E
F
B
0.51 (.020)
1.14 (.045)
D3
A
R
CP
D2
D2
PLCC-A
Note: Drawing is not to scale.
PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
Symbol
inches
Min
Typ
Min
3.18
1.53
0.38
0.33
0.66
Max
3.56
2.41
–
Typ
Max
0.140
0.095
–
A
A1
A2
B
0.125
0.060
0.015
0.013
0.026
0.53
0.81
0.10
12.57
11.51
5.66
–
0.021
0.032
0.004
0.495
0.453
0.223
–
B1
CP
D
12.32
11.35
4.78
–
0.485
0.447
0.188
–
D1
D2
D3
E
7.62
0.300
14.86
13.89
6.05
–
15.11
14.05
6.93
–
0.585
0.547
0.238
–
0.595
0.553
0.273
–
E1
E2
E3
e
10.16
1.27
0.400
0.050
–
–
–
–
F
0.00
32
0.13
0.000
32
0.005
N
R
0.89
–
–
0.035
–
–
34/35
M50LPW012
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2002 STMicroelectronics - All Rights Reserved
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