M54HC112D [STMICROELECTRONICS]
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR; 带预置和清除RAD- HARD双J-K·触发器
| 型号： | M54HC112D |
| 厂家： | 
ST |
| 描述： | RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR |
| 文件： | 总11页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M54HC112
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
■
■
■
■
■
■
■
HIGH SPEED:
= 79MHz (TYP.) at V = 6V
f
MAX
CC
LOW POWER DISSIPATION:
=2µA(MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28% V (MIN.)
V
NIH
NIL
CC
DILC-16
FPC-16
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 4mA (MIN)
OH
OL
BALANCED PROPAGATION DELAYS:
t
t
ORDER CODES
PACKAGE
PLH
PHL
WIDE OPERATING VOLTAGE RANGE:
(OPR) = 2V to 6V
FM
EM
V
CC
DILC
FPC
M54HC112D
M54HC112K
M54HC112D1
M54HC112K1
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 112
■
■
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
individual J, K, clock, and asynchronous set and
clear inputs for each flip-flop. When the clock goes
high, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs
may be allowed to change when the clock pulse is
high and the bistable will function as shown in the
truth table. Input data is transferred to the input on
the negative going edge of the clock pulse.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
■
■
DEVICE FULLY COMPLIANT WITH
SCC-9203-051
DESCRIPTION
The M54HC112 is an high speed CMOS DUAL
J-K FLIP-FLOP WITH PRESET AND CLEAR
2
fabricated with silicon gate C MOS technology.
The M54HC112 dual JK flip-flop features
PIN CONNECTION
March 2004
1/11
M54HC112
IEC LOGIC SYMBOLS
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN N°
SYMBOL
NAME AND FUNCTION
Clock Input (HIGH to
LOW edge triggered)
1, 13
1CK, 2CK
1K, 2K
Data Inputs: Flip-Flop 1
and 2
2, 12
3, 11
Data Inputs: Flip-Flop 1
and 2
1J, 2J
4, 10
5, 9
1PR, 2PR Set Inputs
1Q, 2Q
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
6, 7
1Q, 2Q
15, 14
8
1CLR, 2CLR Reset Inputs
GND
Ground (0V)
V
16
Positive Supply Voltage
CC
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
PR
J
K
CK
Q
Q
L
H
L
H
L
L
X
X
X
X
X
X
X
X
X
L
H
H
H
L
CLEAR
PRESET
----
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
Qn
H
Qn
L
NO CHANGE
----
H
H
X
L
H
----
H
X
Qn
Qn
Qn
Qn
TOGGLE
NO CHANGE
H
X : Don’t Care
2/11
M54HC112
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
CC
V
DC Input Voltage
-0.5 to V + 0.5
I
CC
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
± 20
± 20
mA
mA
mA
mA
mW
°C
IK
I
OK
I
± 25
O
I
or I
DC V
or Ground Current
CC
± 50
CC
GND
P
Power Dissipation
300
D
T
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
265
stg
T
°C
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
2 to 6
0 to V
V
V
CC
V
Input Voltage
I
CC
V
Output Voltage
0 to V
CC
V
O
T
Operating Temperature
Input Rise and Fall Time
-55 to 125
0 to 1000
0 to 500
0 to 400
°C
ns
ns
ns
op
V
V
V
= 2.0V
= 4.5V
= 6.0V
CC
CC
CC
t , t
r
f
3/11
M54HC112
DC SPECIFICATIONS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
IH
V
V
V
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
IL
V
High Level Output
Voltage
I =-20 µA
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
1.9
4.4
OH
O
I =-20 µA
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
O
I =-20 µA
5.9
5.9
V
V
O
I =-4.0 mA
4.18 4.31
4.13
5.63
4.10
5.60
O
I =-5.2 mA
5.68
5.8
0.0
0.0
0.0
O
V
Low Level Output
Voltage
I =20 µA
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =20 µA
O
I =20 µA
0.1
0.1
O
I =4.0 mA
0.17 0.26
0.18 0.26
0.33
0.33
0.40
0.40
O
I =5.2 mA
O
I
Input Leakage
Current
I
V = V or GND
6.0
6.0
± 0.1
± 1
± 1
µA
µA
I
CC
I
Quiescent Supply
Current
CC
V = V or GND
2
20
40
I
CC
4/11
M54HC112
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6ns)
L
r
f
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T
= 25°C
Symbol
Parameter
A
V
CC
(V)
t
t
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
8
75
15
95
19
110
22
TLH THL
ns
ns
7
13
16
19
t
t
t
Propagation Delay
Time (CK - Q, Q)
52
16
14
68
17
14
16
68
79
20
5
125
25
155
31
190
38
PLH PHL
21
26
32
t
Propagation Delay
Time (CLR, PR - Q,
Q)
135
27
170
34
205
41
PLH PHL
ns
23
29
35
f
Maximum Clock
Frequency
8
6.4
32
38
5.4
27
32
MAX
40
47
MHz
ns
t
t
Minimum Pulse
Width (CLOCK)
75
15
13
75
15
13
75
15
13
0
95
19
16
95
19
16
95
19
16
0
110
22
19
110
22
19
110
22
19
0
W(H)
W(L)
4
t
Minimum Pulse
Width (CLR, PR)
20
5
W(L)
ns
4
t
Minimum Set-up
Time
28
7
s
ns
6
t
Minimum Hold
Time
h
0
0
0
ns
0
0
0
t
Minimum Removal
Time (CLR, PR)
24
4
50
10
9
60
12
10
70
14
12
REM
ns
3
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
5.0
5
10
10
10
pF
pF
IN
C
Power Dissipation
Capacitance (note
1)
PD
5.0
33
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP)
= C x V x f + I /2 (per FLIP/
CC(opr)
PD CC IN CC
5/11
M54HC112
TEST CIRCUIT
C
R
= 50pF or equivalent (includes jig and probe capacitance)
L
T
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD
TIME (J to CK) (f=1MHz; 50% duty cycle)
6/11
M54HC112
WAVEFORM 2: PROPAGATIONS DELAY TIME, MINIMUM PULSE WIDTH (CLR, PR)
(f=1MHz; 50% duty cycle)
WAVEFORM 3: MINIMUM REMOVAL TIME (CLR to CK) (f=1MHz; 50% duty cycle)
7/11
M54HC112
WAVEFORM 4: MINIMUM REMOVAL TIME (PR to CK) (f=1MHz; 50% duty cycle)
8/11
M54HC112
DILC-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
MIN.
MAX.
A
a1
a2
B
2.1
3.00
0.63
1.82
0.40
0.20
20.06
7.36
2.71
3.70
1.14
2.39
0.50
0.30
20.58
7.87
0.083
0.118
0.025
0.072
0.016
0.008
0.790
0.290
0.107
0.146
0.045
0.094
0.020
0.012
0.810
0.310
0.88
0.035
b
0.45
0.254
20.32
7.62
0.018
0.010
0.800
0.300
0.100
0.700
0.310
0.295
b1
D
e
e1
e2
e3
F
2.54
17.65
7.62
7.29
17.78
7.87
17.90
8.12
7.70
3.83
12.1
1.5
0.695
0.300
0.287
0.705
0.320
0.303
0.151
0.476
0.059
7.49
I
K
10.90
1.14
0.429
0.045
L
0056437F
9/11
M54HC112
FPC-16 MECHANICAL DATA
mm.
inch
TYP.
0.272
DIM.
MIN.
6.75
9.76
1.49
0.102
8.76
TYP
6.91
9.94
MAX.
7.06
MIN.
0.266
0.384
0.059
0.004
0.345
MAX.
0.278
0.399
0.077
0.006
0.355
A
B
C
D
E
F
10.14
1.95
0.392
0.127
8.89
1.27
0.43
0.152
9.01
0.005
0.350
0.050
0.017
G
H
L
0.38
6.0
0.48
0.015
0.237
0.738
0.013
0.019
18.75
0.33
22.0
0.43
0.867
0.017
M
N
0.38
4.31
0.015
0.170
G
D
F
H
16
9
A
N
L
1
8
H
M
E
B
C
0016030E
10/11
M54HC112
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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11/11
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