M54HCT564F1R [STMICROELECTRONICS]
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 INVERTING - HCT574 NON INVERTING; 八路D型触发器具有三态输出HCT564反相FLOP - HCT574非反相
| 型号： | M54HCT564F1R |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT564 INVERTING - HCT574 NON INVERTING |
| 文件： | 总13页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M54/74HCT564
M54/74HCT574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
HCT564 INVERTING - HCT574 NON INVERTING
.
.
.
.
.
.
.
HIGH SPEED
MAX = 62 MHz (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
COMPATIBLE WITH TTL OUTPUTS
f
V
IH = 2V (MIN.) VIL = 0.8V (MAX)
B1R
(Plastic Package)
F1R
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH = 6 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS564/574
ORDER CODES :
M54HCTXXXF1R
M74HCTXXXB1R
M74HCTXXXM1R
M74HCTXXXC1R
DESCRIPTION
The M54/74HCT564 and M54HCT574 are high
speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-
STATE OUTPUTS fabricated in silicon gate C2MOS
technology. They have the same high speed per-
formance of LSTTL combined with true CMOS low
power comsuption. These 8-bit D-type flip-flops are
controlled by a clockinput(CK) and anouputenable
input (OE). On thepositive transition of theclock, the
Q outputs willbesetto thelogic statethatweresetup
at the D inputs (HCT574) or their complements
(HCT564).
ternal operation of flip-flops. That is, theold data can
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting and non-in-
verting outputs. The 3-state output configuration
and the wide choice of outline make bus-organized
systemssimple. Allinputs are equipped withprotec-
tion circuits against static discharge and transient
excess voltage. This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC2MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption.
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
while high level, the outputs will be in a high imped-
ance state. The output control does not affect the in-
PIN CONNECTION (top view)
HCT564
HCT574
HCT564
HCT574
September 1993
1/13
M54/M74HCT564/574
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION (HCT564)
PIN DESCRIPTION (HCT574)
PIN No
SYMBOL
NAME AND FUNCTION
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3 State output Enable
Input (Active LOW)
1
OE
3 State output Enable
Input (Active LOW)
2, 3, 4, 5,
6, 7, 8, 9
D0 to D7
Q0 to Q7
Data Inputs
2, 3, 4, 5,
6, 7, 8, 9
D0 to D7
Q0 to Q7
Data Inputs
12, 13, 14,
15, 16, 17,
18, 19
3 State outputs
12, 13, 14,
15, 16, 17,
18, 19
3 State outputs
11
CLOCK
Clock Input (LOW to
HIGH, edge triggered)
11
CLOCK
Clock Input (LOW to
HIGH, edge triggered)
10
20
GND
VCC
Ground (0V)
10
20
GND
VCC
Ground (0V)
Positive Supply Voltage
Positive Supply Voltage
IEC LOGIC SYMBOLS
HCT564
HCT574
2/13
M54/M74HCT564/574
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
L
CK
D
X
X
L
Q (HCT574)
Q (HCT564)
X
Z
Z
NO CHANGE
NO CHANGE
L
L
H
L
L
H
H
LOGIC DIAGRAMS
HCT574
HCT564
3/13
M54/M74HCT564/574
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
V
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
mA
mA
mA
mA
mW
oC
IOK
± 20
IO
± 35
ICC or IGND DC VCC or Ground Current
± 70
PD
Tstg
TL
Power Dissipation
500 (*)
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
oC
Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to VCC
0 to VCC
Unit
V
Supply Voltage
Input Voltage
Output Voltage
V
VO
V
Top
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
oC
oC
tr, tf
Input Rise and Fall Time (VCC = 4.5 to 5.5V)
0 to 500
ns
4/13
M54/M74HCT564/574
DC SPECIFICATIONS
Test Conditions
VCC
Value
-40 to 85 oC -55 to 125 oC
74HC 54HC
TA = 25 oC
54HC and 74HC
Symbol
VIH
Parameter
Unit
V
(V)
Min. Typ. Max. Min. Max. Min. Max.
High Level Input
Voltage
4.5
to
2.0
2.0
2.0
5.5
VIL
Low Level Input
Voltage
4.5
to
0.8
0.8
0.8
V
5.5
VOH
High Level
VI = IO=-20 µA
4.4
4.5
4.4
4.4
Output Voltage
VIH
or
VIL
4.5
V
V
IO=-6.0 mA 4.18 4.31
4.13
4.10
VOL
Low Level Output
Voltage
VI = IO= 20 µA
VIH
or
VIL
0.0
0.1
0.1
0.33
±1
0.1
0.4
±1
4.5
5.5
IO= 6.0 mA
0.17 0.26
II
Input Leakage
Current
VI = VCC or GND
±0.1
4
µA
µA
ICC
Quiescent Supply 5.5 VI = VCC or GND
Current
40
80
∆ICC
Additional worst
case supply
current
5.5
Per Input pin
VI = 0.5V or
VI = 2.4V
2.0
2.9
3.0
mA
Other Inputs at
VCC or GND
IO= 0
5/13
M54/M74HCT564/574
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Test Conditions
Value
TA = 25 oC
54HC and 74HC
-40 to 85 oC -55 to 125 oC
Symbol
Parameter
Unit
VCC CL
(V) (pF)
74HC
54HC
Min. Typ. Max. Min. Max. Min. Max.
tTLH
tTHL
tPLH
tPHL
Output Transition
Time
4.5
50
7
12
15
18
ns
ns
Propagation
Delay Time
4.5
50
20
24
19
23
19
30
36
30
36
30
38
45
38
45
38
45
54
45
54
45
4.5 150
tPZL
tPZH
3 State Output
Enable Time
4.5
50 RL = 1 KΩ
ns
4.5 150 RL = 1 KΩ
tPLZ
tPHZ
3 State Output
Disable Time
4.5
4.5
4.5
4.5
4.5
50 RL = 1 KΩ
ns
ns
ns
ns
fMAX
Maximum CLock
Frequency
50
50
50
50
31
50
8
25
21
tW(L)
tW(H)
Minimum Pulse
Width (CLOCK)
15
15
0
19
19
0
22
22
0
ts
Minimum Set-up
Time
7
th
Minimum Hold
Time
ns
pF
pF
CIN
Input Capacitance
5
10
10
10
COUT
Out put
Capacitance
10
CPD (*) Power Dissipation
Capacitance
HCT564
HCT574
67
63
pF
(*) CPD is defined as the value of the IC’sinternal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by thefollowing equation. ICC(opr) = CPD •VCC •fIN + ICC (per Flip-Flop)
6/13
M54/M74HCT564/574
SWITCHING CHARACTERISTICS TEST WAVEFORM
CLOCK DUTY : 50%
1
fMAX
=
TCK
EACH FLIP-FLOP SHALL BE SET HIGH WHEN SWITCH IS CONNECTED TO GND LINE AND IT SHALL BE SET LOW WHEN
SWITCHIS CONNECTED TO VCC LINE.
7/13
M54/M74HCT564/574
TEST CIRCUIT ICC (Opr.)
INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHINGCHARACTERISTICSTEST.
8/13
M54/M74HCT564/574
Plastic DIP20 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.254
1.39
TYP.
MAX.
MIN.
0.010
0.055
MAX.
a1
B
b
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
2.54
22.86
0.335
0.100
0.900
e3
F
7.1
0.280
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
P001J
9/13
M54/M74HCT564/574
Ceramic DIP20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
25
MIN.
MAX.
0.984
0.307
A
B
D
7.8
3.3
0.130
0.900
E
e3
F
0.5
1.78
0.020
0.070
22.86
2.29
0.4
2.79
0.55
1.52
0.31
1.27
0.090
0.016
0.050
0.009
0.020
0.110
0.022
0.060
0.012
0.050
G
I
1.27
0.22
0.51
L
M
N1
P
4° (min.), 15° (max.)
7.9
8.13
5.71
0.311
0.320
0.225
Q
P057H
10/13
M54/M74HCT564/574
SO20 MECHANICAL DATA
mm
inch
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
TYP.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45° (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8° (max.)
P013L
11/13
M54/M74HCT564/574
PLCC20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
10.03
9.04
MIN.
0.385
0.350
0.165
MAX.
0.395
0.356
0.180
A
B
9.78
8.89
4.2
D
4.57
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38
0.290
0.330
0.004
e
1.27
5.08
0.38
0.050
0.200
0.015
e3
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
P027A
12/13
M54/M74HCT564/574
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
13/13
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