M58CR064D120ZB6_技术文档

M58CR064C, M58CR064D

M58CR064P, M58CR064Q

64 Mbit (4Mb x 16, Dual Bank, Burst )

1.8V Supply Flash Memory

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V = 1.65V to 2V for Program, Erase and

DD

Read

– V

= 1.65V to 3.3V for I/O Buffers

DDQ

– V = 12V for fast Program (optional)

PP

■ SYNCHRONOUS / ASYNCHRONOUS READ

– Synchronous Burst Read mode : 54MHz

FBGA

– Asynchronous/ Synchronous Page Read

mode

– Random Access: 85, 100, 120ns

■ PROGRAMMING TIME

– 10µs by Word typical

TFBGA56 (ZB)

6.5 x 10mm

– Double/Quadruple Word Program option

■ MEMORY BLOCKS

– Dual Bank Memory Array: 16/48 Mbit

– Parameter Blocks (Top or Bottom location)

■ DUAL OPERATIONS

■ ELECTRONIC SIGNATURE

– Program Erase in one Bank while Read in

other

– Manufacturer Code: 20h

– Top Device Code, M58CR064C: 88CAh

– Bottom Device Code, M58CR064D: 88CBh

– Top Device Code, M58CR064P: 8801h

– Bottom Device Code, M58CR064Q: 8802h

– No delay between Read and Write operations

■ BLOCK LOCKING

– All blocks locked at Power up

– Any combination of blocks can be locked

– WP for Block Lock-Down

■ SECURITY

– 128 bit user programmable OTP cells

– 64 bit unique device number

– One parameter block permanently lockable

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

August 2002

1/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DD

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDQ

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PP

SS

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SSQ

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS. . . . . . . . . . . . . . . . . . . . . . . . . 19

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Factory Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

V

Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PP

Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reserved Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-Down Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. Wait Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Single Synchronous Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 11. Dual Operations Allowed In Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 29

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 31

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. Asynchronous Random Access Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 12. Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 13. Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 23. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 16. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline. . 47

Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . 47

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 49

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 28. Top Boot Block Addresses, M58CR064C, M58CR064P. . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 29. Bottom Boot Block Addresses, M58CR064D, M58CR064Q . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 33. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 35. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 18. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 19. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 20. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 21. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 61

Figure 22. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 24. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 25. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 65

APPENDIX D. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

SUMMARY DESCRIPTION

The M58CR064 is a 64 Mbit (4Mbit x16) non-vola-

tile Flash memory that may be erased electrically

at block level and programmed in-system on a

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

Word-by-Word basis using a 1.65V to 2V V sup-

DD

ply for the circuitry and a 1.65V to 3.3V V

sup-

DDQ

ply for the Input/Output pins. An optional 12V V

power supply is provided to speed up customer

programming. In M58CR064C and M58CR064D

PP

The device supports synchronous burst read and

asynchronous read from all blocks of the memory

array; at power-up the device is configured for

asynchronous read. In synchronous burst mode,

data is output on each clock cycle at frequencies

of up to 54MHz.

The M58CR064 features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. In M58CR064C and

M58CR064D there is an additional hardware pro-

the V pin can also be used as a control pin to

PP

provide absolute protection against program or

erase. In M58CR064P and M58CR064Q this fea-

ture is disabled.

The device features an asymmetrical block archi-

tecture. M58CR064 has an array of 135 blocks,

and is divided into two banks, Banks A and B. The

Dual Bank Architecture allows Dual Operations,

while programming or erasing in one bank, Read

operations are possible in the other bank. Only

one bank at a time is allowed to be in Program or

Erase mode. It is possible to perform burst reads

that cross bank boundaries. The bank architecture

is summarized in Table 2, and the memory maps

are shown in Figure 4. The Parameter Blocks are

located at the top of the memory address space for

the M58CR064C and M58CR064P, and at the bot-

tom for the M58CR064D and M58CR064Q.

tection against program and erase. When V

≤

PP

V

all blocks are protected against program or

PPLK

erase. All blocks are locked at Power- Up.

The device includes a Protection Register and a

Security Block to increase the protection of a sys-

tem’s design. The Protection Register is divided

into two segments: a 64 bit segment containing a

unique device number written by ST, and a 128 bit

segment One-Time-Programmable (OTP) by the

user. The user programmable segment can be

permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 5, shows the Security Block and

Protection Register Memory Map.

Each block can be erased separately. Erase can

be suspended, in order to perform program in any

other block, and then resumed. Program can be

suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles using the supply

voltage V

.

DD

Program and Erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The memory is offered in a TFBGA56, 6.5 x

10mm, 0.75 mm ball pitch package and is supplied

with all the bits erased (set to ’1’).

6/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 1. Signal Names

Figure 2. Logic Diagram

A0-A21

Address Inputs

Data Input/Outputs, Command

Inputs

DQ0-DQ15

V

DD DDQ PP

E

Chip Enable

Output Enable

Write Enable

Reset/Power-Down

Write Protect

Clock

G

22

16

W

A0-A21

DQ0-DQ15

WAIT

RP

WP

K

W

E

M58CR064C

M58CR064D

M58CR064P

M58CR064Q

G

L

Latch Enable

Wait

RP

WP

L

WAIT

V

DD

Supply Voltage

Supply Voltage for Input/Output

Buffers

V

K

DDQ

Optional Supply Voltage for

Fast Program & Erase

PP

V

SSQ

SS

V

Ground

SS

AI90000

Ground Input/Output Supply

Not Connected Internally

SSQ

NC

7/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 3. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A11

A12

A13

A15

A8

A9

V

A18

A17

A19

WP

A6

A5

A4

A3

A2

A1

A0

G

SS

DD

K

PP

A20

A21

RP

W

A10

L

A7

A14

WAIT

DQ6

DQ13

DQ5

A16

DQ4

DQ12

DQ2

DQ10

DQ3

NC

E

V

DQ15

DQ14

DQ1

DQ9

DDQ

V

DQ11

DQ0

DQ8

SS

G

DQ7

V

SSQ

DD

DDQ

AI90001

Table 2. Bank Architecture

Bank Size

16 Mbit

Parameter Blocks

Main Blocks

Bank A

Bank B

8 blocks of 4 KWord

-

31 blocks of 32 KWord

96 blocks of 32 KWord

48 Mbit

8/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 4. Memory Map

Top Boot Block

Bottom Boot Block

Address lines A21-A0

000000h

007FFFh

000000h

64 Kbit or

512 Kbit or

32 KWord

4 KWord

000FFFh

Total of 8

Parameter

Blocks

(bottom bank)

Total of 96

Main Blocks

(bottom bank)

Bank B

2F8000h

007000h

64 Kbit or

512 Kbit or

32 KWord

4 KWord

2FFFFFh

300000h

007FFFh

Bank A

008000h

512 Kbit or

32 KWord

512 Kbit or

32 KWord

307FFFh

3F0000h

00FFFFh

Total of 31

Main Blocks

(bottom bank)

Total of 31

Main Blocks

(top bank)

0F8000h

512 Kbit or

32 KWord

512 Kbit or

32 KWord

3F7FFFh

3F8000h

0FFFFFh

100000h

Bank A

64 Kbit or

4 KWord

512 Kbit or

32 KWord

3F8FFFh

107FFFh

Total of 8

Parameter

Blocks

Total of 96

Main Blocks

(top bank)

Bank B

(top bank)

3FF000h

3FFFFFh

3F8000h

3FFFFFh

64 Kbit or

4 KWord

512 Kbit or

32 KWord

AI90002

9/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

tied to V

tics).

(refer to Table 19, DC Characteris-

RPH

Latch Enable (L). Latch Enable latches the ad-

Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

dress bits on its rising edge. The address latch is

transparent when Latch Enable is at V and it is in-

IL

hibited when Latch Enable is at V . Latch Enable

IH

can be kept Low (also at board level) when the

Latch Enable function is not required or supported.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Bus Write

operation.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

Clock (K). The clock input synchronizes the

memory to the microcontroller during synchronous

read operations; the address is latched on a Clock

edge (rising or falling, according to the configura-

tion settings) when Latch Enable is at V . Clock is

IL

don't care during asynchronous read and in write

operations.

Wait (WAIT). Wait is an output signal used during

synchronous read to indicate whether the data on

the output bus are valid. This output is high imped-

ance when Chip Enable or Output Enable are at

at V and Reset/Power-Down is at V the device

IL

IH

is in active mode. When Chip Enable is at V the

IH

memory is deselected, the outputs are high imped-

ance and the power consumption is reduced to the

stand-by level.

Output Enable (G). The Output Enable controls

the outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable or Write Enable

whichever occurs first.

V

or Reset/Power-Down is at V . It can be con-

IH

IL

figured to be active during the wait cycle or one

clock cycle in advance.

V

Supply Voltage. V

provides the power

DD

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

V

Supply Voltage. V

provides the power

DDQ

supply to the I/O pins and enables all Outputs to

be powered independently from V . V can be

DD DDQ

tied to V or can use a separate supply.

DD

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

V

Program Supply Voltage. V

is both a

PP

each block. When Write Protect is at V , the Lock-

control input and a power supply pin. In

M58CR064C/D the two functions are selected by

the voltage range applied to the pin. In the

M58CR064P/Q the control feature is disabled.

IL

Down is enabled and the protection status of the

Locked-Down blocks cannot be changed. When

Write Protect is at V , the Lock-Down is disabled

IH

and the Locked-Down blocks can be locked or un-

locked. (refer to Table 13, Lock Status).

In M58CR064C/D if V is kept in a low voltage

PP

range (0V to V

) V is seen as a control input.

DDQ

PP

Reset/Power-Down (RP). The

Reset/Power-

In this case a voltage lower than V

gives an

PPLK

Down input provides a hardware reset of the mem-

ory, and/or Power-Down functions, depending on

the Configuration Register status. When Reset/

absolute protection against program or erase,

while V > V enables these functions (see Ta-

PP

PP1

bles 18 and 19, DC Characteristics for the relevant

Power-Down is at V , the memory is in reset

values). V is only sampled at the beginning of a

IL

PP

mode: the outputs are high impedance and if the

Power-Down function is enabled the current con-

sumption is reduced to the Reset Supply Current

program or erase; a change in its value after the

operation has started does not have any effect and

program or erase operations continue.

I

. Refer to Table 2, DC Characteristics - Cur-

DD2

If V

is in the range of V

it acts as a power

PPH

PP

rents for the value of I

are in the Locked state and the Configuration Reg-

ister is reset. When Reset/Power-Down is at V ,

the device is in normal operation. Exiting reset

mode the device enters asynchronous read mode,

but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset/Power-Down pin can be interfaced with

3V logic without any additional circuitry. It can be

After Reset all blocks

DD2.

supply pin. In this condition V must be stable un-

til the Program/Erase algorithm is completed.

IH

V

Ground. V ground is the reference for the

SS

core supply. It must be connected to the system

ground.

V

Ground. V

ground is the reference for

SSQ

the input/output circuitry driven by V

must be connected to V

. V

DDQ

SSQ

SS

10/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Note: Each device in a system should have

, V and V decoupled with a 0.1µF ce-

ramic capacitor close to the pin (high frequen-

cy, inherently low inductance capacitors

should be as close as possible to the pack-

age). See Figure 9, AC Measurement Load Cir-

cuit. The PCB trace widths should be sufficient

V

DD DDQ

PP

to carry the required V

currents.

program and erase

PP

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Ad-

dress Latch, Output Disable, Standby and Reset.

See Table 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect Bus Write operations.

the Latch Enable should be tied to V during the

bus write operation.

IH

See Figures 14 and 15, Write AC Waveforms, and

Tables 22 and 23, Write AC Characteristics, for

details of the timing requirements.

Address Latch. Address latch operations input

valid addresses. Both Chip enable and Latch En-

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature, the Status Register and the

Common Flash Interface. Both Chip Enable and

able must be at V during address latch opera-

tions. The addresses are latched on the rising

edge of Latch Enable.

IL

Output Disable. The outputs are high imped-

Output Enable must be at V in order to perform a

IL

ance when the Output Enable is at V .

IH

read operation. The Chip Enable input should be

used to enable the device. Output Enable should

be used to gate data onto the output. The data

read depends on the previous command written to

the memory (see Command Interface section).

Refer to the Read AC Waveform figures and Char-

acteristics tables in the DC and AC Parameters

section for details of when the output becomes val-

id.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable and Reset/Power-Down are at

V . The power consumption is reduced to the

IH

stand-by level and the outputs are set to high im-

pedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

V

during a program or erase operation, the de-

IH

Bus Write. Bus Write operations write Com-

mands to the memory or latch Input Data to be

programmed. A bus write operation is initiated

vice enters Standby mode when finished.

Reset. During Reset mode the memory is dese-

lected and the outputs are high impedance. The

memory is in Reset mode when Reset/Power-

when Chip Enable and Write Enable are at V with

IL

Output Enable at V . Commands, Input Data and

IH

Down is at V . The power consumption is reduced

IL

Addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The

addresses can also be latched prior to the write

operation by toggling Latch Enable. In this case

to the Standby level, independently from the Chip

Enable, Output Enable or Write Enable inputs. If

Reset is pulled to V during a Program or Erase,

SS

this operation is aborted and the memory content

is no longer valid.

Table 3. Bus Operations

Operation

E

G

W

L

RP

WAIT

DQ15-DQ0

(2)

V

Bus Read

Data Output

V

IL

IH

IL

(2)

IL

V

IL

V

IH

V

IH

Bus Write

Hi-Z

Data Input

IL

(3)

V

IH

Address Latch

Output Disable

Standby

X

IL

IH

Data Output or Hi-Z

V

IH

V

IH

X

Hi-Z

V

IH

X

IH

V

Reset

X

IL

Note: 1. X = Don’t care.

2. L can be tied to V if the valid address has been previously latched.

IH

3. Depends on G.

11/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time to monitor

the progress or the result of the operation.

Table 4. Command Codes

Hex Code

01h

Command

Block Lock Confirm

03h

Set Configuration Register Confirm

Alternative Program Setup

Block Erase Setup

10h

20h

The Command Interface is reset to read mode

when power is first applied, when exiting from Re-

2Fh

Block Lock-Down Confirm

Double Word Program Setup

Program Setup

30h

set or whenever V

is lower than V

. Com-

DD

LKO

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to read mode.

40h

50h

Clear Status Register

Refer to Table 4, Command Codes and Appendix

D, Tables 36 and 37, Command Interface States -

Modify and Lock Tables, for a summary of the

Command Interface.

The Command Interface is split into two types of

commands: Standard commands and Factory

Program commands. The following sections ex-

plain in detail how to perform each command.

55h

Quadruple Word Program Setup

Block Lock Setup, Block Unlock Setup,

Block Lock Down Setup and Set

Configuration Register Setup

60h

70h

80h

90h

98h

B0h

C0h

Read Status Register

Bank Erase Setup

Read Electronic Signature

Read CFI Query

Program/Erase Suspend

Protection Register Program

Program/Erase Resume, Block Erase

Confirm, Bank Erase Confirm, Block

Unlock Confirm

D0h

FFh

Read Array

12/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

COMMAND INTERFACE - STANDARD COMMANDS

The following commands are the basic commands

used to read, write to and configure the device.

Refer to Table 5, Standard Commands, in con-

junction with the following text descriptions.

Read CFI Query Command

The Read CFI Query command is used to read

data from the Common Flash Interface (CFI)

memory area located in the bottom bank. The

Read CFI Query Command consists of one Bus

Write cycle, to an address within the bottom bank.

Once the command is issued subsequent Bus

Read operations in the same bank read from the

Common Flash Interface.

If a Read CFI Query command is issued in a bank

that is executing a Program or Erase operation the

bank will go into Read Status Register mode, sub-

sequent Bus Read cycles will output the Status

Register and the Program/Erase controller will

continue to Program or Erase in the background.

When the Program or Erase operation has fin-

ished the device will enter Read CFI Query mode.

Read Array Command

The Read Array command returns the addressed

bank to Read Array mode. One Bus Write cycle is

required to issue the Read Array command and re-

turn the addressed bank to Read Array mode.

Subsequent read operations will read the ad-

dressed location and output the data. A Read Ar-

ray command can be issued in one bank while

programming or erasing in the other bank. Howev-

er if a Read Array command is issued to a bank

currently executing a Program or Erase operation

the command will be ignored.

Read Status Register Command

This mode supports asynchronous or single syn-

chronous reads only, it does not support page

mode or synchronous burst reads.

The status of the other banks is not affected by the

command (see Table 11). After issuing a Read

CFI Query command, a Read Array command

should be issued to the addressed bank to return

the bank to read mode.

See Appendix C, Common Flash Interface, Tables

30, 31, 32, 33, 34 and 35 for details on the infor-

mation contained in the Common Flash Interface

memory area.

A Bank’s Status Register indicates when a Pro-

gram or Erase operation is complete and the suc-

cess or failure of operation itself. Issue a Read

Status Register command to read the Status Reg-

ister content of the addressed Bank. The Read

Status Register command can be issued at any

time, even during Program or Erase operations.

The following Bus Read operations output the con-

tent of the Status Register of the addressed bank.

The Status Register is latched on the falling edge

of E or G signals, and can be read until E or G re-

turns to V . Either E or G must be toggled to up-

IH

date the latched data. See Table 8 for the

description of the Status Register Bits. This mode

supports asynchronous or single synchronous

reads only.

Clear Status Register Command

The Clear Status Register command can be used

to reset (set to ‘0’) error bits 1, 3, 4 and 5 in the Sta-

tus Register of the addressed bank. One bus write

cycle is required to issue the Clear Status Register

command. After the Clear Status Register com-

mand the bank returns to Read Array mode.

The error bits in the Status Register do not auto-

matically return to ‘0’ when a new command is is-

sued. The error bits in the Status Register should

be cleared before attempting a new Program or

Erase command.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes, the Block

Locking Status, the Protection Register, and the

Configuration Register.

The Read Electronic Signature command consists

of one write cycle to an address within the bottom

bank. A subsequent read operation in the address

of the bottom bank will output the Manufacturer

Code, the Device Code, the protection Status of

Blocks of the bottom bank, the Die Revision Code,

the Protection Register, or the Read Configuration

Register (see Table 6).

If the first write cycle of Read Electronic Signature

command is issued to an address within the top

bank, a subsequent read operation in an address

of the top bank will output the protection Status of

blocks of the top bank. The status of the other

bank is not affected by the command (see Table

11). This mode supports asynchronous or single

synchronous reads only, it does not support page

mode or synchronous burst reads.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error. The Block

Erase command can be issued at any moment, re-

gardless of whether the block has been pro-

grammed or not.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Erase command.

13/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits 4 and 5 are set and the

command aborts. Erase aborts if Reset turns to

During Bank Erase operations the bank being

erased will only accept the Read Status Register

command, all other commands will be ignored. A

Bank Erase operation cannot be suspended.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being erased. Typical Erase times are

given in Table 14, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

V . As data integrity cannot be guaranteed when

IL

the Erase operation is aborted, the block must be

erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register mode un-

til a Read Array, Read CFI Query or Read Elec-

tronic Signature command is issued.

Program Command

The memory array can be programmed word-by-

word. Only one Word in one bank can be pro-

grammed at any one time. Two bus write cycles

are required to issue the Program Command.

■ The first bus cycle sets up the Program

During Erase operations the bank containing the

block being erased will only accept the Read Sta-

tus Register and the Program/Erase Suspend

command, all other commands will be ignored.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being erased. Typical Erase times are

given in Table 14, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

After programming has started, read operations in

the bank being programmed output the Status

Register content.

During Program operations the bank being pro-

grammed will only accept the Read Status Regis-

ter and the Program/Erase Suspend command.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being programmed. Typical Program

times are given in Table 14, Program, Erase

Times and Program/Erase Endurance Cycles.

See Appendix C, Figure 22, Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

for using the Block Erase command.

Bank Erase Command

The Bank Erase command can be used to erase a

bank. It sets all the bits within the selected bank to

’1’. All previous data in the bank is lost. The Bank

Erase command will ignore any protected blocks

within the bank. If all blocks in the bank are pro-

tected then the Bank Erase operation will abort

and the data in the bank will not be changed. The

Status Register will not output any error.

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the memory location must be

reprogrammed.

See Appendix C, Figure 18, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Two Bus Write cycles are required to issue the

command.

Program/Erase Suspend Command

■ The first bus cycle sets up the Bank Erase

The Program/Erase Suspend command is used to

pause a Program or Block Erase operation. A

Bank Erase operation cannot be suspended.

One bus write cycle is required to issue the Pro-

gram/Erase Suspend command. Once the Pro-

gram/Erase Controller has paused bits 7, 6 and/ or

2 of the Status Register will be set to ‘1’. The com-

mand must be addressed to the bank containing

the Program or Erase operation.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array (cannot read the suspended block),

Read Status Register, Read Electronic Signature

and Read CFI Query commands. Additionally, if

the suspend operation was Erase then the Clear

status Register, Program, Block Lock, Block Lock-

Down or Protection Program commands will also

be accepted. The block being erased may be pro-

command.

■ The second latches the bank address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Bank Erase

Confirm (D0h), Status Register bits b4 and b5 are

set and the command aborts. Erase aborts if Re-

set turns to V . As data integrity cannot be guar-

IL

anteed when the Erase operation is aborted, the

bank must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register mode un-

til a Read Array, Read CFI Query or Read Elec-

tronic Signature command is issued.

14/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

tected by issuing the Block Lock, Block Lock-

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register also protects bit 2 of the Pro-

tection Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of Parameter Block #0 (see Figure 5,

Security Block and Protection Register Memory

Map). Attempting to program a previously protect-

ed Protection Register will result in a Status Reg-

ister error. The protection of the Protection

Register and/or the Security Block is not revers-

ible.

Down or Protection Register Program commands.

Only the blocks not being erased may be read or

programmed correctly. When the Program/Erase

Resume command is issued the operation will

complete. Refer to the Dual Operations section for

detailed information about simultaneous opera-

tions allowed during Program/Erase Suspend.

During a Program/Erase Suspend, the device can

be placed in standby mode by taking Chip Enable

to V . Program/Erase is aborted if Reset turns to

IH

V .

IL

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 25, Protection

Register Program Flowchart and Pseudo Code,

for a flowchart for using the Protection Register

Program command.

See Appendix C, Figure 21, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

23, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

Set Configuration Register Command.

Program/Erase Resume Command

The Set Configuration Register command is used

to write a new value to the Configuration Control

Register which defines the burst length, type, X la-

tency, Synchronous/Asynchronous Read mode

and the valid Clock edge configuration.

Two Bus Write cycles are required to issue the Set

Configuration Register command.

■ The first cycle writes the setup command and

the address corresponding to the Configuration

Register content.

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend command has paused

it. One Bus Write cycle is required to issue the

command. The command must be written to the

bank containing the Program or Erase Suspend.

The Program/Erase Resume command changes

the read mode of the target bank to Read Status

Register mode.

If a Program command is issued during a Block

Erase Suspend, then the erase cannot be re-

sumed until the programming operation has com-

pleted. It is possible to accumulate suspend

operations. For example: suspend an erase oper-

ation, start a programming operation, suspend the

programming operation then read the array. See

Appendix C, Figure 21, Program Suspend & Re-

sume Flowchart and Pseudo Code, and Figure 23,

Erase Suspend & Resume Flowchart and Pseudo

Code for flowcharts for using the Program/Erase

Resume command.

■ The second cycle writes the Configuration

Register data and the confirm command.

Once the command is issued the memory returns

to Read mode.

The value for the Configuration Register is always

presented on A0-A15. CR0 is on A0, CR1 on A1,

etc.; the other address bits are ignored.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Protection Register Program Command

The Protection Register Program command is

used to Program the 128 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Two Bus Write cycles are required to issue the

Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The first bus cycle sets up the Protection

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 13 shows the Lock Status after issuing a

Block Lock command.

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Block Unlock

command. Refer to the section, Block Locking, for

a detailed explanation. See Appendix C, Figure

15/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

24, Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Lock command.

Block Unlock Command

The Block Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Block Unlock command.

down block cannot be programmed or erased, or

have its protection status changed when WP is

low, V . When WP is high, V the Lock-Down

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

IL

IH,

Two Bus Write cycles are required to issue the

Block Lock-Down command.

■ The first bus cycle sets up the Block Unlock

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 13 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation and Ap-

pendix C, Figure 24, Locking Operations Flow-

chart and Pseudo Code, for a flowchart for using

the Unlock command.

Block Lock-Down Command

A locked or unlocked block can be locked-down by

issuing the Block Lock-Down command. A locked-

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 13 shows the Lock Status af-

ter issuing a Block Lock-Down command. Refer to

the section, Block Locking, for a detailed explana-

tion and Appendix C, Figure 24, Locking Opera-

tions Flowchart and Pseudo Code, for a flowchart

for using the Lock-Down command.

16/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 5. Standard Commands

Commands

Bus Operations

1st Cycle

Add

2nd Cycle

Add

Op.

Write

Data

FFh

70h

Op.

Data

RD

Read Array

1+

BKA

WA

Read

(2)

Read Status Register

BKA

SRD

BKA

BBKA or

(3)

Read Electronic Signature

Read CFI Query

1+

Write

90h

98h

Read

ESD

(3)

(2,3)

BKA

(2)

BBKA

QD

BBKA

Clear Status Register

Block Erase

1

2

1

2

Write

BKA

PRA

CRD

BKA

50h

20h

Write

BA

BKA

WA

D0h

PD

Bank Erase

80h

Program

40h or 10h

B0h

Program/Erase Suspend

Program/Erase Resume

Protection Register Program

Set Configuration Register

Block Lock

D0h

C0h

Write

PRA

CRD

BA

PRD

03h

01h

D0h

2Fh

60h

Block Unlock

60h

BA

Block Lock-Down

60h

BA

Note: 1. X = Don’t Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,

QD=Query Data, BA=Block Address, BKA= Bank Address, BBKA= Bottom Bank Address, PD=Program Data, PRA=Protection

Register Address, PRD=Protection Register Data, CRD=Configuration Register Data.

2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.

3. When addressed to a block in the Top Bank, reads Block Protection data only.

17/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 6. Electronic Signature Codes

Code

Address (h)

Data (h)

0020

88CA

88CB

8801

Manufacturer Code

Top (M58CR064C)

Bottom Bank Address + 00

Bottom (M58CR064D)

Device Code

Bottom Bank Address + 01

Top (M58CR064P)

Bottom (M58CR064Q)

Lock

8802

0001

0000

0003

0002

Reserved

CR

Unlocked

Block Protection

Block Address + 02

Locked and Locked-Down

Unlocked and Locked-Down

Reserved

Bottom Bank Address + 03

Bottom Bank Address + 05

Configuration Register

ST Factory Default

xx06

Security Block Permanently Locked

xx02

Protection Register Lock

Bottom Bank Address + 80

OTP Area Permanently Locked

xx04

Security Block and OTP Area Permanently

Locked

xx00

Bottom Bank Address + 81 Unique Device

Bottom Bank Address + 84

Number

Protection Register

Bottom Bank Address + 85

Bottom Bank Address + 8C

OTP Area

Note: CR=Configuration Register.

Figure 5. Security Block and Protection Register Memory Map

PROTECTION REGISTER

8Ch

SECURITY BLOCK

Parameter Block # 0

User Programmable OTP

Unique device number

85h

84h

81h

80h

Protection Register Lock

2

1

0

AI06181

18/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS

The Factory Program commands are used to

speed up programming. They require V to be at

Quadruple Word Program Command

PP

The Quadruple Word Program command im-

proves the programming throughput by writing a

page of four adjacent words in parallel. The four

words must differ only for the addresses A0 and

A1.

V

. Refer to Table 7, Factory Program Com-

PPH

mands, in conjunction with the following text de-

scriptions.

Double Word Program Command

The Double Word Program command improves

the programming throughput by writing a page of

two adjacent words in parallel. The two words

must differ only for the address A0.

Programming should not be attempted when V

PP

is not at V

. The command can be executed if

PPH

V

is below V

but the result is not guaranteed.

PP

PPH

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

Programming should not be attempted when V

PP

. The command can be executed if

PPH

■ The first bus cycle sets up the Double Word

but the result is not guaranteed.

PPH

Program Command.

Three bus write cycles are necessary to issue the

Double Word Program command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The first bus cycle sets up the Double Word

■ The third bus cycle latches the Address and the

Program Command.

Data of the second word to be written.

■ The second bus cycle latches the Address and

■ The fourth bus cycle latches the Address and

the Data of the first word to be written.

the Data of the third word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

■ The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations in the bank being programmed

output the Status Register content after the pro-

gramming has started.

Read operations to the bank being programmed

output the Status Register content after the pro-

gramming has started.

During Double Word Program operations the bank

being programmed will only accept the Read Sta-

tus Register command, all other commands will be

ignored. Dual operations are not supported during

Double Word Program operations. It is not recom-

mended to suspend the Double Word Program

command. Typical Program times are given in Ta-

ble 14, Program, Erase Times and Program/Erase

Endurance Cycles.

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the memory locations must

be reprogrammed.

During Quadruple Word Program operations the

bank being programmed will only accept the Read

Status Register command, all other commands

will be ignored.

Dual operations are not supported during Quadru-

ple Word Program operations. It is not recom-

mended to suspend the Quadruple Word Program

command. Typical Program times are given in Ta-

ble 14, Program, Erase Times and Program/Erase

Endurance Cycles.

See Appendix C, Figure 20, Quadruple Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Quadruple Word Program

command.

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the memory locations must

be reprogrammed.

See Appendix C, Figure 19, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

19/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 7. Factory Program Commands

Bus Write Operations

3rd

Command

Phase

1st

2nd

Add

4th

Add

5th

Add

Data

Add

Data

Add

Data

(2)

3

5

BKA

30h

WA1

PD1

WA2

PD2

Double Word Program

Quadruple Word

BKA

55h

PD1

WA2

PD2

WA3

PD3

WA4

PD4

(3)

Program

Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, WA1 is the Start Address.

2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.

3. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

STATUS REGISTER

The M58CR064 has two Status Registers, one for

each bank. The Status Registers provide informa-

tion on the current or previous Program or Erase

operations executed in each bank. Issue a Read

Status Register command to read the contents of

the Status Register, refer to Read Status Register

Command section for more details. To output the

contents, the Status Register is latched and updat-

ed on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

pauses. After the Program/Erase Controller paus-

es the bit is High.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V

PP

or Output Enable returns to V . The Status Reg-

IH

Status and Block Lock Status bits should be tested

for errors.

ister can only be read using single asynchronous

or single synchronous reads. Bus Read opera-

tions from any address within the bank, always

read the Status Register during Program and

Erase operations.

The various bits convey information about the sta-

tus and any errors of the operation. Bits SR7, SR6

and SR2 give information on the status of the bank

and are set and reset by the device. Bits SR5,

SR4, SR3 and SR1 give information on errors,

they are set by the device but must be reset by is-

suing a Clear Status Register command or a hard-

ware reset. If an error bit is set to ‘1’ the Status

Register should be reset before issuing another

command.

Erase Suspend Status Bit (SR6). The

Erase

Suspend Status bit indicates that an Erase opera-

tion has been suspended or is going to be sus-

pended in the addressed block. When the Erase

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

SR7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

The bits in the Status Register are summarized in

Table 8, Status Register Bits. Refer to Table 8 in

conjunction with the following text descriptions.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Program/Erase Controller Status Bit (SR7). The

Program/Erase Controller Status bit indicates

whether the Program/Erase Controller is active or

inactive in the addressed bank. When the Pro-

gram/Erase Controller Status bit is Low (set to ‘0’),

the Program/Erase Controller is active; when the

bit is High (set to ‘1’), the Program/Erase Control-

ler is inactive, and the device is ready to process a

new command.

Erase Status Bit (SR5). The Erase Status bit

can be used to identify if the memory has failed to

verify that the block or bank has erased correctly.

When the Erase Status bit is High (set to ‘1’), the

Program/Erase Controller has applied the maxi-

mum number of pulses to the block or bank and

still failed to verify that it has erased correctly. The

Erase Status bit should be read once the Program/

Erase Controller Status bit is High (Program/Erase

Controller inactive).

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

20/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Once set High, the Erase Status bit can only be re-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status Bit (SR4). The Program Status

bit is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Program Suspend Status Bit (SR2). The Pro-

gram Suspend Status bit indicates that a Program

operation has been suspended in the addressed

block. When the Program Suspend Status bit is

High (set to ‘1’), a Program/Erase Suspend com-

mand has been issued and the memory is waiting

for a Program/Erase Resume command. The Pro-

gram Suspend Status should only be considered

valid when the Program/Erase Controller Status

bit is High (Program/Erase Controller inactive).

SR2 is set within 5µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status Bit (SR1). The Block

Protection Status bit can be used to identify if a

Program or Block Erase operation has tried to

modify the contents of a locked block.

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

V

Status Bit (SR3). The V Status bit can be

PP

used to identify an invalid voltage on the V pin

PP

during Program and Erase operations. The V

PP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

cur if V becomes invalid during an operation.

PP

When the V Status bit is Low (set to ‘0’), the volt-

PP

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved Bit (SR0). SR0 is reserved. Its value

must be masked.

age on the V pin was sampled at a valid voltage;

PP

when the V Status bit is High (set to ‘1’), the V

PP

pin has a voltage that is below the V

Lockout

PP

Voltage, V

, the memory is protected and Pro-

PPLK

gram and Erase operations cannot be performed.

Once set High, the V Status bit can only be reset

PP

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

21/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 8. Status Register Bits

Bit

Name

Type LogicLevel

Definition

’1’

Ready

SR7 P/E.C. Status

Status

’0’

Busy

’1’

Erase Suspended

SR6 Erase Suspend Status

SR5 Erase Status

Status

’0’

Erase In progress or Completed

Erase Error

’1’

Error

’0’

Erase Success

’1’

Program Error

SR4 Program Status

Error

’0’

Program Success

V

Invalid, Abort

OK

’1’

PP

V

Status

SR3

Error

’0’

PP

’1’

Program Suspended

SR2 Program Suspend Status Status

’0’

’1’

’0’

Program In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

Reserved

SR1 Block Protection Status

Error

SR0

Note: Logic level ’1’ is High, ’0’ is Low.

22/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

CONFIGURATION REGISTER

The Configuration Register is used to configure

the type of bus access that the memory will per-

form. Refer to Read Modes section for details on

read operations.

The Configuration Register is set through the

Command Interface. After a Reset or Power-Up

the device is configured for asynchronous page

read (CR15 = 1). The Configuration Register bits

are described in Table 9. They specify the selec-

tion of the burst length, burst type, burst X latency

and the Read operation. Refer to Figures 6 and 7

for examples of synchronous burst configurations.

Refer to Figure 6, X-Latency and Data Output

Configuration Example.

Power-Down Bit (CR10)

The Power-Down bit is used to enable or disable

the power-down function.

When the Power-Down bit is set to ‘0’ the power-

down function is disabled. If the Reset/Power-

Down, RP, pin goes Low, V , the device is reset

IL

and the supply current, I

is reduced to the

DD,

standby value, I

.

DD3

When the Power-Down bit is set to ‘1’ the power-

down function is enabled. If the Reset/Power-

Read Select Bit (CR15)

Down, RP, pin goes Low, V , the device goes into

IL

The Read Select bit, CR15, is used to switch be-

tween asynchronous and synchronous Bus Read

operations. When the Read Select bit is set to ’1’,

read operations are asynchronous; when the

Read Select bit is set to ’0’, read operations are

synchronous. Synchronous Burst Read is support-

ed in both parameter and main blocks and can be

performed across banks.

the power-down state and the supply current, I

DD,

is reduced to the power-down value, I

.

DD2

The recovery time after a Reset/Power-Down, RP,

pulse is significantly longer when power-down is

enabled (see Table 24).

After a reset the Power-Down Bit is set to ‘0’.

Wait Configuration Bit (CR8)

On reset or power-up the Read Select bit is set

to’1’ for asynchronous access.

X-Latency Bits (CR13-CR11)

In burst mode the Wait bit controls the timing of the

Wait output pin, WAIT. When the Wait bit is ’0’ the

Wait output pin is asserted during the wait state.

When the Wait bit is ’1’ (default) the Wait output

pin is asserted one clock cycle before the wait

state.

WAIT is asserted during a continuous burst and

also during a 4 or 8 burst length if no-wrap config-

uration is selected. WAIT is not asserted during

asynchronous reads, single synchronous reads or

during latency in synchronous reads.

The X-Latency bits are used during Synchronous

Read operations to set the number of clock cycles

between the address being latched and the first

data becoming available. For correct operation the

X-Latency bits can only assume the values in Ta-

ble 9, Configuration Register.

The correspondence between X-Latency settings

and the maximum sustainable frequency must be

calculated taking into account some system pa-

rameters. Two conditions must be satisfied:

Burst Type Bit (CR7)

The Burst Type bit is used to configure the se-

quence of addresses read as sequential or inter-

leaved. When the Burst Type bit is ’0’ the memory

outputs from interleaved addresses; when the

Burst Type bit is ’1’ (default) the memory outputs

from sequential addresses. See Tables 10, Burst

Type Definition, for the sequence of addresses

output from a given starting address in each mode.

1. Depending on whether t

or t

is

DELAY

AVK_CPU

supplied either one of the following two

equations must be satisfied:

(n + 1) t ≥ t

- t

+ t

K

ACC AVK_CPU QVK_CPU

(n + 2) t ≥ t

+ t

K

ACC

DELAY QVK_CPU

2. and also

t > t

+ t

QVK_CPU

Valid Clock Edge Bit (CR6)

K

KQV

where

n is the chosen X-Latency configuration code

t is the clock period

The Valid Clock Edge bit, CR6, is used to config-

ure the active edge of the Clock, K, during Syn-

chronous Burst Read operations. When the Valid

Clock Edge bit is ’0’ the falling edge of the Clock is

the active edge; when the Valid Clock Edge bit is

’1’ the rising edge of the Clock is active.

K

t

is clock to address valid, L Low, or E

AVK_CPU

Low, whichever occurs last

t

is address valid, L Low, or E Low to clock,

DELAY

Wrap Burst Bit (CR3)

whichever occurs last

The burst reads can be confined inside the 4 or 8

Word boundary (wrap) or overcome the boundary

(no wrap). The Wrap Burst bit is used to select be-

tween wrap and no wrap. When the Wrap Burst bit

is set to ‘0’ the burst read wraps; when it is set to

‘1’ the burst read does not wrap.

t

is the data setup time required by the

QVK_CPU

system CPU,

t

is the clock to data valid time

is the random access time of the device.

KQV

ACC

23/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Burst length Bits (CR2-CR0)

If the starting address is aligned to a 4 word

boundary no wait states are needed and the WAIT

output is not asserted.

The Burst Length bits set the number of Words to

be output during a Synchronous Burst Read oper-

ation as result of a single address latch cycle.

They can be set for 4 words, 8 words or continu-

ous burst, where all the words are read sequential-

ly.

In continuous burst mode the burst sequence can

cross bank boundaries.

In continuous burst mode or in 4, 8 words no-wrap,

depending on the starting address, the device as-

serts the WAIT output to indicate that a delay is

necessary before the data is output.

If the starting address is shifted by 1,2 or 3 posi-

tions from the four word boundary, WAIT will be

asserted for 1, 2 or 3 clock cycles when the burst

sequence crosses the first 64 word boundary, to

indicate that the device needs an internal delay to

read the successive words in the array. WAIT will

be asserted only once during a continuous burst

access. See also Table 10, Burst Type Definition.

CR14, CR9, CR5 and CR4 are reserved for future

use.

Table 9. Configuration Register

Bit

Description

Value

Description

0

1

Synchronous Read

CR15

CR14

Read Select

Asynchronous Read (Default at power-on)

Reserved

010

011

100

101

111

2 clock latency

3 clock latency

4 clock latency

CR13-CR11

X-Latency

5 clock latency

Reserved

Other configurations reserved

0

1

Power-Down disabled

Power-Down enabled

Reserved

CR10

CR9

Power-Down

0

WAIT is active during wait state

CR8

CR7

Wait Configuration

1

0

1

0

1

WAIT is active one data cycle before wait state (default)

Interleaved

Burst Type

Sequential (default)

Falling Clock edge

Rising Clock edge

Reserved

CR6

CR5-CR4

CR3

Valid Clock Edge

0

Wrap

Wrap Burst

1

No Wrap

001

010

111

4 words

CR2-CR0

Burst Length

8 words

Continuous (CR7 must be set to ‘1’)

24/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 10. Burst Type Definition

Start

Address

4 Words

8 Words

Continuous Burst

Sequential

Interleaved

0-1-2-3

Sequential

Interleaved

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

0

1

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

3-4-5-6-7-8-9...

1-0-3-2

2

2-3-0-1

3

3-2-1-0

...

7

7-4-5-6

7-6-5-4

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

7-8-9-10-11-12-13...

...

60

61

62

60-61-62-63-64-65-66...

61-62-63-WAIT-64-65-66...

62-63-WAIT-WAIT-64-65-66...

63-WAIT-WAIT-WAIT-64-65-

66...

63

Sequential

0-1-2-3

Interleaved

Sequential

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9...

3-4-5-6-7-8-9-10

Interleaved

0

1

1-2-3-4

2

2-3-4-5

3

3-4-5-6

...

7

7-8-9-10

7-8-9-10-11-12-13-14

Same as for Wrap

(Wrap /No Wrap

has no effect on

Continuous Burst )

...

60-61-62-63-64-65-66-

67

60

61

62

63

60-61-62-63

61-62-63-WAIT-64-65-

66-67-68

61-62-63-WAIT-64

62-63-WAIT-WAIT-

64-65

62-63-WAIT-WAIT-64-

65-66-67-68-69

63-WAIT-WAIT-

WAIT-64-65-66

63-WAIT-WAIT-WAIT-

64-65-66-67-68-69-70

25/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 6. X-Latency and Data Output Configuration Example

X-latency

1st cycle

2nd cycle

3rd cycle

4th cycle

K

E

L

A21-A0

tDELAY

VALID ADDRESS

tAVK_CPU

tQVK_CPU

tK

tQVK_CPU

tACC

tKQV

DQ15-DQ0

VALID DATA VALID DATA

Note. Settings shown: X-latency = 4, Data Output held for one clock cycle

AI90005

Figure 7. Wait Configuration Example

E

K

L

A21-A0

VALID ADDRESS

DQ15-DQ0

VALID DATA VALID DATA NOT VALID VALID DATA

WAIT

CR8 = '0'

WAIT

CR8 = '1'

AI90006

26/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

READ MODES

Read operations can be performed in two different

ways depending on the settings in the Configura-

tion Register. If the clock signal is ‘don’t care’ for

the data output, the read operation is Asynchro-

nous; if the data output is synchronized with clock,

the read operation is Synchronous.

The Read mode and data output format are deter-

mined by the Configuration Register. (See Config-

uration Register section for details). All banks

supports both asynchronous and synchronous

read operations. The Dual Bank architecture al-

lows read operations in one bank, while write op-

erations are being executed in the other (see

Tables 11 and 12).

In Synchronous Burst Read mode the flow of the

data output depends on parameters that are con-

figured in the Configuration Register.

A burst sequence is started at the first clock edge

(rising or falling depending on Valid Clock Edge bit

CR6 in the Configuration Register) after the falling

edge of Latch Enable. Addresses are internally in-

cremented and after a delay of 2 to 5 clock cycles

(X latency bits CR13-CR11) the corresponding

data are output on each clock cycle.

The number of Words to be output during a Syn-

chronous Burst Read operation can be configured

as 4 or 8 Words or Continuous (Burst Length bits

CR2-CR0). The data can be configured to remain

valid for one or two clock cycles (Data Output Con-

figuration bit CR9).

The order of the data output can be modified

through the Burst Type and the Wrap Burst bits in

the Configuration Register. The burst sequence

may be configured to be sequential or interleaved

(CR7). The burst reads can be confined inside the

4 or 8 Word boundary (Wrap) or overcome the

boundary (No Wrap). If the starting address is

aligned to a 4 Word Page the wrapped configura-

tion has no impact on the output sequence. Inter-

leaved mode is not allowed in Continuous Burst

Read mode or with No Wrap sequences.

Asynchronous Read Mode

In Asynchronous Read operations the clock signal

is ‘don’t care’. The device outputs the data corre-

sponding to the address latched, that is the mem-

ory array, Status Register, Common Flash

Interface or Electronic Signature depending on the

command issued. CR15 in the Configuration Reg-

ister must be set to ‘1’ for Asynchronous opera-

tions.

In Asynchronous Read mode a Page of data is in-

ternally read and stored in a Page Buffer. The

Page has a size of 4 Words and is addressed by

A0 and A1 address inputs. The address inputs A0

and A1 are not gated by Latch Enable in Asyn-

chronous Read mode.

A WAIT signal may be asserted to indicate to the

system that an output delay will occur. This delay

will depend on the starting address of the burst se-

quence; the worst case delay will occur when the

sequence is crossing a 64 word boundary and the

starting address was at the end of a four word

boundary.

The first read operation within the Page has a

longer access time (T , Random access time),

acc

subsequent reads within the same Page have

much shorter access times. If the Page changes

then the normal, longer timings apply again.

WAIT is asserted during X latency and the Wait

state and is only deasserted when output data are

valid. In Continuous Burst Read mode a Wait state

will occur when crossing the first 64 Word bound-

ary. If the burst starting address is aligned to a 4

Word Page, the Wait state will not occur.

Asynchronous Read operations can be performed

in two different ways, Asynchronous Random Ac-

cess Read and Asynchronous Page Read. Only

Asynchronous Page Read takes full advantage of

the internal page storage so different timings are

applied.

The WAIT signal is active Low. The WAIT signal is

meaningful only in Synchronous Burst Read

mode, in other modes, WAIT is not asserted (ex-

cept for Read Array mode).

See Table 20, Asynchronous Read AC Character-

istics, Figure 10, Asynchronous Random Access

Read AC Waveform and Figure 11, Asynchronous

Page Read AC Waveform for details.

See Table 21, Synchronous Read AC Character-

istics and Figure 12, Synchronous Burst Read AC

Waveform for details.

Synchronous Burst Read Mode

In Synchronous Burst Read mode the data is out-

put in bursts synchronized with the clock. It is pos-

sible to perform burst reads across bank

boundaries.

Synchronous Burst Read mode can only be used

to read the memory array. For other read opera-

tions, such as Read Status Register, Read CFI

and Read Electronic Signature, Single Synchro-

nous Read or Asynchronous Random Access

Read must be used.

Single Synchronous Read Mode

Single Synchronous Read operations are similar

to Synchronous Burst Read operations except that

only the first data output after the X latency is valid.

Other Configuration Register parameters have no

effect on Single Synchronous Read operations.

Synchronous Single Reads are used to read the

Electronic Signature, Status Register, CFI, Block

27/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Protection Status, Configuration Register Status

or Protection Register. When the addressed bank

is in Read CFI, Read Status Register or Read

Electronic Signature mode, the WAIT signal is al-

ways asserted.

See Table 21, Synchronous Read AC Character-

istics and Figure 13, Single Synchronous Read AC

Waveform for details.

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE

The Dual Operations feature simplifies the soft-

ware management of the device and allows code

to be executed from one bank while the other bank

is being programmed or erased.

The Dual operations feature means that while pro-

gramming or erasing in one bank, Read opera-

tions are possible in the other bank with zero

latency (only one bank at a time is allowed to be in

Program or Erase mode). If a Read operation is re-

quired in a bank which is programming or erasing,

the Program or Erase operation can be suspend-

ed. Also if the suspended operation was Erase

then a Program command can be issued to anoth-

er block, so the device can have one block in

Erase Suspend mode, one programming and the

other bank in Read mode. Bus Read operations

are allowed in the other bank between setup and

confirm cycles of program or erase operations.

The combination of these features means that

read operations are possible at any moment.

Tables 11 and 12 show the dual operations possi-

ble in the other bank and in the same bank. Note

that only the commonly used commands are rep-

resented in these tables. For a complete list of

possible commands refer to Appendix D, Com-

mand Interface State Tables.

Table 11. Dual Operations Allowed In Other Bank

Commands allowed in other bank

Read

Status

Register

Read Read

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

CFI

Electronic Program

Signature

Erase

Query

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Programming

Erasing

–

Program Suspended

Erase Suspended

–

Yes

–

Table 12. Dual Operations Allowed In Same Bank

Commands allowed in same bank

Read

Status

Register

Read

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

Read

CFI Query

Electronic Program

Signature

Erase

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Programming

Erasing

–

(1)

Program Suspended

Erase Suspended

Yes

–

Yes

(1)

–

Yes

Note: 1. Not allowed in the Block or Word that is being erased or programmed.

28/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

BLOCK LOCKING

The M58CR064 features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

software commands. A locked block can be un-

locked by issuing the Unlock command.

■ Lock/Unlock - this first level allows software-

Lock-Down State

only control of block locking.

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their protection status can-

not be changed using software commands alone.

A Locked or Unlocked block can be Locked-Down

by issuing the Lock-Down command. Locked-

Down blocks revert to the Locked state when the

device is reset or powered-down.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■ V ≤ V

- the third level offers a complete

PP

PPLK

hardware protection against program and erase

on all blocks (M58CR064C/D only).

The first two levels (Lock/Unlock and Lock-Down)

are available in M58CR064C/D and M58CR064P/

The Lock-Down function is dependent on the WP

input pin. When WP=0 (V ), the blocks in the

IL

Q. The third level (V ≤ V

) is only available

PPLK

PP

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

for the M58CR064C/D versions, in the

M58CR064P/Q this feature has been disabled.

WP=1 (V ) the Lock-Down function is disabled

IH

For all devices the protection status of each block

can be set to Locked, Unlocked, and Lock-Down.

Table 13, defines all of the possible protection

states (WP, DQ1, DQ0), and Appendix C, Figure

24, shows a flowchart for the locking operations.

(1,1,x) and Locked-Down blocks can be individual-

ly unlocked to the (1,1,0) state by issuing the soft-

ware command, where they can be erased and

programmed. These blocks can then be re-locked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is low , blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

resets all blocks , including those in Lock-Down, to

the Locked state.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 6,

will output the protection status of that block. The

lock status is represented by DQ0 and DQ1. DQ0

indicates the Block Lock/Unlock status and is set

by the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend. Refer to Appendix D, Com-

mand Interface State Table, for detailed informa-

tion on which commands are valid during erase

suspend.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

29/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 13. Lock Status

Current

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

Protection Status

(WP, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Allowed

After

WP transition

Current State

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

30/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES

The Program and Erase times and the number of

Program/ Erase cycles per block are shown in Ta-

ble 14. In the M58CR064 the maximum number of

Program/ Erase cycles depends on the voltage

supply used.

Table 14. Program, Erase Times and Program, Erase Endurance Cycles

Typical

after

100k W/E

Cycles

Parameter

Condition

Min

Typ

Unit

Max

(2)

0.3

0.8

1.1

11

18

33

54

40

1

3

2.5

4

s

Parameter Block (4 KWord) Erase

Main Block (32 KWord) Erase

Preprogrammed

Not Preprogrammed

Preprogrammed

4

s

Bank A (16Mbit) Erase

Bank B (48Mbit) Erase

Not Preprogrammed

Preprogrammed

s

Not Preprogrammed

s

(3)

ms

Parameter Block (4 KWord) Program

(3)

300

ms

Main Block (32 KWord) Program

(3)

10

5

10

100

10

µs

Word Program

Program Suspend Latency

Erase Suspend Latency

5

20

µs

Main Blocks

100,000

cycles

s

Program/Erase Cycles (per Block)

Parameter Blocks

0.3

0.9

13

39

510

8

2.5

4

Parameter Block (4 KWord) Erase

Main Block (32 KWord) Erase

Bank A (16Mbit) Erase

Bank B (48Mbit) Erase

4Mbit Program

s

Quadruple Word

ms

µs

(3)

100

Word/ Double Word/ Quadruple Word Program

Parameter Block (4 KWord)

Quadruple Word

8

ms

(3)

Program

Word

32

ms

Quadruple Word

Word

64

ms

(3)

Main Block (32 KWord) Program

256

Main Blocks

Parameter Blocks

1000 cycles

2500 cycles

Program/Erase Cycles (per Block)

Note: 1. T = –40 to 85°C; V = 1.65V to 2V; V = 1.65V to 3.3V.

DDQ

A

DD

2. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).

3. Excludes the time needed to execute the command sequence.

31/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 15. Absolute Maximum Ratings

Value

Symbol

Parameter

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Min

–40

–55

Max

85

Unit

°C

T

A

T

125

155

°C

BIAS

T

°C

STG

V

DDQ

+0.5

Input or Output Voltage

–0.5

V

IO

Supply Voltage

2.7

3.6

13

DD

V

Input/Output Supply Voltage

Program Voltage

V

DDQ

V

PP

I

Output Short Circuit Current

Time for V at V

100

mA

hours

O

t

VPPH

PP

PPH

32/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 16, Operating

and AC Measurement Conditions. Designers

should check that the operating conditions in their

circuit match the operating conditions when rely-

ing on the quoted parameters.

Table 16. Operating and AC Measurement Conditions

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

85

100

120

Parameter

Supply Voltage

Units

Min

1.8

Max

2.0

Min

1.65

11.4

Max

2.0

Min

1.65

11.4

Max

2.0

V

DD

Supply Voltage

1.8

3.3

DDQ

Supply Voltage (Factory environment)

Supply Voltage (Application environment)

11.4

12.6

PP

V

DDQ

V

DDQ

+0.4

DDQ

V

-0.4

V

+0.4

Ambient Operating Temperature

– 40

85

– 40

85

– 40

85

°C

pF

ns

V

Load Capacitance (C )

30

L

Input Rise and Fall Times

4

0 to V

DDQ

Input Pulse Voltages

DDQ

V

/2

DDQ

V

DDQ

/2

V

/2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 8. AC Measurement I/O Waveform

Figure 9. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DD

0V

16.7kΩ

AI06161

DEVICE

UNDER

TEST

C

L

16.7kΩ

0.1µF

C

includes JIG capacitance

L

AI06162

Table 17. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

8

Unit

C

V

= 0V

6

8

pF

IN

C

OUT

V

OUT

12

Note: Sampled only, not 100% tested.

33/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 18. DC Characteristics - Currents

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V ≤ V ≤ V

LI

IN

DDQ

I

LO

0V ≤ V

≤ V

OUT DDQ

±1

µA

Supply Current

Asynchronous Read (f=6MHz)

E = V , G = V

3

6

mA

IL

IH

4 Word

8 Word

6

8

13

14

10

16

18

25

mA

Supply Current

Synchronous Read (f=40MHz)

I

DD1

Continuous

4 Word

6

7

Supply Current

Synchronous Read (f=54MHz)

8 Word

10

13

Continuous

Supply Current

(Power-Down)

I

RP = V ± 0.2V

2

10

µA

DD2

DD3

SS

E = V ± 0.2V

Supply Current (Standby)

10

8

50

15

20

15

20

µA

mA

DD

V

= V

PPH

PP

Supply Current (Program)

V

= V

10

8

PP

DD

(1)

I

DD4

V

PPH

Supply Current (Erase)

V

PP

= V

DD

10

Program/Erase in one

Bank, Asynchronous

Read in another Bank

13

26

mA

Supply Current

(Dual Operations)

(1,2)

(1)

I

DD5

Program/Erase in one

Bank, Synchronous

Read in another Bank

16

10

30

50

mA

µA

Supply Current Program/ Erase

Suspended (Standby)

E = V ± 0.2V

I

DD

DD6

V

= V

PPH

2

5

mA

µA

mA

µA

PP

V

Supply Current (Program)

Supply Current (Erase)

PP

V

= V

0.2

2

PP

DD

(1)

I

PP1

5

PP

PPH

V

= V

DD

0.2

100

0.2

5

PP

= V

400

5

PP

PPH

I

V

Supply Current (Read)

PP2

PP

V

≤ V

PP

DD

(1)

Supply Current (Standby)

V

5

I

PP3

Note: 1. Sampled only, not 100% tested.

2. V Dual Operation current is the sum of read and program or erase currents.

DD

34/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 19. DC Characteristics - Voltages

Symbol

Parameter

Input Low Voltage

Test Condition

Min

Typ

Max

Unit

V

–0.5

0.4

IL

V

–0.4

V

+ 0.4

Input High Voltage

Output Low Voltage

Output High Voltage

V

IH

DDQ

V

OL

I

= 100µA

0.1

V

OL

V

OH

I

= –100µA

–0.1

V

OH

V

Program Voltage-Logic

Program Voltage Factory

Program, Erase

1

1.8

12

1.95

12.6

0.9

V

PP1

PP

V

PPH

11.4

V

PP

V

Program or Erase Lockout

V Lock Voltage

DD

V

PPLK

V

LKO

1

V

RPH

RP pin Extended High Voltage

3.3

35/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 10. Asynchronous Random Access Read AC Waveforms

36/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 11. Asynchronous Page Read AC Waveforms

37/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 20. Asynchronous Read AC Characteristics

M58CR064

100

Symbol

Alt

Parameter

Unit

85

30

120

45

t

Address Valid to Next Address Valid

Address Valid to Output Valid (Random)

Address Valid to Output Valid (Page)

Address Transition to Output Transition

Chip Enable Low to Wait Valid

Min

Max

Min

100

ns

AVAV

RC

t

ACC

100

AVQV

t

PAGE

45

AVQV1

(1)

t

0

14

85

0

14

100

0

18

120

0

t

OH

AXQX

t

Max

ELTV

(2)

(1)

t

Chip Enable Low to Output Valid

t

CE

ELQV

t

LZ

Chip Enable Low to Output Transition

Chip Enable High to Wait Hi-Z

Min

Max

Min

Max

Min

Max

Min

ns

ELQX

t

20

0

20

0

20

0

EHTZ

(1)

(2)

(1)

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Wait Valid

Output Enable High to Output Transition

t

OH

EHQX

EHQZ

GLQV

t

HZ

20

25

0

20

25

0

20

25

0

t

OE

t

OLZ

GLQX

t

14

0

14

0

18

0

GLTV

(1)

t

OH

GHQX

(1)

t

DF

Output Enable High to Output Hi-Z

Address Valid to Latch Enable High

Chip Enable Low to Latch Enable High

Latch Enable High to Address Transition

Latch Enable Pulse Width

Max

Min

Max

Min

20

10

85

10

20

10

20

10

ns

GHQZ

t

AVLH

ELLH

AVADVH

t

10

ELADVH

ADVHAX

t

10

LHAX

t

ADVLADVH

10

LLLH

LLQV

LHGL

t

Latch Enable Low to Output Valid (Random)

Latch Enable High to Output Enable Low

100

10

120

10

ADVLQV

t

ADVHGL

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

38/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 12. Synchronous Burst Read AC Waveforms

39/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 13. Single Synchronous Read AC Waveforms

40/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 21. Synchronous Read AC Characteristics

M58CR064

Symbol

Alt

Parameter

Unit

85

7

100

7

120

7

t

Address Valid to Clock High

Chip Enable Low to Clock High

Chip Enable Low to Wait Valid

Min

Max

ns

AVKH

AVCLKH

t

7

ELKH

ELCLKH

t

14

18

ELTV

EHEL

EHTZ

Chip Enable Pulse Width

(subsequent synchronous reads)

t

Min

20

ns

t

Chip Enable High to Wait Hi-Z

Clock High to Address Transition

Max

Min

20

10

20

10

20

10

ns

t

KHAX

CLKHAX

t

Clock High to Output Valid

Clock High to WAIT Valid

KHQV

t

Max

Min

14

18

4

ns

CLKHQV

t

KHTV

Clock High to Output Transition

Clock High to WAIT Transition

KHQX

4

7

4

7

CLKHQX

t

KHTX

t

Latch Enable Low to Clock High

Clock Period (f=40MHz)

Clock Period (f=54MHz)

Clock High to Clock Low

Min

7

ns

LLKH

ADVLCLKH

25

t

CLK

KHKH

18

5

18

5

t

5

KHKL

KLKH

CLKHCLKL

t

Clock Low to Clock High

Max

5

ns

CLKLCLKH

Note: 1. Sampled only, not 100% tested.

2. For other timings please refer to Table 20, Asynchronous Read AC Characteristics.

41/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 14. Write AC Waveforms, Write Enable Controlled

42/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 22. Write AC Characteristics, Write Enable Controlled

M58CR064

Symbol

Alt

Parameter

Unit

85

10

60

40

10

0

100

10

60

40

10

0

120

10

60

40

10

0

t

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Address Valid to Write Enable High

Input Valid to Write Enable High

Min

ns

AVAV

WC

t

AVLH

t

AVWH

WC

t

DVWH

DS

t

Chip Enable Low to Latch Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

ELLH

t

ELWL

CS

t

85

20

10

0

100

20

10

0

120

20

10

0

ELQV

t

Output Enable High to Write Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

GHWL

t

LHAX

t

LLLH

t

Write Enable High to Address Valid

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Latch Enable Low

Write Enable High to Clock Valid

WHAV

t

0

WHAX

AH

t

0

WHDX

DH

CH

t

0

WHEH

(2)

50

0

50

0

50

0

t

WHEL

t

WHGL

t

0

WHLL

t

25

30

105

50

0

25

30

120

50

0

25

30

140

50

0

WHKV

t

WPH

Write Enable High to Write Enable Low

Write Enable High to Output Valid

Write Enable Low to Write Enable High

WHWL

t

WHQV

t

WLWH

WP

t

Output (Status Register) Valid to V Low

QVVPL

PP

t

Output (Status Register) Valid to Write Protect Low Min

0

QVWPL

t

V

High to Write Enable High

PP

Min

200

VPHWH

VPS

t

Write Enable High to V Low

WHVPL

PP

t

Write Enable High to Write Protect Low

Write Protect High to Write Enable High

WHWPL

WPHWH

Note: 1. Sampled only, not 100% tested.

2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

WHEL

software No-Op instruction to delay the first read in the same bank after issuing a command. If the read operation is in a different

bank t is 0ns.

WHEL

43/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 15. Write AC Waveforms, Chip Enable Controlled

44/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 23. Write AC Characteristics, Chip Enable Controlled

M58CR064

Symbol

Alt

Parameter

Unit

85

60

10

40

0

100

60

10

40

0

120

60

10

40

0

t

Address Valid to Next Address Valid

Address Valid to Chip Enable High

Address Valid to Latch Enable High

Input Valid to Write Enable High

Min

ns

AVAV

WC

t

AVEH

WC

t

AVLH

t

DVEH

EHAX

EHDX

DS

AH

DH

t

Chip Enable High to Address Transition

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

Latch Enable Low to Output Valid

Output Enable High to Chip Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

t

0

t

WPH

30

0

30

0

30

0

EHEL

EHGL

t

0

EHWH

CH

t

60

10

85

20

10

60

10

100

20

10

60

10

120

20

10

ELEH

WP

t

ELLH

ELQV

GHEL

t

LHAX

t

LLLH

(2)

Write Enable High to Chip Enable Low

Write Enable High to Clock Valid

50

25

0

50

25

0

50

25

0

t

WHEL

t

WHKV

t

Write Enable Low to Chip Enable Low

WLEL

CS

t

Chip Enable High to V Low

200

0

200

0

200

0

EHVPL

PP

t

Chip Enable High to Write Protect Low

EHWPL

t

Output (Status Register) Valid to V Low

QVVPL

PP

t

Output (Status Register) Valid to Write Protect Low Min

0

QVWPL

t

V

PP

High to Chip Enable High

Min

200

VPHEH

VPS

t

Write Protect High to Chip Enable High

WPHEH

Note: 1. Sampled only, not 100% tested.

2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

WHEL

software No-Op instruction to delay the first read in the same bank after issuing a command. If the read operation is in a different

bank t is 0ns.

WHEL

45/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 16. Reset and Power-up AC Waveforms

tPLWL

tPLEL

tPLGL

tPLLL

L

W, E, G,

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI90013c

Table 24. Reset and Power-up AC Characteristics

Symbol

Parameter

Test Condition

During Program

85

10

20

100

10

120

10

Unit

µs

Reset Low to

Min

t

PLWL

Write Enable Low,

Chip Enable Low,

Output Enable Low,

Latch Enable Low

t

PLEL

During Erase

Min

20

µs

t

PLGL

t

Other Conditions

80

50

80

50

80

50

ns

PLLL

(1,2)

(3)

RP Pulse Width

Min

t

PLPH

Supply Voltages High to Reset

High

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 50ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

46/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

PACKAGE MECHANICAL

Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

SD

FE

E

E1

BALL "A1"

A

e

ddd

e

b

A2

A1

BGA-Z20

Note: Drawing is not to scale.

Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.400

Typ

Max

A

A1

A2

b

1.010

0.0398

0.0098

0.0472

0.0157

0.250

0.790

0.400

6.500

5.250

0.0311

0.0157

0.2559

0.2067

0.350

6.400

–

0.450

0.0138

0.2520

–

0.0177

D

6.600

0.2598

D1

ddd

E

–

0.100

0.0039

10.000

4.500

0.750

0.625

2.750

0.375

9.900

10.100

0.3937

0.1772

0.0295

0.0246

0.1083

0.0148

0.3898

0.3976

E1

e

–

FD

FE

SD

47/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

PART NUMBERING

Table 26. Ordering Information Scheme

Example:

M58CR064C

85 ZB

6

T

Device Type

M58

Architecture

C = Dual Bank, Burst Mode

Operating Voltage

R = V = 1.65V to 2.0V, V

= 1.65V to 3.3V

DD

DDQ

Device Function

064C = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot

064D = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot

064P = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot,

V

PP

protection feature disabled

064Q = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot,

protection feature disabled

V

PP

Speed

85 = 85 ns

100 = 100 ns

120 = 120 ns

Package

ZB = TFBGA56: 6.5 x 10mm, 0.75 mm pitch

Temperature Range

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc....) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

48/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

REVISION HISTORY

Table 27. Document Revision History

Date

Version

-01

Revision Details

November 2000

12/20/00

First Issue

-02

Protection/Security clarification

Memory Map diagram clarification (Figure 4)

Single Synchronous Read clarification (Figure 6)

Identifier Codes clarification (Table 6)

X-Latency configuration clarification

CFI Query Identification String change (Table 31)

Synchronous Burst Read Waveforms change (Figure 12)

Reset AC Characteristics clarification (Table 24)

Program Time clarification (Table )

1/08/01

3/02/01

-03

-04

Reset AC Characteristics clarification (Table 24)

Reset AC Waveforms diagram change (Figure 1)

Document type: from Target Specification to Product Preview

Read Status Register clarification

Read Electronic Signature clarification

Protection Register Program clarification

Write Configuration Register clarification

Wait Configuration Sequence change (Figure 7)

CFI Query System Interface clarification (Table 32)

CFI Device Geometry change (Table 33)

Asynchronous Read AC Waveforms change (Figure 10)

Page Read AC Waveforms added (Figure 11)

Write AC Waveforms W Contr. and E Contr. change (Figure 14, 15)

Reset and Power-up AC Characteristics and Waveform change (Table 24, Figure 1)

TFBGA Package Mechanical Data and Outline added (Table 25, Figure 17)

4/05/01

-05

TFBGA Connections change

X-Latency Configuration Sequence change

Reset and Power-up AC Characteristics clarification

V

clarification

DDQ

23-Jul-2001

23-Oct-2001

15-Mar-2002

-06

-07

-08

Complete rewrite and restructure

85ns speed class added, document classified as Preliminary Data

Part numbers M58CR064P/Q added. CFI information clarified: Table 31,data

modified at Offset 13h. Table 32, data modified at Offsets 20h, 23h, 24h and 25h.

Table 35, Offset addresses modified. DC Characteristics table modified, Program,

Erase Times and Program, Erase Endurance Cycles table modified.

23-May-2002

27-Aug-2002

-09

9.1

Document changed to new structure

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot.

(revision version 09 equals 9.0).

Document status changed from Preliminary Data to Datasheet.

Minimum V

and V

supply voltages for 85ns speed class changed to 1.8V in

DD

DDQ

Table16, Operating and AC Measurement Conditions.

49/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

APPENDIX A. BLOCK ADDRESS TABLES

Table 28. Top Boot Block Addresses,

39

32

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

M58CR064C, M58CR064P

Size

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

Bank

#

Address Range

(KWord)

0

4

3FF000-3FFFFF

3FE000-3FEFFF

3FD000-3FDFFF

3FC000-3FCFFF

3FB000-3FBFFF

3FA000-3FAFFF

3F9000-3F9FFF

3F8000-3F8FFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

50/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

79

80

32

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

32

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

51/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 29. Bottom Boot Block Addresses,

M58CR064D, M58CR064Q

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

32

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

Size

Bank

#

Address Range

(KWord)

32

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

3F8000-3FFFFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

98

97

96

95

52/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

32

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32

4

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

007000-007FFF

006000-006FFF

005000-005FFF

004000-004FFF

003000-003FFF

002000-002FFF

001000-001FFF

000000-000FFF

8

7

6

4

5

4

3

4

2

4

1

4

0

4

53/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

APPENDIX B. COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

32, 33, 34 and 35 show the addresses used to re-

trieve the data. The Query data is always present-

ed on the lowest order data outputs (DQ0-DQ7),

the other outputs (DQ8-DQ15) are set to 0.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table , Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

Array command to return to Read mode.

When the Read CFI Query Command is issued

the device enters CFI Query mode and the data

structure is read from the memory. Tables 30, 31,

Table 30. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Lock Protection Register

Unique device Number and

User Programmable OTP

80h

Security Code Area

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 31, 32, 33, 34 and 35. Query data is always presented on the lowest order data outputs.

Table 31. CFI Query Identification String

Offset

Sub-section Name

Description

Value

00h

0020h

Manufacturer Code

ST

88CAh

88CBh

8801h

8802h

Top

Bottom

01h

Device Code (M58CR064C/D/P/Q)

02h

03h

reserved

0051h

Reserved

04h-0Fh

10h

"Q"

"R"

"Y"

11h

0052h

Query Unique ASCII String "QRY"

12h

0059h

13h

0003h

Primary Algorithm Command Set and Control Interface ID code 16

bit ID code defining a specific algorithm

14h

0000h

15h

offset = P = 0039h

0000h

Address for Primary Algorithm extended Query table (see Table 33)

p = 39h

NA

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported

18h

0000h

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Offset

19h

Sub-section Name

value = A = 0000h

0000h

Description

Value

Address for Alternate Algorithm extended Query table

NA

1Ah

Table 32. CFI Query System Interface Information

Offset

Data

Description

Value

V

DD

V

DD

V

PP

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

1.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0020h

0017h

00C0h

2.0V

1.7V

12V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0003h

000Ah

0000h

0003h

0004h

0002h

0000h

16µs

8µs

Typical time-out per single byte/word program = 2 µs

n

Typical time-out for quadruple word program = 2 µs

n

1s

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

128µs

4s

Maximum time-out for word program = 2 times typical

n

Maximum time-out for quadruple word = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

Table 33. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0017h

8 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0003h

0000h

n

8 Byte

2

Maximum number of bytes in multi-byte program or page = 2

2Ch

0002h

Number of identical sized erase block regions within the device

bit 7 to 0 = x = number of Erase Block Regions

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Offset Word

Data

Description

Value

127

Mode

2Dh

2Eh

007Eh

0000h

Region 1 Information

Number of identical-size erase blocks = 007Eh+1

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

64 KByte

8

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase blocks = 000Eh+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

NA

35h

38h

0000h

Reserved for future erase block region information

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

8

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

127

31h

32h

007Eh

0000h

Region 2 Information

Number of identical-size erase block = 007Eh+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

NA

35h

38h

0000h

Reserved for future erase block region information

Table 34. Primary Algorithm-Specific Extended Query Table

Offset

Data

0050h

0052h

0049h

0031h

0030h

00E6h

0003h

0000h

Description

Value

"P"

"R"

"I"

(P)h = 39h

Primary Algorithm extended Query table unique ASCII string “PRI”

(P+3)h = 3Ch

(P+4)h = 3Dh

(P+5)h = 3Eh

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

Chip Erase supported

(1 = Yes, 0 = No)

No

Yes

No

(P+7)h = 40h

(P+8)h = 41h

Erase Suspend supported

Program Suspend supported

Legacy Lock/Unlock supported

Queued Erase supported

Instant individual block locking supported (1 = Yes, 0 = No)

Protection bits supported

Page mode read supported

Synchronous read supported

Simultaneous operation supported

No

Yes

(1 = Yes, 0 = No)

bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31

bit field of optional features follows at the end of the bit-30

field.

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Offset

Data

Description

Supported Functions after Suspend

Value

(P+9)h = 42h

0001h

Read Array, Read Status Register and CFI Query

Yes

bit 0

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

bit 7 to 1

(P+A)h = 43h

(P+B)h = 44h

0003h

0000h

Block Protect Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block protect Status Register Lock/Unlock

bit active

(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

V

Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

DD

(P+C)h = 45h

(P+D)h = 46h

0018h

1.8V

12V

Supply Optimum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

PP

00C0h

0000h

(P+E)h = 47h

(P+F)h = 48h

(P+10)h = 49h

(P+11)h = 4Ah

(P+12)h = 4Bh

Reserved

Table 35. Burst Read Information

Data

Description

Value

Offset

(P+13)h = 4Ch

0003h

Page-mode read capability

8 Bytes

n

bits 0-7

’n’ such that 2 HEX value represents the number of read-

page bytes. See offset 28h for device word width to

determine page-mode data output width.

(P+14)h = 4Dh

(P+15)h = 4Eh

0003h

0001h

Number of synchronous mode read configuration fields that follow.

Synchronous mode read capability configuration 1

3

4

bit 3-7

Reserved

n+1

bit 0-2

’n’ such that 2

HEX value represents the maximum

number of continuous synchronous reads when the device is

configured for its maximum word width. A value of 07h

indicates that the device is capable of continuous linear bursts

that will output data until the internal burst counter reaches

the end of the device’s burstable address space. This field’s

3-bit value can be written directly to the read configuration

register bit 0-2 if the device is configured for its maximum

word width. See offset 28h for word width to determine the

burst data output width.

(P+16)h = 4Fh

(P+17)h = 50h

(P+18)h = 51h

(P+19)h = 52h

0002h

0007h

0036h

0001h

Synchronous mode read capability configuration 2

Synchronous mode read capability configuration 3

Max operating clock frequency (MHz)

8

Cont.

54 MHz

Supported handshaking signal (WAIT pin)

bit 0 during synchronous read (1 = Yes, 0 = No)

bit 1 during asynchronous read (1 = Yes, 0 = No)

Yes

No

57/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 18. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

Write 40h or 10h

writeToFlash (bank_address, 0x40) ;

/*or writeToFlash (bank_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

SR3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

SR4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06170

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 19. Double Word Program Flowchart and Pseudo code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (bank_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

SR7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

SR3 = 0

YES

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

Program

SR4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06171

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

59/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 20. Quadruple Word Program Flowchart and Pseudo Code

Start

quadruple_word_program_command (addressToProgram1, dataToProgram1,

Write 55h

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

Write Address 1

& Data 1 (3)

writeToFlash (bank_address, 0x55) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 2

& Data 2 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

Write Address 3

& Data 3 (3)

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

Write Address 4

& Data 4 (3)

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

SR7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

SR3 = 0

YES

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

Program

SR4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.SR==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06172

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 21. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

program has already completed */

Write 70h

do {

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

SR2 = 1

YES

Program Complete

if (status_register.SR2==0) /*program completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI06173

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 22. Block Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (bank_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

YES

NO

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

SR3 = 0

YES

if ( (status_register.SR4==1) && (status_register.SR5==1) )

/* command sequence error */

Command

Sequence Error (1)

SR4, SR5 = 1

NO

error_handler ( ) ;

if ( (status_register.SR5==1) )

/* erase error */

SR5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06174

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

62/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

writeToFlash (bank_address, 0xB0) ;

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

erase has already completed */

Write 70h

do {

Read Status

Register

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

NO

} while (status_register.SR7== 0) ;

SR7 = 1

YES

if (status_register.SR6==0) /*erase completed */

{ writeToFlash (bank_address, 0xFF) ;

SR6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (bank_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (bank_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI06175

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 24. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

Write 60h

writeToFlash (bank_address, 0x60) ; /*configuration setup*/

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (bank_address, 0x90) ;

Write 90h

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (bank_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI06176

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M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Figure 25. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (bank_address, 0xC0) ;

Write C0h

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

SR3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

SR4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06177

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

65/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

APPENDIX D. COMMAND INTERFACE STATE TABLES

Table 36. Command Interface States - Lock table

Current State of the

Current Bank

Command Input to the Current Bank (and Next State of the Current Bank)

Erase

Confirm

P/E

Resume

Unlock

Confirm

(D0h)

Current

State of

Other

Block Lock

Unlock

Lock-Down

setup

Set CR

setup (60h)

Block

Lock-

Down

Confirm

(2Fh)

Read

Status

Register

(70h)

Clear

Status

Register Signature

(50h)

Read

Electronic

Read

Array

(FFH)

Read

CFI Query

(98h)

Block lock

Confirm

(01h)

Set CR

Confirm

(03h)

Mode

State

Others

Bank

(90h)

Array

CFI

Block Lock,

Unlock,

SEE

Read

Elect.

Sign.

Any State

Read

MODIFY Read Array Read Array Status ReadArray

TABLE

Read CFI Lock-Down, Read Array Read Array Read Array

Electronic

Signature

Register

Set CR

Setup

Status

Setup

Error

Block Lock Block lock

Unlock

Lock-Down Lock-Down

Error, Set Error, Set

CR Error CR Error

Block Lock Block Lock Block Lock Block Lock Block Lock

Block Lock

Unlock

Lock-Down

Block

Block Lock Block Lock

Unlock Unlock

Lock-Down Lock-Down

Block Block

Unlock

Lock-Down Lock-Down Lock-Down Lock-Down Lock-Down

Error, Set Error, Set Error, Set Error, Set Error, Set

Set CR

Lock

Unlock

Lock-Down

CR

CR Error CR Error CR Error CR Error

CR Error

Any State

Block LocK

Unlock

Lock

Unlock

Lock-Down

Block

SEE

Read

Elect.

Sign.

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Register

Setup, Set

CR Setup

Set CR

Block LocK

SEE

Read

Elect.

Sign.

Unlock

Protection

Register

Any State

Done

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Register

Setup, Set

CR Setup

Block LocK

Unlock

Program-

Double/

Quadruple

Program

SEE

Read

Elect.

Sign.

Done

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Register

Setup, Set

CR Setup

Setup

Idle

Read

Array, CFI,

Elect.

Sign.,

Status

SEE

MODIFY

TABLE

PS Read

Status

Register

PS Read

Elect.

Sign.

Program

Suspend

PS Read Program

PS Read

Array

PS Read

CFI

PS Read

Array

PS Read PS Read PS Read

Array

(Busy)

Array

Erase

Suspend

Erase

Error

Erase

Error

Erase

(Busy)

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Idle

Setup

Error

Erase Error

Block/

Bank

Erase

Block LocK

Unlock

SEE

Read

Elect.

Sign.

Any State

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Done

Register

Setup, Set

CR Setup

Erase

(Busy)

Setup

Busy

Idle

Read

Array, CFI,

Elect.

Sign.,

Status

Block LocK

Unlock

Lock-Down

Setup, Set

CR Setup

ES Read

Array

SEE

MODIFY

TABLE

ES Read

Status

Register

ES Read

Elect.

Sign.

Erase

Suspend

ES Read

Array

ES Read

Array

ES Read

CFI

ES Read ES Read ES Read

Array Array Array

Erase

(Busy)

Program

Suspend

ES Read

Array

Note: PS = Program Suspend, ES = Erase Suspend.

66/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Table 37. Command Interface States - Modify Table

Current State of the Current

Bank

Command Input to the Current Bank (and Next State of the Current Bank)

Current State

of the Other

Bank

Protection

Register

Double/

Quadruple

Program Setup Block Erase Program-Erase

Bank Erase

Setup (80h)

Mode

State

Others

(10h/40h)

Setup (20h) Suspend (B0h) ProgramSetup ProgramSetup

(C0h)

(30h/55h)

Setup

Busy

Read Array

Array, CFI,

Electronic

Signature,

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

SEE LOCK

TABLE

Read

Read Array

Program setup

Erase Suspend

Status Register

Read Array

Program

Suspend

Read Array

Setup

Busy

Read Array

Error,

Lock Unlock

Lock-Down

Block,

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

Lock Unlock

Lock-Down CR

SEE LOCK

TABLE

Read Array

Protection

Program setup

Erase Suspend

Set CR

Read Array

Program

Suspend

Read Array

Protection

Read Array

Protection

Idle

Setup

Busy

Setup

Busy

Protection

Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy)

Read Array

Protection

Register

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

SEE LOCK

TABLE

Program Setup

Done

Read Array

Erase Suspend

Read Array

Program

Suspend

Read Array

Any State

Setup

Busy

Program(Busy)

Program(Busy) Program(Busy) Program(Busy)

Program(Busy) Program (Busy) Program (Busy)

PS Read Status

Register

Idle

Setup

Busy

Program

Double/

Quadruple

Word Program

Read Array

Program Setup

Read Array

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

SEE LOCK

TABLE

Done

Read Array

Erase Suspend

Read Array

Program

Suspend

Read Array

Setup

Idle

Read Array,

CFI, Elect.

Sign., Status

Register

Program

Suspend

SEE LOCK

TABLE

PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array

Erase Suspend

SEE LOCK

TABLE

Setup

Busy

Erase Error

Block/ Bank

Erase

Idle

ES Read Status

Register

Erase (Busy)

Setup

Busy

ES Read Array

Program Setup

ES Read Array

Read Array,

CFI, Elect.

Sign., Status

Register

Double/

Quadruple

Program Setup

SEE LOCK

TABLE

Erase Suspend

ES Read Array ES Read Array ES Read Array

ES Read Array

Idle

Program

Suspend

ES Read Array

Note: PS = Program Suspend, ES = Erase Suspend.

67/68

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

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68/68


型号：	M58CR064D120ZB6
厂家：	ST
描述：	4MX16 FLASH 1.8V PROM, 18ns, PBGA56, 6.50 X 10 MM, 0.75 MM PITCH, TFBGA-56 可编程只读存储器内存集成电路闪存
文件：	总68页 (文件大小：476K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58CR064D120ZB6 [STMICROELECTRONICS]

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