M58LR128FB_技术文档

M58LR128FT

M58LR128FB

128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)

1.8V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Package

–

V_DD= 1.7V to 2.0V for program, erase and

read

–

V_DDQ= 1.7V to 2.0V for I/O Buffers

V_PP= 9V for fast program (12V tolerant)

■

SYNCHRONOUS / ASYNCHRONOUS READ

FBGA

–

Synchronous Burst Read mode: 54MHz

Asynchronous Page Read mode

Random Access: 85, 95ns

■

SYNCHRONOUS BURST READ SUSPEND

PROGRAMMING TIME

–

10µs typical Word program time using

Buffer Program

VFBGA56 (ZB)

7.7 x 9mm

■

MEMORY ORGANIZATION

–

Multiple Bank Memory Array: 8 Mbit

Banks

–

Parameter Blocks (Top or Bottom

location)

DUAL OPERATIONS

■

ELECTRONIC SIGNATURE

–

program/erase in one Bank while read in

others

–

Manufacturer Code: 20h

Top Device Code: 88C4h.

Bottom Device Code: 88C5h

–

No delay between read and write

operations

BLOCK LOCKING

–

All blocks locked at power-up

Any combination of blocks can be locked

with zero latency

–

WP for Block Lock-Down

Absolute Write Protection with V_PP= V_SS

■

SECURITY

–

64 bit unique device number

2112 bit user programmable OTP Cells

■

COMMON FLASH INTERFACE (CFI)

100,000 PROGRAM/ERASE CYCLES per

BLOCK

September 2004

1/82

M58LR128FT, M58LR128FB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. VFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V

_DDSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

_DDQSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V_PPProgram Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V

V_SSQGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2/82

M58LR128FT, M58LR128FB

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Buffer Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Buffer Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Protection Register Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program/Erase Controller Status Bit (SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

V

_PPStatus Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Output Configuration Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3/82

M58LR128FT, M58LR128FB

READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Synchronous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 12. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 15. Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 17. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 18. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 20. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 22. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 24. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 25. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4/82

M58LR128FT, M58LR128FB

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19.VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Bottom View Package Outline. . . . 52

Table 26. VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Package Mechanical Data. . . . . . . 52

Figure 20.VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 53

Figure 21.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . . 54

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 28. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 29. Top Boot Block Addresses, M58LR128FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 30. Bottom Boot Block Addresses, M58LR128FB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 31. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 32. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 33. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 35. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 36. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 37. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 38. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 39. Bank and Erase Block Region 1 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 40. Bank and Erase Block Region 2 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 23.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 24.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 70

Figure 25.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 26.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 27.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 28.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 74

Figure 29.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . 75

APPENDIX D.COMMAND INTERFACE STATE TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 41. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 42. Command Interface States - Modify Table, Next Output State . . . . . . . . . . . . . . . . . . . . 78

Table 43. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 44. Command Interface States - Lock Table, Next Output State. . . . . . . . . . . . . . . . . . . . . . 80

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 45. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5/82

M58LR128FT, M58LR128FB

SUMMARY DESCRIPTION

The M58LR128FT/B is a 128 Mbit (8Mbit x16)

non-volatile Flash memory that may be erased

electrically at block level and programmed in-sys-

tem on a Word-by-Word basis using a 1.7V to 2.0V

V_DDsupply for the circuitry and a 1.7V to 2.0V

control the memory is consistent with JEDEC stan-

dards.

The device supports Synchronous Burst Read and

Asynchronous Read from all blocks of the memory

array; at power-up the device is configured for

Asynchronous Read. In Synchronous Burst Read

mode, data is output on each clock cycle at fre-

quencies of up to 54MHz. The Synchronous Burst

Read operation can be suspended and resumed.

The device features an Automatic Standby mode.

When the bus is inactive during Asynchronous

Read operations, the device automatically switch-

es to the Automatic Standby mode. In this condi-

tion the power consumption is reduced to the

standby value and the outputs are still driven.

The M58LR128FT/B features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When V_PP≤ V_PPLKall blocks are protected against

program or erase. All blocks are locked at power-

up.

V_DDQsupply for the Input/Output pins. An optional

9V V_PPpower supply is provided to speed up fac-

tory programming.

The device features an asymmetrical block archi-

tecture and is based on a multi-level cell technolo-

gy. M58LR128FT/B has an array of 131 blocks,

and is divided into 8 Mbit banks. There are 15

banks each containing 8 main blocks of 64

KWords, and one parameter bank containing 4 pa-

rameter blocks of 16 KWords and 7 main blocks of

64 KWords. The Multiple Bank Architecture allows

Dual Operations, while programming or erasing in

one bank, read operations are possible in other

banks. Only one bank at a time is allowed to be in

program or erase mode. It is possible to perform

burst reads that cross bank boundaries. The bank

architecture is summarized in Table 2., and the

memory maps are shown in Figure 4. The Param-

eter Blocks are located at the top of the memory

address space for the M58LR128FT, and at the

bottom for the M58LR128FB.

Each block can be erased separately. Erase can

be suspended, in order to perform program in any

other block, and then resumed. Program can be

suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles using the supply

voltage V_DD. There is a Buffer Enhanced Factory

programming command available to speed up pro-

gramming.

Program and erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

The device includes 17 Protection Registers and 2

Protection Register locks, one for the first Protec-

tion Register and the other for the 16 One-Time-

Programmable (OTP) Protection Registers of 128

bits each. The first Protection Register is divided

into two segments: a 64 bit segment containing a

unique device number written by ST, and a 64 bit

segment One-Time-Programmable (OTP) by the

user. The user programmable segment can be

permanently protected. Figure 5., shows the Pro-

tection Register Memory Map.

The memory is available in a VFBGA56, 7.7x9mm,

0.75 pitch package and is supplied with all the bits

erased (set to ’1’).

6/82

M58LR128FT, M58LR128FB

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A22

Address Inputs

Data Input/Outputs, Command

Inputs

DQ0-DQ15

V

DD DDQ PP

E

Chip Enable

Output Enable

Write Enable

Reset

G

23

16

A0-A22

DQ0-DQ15

WAIT

W

RP

WP

K

W

E

Write Protect

Clock

M58LR128FT

M58LR128FB

G

L

Latch Enable

Wait

RP

WP

L

WAIT

V

Supply Voltage

DD

Supply Voltage for Input/Output

Buffers

K

V

DDQ

PP

Optional Supply Voltage for

Fast Program & Erase

V

SSQ

SS

V

Ground

AI08335

SS

Ground Input/Output Supply

Not Connected Internally

Do Not Use

SSQ

NC

DU

7/82

M58LR128FT, M58LR128FB

Figure 3. VFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A11

A12

A13

A15

A8

A9

V

A18

A17

A19

WP

A6

A5

A4

A3

A2

A1

A0

G

SS

DD

K

PP

A20

A21

RP

W

A10

L

A7

A14

WAIT

DQ6

DQ13

DQ5

A16

DQ4

DQ12

DQ2

DQ10

DQ3

A22

E

V

DQ15

DQ14

DQ1

DQ9

DDQ

V

DQ11

DQ0

DQ8

SS

G

DQ7

V

SSQ

DD

DDQ

AI07562

Table 2. Bank Architecture

Number

Bank Size

8 Mbits

Parameter Blocks

Main Blocks

Parameter Bank

4 blocks of 16 KWords

7 blocks of 64 KWords

8 blocks of 64 KWords

Bank 1

Bank 2

Bank 3

-

Bank 14

Bank 15

8 Mbits

-

8 blocks of 64 KWords

8/82

M58LR128FT, M58LR128FB

Figure 4. Memory Map

M58LR128FT - Top Boot Block

M58LR128FB - Bottom Boot Block

Address lines A22-A0

000000h

00FFFFh

000000h

003FFFh

64 KWord

16 KWord

8 Main

Blocks

4 Parameter

Blocks

Bank 15

070000h

07FFFFh

00C000h

00FFFFh

010000h

01FFFFh

64 KWord

16 KWord

64 KWord

Parameter

Bank

7 Main

Blocks

070000h

07FFFFh

080000h

08FFFFh

64 KWord

600000h

60FFFFh

64 KWord

8 Main

Blocks

8 Main

Blocks

Bank 3

Bank 2

Bank 1

Bank 2

Bank 3

670000h

67FFFFh

680000h

68FFFFh

0F0000h

0FFFFFh

100000h

10FFFFh

64 KWord

8 Main

Blocks

8 Main

Blocks

6F0000h

6FFFFFh

700000h

70FFFFh

170000h

17FFFFh

180000h

18FFFFh

64 KWord

8 Main

Blocks

8 Main

Blocks

770000h

77FFFFh

780000h

78FFFFh

1F0000h

1FFFFFh

64 KWord

7 Main

Blocks

7E0000h

7EFFFFh

7F0000h

7F3FFFh

64 KWord

16 KWord

Parameter

Bank

780000h

78FFFFh

64 KWord

4 Parameter

Blocks

8 Main

Blocks

Bank 15

7FC000h

7FFFFFh

7F0000h

7FFFFFh

16 KWord

AI08336

9/82

M58LR128FT, M58LR128FB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A22). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Bus Write

operation.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at V_ILand Reset is at V_IHthe device is in active

mode. When Chip Enable is at V_IHthe memory is

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

latch is transparent when Latch Enable is at

V_ILand it is inhibited when Latch Enable is at

V_IH. Latch Enable can be kept Low (also at

board level) when the Latch Enable function

is not required or supported.

Clock (K). The clock input synchronizes the

memory to the microcontroller during synchronous

read operations; the address is latched on a Clock

edge (rising or falling, according to the configura-

tion settings) when Latch Enable is at V_IL. Clock is

ignored during asynchronous read and in write op-

erations.

Wait (WAIT). Wait is an output signal used during

synchronous read to indicate whether the data on

the output bus are valid. This output is high imped-

ance when Chip Enable is at V_IH, Output Enable is

at V_IH, or Reset is at V_IL. It can be configured to be

active during the wait cycle or one clock cycle in

advance.

V

_DDSupply Voltage . V_DDprovides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

V_DDQSupply Voltage. V_DDQprovides the power

supply to the I/O pins and enables all Outputs to

be powered independently from V_DD. V_DDQcan be

tied to V_DDor can use a separate supply.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable or Write Enable

whichever occurs first.

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

each block. When Write Protect is at V_IL, the Lock-

Down is enabled and the protection status of the

Locked-Down blocks cannot be changed. When

Write Protect is at V_IH, the Lock-Down is disabled

and the Locked-Down blocks can be locked or un-

locked. (refer to Table 14., Lock Status).

Reset (RP). The Reset input provides a hard-

ware reset of the memory. When Reset is at V_IL,

the memory is in reset mode: the outputs are high

impedance and the current consumption is re-

duced to the Reset Supply Current I_DD2. Refer to

Table 19., DC Characteristics - Currents, for the

value of I_DD2.After Reset all blocks are in the

Locked state and the Configuration Register is re-

set. When Reset is at V_IH, the device is in normal

operation. Exiting reset mode the device enters

asynchronous read mode, but a negative transi-

tion of Chip Enable or Latch Enable is required to

ensure valid data outputs.

V_PPProgram Supply Voltage. V_PPis both a

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin.

If V_PPis kept in a low voltage range (0V to V_DDQ

)

V_PPis seen as a control input. In this case a volt-

age lower than V_PPLKgives an absolute protection

against program or erase, while V_PP> V_PP1en-

ables these functions (see Tables 19 and 20, DC

Characteristics for the relevant values). V_PPis only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

If V_PPis in the range of V_PPHit acts as a power

supply pin. In this condition V_PPmust be stable un-

til the Program/Erase algorithm is completed.

V_SSGround. V_SSground is the reference for the

core supply. It must be connected to the system

ground.

V_SSQGround. V_SSQground is the reference for

the input/output circuitry driven by V_DDQ. V_SSQ

must be connected to V_SS

The Reset pin can be interfaced with 3V logic with-

out any additional circuitry. It can be tied to V_RPH

(refer to Table 20., DC Characteristics - Voltages).

Latch Enable (L). Latch Enable latches the ad-

dress bits on its rising edge. The address

Note: Each device in a system should have

V

_DD, V_DDQand V_PPdecoupled with a 0.1µF ce-

ramic capacitor close to the pin (high frequen-

cy, inherently low inductance capacitors

10/82

M58LR128FT, M58LR128FB

should be as close as possible to the pack-

age). See Figure 9., AC Measurement Load Cir-

cuit. The PCB trace widths should be sufficient

to carry the required V_PPprogram and erase

currents.

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Ad-

dress Latch, Output Disable, Standby and Reset.

See Table 3., Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect Bus Write operations.

the Latch Enable should be tied to V_IHduring the

bus write operation.

See Figures 16 and 17, Write AC Waveforms, and

Tables 23 and 24, Write AC Characteristics, for

details of the timing requirements.

Address Latch. Address latch operations input

valid addresses. Both Chip enable and Latch En-

able must be at V_ILduring address latch opera-

tions. The addresses are latched on the rising

edge of Latch Enable.

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature, the Status Register and the

Common Flash Interface. Both Chip Enable and

Output Enable must be at V_ILin order to perform a

read operation. The Chip Enable input should be

used to enable the device. Output Enable should

be used to gate data onto the output. The data

read depends on the previous command written to

the memory (see Command Interface section).

See Figures 10, 11, 12 and 13 Read AC Wave-

forms, and Tables 21 and 22 Read AC Character-

istics, for details of when the output becomes

valid.

Bus Write. Bus Write operations write Com-

mands to the memory or latch Input Data to be

programmed. A bus write operation is initiated

when Chip Enable and Write Enable are at V_ILwith

Output Enable at V_IH. Commands, Input Data and

Addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The

addresses can also be latched prior to the write

operation by toggling Latch Enable. In this case

Output Disable. The outputs are high imped-

ance when the Output Enable is at V_IH.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in standby when

Chip Enable and Reset are at V_IH. The power con-

sumption is reduced to the standby level I_DD4and

the outputs are set to high impedance, indepen-

dently from the Output Enable or Write Enable in-

puts. If Chip Enable switches to V_IHduring a

program or erase operation, the device enters

Standby mode when finished.

Reset. During Reset mode the memory is dese-

lected and the outputs are high impedance. The

memory is in Reset mode when Reset is at V_IL.

The power consumption is reduced to the Standby

level, independently from the Chip Enable, Output

Enable or Write Enable inputs. If Reset is pulled to

V_SSduring a Program or Erase, this operation is

aborted and the memory content is no longer valid.

Table 3. Bus Operations

(4)

Operation

Bus Read

E

G

W

L

RP

DQ15-DQ0

Data Output

Data Input

WAIT

(2)

V

IL

IH

V

IH

IL

(2)

V

Bus Write

IH

IL

IH

IL

(3)

V

Address Latch

Output Disable

Standby

X

IL

IH

IL

IH

Data Output or Hi-Z

V

X

Hi-Z

IH

V

X

IH

V

IL

Reset

X

Note: 1. X = Don't care.

2. L can be tied to V if the valid address has been previously latched.

IH

3. Depends on G.

4. WAIT signal polarity is configured using the Set Configuration Register command.

11/82

M58LR128FT, M58LR128FB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the program and erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time to monitor

the progress or the result of the operation.

The Command Interface is reset to read mode

when power is first applied, when exiting from Re-

set or whenever V_DDis lower than V_LKO. Com-

mand sequences must be followed exactly. Any

invalid combination of commands will be ignored.

Refer to Table 4., Command Codes, Table

5., Standard Commands, and Table 6., Factory

Program Command, for a summary of the Com-

mand Interface.

Read Array Command

The Read Array command returns the addressed

bank to Read Array mode.

One Bus Write cycle is required to issue the Read

Array command. Once a bank is in Read Array

mode, subsequent read operations will output the

data from the memory array.

A Read Array command can be issued to any

banks while programming or erasing in another

bank.

If the Read Array command is issued to a bank

currently executing a program or erase operation,

the bank will return to Read Array mode but the

program or erase operation will continue, however

the data output from the bank is not guaranteed

until the program or erase operation has finished.

The read modes of other banks are not affected.

Read Status Register Command

The device contains a Status Register that is used

to monitor program or erase operations.

The Read Status Register command is used to

read the contents of the Status Register for the ad-

dressed bank.

One Bus Write cycle is required to issue the Read

Status Register command. Once a bank is in Read

Status Register mode, subsequent read opera-

tions will output the contents of the Status Regis-

ter.

The Status Register data is latched on the falling

edge of the Chip Enable or Output Enable signals.

Either Chip Enable or Output Enable must be tog-

gled to update the Status Register data

The Read Status Register command can be is-

sued at any time, even during program or erase

operations. The Read Status Register command

will only change the read mode of the addressed

bank. The read modes of other banks are not af-

fected. Only Asynchronous Read and Single Syn-

chronous Read operations should be used to read

the Status Register. A Read Array command is re-

quired to return the bank to Read Array mode.

Table 4. Command Codes

Hex Code

01h

Command

Block Lock Confirm

03h

Set Configuration Register Confirm

Alternative Program Setup

Block Erase Setup

10h

20h

2Fh

Block Lock-Down Confirm

Program Setup

40h

50h

Clear Status Register

Block Lock Setup, Block Unlock Setup,

Block Lock Down Setup and Set

Configuration Register Setup

60h

70h

80h

90h

98h

B0h

C0h

Read Status Register

Buffer Enhanced Factory Program

Read Electronic Signature

Read CFI Query

Program/Erase Suspend

Protection Register Program

See Table 9. for the description of the Status Reg-

ister Bits.

Read Electronic Signature Command

Program/Erase Resume, Block Erase

Confirm, Block Unlock Confirm or Buffer

Program Confirm

The Read Electronic Signature command is used

to read the Manufacturer and Device Codes, the

Lock Status of the addressed bank, the Protection

Register, and the Configuration Register.

One Bus Write cycle is required to issue the Read

Electronic Signature command. Once a bank is in

Read Electronic Signature mode, subsequent

read operations in the same bank will output the

Manufacturer Code, the Device Code, the Lock

D0h

E8h

FFh

Buffer Program

Read Array

12/82

M58LR128FT, M58LR128FB

Status of the addressed bank, the Protection Reg-

ister, or the Configuration Register (see Table 7.).

The Read Electronic Signature command can be

issued at any time, even during program or erase

operations, except during Protection Register Pro-

gram operations.

The error bits in the Status Register do not auto-

matically return to ‘0’ when a new command is is-

sued. The error bits in the Status Register should

be cleared before attempting a new program or

erase command.

Block Erase Command

If a Read Electronic Signature command is issued

to a bank that is executing a program or erase op-

eration the bank will go into Read Electronic Sig-

nature mode. Subsequent Bus Read cycles will

output the Electronic Signature data and the Pro-

gram/Erase controller will continue to program or

erase in the background.

The Read Electronic Signature command will only

change the read mode of the addressed bank. The

read modes of other banks are not affected. Only

Asynchronous Read and Single Synchronous

Read operations should be used to read the Elec-

tronic Signature. A Read Array command is re-

quired to return the bank to Read Array mode.

Read CFI Query Command

The Read CFI Query command is used to read

data from the Common Flash Interface (CFI).

One Bus Write cycle is required to issue the Read

CFI Query command. Once a bank is in Read CFI

Query mode, subsequent Bus Read operations in

the same bank read from the Common Flash Inter-

face.

The Block Erase command is used to erase a

block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost.

If the block is protected then the erase operation

will abort, the data in the block will not be changed

and the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

■

The first bus cycle sets up the Block Erase

command.

■

The second latches the block address and

starts the Program/Erase Controller.

If the second bus cycle is not the Block Erase Con-

firm code, Status Register bits SR4 and SR5 are

set and the command is aborted.

Once the command is issued the bank enters

Read Status Register mode and any read opera-

tion within the addressed bank will output the con-

tents of the Status Register. A Read Array

command is required to return the bank to Read

Array mode.

During Block Erase operations the bank contain-

ing the block being erased will only accept the

Read Array, Read Status Register, Read Electron-

ic Signature, Read CFI Query and the Program/

Erase Suspend command, all other commands

will be ignored.

The Block Erase operation aborts if Reset, RP,

goes to V_IL. As data integrity cannot be guaran-

teed when the Block Erase operation is aborted,

the block must be erased again.

The Read CFI Query command can be issued at

any time, even during program or erase opera-

tions.

If a Read CFI Query command is issued to a bank

that is executing a program or erase operation the

bank will go into Read CFI Query mode. Subse-

quent Bus Read cycles will output the CFI data

and the Program/Erase controller will continue to

program or erase in the background.

The Read CFI Query command will only change

the read mode of the addressed bank. The read

modes of other banks are not affected. Only Asyn-

chronous Read and Single Synchronous Read op-

erations should be used to read from the CFI. A

Read Array command is required to return the

bank to Read Array mode.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being erased.

Typical Erase times are given in Table

15., Program, Erase Times and Endurance Cy-

cles.

See APPENDIX C., Figure 25., Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

for using the Block Erase command.

See APPENDIX B., COMMON FLASH INTER-

FACE, Tables 31, 32, 33, 34, 35, 37, 38, 39 and 40

for details on the information contained in the

Common Flash Interface memory area.

Program Command

Clear Status Register Command

The program command is used to program a sin-

gle Word to the memory array.

Two Bus Write cycles are required to issue the

Program Command.

The Clear Status Register command can be used

to reset (set to ‘0’) all error bits (SR1, 3, 4 and 5) in

the Status Register.

One Bus Write cycle is required to issue the Clear

Status Register command. The Clear Status Reg-

ister command does not change the read mode of

the addressed bank.

■

The first bus cycle sets up the Program

command.

13/82

M58LR128FT, M58LR128FB

■

The second latches the address and data to

be programmed and starts the Program/Erase

Controller.

Optimum performance is obtained when the

start address corresponds to a 32 Word

boundary. If the start address is not aligned to

a 32 word boundary, the total programming

time is doubled

Once the programming has started, read opera-

tions in the bank being programmed output the

Status Register content.

During a Program operation, the bank containing

the Word being programmed will only accept the

Read Array, Read Status Register, Read Electron-

ic Signature, Read CFI Query and the Program/

Erase Suspend command, all other commands

will be ignored. A Read Array command is re-

quired to return the bank to Read Array mode.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being programmed.

Typical Program times are given in Table

15., Program, Erase Times and Endurance Cy-

cles.

4. The final Bus Write cycle confirms the Buffer

Program command and starts the program

operation.

All the addresses used in the Buffer Program op-

eration must lie within the same block.

Invalid address combinations or failing to follow

the correct sequence of Bus Write cycles will set

an error in the Status Register and abort the oper-

ation without affecting the data in the memory ar-

ray.

If the Status Register bits SR4 and SR5 are set to

'1', the Buffer Program Command is not accepted.

Clear the Status Register before re-issuing the

command.

The Program operation aborts if Reset, RP, goes

to V_IL. As data integrity cannot be guaranteed

when the Program operation is aborted, the Word

must be reprogrammed.

If the block being programmed is protected an er-

ror will be set in the Status Register and the oper-

ation will abort without affecting the data in the

memory array.

See APPENDIX C., Figure 22., Program Flow-

chart and Pseudo Code, for the flowchart for using

the Program command.

During Buffer Program operations the bank being

programmed will only accept the Read Array,

Read Status Register, Read Electronic Signature,

Read CFI Query and the Program/Erase Suspend

command, all other commands will be ignored.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being programmed.

Buffer Program Command

The Buffer Program Command makes use of the

device’s 32-Word Write Buffer to speed up pro-

gramming. Up to 32 Words can be loaded into the

Write Buffer. The Buffer Program command dra-

matically reduces in-system programming time

compared to the standard non-buffered Program

command.

See Appendix C, figure 27, Buffer Program Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Buffer Program command.

Four successive steps are required to issue the

Buffer Program command.

1. The first Bus Write cycle sets up the Buffer

Program command. The setup code can be

addressed to any location within the targeted

block.

After the first Bus Write cycle, read operations in

the bank will output the contents of the Status

Register. Status Register bit SR7 should be read

to check that the buffer is available (SR7 = 1). If

the buffer is not available (SR7 = 0), re-issue the

Buffer Program command to update the Status

Register contents.

2. The second Bus Write cycle sets up the

number of Words to be programmed. Value n

is written to the same block address, where

n+1 is the number of Words to be

programmed.

Buffer Enhanced Factory Program Command

The Buffer Enhanced Factory Program command

has been specially developed to speed up pro-

gramming in manufacturing environments where

the programming time is critical.

It is used to program one or more Write Buffer(s)

of 32 Words to a block. Once the device enters

Buffer Enhanced Factory Program mode, the

Write Buffer can be reloaded any number of times

as long as the address remains within the same

block. Only one block can be programmed at a

time.

The use of the Buffer Enhanced Factory Program

command requires certain operating conditions:

■

V_PPmust be set to V_PPH

V_DDmust be within operating range

Ambient temperature, T_Amust be 25°C ± 5°C

The targeted block must be unlocked

The start address must be aligned with the

start of a 32 Word buffer boundary

3. Use n+1 Bus Write cycles to load the address

and data for each Word into the Write Buffer.

Addresses must lie within the range from the

start address to the start address + n.

14/82

M58LR128FT, M58LR128FB

■

The address must remain the Start Address

throughout programming.

3. Once the Write Buffer is full, the data is pro-

grammed sequentially to the memory array.

After the program operation the device auto-

matically verifies the data and reprograms if

necessary.

Dual operations are not supported during the Buff-

er Enhanced Factory Program operation and the

command cannot be suspended.

The Program and Verify phase can be repeated,

without re-issuing the command, to program addi-

tional 32 Word locations as long as the address re-

mains in the same block.

4. Finally, after all Words, or the entire block

have been programmed, write one Bus Write

operation to any address outside the block

containing the Start Address, to terminate

Program and Verify Phase.

Status Register bit SR0 must be checked to deter-

mine whether the program operation is finished.

The Status Register may be checked for errors at

any time but it must be checked after the entire

block has been programmed.

Exit Phase. Status Register P/E.C. bit SR7 set to

‘1’ indicates that the device has exited the Buffer

Enhanced Factory Program operation and re-

turned to Read Status Register mode. A full Status

Register check should be done to ensure that the

block has been successfully programmed. See the

section on the Status Register for more details.

For optimum performance the Buffer Enhanced

Factory Program command should be limited to a

maximum of 100 program/erase cycles per block.

If this limit is exceeded the internal algorithm will

continue to work properly but some degradation in

performance is possible. Typical program times

are given in Table 15..

See APPENDIX C., Figure 29., Buffer Enhanced

Factory Program Flowchart and Pseudo Code, for

a suggested flowchart on using the Buffer En-

hanced Factory Program command.

The Buffer Enhanced Factory Program Command

consists of three phases: the Setup Phase, the

Program and Verify Phase, and the Exit Phase,

Please refer to Table 7. Factory Program Com-

mands for detail information.

Refer to Table 6., Factory Program Command,

and Figure 29., Buffer Enhanced Factory Program

Flowchart and Pseudo Code.

Setup Phase. The Buffer Enhanced Factory Pro-

gram command requires two Bus Write cycles to

initiate the command.

■

The first Bus Write cycle sets up the Buffer

Enhanced Factory Program command.

■

The second Bus Write cycle confirms the

command.

After the confirm command is issued, read opera-

tions output the contents of the Status Register.

The read Status Register command must not be

issued as it will be interpreted as data to program.

The Status Register P/E.C. Bit SR7 should be

read to check that the P/E.C. is ready to proceed

to the next phase.

If an error is detected, SR4 goes high (set to ‘1’)

and the Buffer Enhanced Factory Program opera-

tion is terminated. See Status Register section for

details on the error.

Program and Verify Phase. The Program and

Verify Phase requires 32 cycles to program the 32

Words to the Write Buffer. The data is stored se-

quentially, starting at the first address of the Write

Buffer, until the Write Buffer is full (32 Words). To

program less than 32 Words, the remaining Words

should be programmed with FFFFh.

Three successive steps are required to issue and

execute the Program and Verify Phase of the com-

mand.

1. Use one Bus Write operation to latch the Start

Address and the first Word to be programmed.

The Status Register Bank Write Status bit SR0

should be read to check that the P/E.C. is

ready for the next Word.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Block Erase operation. The

command can be addressed to any bank.

The Program/Erase Resume command is re-

quired to restart the suspended operation.

One bus write cycle is required to issue the Pro-

gram/Erase Suspend command. Once the Pro-

gram/Erase Controller has paused bits SR7, SR6

and/ or SR2 of the Status Register will be set to ‘1’.

2. Each subsequent Word to be programmed is

latched with a new Bus Write operation. The

address must remain the Start Address as the

P/E.C. increments the address location.If any

address that is not in the same block as the

Start Address is given, the Program and Verify

Phase terminates. Status Register bit SR0

should be read between each Bus Write cycle

to check that the P/E.C. is ready for the next

Word.

The following commands are accepted during Pro-

gram/Erase Suspend:

–

Program/Erase Resume

Read Array (data from erase-suspended

block or program-suspended Word is not

valid)

–

Read Status Register

Read Electronic Signature

15/82

M58LR128FT, M58LR128FB

–

Read CFI Query.

See APPENDIX C., Figure 24., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 26., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Resume command.

Additionally, if the suspended operation was erase

then the following commands are also accepted:

–

Clear Status Register

Program (except in erase-suspended

block)

Block Lock

Block Lock-Down

Block Unlock.

Protection Register Program Command

The Protection Register Program command is

used to program the user One-Time-Programma-

ble (OTP) segments of the Protection Register and

the two Protection Register Locks.

–

The device features 16 OTP segments of 128 bits

and one OTP segment of 64 bits, as shown in Fig-

ure 5., Protection Register Memory Map.

The segments are programmed one Word at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

During an erase suspend the block being erased

can be protected by issuing the Block Lock or

Block Lock-Down commands. When the Program/

Erase Resume command is issued the operation

will complete.

It is possible to accumulate multiple suspend oper-

ations. For example: suspend an erase operation,

start a program operation, suspend the program

operation, then read the array.

If a Program command is issued during a Block

Erase Suspend, the erase operation cannot be re-

sumed until the program operation has completed.

The Program/Erase Suspend command does not

change the read mode of the banks. If the sus-

pended bank was in Read Status Register, Read

Electronic signature or Read CFI Query mode the

bank remains in that mode and outputs the corre-

sponding data.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed

during Program/Erase Suspend.

During a Program/Erase Suspend, the device can

be placed in standby mode by taking Chip Enable

to V_IH. Program/erase is aborted if Reset, RP,

goes to V_IL.

See APPENDIX C., Figure 24., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 26., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Suspend command.

Two Bus Write cycles are required to issue the

Protection Register Program command.

■

The first bus cycle sets up the Protection

Register Program command.

■

The second latches the address and data to

be programmed to the Protection Register and

starts the Program/Erase Controller.

Read operations to the bank being programmed

output the Status Register content after the pro-

gram operation has started.

Attempting to program a previously protected Pro-

tection Register will result in a Status Register er-

ror.

The Protection Register Program cannot be sus-

pended.

The two Protection Register Locks are used to

protect the OTP segments from further modifica-

tion. The protection of the OTP segments is not re-

versible. Refer to Figure 5., Protection Register

Memory Map, and Table 8., Protection Register

Locks, for details on the Lock bits.

See APPENDIX C., Figure 28., Protection Regis-

ter Program Flowchart and Pseudo Code, for a

flowchart for using the Protection Register Pro-

gram command.

Program/Erase Resume Command

The Program/Erase Resume command is used to

restart the program or erase operation suspended

by the Program/Erase Suspend command. One

Bus Write cycle is required to issue the command.

The command can be issued to any address.

The Program/Erase Resume command does not

change the read mode of the banks. If the sus-

pended bank was in Read Status Register, Read

Electronic signature or Read CFI Query mode the

bank remains in that mode and outputs the corre-

sponding data.

Set Configuration Register Command

The Set Configuration Register command is used

to write a new value to the Configuration Register.

Two Bus Write cycles are required to issue the Set

Configuration Register command.

■

The first cycle sets up the Set Configuration

Register command and the address

corresponding to the Configuration Register

content.

■

The second cycle writes the Configuration

Register data and the confirm command.

If a Program command is issued during a Block

Erase Suspend, then the erase cannot be re-

sumed until the program operation has completed.

The Configuration Register data must be written

as an address during the bus write cycles, that is

16/82

M58LR128FT, M58LR128FB

A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses

A16- A22 are ignored.

■

The second Bus Write cycle latches the block

address and unlocks the block.

Once the Set Configuration Register command

has been issued, read operations will output the

array contents.

The Read Electronic Signature command is re-

quired to read the updated contents of the Config-

uration Register.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 14. shows the protection status after issuing

a Block Unlock command.

Refer to the section, Block Locking, for a detailed

explanation

and

APPENDIX

C.,

Figure

27., Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Block Unlock

command.

Block Lock-Down Command

The Block Lock-Down command is used to lock-

down a locked or unlocked block.

A locked-down block cannot be programmed or

erased. The lock status of a locked-down block

cannot be changed when WP is low, V_IL. When

WP is high, V_IH,the lock-down function is disabled

and the locked blocks can be individually unlocked

by the Block Unlock command.

Block Lock Command

The Block Lock command is used to lock a block

and prevent program or erase operations from

changing the data in it. All blocks are locked after

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

■

The first bus cycle sets up the Block Lock

command.

■

The second Bus Write cycle latches the block

address and locks the block.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 14. shows the Lock Status after issuing a

Block Lock command.

Once set, the Block Lock bits remain set until a

hardware reset or power-down/power-up. They

are cleared by a Block Unlock command.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

■

The first bus cycle sets up the Block Lock-

Down command.

■

The second Bus Write cycle latches the block

address and locks-down the block.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table 14. shows the Lock Status af-

ter issuing a Block Lock-Down command.

Refer to the section, Block Locking, for a detailed

explanation. See APPENDIX C., Figure

27., Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Lock command.

Block Unlock Command

The Block Unlock command is used to unlock a

block, allowing the block to be programmed or

erased.

Two Bus Write cycles are required to issue the

Block Unlock command.

Refer to the section, Block Locking, for a detailed

explanation

and

APPENDIX

C.,

Figure

27., Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Lock-Down

command.

■

The first bus cycle sets up the Block Unlock

command.

17/82

M58LR128FT, M58LR128FB

Table 5. Standard Commands

Bus Operations

Commands

1st Cycle

Add

2nd Cycle

Add

Op.

Write

Data

FFh

70h

90h

98h

50h

Op.

Read

Data

RD

Read Array

1+

1

BKA

WA

(2)

Read Status Register

Read Electronic Signature

Read CFI Query

BKA

SRD

ESD

QD

BKA

(2)

BKA

(2)

BKA

Clear Status Register

BKA

BKA or

Block Erase

Program

2

Write

20h

Write

BA

D0h

(3)

BA

BKA or

40h or 10h

E8h

WA

BA

PD

n

(3)

WA

Write

BA

Write

PA

PD

PA

PD

Buffer Program

n+4

1

2

PA

PD

X

D0h

n+1

Program/Erase Suspend

Program/Erase Resume

Protection Register Program

Set Configuration Register

1

2

X

B0h

D0h

C0h

60h

PRA

CRD

BKA or

Write

PRA

CRD

PRD

03h

Block Lock

2

Write

60h

Write

BA

01h

D0h

2Fh

(3)

BA

BKA or

Block Unlock

Block Lock-Down

(3)

BA

BKA or

(3)

BA

Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,

QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection

Register Data, CRD=Configuration Register Data.

2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.

3. Any address within the bank can be used.

4. n+1 is the number of Words to be programmed.

18/82

M58LR128FT, M58LR128FB

Table 6. Factory Program Command

Bus Write Operations

3rd

Add Data Add Data

Command

Phase

1st

2nd

Final -1

Final

Add

Data

Add

Data

Add

Data

BKA or

WA

Setup

2

≥32

1

80h

D0h

1

(4)

WA

Buffer

Enhanced

Factory

Program/

WA

PD

WA

PD

WA

PD

WA

PD

1

2

1

3

1

31

1

32

(3))

Verify

Program

NOT

Exit

X

(2)

BA

1

Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address, X = Don’t Care.

2. WA is the Start Address, NOT BA = Not Block Address of WA .

1

3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block.

4. Any address within the bank can be used.

Table 7. Electronic Signature Codes

Code

Address (h)

Bank Address + 00

Bank Address + 01

Data (h)

0020

88C4

88C5

0001

0000

0003

0002

CR

Manufacturer Code

Device Code

Top

Bottom

Locked

Unlocked

Block Protection

Block Address + 02

Locked and Locked-Down

Unlocked and Locked-Down

Configuration Register

Bank Address + 05

Bank Address + 80

ST Factory Default

0002

0000

Protection Register PR0

Lock

OTP Area Permanently Locked

Bank Address + 81

Bank Address + 84

Unique Device

Number

Protection Register PR0

Bank Address + 85

Bank Address + 88

OTP Area

PRLD

Protection Register PR1 through PR16 Lock

Bank Address + 89

Bank Address + 8A

Bank Address + 109

Protection Registers PR1-PR16

OTP Area

Note: CR = Configuration Register, PRLD = Protection Register Lock Data.

19/82

M58LR128FT, M58LR128FB

Figure 5. Protection Register Memory Map

PROTECTION REGISTERS

109h

PR16

User Programmable OTP

102h

91h

PR1

User Programmable OTP

8Ah

89h

Protection Register Lock

14

15 13 121110 9 8 7 6 5 4 3 2 1 0

88h

PR0

User Programmable OTP

85h

84h

Unique device number

81h

80h

Protection Register Lock

1 0

AI07563

20/82

M58LR128FT, M58LR128FB

Table 8. Protection Register Locks

Lock

Description

Number

Address

Bits

preprogrammed to protect Unique Device Number, address 81h to

84h in PR0

Bit 0

Lock 1

80h

Bit 1

Bits 2 to 15

Bit 0

protects 64bits of OTP segment, address 85h to 88h in PR0

reserved

protects 128bits of OTP segment PR1

protects 128bits of OTP segment PR2

protects 128bits of OTP segment PR3

Bit 1

Bit 2

Lock 2

89h

Bit 13

Bit 14

Bit 15

protects 128bits of OTP segment PR14

protects 128bits of OTP segment PR15

protects 128bits of OTP segment PR16

21/82

M58LR128FT, M58LR128FB

STATUS REGISTER

The Status Register provides information on the

current or previous program or erase operations.

Issue a Read Status Register command to read

the contents of the Status Register, refer to Read

Status Register Command section for more de-

tails. To output the contents, the Status Register is

latched and updated on the falling edge of the

Chip Enable or Output Enable signals and can be

read until Chip Enable or Output Enable returns to

V_IH. The Status Register can only be read using

single Asynchronous or Single Synchronous

reads. Bus Read operations from any address

within the bank, always read the Status Register

during program and erase operations.

The various bits convey information about the sta-

tus and any errors of the operation. Bits SR7, SR6,

SR2 and SR0 give information on the status of the

device and are set and reset by the device. Bits

SR5, SR4, SR3 and SR1 give information on er-

rors, they are set by the device but must be reset

by issuing a Clear Status Register command or a

hardware reset. If an error bit is set to ‘1’ the Status

Register should be reset before issuing another

command.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status Bit (SR5). The Erase Status bit is

used to identify if there was an error during a block

or bank erase operation. When the Erase Status

bit is High (set to ‘1’), the Program/Erase Control-

ler has applied the maximum number of pulses to

the block or bank and still failed to verify that it has

erased correctly.

The Erase Status bit should be read once the Pro-

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive).

Once set High, the Erase Status bit must be set

Low by a Clear Status Register command or a

hardware reset before a new erase command is is-

sued, otherwise the new command will appear to

fail.

Program Status Bit (SR4). The Program Status

bit is used to identify if there was an error during a

program operation.

The Program Status bit should be read once the

Program/Erase Controller Status bit is High (Pro-

gram/Erase Controller inactive).

The bits in the Status Register are summarized in

Table 9., Status Register Bits. Refer to Table 9. in

conjunction with the following text descriptions.

Program/Erase Controller Status Bit (SR7). The

Program/Erase Controller Status bit indicates

whether the Program/Erase Controller is active or

inactive in any bank.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status bit is Low

immediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

When the Program Status bit is High (set to ‘1’),

the Program/Erase Controller has applied the

maximum number of pulses to the Word and still

failed to verify that it has programmed correctly.

Attempting to program a '1' to an already pro-

grammed bit while V_PP= V_PPHwill also set the

Program Status bit High. If V_PPis different from

V_PPH, SR4 remains Low (set to '0') and the attempt

is not shown.

Once set High, the Program Status bit must be set

Low by a Clear Status Register command or a

hardware reset before a new program command is

issued, otherwise the new command will appear to

fail.

V

_PPStatus Bit (SR3). The V_PPStatus bit is used

to identify an invalid voltage on the V_PPpin during

program and erase operations. The V_PPpin is only

sampled at the beginning of a program or erase

operation. Program and erase operations are not

guaranteed if V_PPbecomes invalid during an oper-

ation.

Erase Suspend Status Bit (SR6). The

Erase

Suspend Status bit indicates that an erase opera-

tion has been suspended in the addressed block.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

When the V_PPStatus bit is Low (set to ‘0’), the volt-

age on the V_PPpin was sampled at a valid voltage.

when the V_PPStatus bit is High (set to ‘1’), the V_PP

pin has a voltage that is below the V_PPLockout

Voltage, V_PPLK, the memory is protected and pro-

gram and erase operations cannot be performed.

Once set High, the V_PPStatus bit must be set Low

by a Clear Status Register command or a hard-

ware reset before a new program or erase com-

mand is issued, otherwise the new command will

appear to fail.

The Erase Suspend Status bit should only be con-

sidered valid when the Program/Erase Controller

Status bit is High (Program/Erase Controller inac-

tive). SR6 is set within the Erase Suspend Latency

time of the Program/Erase Suspend command be-

ing issued therefore the memory may still com-

plete the operation rather than entering the

Suspend mode.

22/82

M58LR128FT, M58LR128FB

Program Suspend Status Bit (SR2). The Pro-

gram Suspend Status bit indicates that a program

operation has been suspended in the addressed

block. The Program Suspend Status bit should

only be considered valid when the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

When the Program Suspend Status bit is High (set

to ‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

SR2 is set within the Program Suspend Latency

time of the Program/Erase Suspend command be-

ing issued therefore the memory may still com-

plete the operation rather than entering the

Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

or erase command is issued, otherwise the new

command will appear to fail.

Bank Write/Multiple Word Program Status Bit

(SR0). The Bank Write Status bit indicates wheth-

er the addressed bank is programming or erasing.

In Buffer Enhanced Factory Program mode the

Multiple Word Program bit shows if the device is

ready to accept a new Word to be programmed to

the memory array.

The Bank Write Status bit should only be consid-

ered valid when the Program/Erase Controller Sta-

tus SR7 is Low (set to ‘0’).

When both the Program/Erase Controller Status bit

and the Bank Write Status bit are Low (set to ‘0’),

the addressed bank is executing a program or

erase operation. When the Program/Erase Con-

troller Status bit is Low (set to ‘0’) and the Bank

Write Status bit is High (set to ‘1’), a program or

erase operation is being executed in a bank other

than the one being addressed.

In Buffer Enhanced Factory Program mode if Mul-

tiple Word Program Status bit is Low (set to ‘0’),

the device is ready for the next Word, if the Multi-

ple Word Program Status bit is High (set to ‘1’) the

device is not ready for the next Word.

Block Protection Status Bit (SR1). The Block

Protection Status bit is used to identify if a Pro-

gram or Block Erase operation has tried to modify

the contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a program or erase operation has been at-

tempted on a locked block.

For further details on how to use the Status Regis-

ter, see the Flowcharts and Pseudocodes provid-

ed in APPENDIX C.

Once set High, the Block Protection Status bit

must be set Low by a Clear Status Register com-

mand or a hardware reset before a new program

23/82

M58LR128FT, M58LR128FB

Table 9. Status Register Bits

Bit

Name

Type LogicLevel

Definition

'1'

Ready

SR7 P/E.C. Status

Status

'0'

Busy

'1'

Erase Suspended

SR6 Erase Suspend Status

SR5 Erase Status

Status

'0'

Erase In progress or Completed

Erase Error

'1'

Error

'0'

Erase Success

'1'

Program Error

SR4 Program Status

Error

'0'

Program Success

V

Invalid, Abort

OK

'1'

PP

V

PP

Status

SR3

Error

'0'

V

'1'

Program Suspended

SR2 Program Suspend Status Status

'0'

'1'

'0'

Program In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

SR7 = ‘1’ Not Allowed

SR1 Block Protection Status

Bank Write Status

Error

'1'

Program or erase operation in a bank other than

SR7 = ‘0’

the addressed bank

Status

SR7 = ‘1’ No Program or erase operation in the device

SR7 = ‘0’ Program or erase operation in addressed bank

SR7 = ‘1’ Not Allowed

'0'

'1'

'0'

SR0

Multiple Word Program

Status (Buffer Enhanced Status

Factory Program mode)

SR7 = ‘0’ the device is NOT ready for the next Word

SR7 = ‘1’ the device is exiting from BEFP

SR7 = ‘0’ the device is ready for the next Word

Note: Logic level '1' is High, '0' is Low.

24/82

M58LR128FT, M58LR128FB

CONFIGURATION REGISTER

The Configuration Register is used to configure

the type of bus access that the memory will per-

form. Refer to Read Modes section for details on

read operations.

■

t_{QVK_CPU}is the data setup time required by

the system CPU,

t_KQVis the clock to data valid time

■

t_AVQVis the random access time of the device.

The Configuration Register is set through the

Command Interface using the Set Configuration

Register command. After a reset or power-up the

device is configured for asynchronous read (CR15

= 1). The Configuration Register bits are described

in Table 10. They specify the selection of the burst

length, burst type, burst X latency and the read op-

eration. Refer to Figures 6 and 7 for examples of

synchronous burst configurations.

Refer to Figure 6., X-Latency and Data Output

Configuration Example.

Wait Polarity Bit (CR10)

The Wait Polarity bit is used to set the polarity of

the Wait signal used in Synchronous Burst Read

mode. During Synchronous Burst Read mode the

Wait signal indicates whether the data output are

valid or a WAIT state must be inserted.

Read Select Bit (CR15)

When the Wait Polarity bit is set to ‘0’ the Wait sig-

nal is active Low. When the Wait Polarity bit is set

to ‘1’ the Wait signal is active High (default).

The Read Select bit, CR15, is used to switch be-

tween Asynchronous and Synchronous Read op-

erations.

Data Output Configuration Bit (CR9)

When the Read Select bit is set to ’1’, read opera-

tions are asynchronous; when the Read Select bit

is set to ’0’, read operations are synchronous.

The Data Output Configuration bit is used to con-

figure the output to remain valid for either one or

two clock cycles during synchronous mode.

Synchronous Burst Read is supported in both pa-

rameter and main blocks and can be performed

across banks.

On reset or power-up the Read Select bit is set to

’1’ for asynchronous access (default).

When the Data Output Configuration Bit is ’0’ the

output data is valid for one clock cycle, when the

Data Output Configuration Bit is ’1’ the output data

is valid for two clock cycles.

The Data Output Configuration must be config-

ured using the following condition:

X-Latency Bits (CR13-CR11)

■

t_K> t_KQV+ t_{QVK_CPU}

The X-Latency bits are used during Synchronous

Read operations to set the number of clock cycles

between the address being latched and the first

data becoming available.

For correct operation the X-Latency bits can only

assume the values in Table 10., Configuration

Register.

where

■

t_Kis the clock period

t_{QVK_CPU}is the data setup time required by

the system CPU

■

t_KQVis the clock to data valid time.

If this condition is not satisfied, the Data Output

Configuration bit should be set to ‘1’ (two clock cy-

cles). Refer to Figure 6., X-Latency and Data Out-

put Configuration Example.

The correspondence between X-Latency settings

and the maximum sustainable frequency must be

calculated taking into account some system pa-

rameters. Two conditions must be satisfied:

1. Depending on whether t_{AVK_CPU}or t_DELAYis

supplied either one of the following two

equations must be satisfied:

(n + 1) t_K≥ t_AVQV- t_{AVK_CPU}+ t_{QVK_CPU}

(n + 2) t_K≥ t_AVQV+ t_DELAY+ t_{QVK_CPU}

2. and also

Wait Configuration Bit (CR8)

The Wait Configuration bit is used to control the

timing of the Wait output pin, WAIT, in Synchro-

nous Burst Read mode.

When WAIT is asserted, Data is Not Valid and

when WAIT is deasserted, Data is Valid.

When the Wait Configuration bit is Low (set to ’0’)

the Wait output pin is asserted during the wait

state. When the Wait Configuration bit is High (set

to ’1’) (default) the Wait output pin is asserted one

clock cycle before the wait state.

Burst Type Bit (CR7)

The Burst Type bit determines the sequence of ad-

dresses read during Synchronous Burst Reads.

The Burst Type bit is High (set to ’1’), as the mem-

ory outputs from sequential addresses only.

t_K> t_KQV+ t_{QVK_CPU}

where

■

n is the chosen X-Latency configuration code

t_Kis the clock period

t_{AVK_CPU}is clock to address valid, L Low, or E

Low, whichever occurs last

■

t_DELAYis address valid, L Low, or E Low to

clock, whichever occurs last

25/82

M58LR128FT, M58LR128FB

See Table 11., Burst Type Definition, for the se-

quence of addresses output from a given starting

address in sequential mode.

Read operation as result of a single address latch

cycle.

They can be set for 4 Words, 8 Words, 16 Words

or continuous burst, where all the Words are read

sequentially. In continuous burst mode the burst

sequence can cross bank boundaries.

In continuous burst mode, in 4, 8 or 16 Words no-

wrap, depending on the starting address, the de-

vice asserts the WAIT signal to indicate that a de-

lay is necessary before the data is output.

If the starting address is aligned to a 4 Word

boundary no wait states are needed and the WAIT

output is not asserted.

If the starting address is shifted by 1, 2 or 3 posi-

tions from the four word boundary, WAIT will be

asserted for 1, 2 or 3 clock cycles when the burst

sequence crosses the first 16 Word boundary, to

indicate that the device needs an internal delay to

read the successive Words in the array. WAIT will

be asserted only once during a continuous burst

access. See also Table 11., Burst Type Definition.

Valid Clock Edge Bit (CR6)

The Valid Clock Edge bit, CR6, is used to config-

ure the active edge of the Clock, K, during syn-

chronous read operations. When the Valid Clock

Edge bit is Low (set to ’0’) the falling edge of the

Clock is the active edge. When the Valid Clock

Edge bit is High (set to ’1’) the rising edge of the

Clock is the active edge.

Wrap Burst Bit (CR3)

The Wrap Burst bit, CR3, is used to select be-

tween wrap and no wrap. Synchronous burst

reads can be confined inside the 4, 8 or 16 Word

boundary (wrap) or overcome the boundary (no

wrap).

When the Wrap Burst bit is Low (set to ‘0’) the

burst read wraps. When it is High (set to ‘1’) the

burst read does not wrap.

Burst length Bits (CR2-CR0)

The Burst Length bits are used to set the number

of Words to be output during a Synchronous Burst

CR14, CR5 and CR4 are reserved for future use.

26/82

M58LR128FT, M58LR128FB

Table 10. Configuration Register

Bit

Description

Value

Description

0

1

Synchronous Read

CR15

CR14

Read Select

Asynchronous Read (Default at power-on)

Reserved

010

011

100

101

111

2 clock latency

3 clock latency

4 clock latency

CR13-CR11

X-Latency

5 clock latency

Reserved (default)

Other configurations reserved

0

1

0

1

0

1

0

1

0

1

WAIT is active Low

WAIT is active high (default)

Data held for one clock cycle

Data held for two clock cycles (default)

WAIT is active during wait state

WAIT is active one data cycle before wait state (default)

Reserved

CR10

CR9

CR8

CR7

Wait Polarity

Data Output

Configuration

Wait Configuration

Burst Type

Sequential (default)

Falling Clock edge

CR6

CR5-CR4

CR3

Valid Clock Edge

Rising Clock edge (default)

Reserved

0

Wrap

Wrap Burst

1

No Wrap (default)

001

010

011

111

4 Words

8 Words

CR2-CR0

Burst Length

16 Words

Continuous (default)

27/82

M58LR128FT, M58LR128FB

Table 11. Burst Type Definition

4 Words

8 Words

16 Words

Start

Add

Continuous

Burst

Sequen-tial

Sequential

0-1-2-3-4-5-6-7-8-9-10-11-12-13-

14-15

0

1

2

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6...

1-2-3-4-5-6-7-8-9-10-11-12-13-14- 1-2-3-4-5-6-7-...15-WAIT-16-

15-0 17-18...

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

2-3-4-5-6-7-8-9-10-11-12-13-14- 2-3-4-5-6-7...15-WAIT-WAIT-

15-0-1

16-17-18...

3-4-5-6-7-8-9-10-11-12-13-14-15-

0-1-2

3-4-5-6-7...15-WAIT-WAIT-

WAIT-16-17-18...

3

...

7

7-8-9-10-11-12-13-14-15-0-1-2-3-

4-5-6

7-8-9-10-11-12-13-14-15-

WAIT-WAIT-WAIT-16-17...

7-4-5-6

7-0-1-2-3-4-5-6

...

12

13

14

12-13-14-15-16-17-18...

13-14-15-WAIT-16-17-18...

14-15-WAIT-WAIT-16-17-18....

15-WAIT-WAIT-WAIT-16-17-

18...

15

0

0-1-2-3-4-5-6-7-8-9-10-11-12-13-

14-15

0-1-2-3

1-2-3-4

2-3-4-5

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9...

1-2-3-4-5-6-7-8-9-10-11-12-13-14-

15-WAIT-16

1

2-3-4-5-6-7-8-9-10-11-12-13-14-

15-WAIT-WAIT-16-17

2

3-4-5-6-7-8-9-10-11-12-13-14-15-

WAIT-WAIT-WAIT-

16-17-18

3

3-4-5-6

3-4-5-6-7-8-9-10

...

7

Same as for Wrap

(Wrap /No Wrap

has no effect on

Continuous Burst)

7-8-9-10-11-12-13-14-15-WAIT-

WAIT-WAIT-16-17-18-19-20-21-22

7-8-9-10

7-8-9-10-11-12-13-14

...

12

12-13-14-15-16-17- 12-13-14-15-16-17-18-19-20-21-

18-19 22-23-24-25-26-27

12-13-14-15

13-14-15-WAIT- 13-14-15-WAIT-16- 13-14-15-WAIT-16-17-18-19-20-

13

14

16

17-18-19-20

21-22-23-24-25-26-27-28

14-15-WAIT-

WAIT-16-17

14-15-WAIT-WAIT-

16-17-18-19-20-21

14-15-WAIT-WAIT-16-17-18-19-

20-21-22-23-24-25-26-27-28-29

15-WAIT-WAIT-

WAIT-16-17-18-19- 20-21-22-23-24-25-26-27-28-29-

20-21-22 30

15-WAIT-WAIT-WAIT-16-17-18-19-

15-WAIT-WAIT-

WAIT-16-17-18

15

28/82

M58LR128FT, M58LR128FB

Figure 6. X-Latency and Data Output Configuration Example

X-latency

1st cycle

2nd cycle

3rd cycle

4th cycle

K

E

L

A22-A0

tDELAY

VALID ADDRESS

tAVK_CPU

tQVK_CPU

tK

tQVK_CPU

tACC

tKQV

DQ15-DQ0

VALID DATA VALID DATA

Note. Settings shown: X-latency = 4, Data Output held for one clock cycle

AI06182

Figure 7. Wait Configuration Example

E

K

L

A22-A0

VALID ADDRESS

DQ15-DQ0

VALID DATA VALID DATA NOT VALID VALID DATA

WAIT

CR8 = '0'

CR10 = '0'

WAIT

CR8 = '1'

CR10 = '0'

WAIT

CR8 = '0'

CR10 = '1'

WAIT

CR8 = '1'

CR10 = '1'

AI06972

29/82

M58LR128FT, M58LR128FB

READ MODES

Read operations can be performed in two different

ways depending on the settings in the Configura-

tion Register. If the clock signal is ‘don’t care’ for

the data output, the read operation is asynchro-

nous; if the data output is synchronized with clock,

the read operation is synchronous.

Synchronous Burst Read mode can only be used

to read the memory array. For other read opera-

tions, such as Read Status Register, Read CFI

and Read Electronic Signature, Single Synchro-

nous Read or Asynchronous Random Access

Read must be used.

The read mode and format of the data output are

determined by the Configuration Register. (See

Configuration Register section for details). All

banks support both asynchronous and synchro-

nous read operations.

In Synchronous Burst Read mode the flow of the

data output depends on parameters that are con-

figured in the Configuration Register.

A burst sequence starts at the first clock edge (ris-

ing or falling depending on Valid Clock Edge bit

CR6 in the Configuration Register) after the falling

edge of Latch Enable or Chip Enable, whichever

occurs last. Addresses are internally incremented

and data is output on each data cycle after a delay

which depends on the X latency bits CR13-CR11

of the Configuration Register.

The number of Words to be output during a Syn-

chronous Burst Read operation can be configured

as 4 Words, 8 Words, 16 Words or Continuous

(Burst Length bits CR2-CR0). The data can be

configured to remain valid for one or two clock cy-

cles (Data Output Configuration bit CR9).

The order of the data output can be modified

through the Wrap Burst bit in the Configuration

Register. The burst sequence is sequential and

can be confined inside the 4, 8 or 16 Word bound-

ary (Wrap) or overcome the boundary (No Wrap).

The WAIT signal may be asserted to indicate to

the system that an output delay will occur. This de-

lay will depend on the starting address of the burst

sequence and on the burst configuration.

WAIT is asserted during the X latency, the Wait

state and at the end of a 4, 8 and 16 Word burst. It

is only deasserted when output data are valid. In

Continuous Burst Read mode a Wait state will oc-

cur when crossing the first 16 Word boundary. If

the burst starting address is aligned to a 4 Word

Page, the Wait state will not occur.

The WAIT signal can be configured to be active

Low or active High by setting CR10 in the Config-

uration Register.

Asynchronous Read Mode

In Asynchronous Read operations the clock signal

is ‘don’t care’. The device outputs the data corre-

sponding to the address latched, that is the mem-

ory array, Status Register, Common Flash

Interface or Electronic Signature depending on the

command issued. CR15 in the Configuration Reg-

ister must be set to ‘1’ for asynchronous opera-

tions.

Asynchronous Read operations can be performed

in two different ways, Asynchronous Random Ac-

cess Read and Asynchronous Page Read. Only

Asynchronous Page Read takes full advantage of

the internal page storage so different timings are

applied.

In Asynchronous Read mode a Page of data is in-

ternally read and stored in a Page Buffer. The

Page has a size of 4 Words and is addressed by

address inputs A0 and A1.

The first read operation within the Page has a

longer access time (t_AVQV, Random access time),

subsequent reads within the same Page have

much shorter access times (t_AVQV1, Page access

time). If the Page changes then the normal, longer

timings apply again.

The device features an Automatic Standby mode.

During Asynchronous Read operations, after a

bus inactivity of 150ns, the device automatically

switches to the Automatic Standby mode. In this

condition the power consumption is reduced to the

standby value and the outputs are still driven.

In Asynchronous Read mode, the WAIT signal is

always deasserted.

See Table 21., Asynchronous Read AC Charac-

teristics, Figure 10., Asynchronous Random Ac-

cess Read AC Waveforms, and Figure

11., Asynchronous Page Read AC Waveforms, for

details.

See Table 22., Synchronous Read AC Character-

istics, and Figure 12., Synchronous Burst Read

AC Waveforms, for details.

Synchronous Burst Read Suspend. A

Syn-

chronous Burst Read operation can be suspend-

ed, freeing the data bus for other higher priority

devices. It can be suspended during the initial ac-

cess latency time (before data is output) in which

case the initial latency time can be reduced to ze-

ro, or after the device has output data. When the

Synchronous Burst Read operation is suspended,

internal array sensing continues and any previous-

ly latched internal data is retained. A burst se-

Synchronous Burst Read Mode

In Synchronous Burst Read mode the data is out-

put in bursts synchronized with the clock. It is pos-

sible to perform burst reads across bank

boundaries.

30/82

M58LR128FT, M58LR128FB

quence can be suspended and resumed as often

as required as long as the operating conditions of

the device are met.

A Synchronous Burst Read operation is suspend-

ed when Chip Enable, E, is Low and the current

address has been latched (on a Latch Enable ris-

ing edge or on a valid clock edge). The Clock sig-

nal is then halted at V_IHor at V_IL, and Output

Enable, G, goes High.

When Output Enable, G, becomes Low again and

the Clock signal restarts, the Synchronous Burst

Read operation is resumed exactly where it

stopped.

WAIT will revert to high-impedance when Output

Enable, G, or Chip Enable, E, goes High.

Single Synchronous Read Mode

Single Synchronous Read operations are similar

to Synchronous Burst Read operations except that

the memory outputs the same data to the end of

the operation.

Synchronous Single Reads are used to read the

Electronic Signature, Status Register, CFI, Block

Protection Status, Configuration Register Status

or Protection Register. When the addressed bank

is in Read CFI, Read Status Register or Read

Electronic Signature mode, the WAIT signal is as-

serted during the X latency, the Wait state and at

the end of a 4, 8 and 16 Word burst. It is only deas-

serted when output data are valid.

See Table 22., Synchronous Read AC Character-

istics, and Figure 12., Synchronous Burst Read

AC Waveforms, for details.

See Table 22., Synchronous Read AC Character-

istics, and Figure 14., Synchronous Burst Read

Suspend AC Waveforms, for details.

31/82

M58LR128FT, M58LR128FB

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE

The Multiple Bank Architecture of the

M58LR128FT/B gives greater flexibility for soft-

ware developers to split the code and data spaces

within the memory array. The Dual Operations fea-

ture simplifies the software management of the de-

vice by allowing code to be executed from one

bank while another bank is being programmed or

erased.

Also if the suspended operation was erase then a

program command can be issued to another

block, so the device can have one block in Erase

Suspend mode, one programming and other

banks in read mode.

Bus Read operations are allowed in another bank

between setup and confirm cycles of program or

erase operations.

The Dual Operations feature means that while pro-

gramming or erasing in one bank, read operations

are possible in another bank with zero latency

(only one bank at a time is allowed to be in pro-

gram or erase mode).

If a read operation is required in a bank, which is

programming or erasing, the program or erase op-

eration can be suspended.

By using a combination of these features, read op-

erations are possible at any moment in the

M58LR128FT/B device.

Tables 12 and 13 show the dual operations possi-

ble in other banks and in the same bank.

Table 12. Dual Operations Allowed In Other Banks

Commands allowed in another bank

Read

Status

Read

CFI

Read

Electronic

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

Program,

Buffer Program Erase

Block

Register Query Signature

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Programming

Erasing

–

Program Suspended

Erase Suspended

–

Yes

–

Table 13. Dual Operations Allowed In Same Bank

Commands allowed in same bank

Read

Status

Register

Read

Electronic

Signature

Program,

Buffer

Program

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

Read

CFI Query

Block

Erase

Idle

Yes

–

Yes

–

Yes

–

Yes

–

(2)

Programming

–

(2)

Erasing

–

(1)

Program Suspended

Erase Suspended

–

Yes

(1)

–

Yes

Note: 1. Not allowed in the Block or Word that is being erased or programmed.

2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.

32/82

M58LR128FT, M58LR128FB

BLOCK LOCKING

The M58LR128FT/B features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

Locked or Locked-Down using the appropriate

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

■

Lock/Unlock - this first level allows software

only control of block locking.

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their protection status can-

not be changed using software commands alone.

A Locked or Unlocked block can be Locked-Down

by issuing the Lock-Down command. Locked-

Down blocks revert to the Locked state when the

device is reset or powered-down.

The Lock-Down function is dependent on the Write

Protect, WP, input pin.

When WP=0 (V_IL), the blocks in the Lock-Down

state (0,1,x) are protected from program, erase

and protection status changes.

When WP=1 (V_IH) the Lock-Down function is dis-

abled (1,1,x) and Locked-Down blocks can be in-

dividually unlocked to the (1,1,0) state by issuing

the software command, where they can be erased

and programmed.

When the Lock-Down function is disabled (WP=1)

blocks can be locked (1,1,1) and unlocked (1,1,0)

as desired. When WP=0 blocks that were previ-

ously Locked-Down return to the Lock-Down state

(0,1,x) regardless of any changes that were made

while WP=1.

■

Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■

V_PP≤ V_PPLK- the third level offers a complete

hardware protection against program and

erase on all blocks.

The protection status of each block can be set to

Locked, Unlocked, and Locked-Down. Table 14.,

defines all of the possible protection states (WP,

DQ1, DQ0), and APPENDIX C., Figure 27., shows

a flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode issue the Read Electronic Signa-

ture command. Subsequent reads at the address

specified in Table 7., will output the protection sta-

tus of that block.

The lock status is represented by DQ0 and DQ1.

DQ0 indicates the Block Lock/Unlock status and is

set by the Lock command and cleared by the Un-

lock command. DQ0 is automatically set when en-

tering Lock-Down. DQ1 indicates the Lock-Down

status and is set by the Lock-Down command.

DQ1 cannot be cleared by software, only by a

hardware reset or power-down.

Device reset or power-down resets all blocks, in-

cluding those in Lock-Down, to the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

program or erase operations. Any program or

erase operations attempted on a locked block will

return an error in the Status Register. The Status

of a Locked block can be changed to Unlocked or

Locked-Down using the appropriate software

commands. An Unlocked block can be Locked by

issuing the Lock command.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the Status Register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

33/82

M58LR128FT, M58LR128FB

Table 14. Lock Status

Current

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

Protection Status

(WP, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Current State

After

WP transition

Allowed

1,0,0

yes

1,0,1

1,0,0

1,1,1

0,0,0

(2)

no

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,1

0,1,1

1,0,0

1,0,1

1,1,0

1,1,1

0,0,0

yes

(2)

no

0,0,1

0,1,1

0,0,0

0,1,1

1,0,1

0,0,1

(3)

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

34/82

M58LR128FT, M58LR128FB

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES

The Program and Erase times and the number of

Program/ Erase cycles per block are shown in Ta-

ble 15. In the M58LR128FT/B the maximum num-

ber of Program/ Erase cycles depends on the

voltage supply used.

Table 15. Program, Erase Times and Endurance Cycles

Typical after

100k W/E

Cycles

Parameter

Condition

Min

Typ

Max

Unit

Preprogrammed

Not Preprogrammed

Preprogrammed

Not Preprogrammed

Word Program

0.65

0.8

1.4

1.8

10

1

2.5

4

s

Parameter Block

(16 KWords)

Erase

3

s

Main Block (64

KWords)

4

s

100

µs

ms

µs

cycles

s

Single Cell

Buffer Program

Word Program

10

100

(3)

Single Word

Program

Buffer Program

10

Buffer (32 Words) (Buffer Program)

Main Block (64 KWords)

Program

320

640

5

10

25

Suspend Latency

Erase

5

Main Blocks

100,000

Program/Erase

Cycles (per Block)

Parameter Blocks

Parameter Block (16 KWords)

Main Block (64 KWords)

0.7

1.2

10

2.5

4

Erase

s

Single Cell

Word Program

100

µs

Word Program

10

Single Word

Buffered Enhanced

3.5

320

100

640

200

5

µs

ms

s

(4)

Factory Program

Word Program

Buffer (32

Words)

Buffered Enhanced

(4)

(3)

Factory Program

Program

Word Program

Main Block (64

KWords)

Buffered Enhanced

(4)

Factory Program

Word Program

Bank (8 Mbits)

Buffered Enhanced

1.6

s

(4)

Factory Program

Main Blocks

1000 cycles

2500 cycles

Program/Erase

Cycles (per Block)

Parameter Blocks

Note: 1. T = –40 to 85°C; V = 1.7V to 2.0V; V = 1.7V to 2.0V.

DDQ

A

DD

2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution).

3. Excludes the time needed to execute the command sequence.

4. Average on entire device.

35/82

M58LR128FT, M58LR128FB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 16. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–25

–65

–0.5

–0.2

Max

85

T

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

°C

V

A

T

85

BIAS

T

125

3.8

2.5

14

STG

V

IO

V

DD

V

Input/Output Supply Voltage

Program Voltage

V

DDQ

V

PP

V

I

Output Short Circuit Current

Time for V at V

100

mA

hours

O

t

VPPH

PP

PPH

36/82

M58LR128FT, M58LR128FB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 17., Operating

and AC Measurement Conditions. Designers

should check that the operating conditions in their

circuit match the operating conditions when rely-

ing on the quoted parameters.

Table 17. Operating and AC Measurement Conditions

M58LR128FT, M58LR128FB

Parameter

85

95

Units

Min

1.7

Max

2.0

Min

1.7

Max

2.0

V

Supply Voltage

V

DD

Supply Voltage

1.7

2.0

1.7

2.0

DDQ

Supply Voltage (Factory environment)

Supply Voltage (Application environment)

8.5

12.6

8.5

12.6

V

PP

V

+0.4

V

+0.4

DDQ

–0.4

–25

–0.4

–25

V

DDQ

Ambient Operating Temperature

85

5

°C

pF

ns

V

Load Capacitance (C )

30

L

Input Rise and Fall Times

5

0 to V

Input Pulse Voltages

DDQ

V /2

DDQ

V

/2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 8. AC Measurement I/O Waveform

Figure 9. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DD

0V

16.7kΩ

AI06161

DEVICE

UNDER

TEST

C

L

16.7kΩ

0.1µF

C

includes JIG capacitance

L

AI06162

Table 18. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

8

Unit

C

V

IN

= 0V

6

8

pF

IN

C

V

OUT

12

OUT

Note: Sampled only, not 100% tested.

37/82

M58LR128FT, M58LR128FB

Table 19. DC Characteristics - Currents

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Typ

Max

±1

Unit

µA

I

LI

0V ≤ V ≤ V

IN

DDQ

I

LO

0V ≤ V ≤ V

OUT DDQ

±1

µA

Supply Current

Asynchronous Read (f=6MHz)

E = V , G = V

10

15

mA

IL

IH

4 Word

8 Word

7

16

18

20

25

18

20

25

27

mA

10

13

18

16

18

21

22

Supply Current

Synchronous Read (f=40MHz)

16 Word

Continuous

4 Word

I

DD1

8 Word

Supply Current

Synchronous Read (f=54MHz)

16 Word

Continuous

Supply Current

(Reset)

I

RP = V ± 0.2V

25

70

µA

DD2

DD3

DD4

SS

E = V ± 0.2V

Supply Current (Standby)

DD

Supply Current (Automatic

Standby)

E = V , G = V

IL

IH

V

= V

PPH

8

10

8

15

20

15

20

mA

PP

Supply Current (Program)

Supply Current (Erase)

V

= V

PP

DD

(1)

I

DD5

V

PP

PPH

V

= V

DD

10

PP

Program/Erase in one

Bank, Asynchronous

Read in another Bank

20

35

mA

Supply Current

(Dual Operations)

(1,2)

(1)

I

DD6

Program/Erase in one

Bank, Synchronous

Read in another Bank

32

25

47

70

mA

µA

Supply Current Program/ Erase

Suspended (Standby)

E = V ± 0.2V

I

DD

DD7

V

= V

PPH

2

5

mA

µA

mA

µA

PP

V

Supply Current (Program)

Supply Current (Erase)

PP

V

= V

0.2

2

PP

DD

(1)

PP1

V

PPH

V

= V

0.2

PP

DD

I

V

Supply Current (Read)

V

≤ V

PP2

PP

DD

(1)

Supply Current (Standby)

V

PP

0.2

5

µA

I

PP

DD

PP3

Note: 1. Sampled only, not 100% tested.

2. V Dual Operation current is the sum of read and program or erase currents.

DD

38/82

M58LR128FT, M58LR128FB

Table 20. DC Characteristics - Voltages

Symbol

Parameter

Input Low Voltage

Test Condition

Min

Typ

Max

Unit

V

IL

–0.5

0.4

V

–0.4

V

+ 0.4

DDQ

Input High Voltage

Output Low Voltage

Output High Voltage

V

IH

DDQ

V

I

= 100µA

OL

0.1

V

OL

V

I

= –100µA

OH

–0.1

V

OH

DDQ

V

Program Voltage-Logic

Program Voltage Factory

Program, Erase

1.1

1.8

9.0

3.3

12.6

0.4

V

PP1

PP

V

PP

8.5

V

PPH

V

Program or Erase Lockout

V Lock Voltage

DD

V

PPLK

V

LKO

1

V

RP pin Extended High Voltage

3.3

V

RPH

39/82

M58LR128FT, M58LR128FB

Figure 10. Asynchronous Random Access Read AC Waveforms

40/82

M58LR128FT, M58LR128FB

Figure 11. Asynchronous Page Read AC Waveforms

A2-A22

VALID ADDRESS

tAVAV

VALID ADDRESS

tAVLH

A0-A1

L

VALID ADD. VALID ADD. VALID ADD.

tLHAX

tLLLH

tLLQV

tELLH

E

tELQV

tELQX

G

tGLTV

tELTV

Hi-Z

(1)

WAIT

tGLQV

tGLQX

tAVQV1

VALID

DATA

VALID

DATA

VALID

DATA

VALID

DATA

DQ0-DQ15

Outputs

Enabled

Valid Data

Valid Address Latch

Standby

Note 1. WAIT is active Low.

AI08334

41/82

M58LR128FT, M58LR128FB

Table 21. Asynchronous Read AC Characteristics

M58LR128FT/B

Symbol

Alt

Parameter

Unit

85

25

95

25

t

Address Valid to Next Address Valid

Address Valid to Output Valid (Random)

Address Valid to Output Valid (Page)

Address Transition to Output Transition

Chip Enable Low to Wait Valid

Min

Max

Min

ns

AVAV

RC

t

ACC

AVQV

t

PAGE

AVQV1

(1)

t

0

14

85

0

17

95

0

t

OH

AXQX

t

Max

ELTV

(2)

t

Chip Enable Low to Output Valid

t

CE

ELQV

(1)

t

Chip Enable Low to Output Transition

Chip Enable High to Wait Hi-Z

Min

Max

Min

ns

LZ

ELQX

t

17

0

20

0

EHTZ

(1)

(2)

(1)

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Wait Valid

t

OH

EHQX

EHQZ

GLQV

t

Max

Min

17

20

0

20

25

0

HZ

t

OE

t

OLZ

GLQX

t

Max

Min

14

0

17

0

GLTV

(1)

t

Output Enable High to Output Transition

t

OH

GHQX

(1)

t

Output Enable High to Output Hi-Z

Output Enable High to Wait Hi-Z

Max

Min

Max

17

7

20

10

95

ns

DF

GHQZ

t

GHTZ

t

Address Valid to Latch Enable High

Chip Enable Low to Latch Enable High

Latch Enable High to Address Transition

Latch Enable Pulse Width

AVLH

AVADVH

t

10

7

ELLH

LHAX

ELADVH

t

ADVHAX

t

ADVLADVH

7

LLLH

t

Latch Enable Low to Output Valid (Random)

85

LLQV

ADVLQV

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV GLQV

ELQV

42/82

M58LR128FT, M58LR128FB

Figure 12. Synchronous Burst Read AC Waveforms

43/82

M58LR128FT, M58LR128FB

Figure 13. Single Synchronous Read AC Waveforms

A0-A22

VALID ADDRESS

tAVKH

L

tLLKH

K⁽²⁾

tELKH

tKHQV

tELQV

E

tGLQV

tGLQX

G

tELQX

tGHTZ

Hi-Z

DQ0-DQ15

VALID

tKHTV

tGLTV

WAIT^(1,2)

Note 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can

be configured as the active edge. Here, the active edge is the rising one.

AI08312

44/82

M58LR128FT, M58LR128FB

Figure 14. Synchronous Burst Read Suspend AC Waveforms

45/82

M58LR128FT, M58LR128FB

Figure 15. Clock input AC Waveform

tKHKL

tKHKH

tf

tr

tKLKH

AI06981

Table 22. Synchronous Read AC Characteristics

M58LR128FT/B

Symbol

Alt

Parameter

Unit

85

7

95

9

t

Address Valid to Clock High

Min

Max

ns

AVKH

AVCLKH

t

Chip Enable Low to Clock High

Chip Enable Low to Wait Valid

7

9

ELKH

ELCLKH

t

14

17

ELTV

Chip Enable Pulse Width (subsequent

synchronous reads)

Min

14

17

ns

EHEL

t

Chip Enable High to Wait Hi-Z

Clock High to Address Transition

Max

Min

17

7

20

10

ns

EHTZ

t

KHAX

CLKHAX

t

Clock High to Output Valid

Clock High to WAIT Valid

KHQV

t

Max

Min

14

17

4

ns

CLKHQV

KHTV

t

Clock High to Output Transition

Clock High to WAIT Transition

KHQX

3

7

CLKHQX

KHTX

t

ADVLCLKH

Latch Enable Low to Clock High

Clock Period (f=40MHz)

Clock Period (f=47MHz)

Clock Period (f=54MHz)

Min

9

ns

LLKH

25

t

KHKH

CLK

18.5

3.5

ns

t

Clock High to Clock Low

Clock Low to Clock High

KHKL

Min

5

3

KLKH

t

f

Clock Fall or Rise Time

Max

3

ns

t

r

Note: 1. Sampled only, not 100% tested.

2. For other timings please refer to Table 21., Asynchronous Read AC Characteristics.

46/82

M58LR128FT, M58LR128FB

Figure 16. Write AC Waveforms, Write Enable Controlled

47/82

M58LR128FT, M58LR128FB

Table 23. Write AC Characteristics, Write Enable Controlled

M58LR128FT/B

Symbol

Alt

Parameter

Unit

85

7

95

10

t

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Min

ns

AVAV

WC

t

AVLH

(3)

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Min

50

10

0

50

10

0

ns

t

WC

AVWH

t

DVWH

DS

t

Chip Enable Low to Latch Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

Chip Enable Low to Clock Valid

ELLH

t

ELWL

CS

t

85

9

95

9

ELQV

t

ELKV

t

Output Enable High to Write Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

17

9

20

10

GHWL

t

LHAX

t

9

LLLH

(3)

Write Enable High to Address Valid

Min

0

ns

t

WHAV

(3)

t

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Min

0

ns

AH

WHAX

t

WHDX

DH

CH

t

0

WHEH

(2)

25

t

WHEL

t

Write Enable High to Output Enable Low

Write Enable High to Latch Enable Low

Write Enable High to Write Enable Low

Write Enable High to Output Valid

Min

0

ns

WHGL

t

WHLL

t

WPH

25

110

50

0

25

120

50

0

WHWL

t

WHQV

t

Write Enable Low to Write Enable High

WLWH

WP

t

Output (Status Register) Valid to V Low

QVVPL

PP

t

Output (Status Register) Valid to Write Protect Low

0

QVWPL

t

V

High to Write Enable High

PP

200

VPHWH

VPS

t

Write Enable High to V Low

WHVPL

PP

t

Write Enable High to Write Protect Low

Write Protect High to Write Enable High

WHWPL

WPHWH

Note: 1. Sampled only, not 100% tested.

2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

WHEL

software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a

different bank t is 0ns.

WHEL

3. Meaningful only if L is always kept low.

48/82

M58LR128FT, M58LR128FB

Figure 17. Write AC Waveforms, Chip Enable Controlled

49/82

M58LR128FT, M58LR128FB

Table 24. Write AC Characteristics, Chip Enable Controlled

M58LR128FT/B

Symbol

Alt

Parameter

Unit

85

50

7

95

50

10

50

0

t

Address Valid to Next Address Valid

Address Valid to Chip Enable High

Address Valid to Latch Enable High

Data Valid to Write Enable High

Min

ns

AVAV

WC

t

AVEH

WC

t

AVLH

t

50

0

DVEH

DS

AH

DH

t

Chip Enable High to Address Transition

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Clock Valid

EHAX

t

0

EHDX

t

CPH

25

0

25

0

EHEL

t

EHGL

t

0

EHWH

CH

t

9

ELKV

ELEH

t

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

Chip Enable Low to Output Valid

50

10

85

17

9

50

10

95

20

10

CP

t

ELLH

ELQV

GHEL

t

Output Enable High to Chip Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

t

LHAX

t

9

LLLH

(2)

Write Enable High to Chip Enable Low

Write Enable High to Output Valid

Write Enable Low to Chip Enable Low

Min

25

110

0

25

120

0

ns

t

WHEL

t

WHQV

t

WLEL

CS

t

Chip Enable High to V Low

200

0

200

0

EHVPL

PP

t

Chip Enable High to Write Protect Low

EHWPL

t

Output (Status Register) Valid to V Low

QVVPL

PP

Output (Status Register) Valid to Write Protect

Low

t

Min

0

ns

QVWPL

t

V

High to Chip Enable High

Min

200

ns

VPHEH

VPS

PP

t

Write Protect High to Chip Enable High

WPHEH

Note: 1. Sampled only, not 100% tested.

2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

WHEL

software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a

different bank t is 0ns.

WHEL

50/82

M58LR128FT, M58LR128FB

Figure 18. Reset and Power-up AC Waveforms

tPHWL

tPLWL

tPLEL

tPLGL

tPLLL

W, E, G, L

tPHEL

tPHGL

tPHLL

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI06976

Table 25. Reset and Power-up AC Characteristics

Symbol

Parameter

Test Condition

During Program

85

10

25

95

10

25

Unit

µs

Reset Low to

Min

t

PLWL

Write Enable Low,

Chip Enable Low,

Output Enable Low,

Latch Enable Low

t

PLEL

During Erase

µs

t

PLGL

t

Other Conditions

Min

80

ns

PLLL

Reset High to

t

PHWL

Write Enable Low

Chip Enable Low

Output Enable Low

Latch Enable Low

t

PHEL

Min

30

t

PHGL

t

PHLL

(1,2)

(3)

RP Pulse Width

Min

50

ns

µs

t

PLPH

Supply Voltages High to Reset

High

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 50ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

51/82

M58LR128FT, M58LR128FB

PACKAGE MECHANICAL

Figure 19. VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

E

E1

ddd

BALL "A1"

e

b

A

A2

A1

BGA-Z38

Note: Drawing is not to scale.

Table 26. VFBGA56 7.7x9mm - 8x7 ball array, 0.75mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.000

0.0394

0.200

0.0079

0.660

0.350

7.700

5.250

0.0260

0.0138

0.3031

0.2067

0.300

7.600

–

0.400

0.0118

0.2992

–

0.0157

D

7.800

0.3071

D1

ddd

e

–

0.080

0.0031

0.750

9.000

4.500

1.225

2.250

0.375

–

0.0295

0.3543

0.1772

0.0482

0.0886

0.0148

–

E

8.900

9.100

0.3504

0.3583

E1

FD

FE

SD

–

52/82

M58LR128FT, M58LR128FB

Figure 20. VFBGA56 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

AI08301

53/82

M58LR128FT, M58LR128FB

Figure 21. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)

1

2

3

4

5

6

7

8

START POINT

A

B

C

D

E

F

G

END POINT

AI07755

54/82

M58LR128FT, M58LR128FB

PART NUMBERING

Table 27. Ordering Information Scheme

Example:

M58LR128FT

85 ZB

6

T

Device Type

M58

Architecture

L = Multilevel, Multiple Bank, Burst Mode

Operating Voltage

R = V = 1.7V to 2.0V, V

= 1.7V to 2.0V

DDQ

DD

Device Function

128FT = 128 Mbit (x16), Top Boot

128FB = 128 Mbit (x16), Bottom Boot

Speed

85 = 85ns

95 = 95ns

Package

ZB = VFBGA56 7.7 x 9mm

Temperature Range

6 = –40 to 85°C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free Package, Standard Packing

F = Lead-Free Package, Tape & Reel Packing

Table 28. Daisy Chain Ordering Scheme

Example:

M58LR128F

-ZB T

Device Type

M58LR128F

Daisy Chain

ZB = VFBGA56 7.7 x 9mm

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free Package, Standard Packing

F = Lead-Free Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

55/82

M58LR128FT, M58LR128FB

APPENDIX A. BLOCK ADDRESS TABLES

Table 29. Top Boot Block Addresses,

M58LR128FT

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

64

5F0000-5FFFFF

5E0000-5EFFFF

5D0000-5DFFFF

5C0000-5CFFFF

5B0000-5BFFFF

5A0000-5AFFFF

590000-59FFFF

580000-58FFFF

570000-57FFFF

560000-56FFFF

550000-55FFFF

540000-54FFFF

530000-53FFFF

520000-52FFFF

510000-51FFFF

500000-50FFFF

4F0000-4FFFFF

4E0000-4EFFFF

4D0000-4DFFFF

4C0000-4CFFFF

4B0000-4BFFFF

4A0000-4AFFFF

490000-49FFFF

480000-48FFFF

470000-47FFFF

460000-46FFFF

450000-45FFFF

440000-44FFFF

430000-43FFFF

420000-42FFFF

410000-41FFFF

400000-40FFFF

3F0000-3FFFFF

3E0000-3EFFFF

3D0000-3DFFFF

3C0000-3CFFFF

3B0000-3BFFFF

3A0000-3AFFFF

390000-39FFFF

380000-38FFFF

Size

Bank

#

Address Range

(KWord)

16

64

0

7FC000-7FFFFF

7F8000-7FBFFF

7F4000-7F7FFF

7F0000-7F3FFF

7E0000-7EFFFF

7D0000-7DFFFF

7C0000-7CFFFF

7B0000-7BFFFF

7A0000-7AFFFF

790000-79FFFF

780000-78FFFF

770000-77FFFF

760000-76FFFF

750000-75FFFF

740000-74FFFF

730000-73FFFF

720000-72FFFF

710000-71FFFF

700000-70FFFF

6F0000-6FFFFF

6E0000-6EFFFF

6D0000-6DFFFF

6C0000-6CFFFF

6B0000-6BFFFF

6A0000-6AFFFF

690000-69FFFF

680000-68FFFF

670000-67FFFF

660000-66FFFF

650000-65FFFF

640000-64FFFF

630000-63FFFF

620000-62FFFF

610000-61FFFF

600000-60FFFF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

56/82

M58LR128FT, M58LR128FB

75

76

64

370000-37FFFF

360000-36FFFF

350000-35FFFF

340000-34FFFF

330000-33FFFF

320000-32FFFF

310000-31FFFF

300000-30FFFF

2F0000-2FFFFF

2E0000-2EFFFF

2D0000-2DFFFF

2C0000-2CFFFF

2B0000-2BFFFF

2A0000-2AFFFF

290000-29FFFF

280000-28FFFF

270000-27FFFF

260000-26FFFF

250000-25FFFF

240000-24FFFF

230000-23FFFF

220000-22FFFF

210000-21FFFF

200000-20FFFF

1F0000-1FFFFF

1E0000-1EFFFF

1D0000-1DFFFF

1C0000-1CFFFF

1B0000-1BFFFF

1A0000-1AFFFF

190000-19FFFF

180000-18FFFF

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

64

170000-17FFFF

160000-16FFFF

150000-15FFFF

140000-14FFFF

130000-13FFFF

120000-12FFFF

110000-11FFFF

100000-10FFFF

0F0000-0FFFFF

0E0000-0EFFFF

0D0000-0DFFFF

0C0000-0CFFFF

0B0000-0BFFFF

0A0000-0AFFFF

090000-09FFFF

080000-08FFFF

070000-07FFFF

060000-06FFFF

050000-05FFFF

040000-04FFFF

030000-03FFFF

020000-02FFFF

010000-01FFFF

000000-00FFFF

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

Note: There are two Bank Regions: Bank Region 1 contains all the

banks that are made up of main blocks only; Bank Region 2

contains the banks that are made up of the parameter and

main blocks (Parameter Bank).

99

100

101

102

103

104

105

106

57/82

M58LR128FT, M58LR128FB

Table 30. Bottom Boot Block Addresses,

M58LR128FB

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

64

570000-57FFFF

560000-56FFFF

550000-55FFFF

540000-54FFFF

530000-53FFFF

520000-52FFFF

510000-51FFFF

500000-50FFFF

4F0000-4FFFFF

4E0000-4EFFFF

4D0000-4DFFFF

4C0000-4CFFFF

4B0000-4BFFFF

4A0000-4AFFFF

490000-49FFFF

480000-48FFFF

470000-47FFFF

460000-46FFFF

450000-45FFFF

440000-44FFFF

430000-43FFFF

420000-42FFFF

410000-41FFFF

400000-40FFFF

3F0000-3FFFFF

3E0000-3EFFFF

3D0000-3DFFFF

3C0000-3CFFFF

3B0000-3BFFFF

3A0000-3AFFFF

390000-39FFFF

380000-38FFFF

370000-37FFFF

360000-36FFFF

350000-35FFFF

340000-34FFFF

330000-33FFFF

320000-32FFFF

310000-31FFFF

300000-30FFFF

Size

Bank

#

Address Range

(KWord)

64

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

7F0000-7FFFFF

7E0000-7EFFFF

7D0000-7DFFFF

7C0000-7CFFFF

7B0000-7BFFFF

7A0000-7AFFFF

790000-79FFFF

780000-78FFFF

770000-77FFFF

760000-76FFFF

750000-75FFFF

740000-74FFFF

730000-73FFFF

720000-72FFFF

710000-71FFFF

700000-70FFFF

6F0000-6FFFFF

6E0000-6EFFFF

6D0000-6DFFFF

6C0000-6CFFFF

6B0000-6BFFFF

6A0000-6AFFFF

690000-69FFFF

680000-68FFFF

670000-67FFFF

660000-66FFFF

650000-65FFFF

640000-64FFFF

630000-63FFFF

620000-62FFFF

610000-61FFFF

600000-60FFFF

5F0000-5FFFFF

5E0000-5EFFFF

5D0000-5DFFFF

5C0000-5CFFFF

5B0000-5BFFFF

5A0000-5AFFFF

590000-59FFFF

580000-58FFFF

98

97

96

95

94

93

92

91

58/82

M58LR128FT, M58LR128FB

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

64

2F0000-2FFFFF

2E0000-2EFFFF

2D0000-2DFFFF

2C0000-2CFFFF

2B0000-2BFFFF

2A0000-2AFFFF

290000-29FFFF

280000-28FFFF

270000-27FFFF

260000-26FFFF

250000-25FFFF

240000-24FFFF

230000-23FFFF

220000-22FFFF

210000-21FFFF

200000-20FFFF

1F0000-1FFFFF

1E0000-1EFFFF

1D0000-1DFFFF

1C0000-1CFFFF

1B0000-1BFFFF

1A0000-1AFFFF

190000-19FFFF

180000-18FFFF

170000-17FFFF

160000-16FFFF

150000-15FFFF

140000-14FFFF

130000-13FFFF

120000-12FFFF

110000-11FFFF

1F0000-1FFFFF

18

17

16

15

14

13

12

11

10

9

64

16

0F0000-0FFFFF

0E0000-0EFFFF

0D0000-0DFFFF

0C0000-0CFFFF

0B0000-0BFFFF

0A0000-0AFFFF

090000-09FFFF

080000-08FFFF

070000-07FFFF

060000-06FFFF

050000-05FFFF

040000-04FFFF

030000-03FFFF

020000-02FFFF

010000-01FFFF

00C000-00FFFF

008000-00BFFF

004000-007FFF

000000-003FFF

8

7

6

5

4

3

2

1

0

Note: There are two Bank Regions: Bank Region 2 contains all the

banks that are made up of main blocks only; Bank Region 1

contains the banks that are made up of the parameter and

main blocks (Parameter Bank).

59/82

M58LR128FT, M58LR128FB

APPENDIX B. COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

When the Read CFI Query Command is issued

the device enters CFI Query mode and the data

structure is read from the memory. Tables 31, 32,

33, 34, 35, 36, 37, 38, 39 and 40 show the ad-

dresses used to retrieve the data. The Query data

is always presented on the lowest order data out-

puts (DQ0-DQ7), the other outputs (DQ8-DQ15)

are set to 0.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Figure 5., Protection Register Memory

Map). This area can be accessed only in Read

mode by the final user. It is impossible to change

the security number after it has been written by

ST. Issue a Read Array command to return to

Read mode.

Table 31. Query Structure Overview

Offset

000h

010h

01Bh

027h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

CFI Query Identification String

System Interface Information

Device Geometry Definition

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Lock Protection Register

Unique device Number and

User Programmable OTP

080h

Security Code Area

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 32, 33, 34, and 35. Query data is always presented on the lowest order data outputs.

Table 32. CFI Query Identification String

Offset

Sub-section Name

Description

Value

000h

0020h

Manufacturer Code

Device Code

ST

88C4h

88C5h

Top

Bottom

001h

002h

003h

Reserved

0051h

Reserved

004h-00Fh

010h

"Q"

"R"

"Y"

011h

0052h

Query Unique ASCII String "QRY"

012h

0059h

013h

0003h

Primary Algorithm Command Set and Control Interface ID code 16

bit ID code defining a specific algorithm

014h

0000h

015h

offset = P = 000Ah

0001h

Address for Primary Algorithm extended Query table (see Table

34.)

p = 10Ah

NA

016h

017h

0000h

Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported

018h

0000h

019h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

NA

01Ah

60/82

M58LR128FT, M58LR128FB

Table 33. CFI Query System Interface Information

Offset

Data

Description

Value

V

Logic Supply Minimum Program/Erase or Write voltage

DD

01Bh

0017h

1.7V

2V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

DD

01Ch

01Dh

01Eh

0020h

0085h

0095h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

PP

8.5V

9.5V

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

[Programming] Supply Maximum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

n

01Fh

020h

021h

022h

023h

024h

025h

026h

0004h

0009h

000Bh

0000h

0003h

0001h

0000h

16µs

512µs

2s

Typical time-out per single byte/word program = 2 µs

n

Typical time-out for Buffer Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

128µs

1024µs

4s

Maximum time-out for word program = 2 times typical

n

Maximum time-out for Buffer Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

61/82

M58LR128FT, M58LR128FB

Table 34. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

027h

0018h

16 MBytes

Device Size = 2 in number of bytes

028h

029h

0001h

0000h

x16

Async.

Flash Device Interface Code description

02Ah

02Bh

0006h

0000h

n

64 Bytes

Maximum number of bytes in multi-byte program or page = 2

02Ch

0002h

Number of identical sized erase block regions within the device

bit 7 to 0 = x = number of Erase Block Regions

2

127

02Dh

02Eh

007Eh

0000h

Region 1 Information

Number of identical-size erase blocks = 007Eh+1

02Fh

030h

0000h

0002h

Region 1 Information

Block size in Region 1 = 0200h * 256 Byte

128 KByte

4

031h

032h

0003h

0000h

Region 2 Information

Number of identical-size erase blocks = 0003h+1

033h

034h

0080h

0000h

Region 2 Information

Block size in Region 2 = 0080h * 256 Byte

32 KByte

NA

035h

038h

Reserved Reserved for future erase block region information

02Dh

02Eh

0003h

0000h

Region 1 Information

Number of identical-size erase block = 0003h+1

4

02Fh

030h

0080h

0000h

Region 1 Information

Block size in Region 1 = 0080h * 256 bytes

32 KBytes

127

031h

032h

007Eh

0000h

Region 2 Information

Number of identical-size erase block = 007Eh+1

033h

034h

0000h

0002h

Region 2 Information

Block size in Region 2 = 0200h * 256 bytes

128 KBytes

NA

035h

038h

Reserved Reserved for future erase block region information

62/82

M58LR128FT, M58LR128FB

Table 35. Primary Algorithm-Specific Extended Query Table

Offset

Data

0050h

0052h

0049h

0031h

0033h

00E6h

0003h

0000h

Description

Value

(P)h = 10Ah

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

"R"

"I"

(P+3)h = 10Dh

(P+4)h = 10Eh

(P+5)h = 10Fh

Major version number, ASCII

Minor version number, ASCII

"1"

"3"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

Chip Erase supported

(1 = Yes, 0 = No)

No

Yes

No

(P+7)h = 111h

(P+8)h = 112h

Erase Suspend supported

Program Suspend supported

Legacy Lock/Unlock supported

Queued Erase supported

Instant individual block locking supported (1 = Yes, 0 = No)

Protection bits supported

Page mode read supported

Synchronous read supported

Simultaneous operation supported

No

Yes

(1 = Yes, 0 = No)

bit 10 to 31Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31

bit field of optional features follows at the end of the bit-30

field.

(P+9)h = 113h

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query

Yes

bit 0

Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’

(P+A)h = 114h

(P+B)h = 115h

0003h

0000h

Block Protect Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block protect Status Register Lock/Unlock

bit active

(1 = Yes, 0 = No)

Yes

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

V

Logic Supply Optimum Program/Erase voltage (highest performance)

DD

(P+C)h = 116h

(P+D)h = 117h

0018h

0090h

1.8V

9V

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

63/82

M58LR128FT, M58LR128FB

Table 36. Protection Register Information

Offset

Data

Description

Value

Number of protection register fields in JEDEC ID space. 0000h indicates that

256 fields are available.

(P+E)h = 118h

0002h

2

(P+F)h = 119h

(P+10)h = 11Ah

(P+11)h = 11Bh

(P+12)h = 11Ch

(P+13)h = 11Dh

(P+14)h = 11Eh

(P+15)h = 11Fh

(P+16)h = 120h

(P+17)h = 121h

(P+18)h = 122h

(P+19)h = 123h

(P+1A)h = 124h

(P+1B)h = 125h

(P+1C)h = 126h

0080h

0000h

0003h

0089h

0000h

0010h

0000h

0004h

80h

00h

8 Bytes

89h

00h

0

Protection Field 1: Protection Description

Bits 0-7 Lower byte of protection register address

Bits 8-15 Upper byte of protection register address

n

Bits 16-23 2 bytes in factory pre-programmed region

n

Bits 24-31 2 bytes in user programmable region

Protection Register 2: Protection Description

Bits 0-31 protection register address

Bits 32-39 n number of factory programmed regions (lower byte)

Bits 40-47 n number of factory programmed regions (upper byte)

n

Bits 48-55 2 bytes in factory programmable region

Bits 56-63 n number of user programmable regions (lower byte)

Bits 64-71 n number of user programmable regions (upper byte)

n

Bits 72-79 2 bytes in user programmable region

0

16

0

16

Table 37. Burst Read Information

Offset

Data

Description

Value

(P+1D)h = 127h

0003h

Page-mode read capability

8 Bytes

n

bits 0-7

’n’ such that 2 HEX value represents the number of read-

page bytes. See offset 28h for device word width to

determine page-mode data output width.

(P+1E)h = 128h

(P+1F)h = 129h

0004h

0001h

Number of synchronous mode read configuration fields that follow.

Synchronous mode read capability configuration 1

4

bit 3-7

Reserved

n+1

bit 0-2

’n’ such that 2

HEX value represents the maximum

number of continuous synchronous reads when the device is

configured for its maximum word width. A value of 07h

indicates that the device is capable of continuous linear

bursts that will output data until the internal burst counter

reaches the end of the device’s burstable address space.

This field’s 3-bit value can be written directly to the read

configuration register bit 0-2 if the device is configured for its

maximum word width. See offset 28h for word width to

determine the burst data output width.

(P+20)h = 12Ah

(P-21)h = 12Bh

(P+22)h = 12Ch

0002h

0003h

0007h

Synchronous mode read capability configuration 2

Synchronous mode read capability configuration 3

Synchronous mode read capability configuration 4

8

16

Cont.

64/82

M58LR128FT, M58LR128FB

Table 38. Bank and Erase Block Region Information

Flash memory (top)

Flash memory (bottom)

Description

Offset

Data

Offset

Data

(P+23)h = 12Dh

02h

(P+23)h = 12Dh

02h

Number of Bank Regions within the device

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, see Table 29. and Table 30.

Table 39. Bank and Erase Block Region 1 Information

Flash memory (top)

Flash memory (bottom)

Description

Offset

Data

0Fh

00h

Offset

Data

01h

00h

(P+24)h = 12Eh

(P+25)h = 12Fh

(P+24)h = 12Eh

(P+25)h = 12Fh

Number of identical banks within Bank Region 1

Number of program or erase operations allowed in Bank

Region 1:

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+26)h = 130h

(P+27)h = 131h

(P+28)h = 132h

11h

00h

(P+26)h = 130h

(P+27)h = 131h

(P+28)h = 132h

11h

00h

Number of program or erase operations allowed in other banks

while a bank in same region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other banks

while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Types of erase block regions in Bank Region 1

n = number of erase block regions with contiguous same-size

(P+29)h = 133h

01h

(P+29)h = 133h

02h

erase blocks.

(2)

Symmetrically blocked banks have one blocking region

.

(P+2A)h = 134h

(P+2B)h = 135h

(P+2C)h = 136h

(P+2D)h = 137h

(P+2E)h = 138h

(P+2F)h = 139h

77h

00h

02h

64h

00h

(P+2A)h = 134h

(P+2B)h = 135h

(P+2C)h = 136h

(P+2D)h = 137h

(P+2E)h = 138h

(P+2F)h = 139h

03h

00h

80h

00h

64h

00h

Bank Region 1 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000

Bank Region 1 (Erase Block Type 1): BIts per cell, internal

ECC

(P+30)h = 13Ah

(P+31)h = 13Bh

02h

03h

(P+30)h = 13Ah

(P+31)h = 13Bh

02h

03h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

Bank Region 1 (Erase Block Type 1): Page mode and

Synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

65/82

M58LR128FT, M58LR128FB

Flash memory (top)

Offset Data

Flash memory (bottom)

Description

Offset

Data

06h

00h

02h

64h

00h

(P+32)h = 13Ch

(P+33)h = 13Dh

(P+34)h = 13Eh

(P+35)h = 13Fh

(P+36)h = 140h

(P+37)h = 141h

Bank Region 1 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 1 (Erase Block Type 2)

Minimum block erase cycles × 1000

Bank Regions 1 (Erase Block Type 2): BIts per cell, internal

ECC

(P+38)h = 142h

(P+39)h = 143h

02h

03h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

Bank Region 1 (Erase Block Type 2): Page mode and

Synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, There are two Bank Regions, see Table 29. and Table 30.

Table 40. Bank and Erase Block Region 2 Information

Flash memory (top)

Flash memory (bottom)

Description

Offset

Data

01h

00h

Offset

Data

0Fh

00h

(P+32)h = 13Ch

(P+33)h = 13Dh

(P+3A)h = 144h

(P+3B)h = 145h

Number of identical banks within Bank Region 2

Number of program or erase operations allowed in Bank

Region 2:

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+34)h = 13Eh

(P+35)h = 13Fh

(P+36)h = 140h

(P+37)h = 141h

11h

00h

02h

(P+3C)h = 146h

(P+3D)h = 147h

(P+3E)h = 148h

(P+3F)h = 149h

11h

00h

01h

Number of program or erase operations allowed in other

banks while a bank in this region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other

banks while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Types of erase block regions in Bank Region 2

n = number of erase block regions with contiguous same-size

erase blocks.

(2)

Symmetrically blocked banks have one blocking region.

(P+38)h = 142h

(P+39)h = 143h

(P+3A)h = 144h

(P+3B)h = 145h

06h

00h

02h

(P+40)h = 14Ah

(P+41)h = 14Bh

(P+42)h = 14Ch

(P+43)h = 14Dh

77h

00h

02h

Bank Region 2 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

66/82

M58LR128FT, M58LR128FB

Flash memory (top)

Flash memory (bottom)

Description

Offset

Data

64h

00h

Offset

Data

64h

00h

(P+3C)h = 146h

(P+3D)h = 147h

(P+44)h = 14Eh

(P+45)h = 14Fh

Bank Region 2 (Erase Block Type 1)

Minimum block erase cycles × 1000

Bank Region 2 (Erase Block Type 1): BIts per cell, internal

ECC

(P+3E)h = 148h

(P+3F)h = 149h

02h

03h

(P+46)h = 150h

(P+47)h = 151h

02h

03h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

Bank Region 2 (Erase Block Type 1):Page mode and

Synchronous mode capabilities (defined in Table 37.)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+40)h = 14Ah

(P+41)h = 14Bh

(P+42)h = 14Ch

(P+43)h = 14Dh

(P+44)h =14Eh

(P+45)h = 14Fh

03h

00h

80h

00h

64h

00h

Bank Region 2 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000

Bank Region 2 (Erase Block Type 2): BIts per cell, internal

ECC

(P+46)h = 150h

(P+47)h = 151h

02h

03h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

Bank Region 2 (Erase Block Type 2): Page mode and

Synchronous mode capabilities (defined in Table 37.)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+48)h = 152h

(P+49)h = 153h

(P+48)h = 152h

(P+43)h = 153h

Feature Space definitions

Reserved

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, There are two Bank Regions, see Table 29. and Table 30.

67/82

M58LR128FT, M58LR128FB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 22. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (addressToProgram, 0x40);

/*writeToFlash (addressToProgram, 0x10);*/

/*see note (3)*/

Write 40h or 10h (3)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register (3)

status_register=readFlash (addressToProgram);

"see note (3)";

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

V

Invalid

if (status_register.SR3==1) /*V

invalid error */

PP

SR3 = 0

YES

Error (1, 2)

error_handler ( ) ;

NO

Program

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

SR4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06170b

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Any address within the bank can equally be used.

68/82

M58LR128FT, M58LR128FB

Figure 23. Buffer Program Flowchart and Pseudo Code

Start

Buffer Program E8h

Command,

Block Address

Write n⁽¹⁾

,

Block Address

Write Buffer Data,

Start Address

X = 0

YES

X = n

NO

Write Next Buffer Data,

(2)

Next Program Address

X = X + 1

Program

Buffer to Flash

Confirm D0h

Read Status

Register

NO

SR7 = 1

YES

Full Status

Register Check⁽³⁾

End

AI07301b

69/82

M58LR128FT, M58LR128FB

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

SR2 = 1

Program Complete

Write FFh

if (status_register.SR2==0) /*program completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ;

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Read Data

YES

}

else

Write FFh

{ writeToFlash (bank_address, 0xFF) ;

Read data from

another address

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

writeToFlash (bank_address, 0x70) ;

/*read status register to check if program has completed */

Write 70h⁽¹⁾

}

Program Continues with

Bank in Read Status

Register Mode

}

AI10117b

Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.

70/82

M58LR128FT, M58LR128FB

Figure 25. Block Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (blockToErase, 0x20) ;

/*see note (2) */

Write 20h (2)

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A22 are significant */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register (2)

status_register=readFlash (blockToErase) ;

/* see note (2) */

/* E or G must be toggled*/

NO

SR7 = 1

} while (status_register.SR7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.SR3==1) /*V_PPinvalid error */

error_handler ( ) ;

PP

Error (1)

SR3 = 0

YES

if ( (status_register.SR4==1) && (status_register.SR5==1) )

/* command sequence error */

Command

Sequence Error (1)

SR4, SR5 = 1

NO

error_handler ( ) ;

if ( (status_register.SR5==1) )

/* erase error */

SR5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI10524

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

2. Any address within the bank can equally be used.

71/82

M58LR128FT, M58LR128FB

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

Write 70h

writeToFlash (bank_address, 0xB0) ;

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

NO

} while (status_register.SR7== 0) ;

SR7 = 1

YES

SR6 = 1

Erase Complete

Write FFh

if (status_register.SR6==0) /*erase completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ;

Read Data

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

YES

}

else

Write FFh

{ writeToFlash (bank_address, 0xFF) ;

read_program_data ( );

Read data from another block

or

Program/Protection Register Program

or

/*read or program data from another block*/

Block Lock/Unlock/Lock-Down

writeToFlash (bank_address, 0xD0) ;

/*write 0xD0 to resume erase*/

Write D0h

writeToFlash (bank_address, 0x70) ;

/*read status register to check if erase has completed */

Write 70h⁽¹⁾

}

Erase Continues with

Bank in Read Status

Register Mode

AI10116b

Note: The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.

72/82

M58LR128FT, M58LR128FB

Figure 27. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

writeToFlash (address, 0x60) ; /*configuration setup*/

Write 60h (1)

/* see note (1) */

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (address, 0x90) ;

/*see note (1) */

Write 90h (1)

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/

/*see note (1) */

Write FFh (1)

}

End

AI06176b

Note: 1. Any address within the bank can equally be used.

73/82

M58LR128FT, M58LR128FB

Figure 28. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

Write C0h (3)

writeToFlash (addressToProgram, 0xC0) ;

/*see note (3) */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register (3)

status_register=readFlash (addressToProgram) ;

/* see note (3) */

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

SR3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

SR4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06177b

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Any address within the bank can equally be used.

74/82

M58LR128FT, M58LR128FB

Figure 29. Buffer Enhanced Factory Program Flowchart and Pseudo Code

SETUP PHASE Buffer_Enhanced_Factory_Program_Command

(start_address, DataFlow[]) {

Start

Write 80h to

Address WA1

writeToFlash (start_address, 0x80) ;

Write D0h to

Address WA1

writeToFlash (start_address, 0xD0) ;

do{

do {

Read Status

Register

status_register = readFlash (start_address);

if (status_register.SR4==1) { /*error*/

if (status_register.SR3==1) /*V_PPerror */

error_handler ( ) ;

NO

SR7 = 0

YES

if (status_register.SR1==1) /* Locked Block */

NO

error_handler ( ) ;

PROGRAM AND

VERIFY PHASE

Initialize count

X = 0

SR4 = 1

}

while (status_register.SR7==1)

x=0; /* initialize count */

Write PDX

Address WA1

Read Status Register

SR3 and SR1for errors

Increment Count

X = X + 1

do {

Exit

writeToFlash (start_address, DataFlow[x]);

x++;

}while (x<32)

NO

X = 32

YES

do {

status_register = readFlash (start_address);

}while (status_register.SR0==1)

Read Status

Register

NO

SR0 = 0

YES

Last data?

} while (not last data)

YES

Write FFFFh to

Address = NOT WA1

writeToFlash (another_block_address, FFFFh)

do {

EXIT PHASE

Read Status

Register

status_register = readFlash (start_address)

}while (status_register.SR7==0)

full_status_register_check();

NO

SR7 = 1

YES

Full Status Register

Check

End

AI07302B

75/82

M58LR128FT, M58LR128FB

APPENDIX D. COMMAND INTERFACE STATE TABLES

Table 41. Command Interface States - Modify Table, Next State

Command Input

Erase Confirm

Buffer

Program,

Program/

Erase

Suspend

(B0h)

Read

Block

Erase,

Setup

(3,4)

P/E Resume,

Block Unlock

confirm,

BEFP Confirm

(3,4)

Clear

status

Register

(5)

Read

Status

Register

(70h)

Electronic

Signature,

Read CFI

Query

Program Buffer

Setup Program

Read

BEFP

Setup

(80h)

Current CI State

(2)

Array

(FFh)

(3,4)

(10/40h)

(E8h)

(20h)

(50h)

(90h, 98h)

(D0h)

Buffer

Program

Setup

Program

Setup

Erase

Setup

BEFP

Setup

Ready

(unlock block)

Lock/CR Setup

Ready (Lock Error)

Setup

OTP

OTP Busy

Busy

Setup

Program Busy

Program

Suspend

Program

Busy

Program Busy

Program Suspend

Program Busy

Program Suspend

Suspend

Setup

Program Busy

Buffer Program Load 1 (give word count load (N-1));

Buffer

Load 1

if N=0 go to Buffer Program Confirm. Else (N not =0) go to Buffer Program Load 2 (data load)

Buffer

Load 2

Buffer Program Confirm when count =0; Else Buffer Program Load 2

(note: Buffer Program will fail at this point if any block address is different from the first address)

Buffer Program

Buffer

Program

Confirm

Ready (error)

Busy

Buffer

Busy

Buffer Program Busy

Program

Suspend

Buffer Program Busy

Buffer Program

Busy

Suspend

Setup

Buffer Program Suspend

Ready (error)

Buffer Program Suspend

Ready (error)

Erase Busy

Erase

Suspend

Busy

Erase Busy

Buffer

Program Program

Erase

Suspend

in Erase

Suspend

Setup in

Erase

Erase Suspend

Erase Busy

Erase Suspend

Suspend

Setup

Busy

Program Busy in Erase Suspend

Program

Suspend in

Erase

Program

in Erase

Suspend

Program Busy in Erase Suspend

Suspend

Program Busy

in Erase

Suspend

Program Suspend in Erase Suspend

Suspend

76/82

M58LR128FT, M58LR128FB

Command Input

Erase Confirm

P/E Resume,

Block Unlock

confirm,

BEFP Confirm

(3,4)

Buffer

Program,

Program/

Erase

Suspend

(B0h)

Read

Block

Erase,

Setup

(3,4)

Clear

status

Register

(5)

Read

Status

Register

(70h)

Electronic

Signature,

Read CFI

Query

Program Buffer

Setup Program

Read

BEFP

Setup

(80h)

Current CI State

(2)

Array

(FFh)

(3,4)

(10/40h)

(E8h)

(20h)

(50h)

(90h, 98h)

(D0h)

Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N

not =0) go to Buffer Program Load 2

Setup

Buffer

Load 1

Buffer Program Load 2 in Erase Suspend (data load)

Buffer

Load 2

Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note:

Buffer Program will fail at this point if any block address is different from the first address)

Buffer Program

Busy in Erase

Suspend

Buffer

Program

in Erase

Suspend

Confirm

Ready (error)

Buffer

Program

Suspend in

Erase

Buffer Program Busy in Erase

Suspend

Busy

Buffer Program Busy in Erase Suspend

Suspend

Buffer Program

Suspend

Buffer Program Suspend in Erase Suspend

Busy in Erase Buffer Program Suspend in Erase Suspend

Suspend

Lock/CR Setup

in Erase Suspend

Erase Suspend (Lock Error)

Ready (error)

Erase Suspend

BEFP Busy

Erase Suspend (Lock Error)

Ready (error)

Setup

Busy

Buffer

EFP

(6)

BEFP Busy

Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con-

troller.

2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data out-

put.

3. The two cycle command should be issued to the same bank address.

4. If the P/E.C. is active, both cycles are ignored.

5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.

6. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other

commands are treated as data.

77/82

M58LR128FT, M58LR128FB

Table 42. Command Interface States - Modify Table, Next Output State

Command Input

Erase

Confirm

P/E

Resume,

Block

Unlock

confirm,

BEFP

Confirm

(4,5)

Read

Block

Erase,

Setup

(4,5)

(20h)

Program/ Read

Erase Status

Suspend Register Register

Clear

status

Electronic

signature,

Read CFI

Query

Read Program

Buffer

Program

(E8h)

BEFP

Setup

(80h)

Current CI State

Array

(3)

Setup

(4,5)

(FFh) (10/40h)

(B0h)

(70h)

(50h)

(90h, 98h)

(D0h)

Program Setup

Erase Setup

OTP Setup

Program in Erase Suspend

BEFP Setup

BEFP Busy

Buffer Program Setup

Buffer Program Load 1

Buffer Program Load 2

Buffer Program Confirm

Status Register

Buffer Program Setup in

Erase Suspend

Buffer Program Load 1 in

Erase Suspend

Buffer Program Load 2 in

Erase Suspend

Buffer Program Confirm in

Erase Suspend

Lock/CR Setup

Lock/CR Setup in Erase

Suspend

Status

Register

OTP Busy

Ready

Program Busy

Erase Busy

Buffer Program Busy

Program/Erase Suspend

Buffer Program Suspend

Status

Register Unchanged

Output

Array

Status Register

Output Unchanged

Electronic

Signature/

CFI

Program Busy in Erase

Suspend

Buffer Program Busy in

Erase Suspend

Program Suspend in Erase

Suspend

Buffer Program Suspend in

Erase Suspend

Note: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A

bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the com-

mand issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend

on the bank output state.

2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con-

troller.

3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data out-

put.

4. The two cycle command should be issued to the same bank address.

5. If the P/E.C. is active, both cycles are ignored.

78/82

M58LR128FT, M58LR128FB

Table 43. Command Interface States - Lock Table, Next State

Command Input

Block

Lock/CR

OTP Setup Block Lock

Set CR

Confirm

(03h)

Illegal

Command Operation

WSM

Current CI State

Address

Lock-Down

Confirm

(2Fh)

(2)

Confirm

(01h)

Setup

(60h)

(3)

(WA0)

(C0h)

(5)

Completed

(XXXXh)

Lock/CR

Setup

Ready

OTP Setup

Ready

N/A

Lock/CR Setup

Ready (Lock error)

Ready

Ready (Lock error)

N/A

Setup

OTP

OTP Busy

Busy

Ready

N/A

Setup

Program Busy

Program

Busy

Suspend

Setup

Ready

N/A

Program Suspend

Buffer Program Load 1 (give word count load (N-1));

N/A

Buffer

Load 1

(6)

Exit

N/A

Buffer Program Load 2

see note

Buffer

Load 2

Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail

at this point if any block address is different from the first address)

Buffer

Program

Confirm

Busy

Ready (error)

N/A

Ready

N/A

Buffer Program Busy

Suspend

Setup

Buffer Program Suspend

Ready (error)

N/A

Busy

Erase Busy

Ready

Lock/CR

Erase

Setup in

Suspend

Erase Suspend

Erase

N/A

Suspend

Setup

Busy

Program Busy in Erase Suspend

N/A

Program in

Erase

Suspend

Erase

Suspend

Program Busy in Erase Suspend

Suspend

Setup

Program Suspend in Erase Suspend

Buffer Program Load 1 in Erase Suspend (give word count load (N-1))

Buffer

Load 1

(7)

Exit

Buffer Program Load 2 in Erase Suspend

see note

Buffer

Program in

Erase

Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase

Suspend (note: Buffer Program will fail at this point if any block address is different from the first

address)

Buffer

Load 2

N/A

Suspend

Confirm

Busy

Ready (error)

Buffer Program Busy in Erase Suspend

Buffer Program Suspend in Erase Suspend

Erase Suspend

Suspend

Lock/CR Setup

in Erase Suspend

Erase Suspend (Lock error)

Erase Suspend

N/A

(Lock error)

Setup

Ready (error)

BEFP

Busy

BEFP

(4)

Exit

BEFP Busy

(4)

Busy

Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con-

troller, WA0 = Address in a block different from first BEFP address.

2. If the P/E.C. is active, both cycles are ignored.

3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.

4. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other

commands are treated as data.

5. Illegal commands are those not defined in the command set.

6. if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load).

7. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N ≠ 0) go to Buffer Program Load 2 in Erase Suspend.

79/82

M58LR128FT, M58LR128FB

Table 44. Command Interface States - Lock Table, Next Output State

Command Input

Block

Lock/CR

OTP

Block Lock

Confirm

(01h)

Set CR

Confirm

(03h)

WSM

Operation

Completed

Illegal

Command

(5)

(4)

Current CI State

Lock-Down

Confirm

(2Fh)

BEFP Exit

(FFFFh)

(3)

Setup

(60h)

Setup

(C0h)

Program Setup

Erase Setup

OTP Setup

Program in Erase

Suspend

BEFP Setup

BEFP Busy

Buffer Program

Setup

Buffer Program

Load 1

Buffer Program

Load 2

Status Register

Buffer Program

Confirm

Buffer Program

Setup in Erase

Suspend

Buffer Program

Load 1 in Erase

Suspend

Buffer Program

Load 2 in Erase

Suspend

Buffer Program

Confirm in Erase

Suspend

Output

Unchanged

Lock/CR Setup

Status Register

Array

Status Register

Lock/CR Setup in

Erase Suspend

OTP Busy

Ready

Program Busy

Erase Busy

Buffer Program

Busy

Program/Erase

Suspend

Buffer Program

Suspend

Status

Register

Output

Unchanged

Output Unchanged

Array

Program Busy in

Erase Suspend

Buffer Program

Busy in Erase

Suspend

Program Suspend in

Erase Suspend

Buffer Program

Suspend in Erase

Suspend

Note: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A

bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the com-

mand issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend

on the bank's output state.

2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Con-

troller, WA0 = Address in a block different from first BEFP address.

3. If the P/E.C. is active, both cycles are ignored.

4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.

5. Illegal commands are those not defined in the command set.

80/82

M58LR128FT, M58LR128FB

REVISION HISTORY

Table 45. Document Revision History

Date

Version

Revision Details

07-May-2003

0.1

First Issue

Clear Status Register Command and Set Configuration Register Command clarified.

Table 15., Program, Erase Times and Endurance Cycles reformatted, and Buffer

Enhanced Factory Program timings added.

In Table 19., DC Characteristics - Currents, I

, I

and I

,

DD1 DD2 DD3 DD4 DD6

DD

values changed and 16 Word burst values added. V

and V

values modified

PPLK

PP1

in Table 20., DC Characteristics - Voltages.

08-Mar-2004

0.2

APPENDIX A., BLOCK ADDRESS TABLES reformatted. In APPENDIX

B., COMMON FLASH INTERFACE, 0 added in front of 2-digit offset values. Data

modified at address offset (P + 1D)h = 127h in Table 37., Burst Read Information.

Figure 29., Buffer Enhanced Factory Program Flowchart and Pseudo Code modified.

APPENDIX D., COMMAND INTERFACE STATE TABLES added.

Document promoted from Target Specification to Preliminary Data status.

I

values changed in Table 19., DC Characteristics - Currents.

DD6

Sub-section Name and Description at address offset 003h modified in Table 32., CFI

Query Identification String.

Figure 24., Program Suspend & Resume Flowchart and Pseudo Code and Figure

26., Erase Suspend & Resume Flowchart and Pseudo Code modified. Write to

Buffer and Program command renamed Buffer Program. Duplicate timings removed

10-Sep-2004

24-Sep-2004

0.3

1.0

from Figure 12., Synchronous Burst Read AC Waveforms and t

timing line

KHTX

modified. Table 43., Command Interface States - Lock Table, Next State modified.

Document status promoted from Preliminary Data to full Datasheet.

Figure 24., Program Suspend & Resume Flowchart and Pseudo Code, Figure

25., Block Erase Flowchart and Pseudo Code and Figure 26., Erase Suspend &

Resume Flowchart and Pseudo Code modified. Small text changes.

81/82

M58LR128FT, M58LR128FB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

82/82


型号：	M58LR128FB
厂家：	ST
描述：	128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory 128兆位（8MB X16 ，多银行，多层次，突发） 1.8V供应快闪记忆体
文件：	总82页 (文件大小：534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58LR128FB [STMICROELECTRONICS]

相关型号：

M58LR128FB85ZB6

M58LR128FB85ZB6E

M58LR128FB85ZB6F

M58LR128FB85ZB6T

M58LR128FB95ZB6

M58LR128FB95ZB6E

M58LR128FB95ZB6F

M58LR128FB95ZB6T

M58LR128FT

M58LR128FT85ZB6

M58LR128FT85ZB6E

M58LR128FT85ZB6F