M58LT128GSB_技术文档

M58LT128GST

M58LT128GSB

128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)

1.8V Supply Secure Flash Memories

PRELIMINARY DATA

Features Summary

■ SUPPLY VOLTAGE

BGA

– V_DD= 1.7 to 2.0V for program, erase and

read

– V_DDQ= 2.7 to 3.6V for I/O Buffers

– V_PP= 9V for fast program

TBGA64 (ZA)

10 x 13mm

■ SYNCHRONOUS / ASYNCHRONOUS READ

– Random Access: 110ns

– Asynchronous Page Read: 25ns.

– Synchronous Burst Read: 52MHz

■ 100,000 PROGRAM/ERASE CYCLES per

■ SYNCHRONOUS BURST READ SUSPEND

■ PROGRAMMING TIME

BLOCK

■ ELECTRONIC SIGNATURE

– 10µs typical Word program time using

Buffer Enhanced Factory Program

command

– Manufacturer Code: 20h

– Device Code:

M58LT128GST: 88C6h

M58LT128GSB: 88C7h

■ MEMORY ORGANIZATION

– Multiple Bank Memory Array:

8 Mbit Banks

■ ECOPACK^®PACKAGE AVAILABLE

– Parameter Blocks (Top or Bottom location)

■ DUAL OPERATIONS

– program/erase in one Bank while read in

others

– No delay between read and write

operations

■ HARDWARE PROTECTION

– All Blocks Write Protected when V_PP≤V_PPLK

■ SECURITY

– Software Security Features

– 64-bit Unique Device Identifier

– 2112 bits of User-Programmable OTP

memory

■ COMMON FLASH INTERFACE (CFI)

Rev 1.0

September 2005

1/98

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

M58LT128GST, M58LT128GSB

Contents

1

2

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DD

2.10.1 V_DDQSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.11

2.12

2.13

V

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PP

SS

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SSQ

3

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

3.2

3.3

3.4

3.5

3.6

Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4

Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

4.2

4.3

4.4

4.5

Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/98

M58LT128GST, M58LT128GSB

4.6

4.7

4.8

4.9

Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . 23

4.9.1 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.9.2 Program and Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.9.3 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.11.1 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.12 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . 31

Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

V

Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PP

Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . 33

6

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Wrap Burst Bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7

Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1

Asynchronous Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1.1 Asynchronous Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3/98

M58LT128GST, M58LT128GSB

7.1.2 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2

Synchronous Burst Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.1 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.2 Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8

Dual Operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . . . 45

Program and Erase times and Endurance cycles . . . . . . . . . . . . . . . . . . 47

Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9

10

11

12

13

Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Appendix B Common Flash Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Appendix C Flowcharts and Pseudo Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Appendix D Command Interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

14

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4/98

M58LT128GST, M58LT128GSB

List of tables

Table 1.

Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Standard Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Protection Register Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Wait at the Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Dual Operations Allowed In Same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Dual Operation Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Program/Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DC Characteristics - Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

DC Characteristics - Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Package Mechanical Data . . . . . . 66

Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

M58LT128GST - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

M58LT128GST - Main Bank Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

M58LT128GST - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

M58LT128GSB - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

M58LT128GSB- Main Bank Base Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

M58LT128GSB - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Burst Read Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Command Interface States - Modify Table, Next Output State. . . . . . . . . . . . . . . . . . . . . . 92

Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

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M58LT128GST, M58LT128GSB

Table 49.

Table 50.

Command Interface States - Lock Table, Next Output State . . . . . . . . . . . . . . . . . . . . . . . 95

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6/98

M58LT128GST, M58LT128GSB

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Protection Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

X-Latency and Data Output Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10. Asynchronous Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 11. Synchronous Burst Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 12. Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 13. Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14. Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 15. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 16. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 17. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 18. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Bottom View Package Outline . . . 66

Figure 19. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 20. Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 21. Program Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 22. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 24. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 25. Buffer Enhanced Factory Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . 89

7/98

1 Summary description

M58LT128GST, M58LT128GSB

1

Summary description

The M58LT128GST and M58LT128GSB are 128 Mbit (8 Mbit x16) non-volatile Secure Flash

memories.

The devices may be erased electrically at block level and programmed in-system on a Word-by-

Word basis using a 1.7 to 2.0V V_DDsupply for the circuitry and a 2.7 to 3.6V V_DDQsupply for

the Input/Output pins. An optional 9V V_PPpower supply is provided to speed up factory

programming.

The devices feature an asymmetrical block architecture and are based on a multi-level cell

technology. The memory array is organized as 131 blocks, and is divided into 8 Mbit banks.

There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank

containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords.

The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one

bank, read operations are possible in other banks. Only one bank at a time is allowed to be in

program or erase mode. It is possible to perform burst reads that cross bank boundaries. The

bank architecture is summarized in Table 2, and the memory maps are shown in Figure 3. The

Parameter Blocks are located at the top of the memory address space for the M58LT128GST,

and at the bottom for the M58LT128GSB.

Each block can be erased separately. Erase can be suspended, in order to perform a program

or read operation in any other block, and then resumed. Program can be suspended to read

data at any memory location except for the one being programmed, and then resumed. Each

block can be programmed and erased over 100,000 cycles using the supply voltage V_DD. There

is a Buffer Enhanced Factory programming command available to speed up programming.

Program and erase commands are written to the Command Interface of the memory. An

internal Program/Erase Controller takes care of the timings necessary for program and erase

operations. The end of a program or erase operation can be detected and any error conditions

identified in the Status Register. The command set required to control the memory is consistent

with JEDEC standards.

The device supports Synchronous Burst Read and Asynchronous Read and Page Read from

all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In

Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to

52MHz. The Synchronous Burst Read operation can be suspended and resumed.

The device features an Automatic Standby mode. When the bus is inactive during

Asynchronous Read operations, the device automatically switches to the Automatic Standby

mode. In this condition the power consumption is reduced to the standby value and the outputs

are still driven.

The M58LT128GST and M58LT128GSB are equipped with several features to increase data

protection:

■

Hardware Protection: all blocks are protected from program and erase operations when

the V_PP≤V_PPLK

.

■

A full set of Software Security Features described in a dedicated Application Note. Please

contact STMicroelectronics for further details.

■

64-bit Unique Device Identifier

2112 bits of User-Programmable OTP memory

8/98

M58LT128GST, M58LT128GSB

1 Summary description

The device includes 17 Protection Registers and 2 Protection Register locks, one for the first

Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection

Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit

segment containing a unique device number written by ST, and a 64 bit segment One-Time-

Programmable (OTP) by the user. The user programmable segment can be permanently

protected. Figure 4 shows the Protection Register Memory Map.

The devices are offered in TBGA64 10 x 13mm, 1mm pitch.

In order to meet environmental requirements, ST offers the M58LT128GST and M58LT128GSB

in ECOPACK^®package. ECOPACK package is Lead-free. The category of second Level

Interconnect is marked on the package and on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:

www.st.com.

The memories are supplied with all the bits erased (set to ’1’).

Figure 1. Logic Diagram

V

DD DDQ PP

16

DQ0-DQ15

WAIT

A0-A22

W

E

M58LT128GSB

M58LT128GST

G

RP

L

K

V

SSQ

SS

AI10259b

9/98

1 Summary description

M58LT128GST, M58LT128GSB

Table 1.

Signal Names

Address Inputs

A0-A22

DQ0-DQ15

Data Input/Outputs, Command Inputs

E

Chip Enable

Output Enable

Write Enable

Reset

G

W

RP

K

Clock

L

Latch Enable

Wait

WAIT

V_DD

Supply Voltage

V_DDQ

V_PP

Supply Voltage for Input/Output Buffers

Optional Supply Voltage for Fast Program & Erase and Write Protect

Ground

V_SS

V_SSQ

NC

Ground Input/Output Supply

Not Connected Internally

10/98

M58LT128GST, M58LT128GSB

1 Summary description

Figure 2. TBGA64 Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A0

A1

A5

A7

A8

V

A12

A13

V

A17

A18

A21

PP

DD

WAIT

V

E

NC

SS

A2

A6

A9

A11

RP

A14

A19

A20

A3

A4

DQ1

DQ0

NC

A10

DQ9

DQ10

DQ2

NC

A15

A16

NC

DQ8

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

NC

DQ15

NC

K

NC

G

W

A22

G

H

V

DQ6

DQ14

DQ7

DDQ

L

NC

V

NC

DD

SSQ

SS

AI10270b

Table 2.

Bank Architecture

Number

Bank Size

Parameter Blocks

Main Blocks

Parameter Bank

Bank 1

8 Mbits

4 blocks of 16 KWords

7 blocks of 64 KWords

8 blocks of 64 KWords

-

Bank 2

Bank 3

Bank 14

Bank 15

8 Mbits

-

8 blocks of 64 KWords

11/98

1 Summary description

M58LT128GST, M58LT128GSB

Figure 3. Memory Map

M58LT128GST - Top Boot Block

M58LT128GSB - Bottom Boot Block

Address lines A22-A0

000000h

00FFFFh

000000h

003FFFh

64 KWord

16 KWord

8 Main

Blocks

4 Parameter

Blocks

Bank 15

070000h

07FFFFh

00C000h

00FFFFh

010000h

01FFFFh

64 KWord

16 KWord

64 KWord

Parameter

Bank

7 Main

Blocks

070000h

07FFFFh

080000h

08FFFFh

64 KWord

600000h

60FFFFh

64 KWord

8 Main

Blocks

8 Main

Blocks

Bank 3

Bank 2

Bank 1

Bank 2

Bank 3

670000h

67FFFFh

680000h

68FFFFh

0F0000h

0FFFFFh

100000h

10FFFFh

64 KWord

8 Main

Blocks

8 Main

Blocks

6F0000h

6FFFFFh

700000h

70FFFFh

170000h

17FFFFh

180000h

18FFFFh

64 KWord

8 Main

Blocks

8 Main

Blocks

770000h

77FFFFh

780000h

78FFFFh

1F0000h

1FFFFFh

64 KWord

7 Main

Blocks

7E0000h

7EFFFFh

7F0000h

7F3FFFh

64 KWord

16 KWord

Parameter

Bank

780000h

78FFFFh

64 KWord

4 Parameter

Blocks

8 Main

Blocks

Bank 15

7FC000h

7FFFFFh

7F0000h

7FFFFFh

16 KWord

AI10261

12/98

M58LT128GST, M58LT128GSB

2 Signal descriptions

2

Signal descriptions

See Figure 1: Logic Diagram and Table 1: Signal Names, for a brief overview of the signals

connected to this device.

2.1

Address Inputs (A0-A22)

The Address Inputs select the cells in the memory array to access during Bus Read operations.

During Bus Write operations they control the commands sent to the Command Interface of the

Program/Erase Controller.

2.2

2.3

Data Input/Output (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or

input a command or the data to be programmed during a Bus Write operation.

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and sense

amplifiers. When Chip Enable is at V_ILand Reset is at V_IHthe device is in active mode. When

Chip Enable is at V_IHthe memory is deselected, the outputs are high impedance and the power

consumption is reduced to the stand-by level.

2.4

2.5

Output Enable (G)

The Output Enable input controls data outputs during the Bus Read operation of the memory.

Write Enable (W)

The Write Enable input controls the Bus Write operation of the memory’s Command Interface.

The data and address inputs are latched on the rising edge of Chip Enable or Write Enable

whichever occurs first.

2.6

Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at V_IL, the memory is

in reset mode: the outputs are high impedance and the current consumption is reduced to the

Reset Supply Current I_DD2. Refer to Table 20: DC Characteristics - Currents, for the value of

I_DD2.After Reset all blocks are in the Protected state and the Configuration Register is reset.

When Reset is at V_IH, the device is in normal operation. Exiting reset mode the device enters

asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required

to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to

V

_RPH(refer to Table 21: DC Characteristics - Voltages).

13/98

2 Signal descriptions

M58LT128GST, M58LT128GSB

2.7

2.8

Latch Enable (L)

Latch Enable latches the A0-A22 address bits on its rising edge. The address latch is

transparent when Latch Enable is at V_ILand it is inhibited when Latch Enable is at V_IH.

Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read

operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at V_IL. Clock is ignored during asynchronous read

and in write operations.

2.9

Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the

output bus are valid. This output is high impedance when Chip Enable is at V_IHor Reset is at

V_IL. It can be configured to be active during the wait cycle or one clock cycle in advance. The

WAIT signal is forced deasserted when Output Enable is at V_IH.

2.10 V Supply Voltage

DD

V_DDprovides the power supply to the internal core of the memory device. It is the main power

supply for all operations (Read, Program and Erase).

2.10.1 V

Supply Voltage

DDQ

V_DDQprovides the power supply to the I/O pins and enables all Outputs to be powered

independently from V_DD. V_DDQcan be tied to V_DDor can use a separate supply.

2.11 V Program Supply Voltage

PP

The V_PPpin is both a power supply and a write protect pin. The functions are selected by the

voltage range applied to the pin.

When V_PPis lower than V_PPLK, it is seen as a write protect pin protecting the whole memory

array. Program and erase operations on all blocks are ignored while V_PPis Low.

When V_PPis Higher than V_PP1, the memory reverts to the previous protection state of the

memory array. Program and erase operations can now modify the data in any block (refer to

Table 21: DC Characteristics - Voltages for V_PPLKand V_PP1values). V_PPis only sampled at the

beginning of a program or erase; a change in its value after the operation has started does not

have any effect and program or erase operations continue.

If V_PPis in the range of V_PPHit acts as a power supply pin. In this condition V_PPmust be stable

until the Program/Erase algorithm is completed.

The V_PPpin must not be left floating or unconnected or the device may become unreliable. A

0.1µF capacitor should be connected between the V_PPpin and the V_SSGround pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the

currents required during Unlock Bypass Program, I_PP.

14/98

M58LT128GST, M58LT128GSB

2 Signal descriptions

2.12 V Ground

SS

V_SSground is the reference for the core supply. It must be connected to the system ground.

2.13 V

Ground

SSQ

V_SSQground is the reference for the input/output circuitry driven by V_DDQ. V_SSQmust be

connected to V_SS

Note: Each device in a system should have V_DD, V_DDQand V_PPdecoupled with a 0.1µF

ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should

be as close as possible to the package). See Figure 8: AC Measurement Load Circuit. The

PCB track widths should be sufficient to carry the required V_PPprogram and erase currents.

15/98

3 Bus operations

M58LT128GST, M58LT128GSB

3

Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus Write,

Address Latch, Output Disable, Standby and Reset. See Table 3: Bus Operations, for a

summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory

and do not affect Bus Write operations.

3.1

3.2

3.3

Bus Read

Bus Read operations are used to output the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output

Enable must be at V_ILin order to perform a read operation. The Chip Enable input should be

used to enable the device. Output Enable should be used to gate data onto the output. The

data read depends on the previous command written to the memory (see Command Interface

section). See Figure 9, Figure 11 and Figure 12 Read AC Waveforms, and Table 22 and

Table 23 Read AC Characteristics, for details of when the output becomes valid.

Bus Write

Bus Write operations write Commands to the memory or latch Input Data to be programmed. A

bus write operation is initiated when Chip Enable and Write Enable are at V_ILwith Output

Enable at V_IH. Commands, Input Data and Addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the

write operation by toggling Latch Enable. In this case the Latch Enable should be tied to V_IH

during the bus write operation. See Figure 15 and Figure 16, Write AC Waveforms, and

Table 24 and Table 25, Write AC Characteristics, for details of the timing requirements.

Address Latch

Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at

V_ILduring address latch operations. The addresses are latched on the rising edge of Latch

Enable.

3.4

3.5

Output Disable

The outputs are high impedance when the Output Enable is at V_IH.

Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current

consumption. The memory is in standby when Chip Enable and Reset are at V_IH. The power

consumption is reduced to the standby level I_DD3and the outputs are set to high impedance,

independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V_IH

during a program or erase operation, the device enters Standby mode when finished.

16/98

M58LT128GST, M58LT128GSB

3 Bus operations

3.6

Reset

During Reset mode the memory is deselected and the outputs are high impedance. The

memory is in Reset mode when Reset is at V_IL. The power consumption is reduced to the

Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If

Reset is pulled to V_SSduring a Program or Erase, this operation is aborted and the memory

content is no longer valid.

Table 3.

Bus Operations

Operation⁽¹⁾

WAIT⁽²⁾

E

G

W

L

RP

DQ15-DQ0

V_IL

V_IH

X

V_IL

V_IH

X

V_IH

V_IL

V_IH

V_IL

V_IH

X

V_IH

V_IL

Bus Read

Bus Write

Data Output

Data Input

Address Input

Hi-Z

Address Latch

Output Disable

Standby

X

V_IH

X

Hi-Z

Reset

X

Hi-Z

1. X = Don't care.

2. WAIT signal polarity is configured using the Set Configuration Register command.

17/98

4 Command Interface

M58LT128GST, M58LT128GSB

4

Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface. Commands

consist of one or more sequential Bus Write operations. An internal Program/Erase Controller

handles all timings and verifies the correct execution of the program and erase commands. The

Program/Erase Controller provides a Status Register whose output may be read at any time to

monitor the progress or the result of the operation.

The Command Interface is reset to read mode when power is first applied, when exiting from

Reset or whenever V_DDis lower than V_LKO. Command sequences must be followed exactly.

Any invalid combination of commands will be ignored.

Refer to Table 4: Command Codes, Table 5: Standard Commands, Table 6: Factory Program

Command, and Appendix D: Command Interface state tables, for a summary of the Command

Interface.

Note: The security features are described in a dedicated Application Note. Please contact

STMicroelectronics for further details.

Table 4.

Command Codes

Hex Code

Command

Set Configuration Register Confirm

03h

10h

20h

40h

50h

70h

80h

90h

98h

B0h

C0h

D0h

E8h

FFh

Alternative Program Setup

Block Erase Setup

Program Setup

Clear Status Register

Read Status Register

Buffer Enhanced Factory Program

Read Electronic Signature

Read CFI Query

Program/Erase Suspend

Program Register Program

Program/Erase Resume, Block Erase Confirm, or Buffer Program Confirm

Buffer Program

Read Array

18/98

M58LT128GST, M58LT128GSB

4 Command Interface

4.1

Read Array command

The Read Array command returns the addressed bank to Read Array mode.

One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read

Array mode, subsequent read operations will output the data from the memory array.

A Read Array command can be issued to any banks while programming or erasing in another

bank.

If the Read Array command is issued to a bank currently executing a program or erase

operation, the bank will return to Read Array mode but the program or erase operation will

continue, however the data output from the bank is not guaranteed until the program or erase

operation has finished. The read modes of other banks are not affected.

4.2

Read Status Register command

The device contains a Status Register that is used to monitor program or erase operations.

The Read Status Register command is used to read the contents of the Status Register for the

addressed bank.

One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in

Read Status Register mode, subsequent read operations will output the contents of the Status

Register.

The Status Register data is latched on the falling edge of the Chip Enable or Output Enable

signals. Either Chip Enable or Output Enable must be toggled to update the Status Register

data

The Read Status Register command can be issued at any time, even during program or erase

operations. The Read Status Register command will only change the read mode of the

addressed bank. The read modes of other banks are not affected. Only Asynchronous Read

and Single Synchronous Read operations should be used to read the Status Register. A Read

Array command is required to return the bank to Read Array mode.

See Table 9 for the description of the Status Register Bits.

4.3

Read Electronic Signature command

The Read Electronic Signature command is used to read the Manufacturer and Device Codes,

the Protection Status of the addressed bank, the Configuration Register and the Protection

Register.

One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank

is in Read Electronic Signature mode, subsequent read operations in the same bank will output

the Manufacturer Code, the Device Code, the Protection Status of the addressed bank, or the

Configuration Register (see Table 7).

The Read Electronic Signature command can be issued at any time, even during program or

erase operations, except during Protection Register Program operations. Dual operations

between the Parameter bank and the Electronic Signature location are not allowed (see

Table 15: Dual Operation Limitations for details).

If a Read Electronic Signature command is issued to a bank that is executing a program or

erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read

19/98

4 Command Interface

M58LT128GST, M58LT128GSB

cycles will output the Electronic Signature data and the Program/Erase controller will continue

to program or erase in the background.

The Read Electronic Signature command will only change the read mode of the addressed

bank. The read modes of other banks are not affected. Only Asynchronous Read and Single

Synchronous Read operations should be used to read the Electronic Signature. A Read Array

command is required to return the bank to Read Array mode.

4.4

Read CFI Query command

The Read CFI Query command is used to read data from the Common Flash Interface (CFI).

One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in

Read CFI Query mode, subsequent Bus Read operations in the same bank read from the

Common Flash Interface.

The Read CFI Query command can be issued at any time, even during program or erase

operations.

If a Read CFI Query command is issued to a bank that is executing a program or erase

operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output

the CFI data and the Program/Erase controller will continue to program or erase in the

background.

The Read CFI Query command will only change the read mode of the addressed bank. The

read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous

Read operations should be used to read from the CFI. A Read Array command is required to

return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI

memory space are not allowed (see Table 15: Dual Operation Limitations for details).

See Appendix B: Common Flash Interface, Table 36, Table 37, Table 38, Table 39, Table 40,

Table 42, Table 43, Table 44 and Table 45 for details on the information contained in the

Common Flash Interface memory area.

4.5

Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4

and 5) in the Status Register.

One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status

Register command does not affect the read mode of the bank.

The error bits in the Status Register do not automatically return to ‘0’ when a new command is

issued. The error bits in the Status Register should be cleared before attempting a new

program or erase command.

20/98

M58LT128GST, M58LT128GSB

4 Command Interface

4.6

Block Erase command

The Block Erase command is used to erase a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost.

If the block is protected then the erase operation will abort, the data in the block will not be

changed and the Status Register will output the error.

Two Bus Write cycles are required to issue the command.

1. The first bus cycle sets up the Block Erase command.

2. The second latches the block address and starts the Program/Erase Controller.

If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5

are set and the command is aborted.

Once the command is issued the bank enters Read Status Register mode and any read

operation within the addressed bank will output the contents of the Status Register. A Read

Array command is required to return the bank to Read Array mode.

During Block Erase operations the bank containing the block being erased will only accept the

Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the

Program/Erase Suspend command, all other commands will be ignored.

The Block Erase operation aborts if Reset, RP, goes to V_IL. As data integrity cannot be

guaranteed when the Block Erase operation is aborted, the block must be erased again.

Refer to Dual Operations section for detailed information about simultaneous operations

allowed in banks not being erased.

Typical Erase times are given in Table 16: Program/Erase Times and Endurance Cycles.

See Appendix C, Figure 22: Block Erase Flowchart and Pseudo Code, for a suggested

flowchart for using the Block Erase command.

4.7

Program command

The program command is used to program a single Word to the memory array.

Two Bus Write cycles are required to issue the Program Command.

1. The first bus cycle sets up the Program command.

2. The second latches the address and data to be programmed and starts the Program/

Erase Controller.

Once the programming has started, read operations in the bank being programmed output the

Status Register content.

During a Program operation, the bank containing the Word being programmed will only accept

the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the

Program/Erase Suspend command, all other commands will be ignored. A Read Array

command is required to return the bank to Read Array mode.

Refer to Dual Operations section for detailed information about simultaneous operations

allowed in banks not being programmed.

Typical Program times are given in Table 16: Program/Erase Times and Endurance Cycles.

The Program operation aborts if Reset, RP, goes to V_IL. As data integrity cannot be guaranteed

when the Program operation is aborted, the Word must be reprogrammed.

21/98

4 Command Interface

M58LT128GST, M58LT128GSB

See Appendix C, Figure 19: Program Flowchart and Pseudo Code, for the flowchart for using

the Program command.

4.8

Buffer Program command

The Buffer Program Command makes use of the device’s 32-Word Write Buffer to speed up

programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program

command dramatically reduces in-system programming time compared to the standard non-

buffered Program command.

Four successive steps are required to issue the Buffer Program command.

1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be

addressed to any location within the targeted block.

After the first Bus Write cycle, read operations in the bank will output the contents of the

Status Register. Status Register bit SR7 should be read to check that the buffer is

available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program

command to update the Status Register contents.

2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is

written to the same block address, where n+1 is the number of Words to be programmed.

3. Use n+1 Bus Write cycles to load the address and data for each Word into the Write

Buffer. Addresses must lie within the range from the start address to the start address + n.

Optimum performance is obtained when the start address corresponds to a 32 Word

boundary. If the start address is not aligned to a 32 word boundary, the total programming

time is doubled

4. The final Bus Write cycle confirms the Buffer Program command and starts the program

operation.

All the addresses used in the Buffer Program operation must lie within the same block.

Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will

set an error in the Status Register and abort the operation without affecting the data in the

memory array.

If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not

accepted. Clear the Status Register before re-issuing the command.

If the block being programmed is protected an error will be set in the Status Register and the

operation will abort without affecting the data in the memory array.

During Buffer Program operations the bank being programmed will only accept the Read Array,

Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase

Suspend command, all other commands will be ignored.

Refer to Dual Operations section for detailed information about simultaneous operations

allowed in banks not being programmed.

See Appendix C, Figure 20: Buffer Program Flowchart and Pseudo Code, for a suggested

flowchart on using the Buffer Program command.

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M58LT128GST, M58LT128GSB

4 Command Interface

4.9

Buffer Enhanced Factory Program command

The Buffer Enhanced Factory Program command has been specially developed to speed up

programming in manufacturing environments where the programming time is critical.

It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device

enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number

of times as long as the address remains within the same block. Only one block can be

programmed at a time.

The use of the Buffer Enhanced Factory Program command requires certain operating

conditions:

■

The targeted block must be unprotected. if it is protected, the user must return the device

to read mode.

■

V_PPmust be set to V_PPH.

V_DDmust be within operating range.

Ambient temperature T_Amust be 30°C ± 10°C.

■

The start address must be aligned with the start of a 32 Word buffer boundary.

The address must remain the Start Address throughout programming.

Dual operations are not supported during the Buffer Enhanced Factory Program operation and

the command cannot be suspended.

The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase,

the Program and Verify Phase, and the Exit Phase, See Appendix C, Figure 25: Buffer

Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using

the Buffer Program command and to Table 6: Factory Program Command for details on the

Buffer Enhanced Factory Program command.

4.9.1 Setup phase

The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the

command.

1. The first Bus Write cycle sets up the Buffer Enhanced Factory Program command.

2. The second Bus Write cycle confirms the command.

After the confirm command is issued, read operations output the contents of the Status

Register. The read Status Register command must not be issued as it will be interpreted as

data to program.

The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed

to the next phase.

If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program

operation is terminated. See Status Register section for details on the error.

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4 Command Interface

M58LT128GST, M58LT128GSB

4.9.2 Program and Verify phase

The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer.

The data is stored sequentially, starting at the first address of the Write Buffer, until the Write

Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be

programmed with FFFFh.

Three successive steps are required to issue and execute the Program and Verify Phase of the

command.

1. Use one Bus Write operation to latch the Start Address and the first Word to be

programmed. The Status Register Bank Write Status bit SR0 should be read to check that

the P/E.C. is ready for the next Word.

2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The

address must remain the Start Address as the P/E.C. increments the address location.If

any address that is not in the same block as the Start Address is given, the Program and

Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write

cycle to check that the P/E.C. is ready for the next Word.

3. Once the Write Buffer is full, the data is programmed sequentially to the memory array.

After the program operation the device automatically verifies the data and reprograms if

necessary.

The Program and Verify phase can be repeated, without re-issuing the command, to

program additional 32 Word locations as long as the address remains in the same block.

4. Finally, after all Words, or the entire block have been programmed, write one Bus Write

operation to any address outside the block containing the Start Address, to terminate

Program and Verify Phase.

Status Register bit SR0 must be checked to determine whether the program operation is

finished. The Status Register may be checked for errors at any time but it must be checked after

the entire block has been programmed.

4.9.3 Exit phase

Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer

Enhanced Factory Program operation and returned to Read Status Register mode. A full Status

Register check should be done to ensure that the block has been successfully programmed.

See the section on the Status Register for more details.

For optimum performance the Buffer Enhanced Factory Program command should be limited to

a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal

algorithm will continue to work properly but some degradation in performance is possible.

Typical program times are given in Table 16

See Appendix C, Figure 25: Buffer Enhanced Factory Program Flowchart and Pseudo Code,

for a suggested flowchart on using the Buffer Enhanced Factory Program command.

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M58LT128GST, M58LT128GSB

4 Command Interface

4.10 Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Block Erase operation.

The command can be addressed to any bank.

The Program/Erase Resume command is required to restart the suspended operation.

One bus write cycle is required to issue the Program/Erase Suspend command. Once the

Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be

set to ‘1’.

The following commands are accepted during Program/Erase Suspend:

■

Program/Erase Resume

Read Array (data from erase-suspended block or program-suspended Word is not valid)

Read Status Register

Read Electronic Signature

Read CFI Query.

In addition, if the suspended operation was a Block Erase then the following commands are

also accepted:

■

Clear Status Register

Program (except in erase-suspended block)

Buffer Program (except in erase suspended blocks)

It is possible to accumulate multiple suspend operations. For example: suspend an erase

operation, start a program operation, suspend the program operation, then read the array.

If a Program command is issued during a Block Erase Suspend, the erase operation cannot be

resumed until the program operation has completed.

The Program/Erase Suspend command does not change the read mode of the banks. If the

suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query

mode the bank remains in that mode and outputs the corresponding data.

Refer to Dual Operations section for detailed information about simultaneous operations

allowed during Program/Erase Suspend.

During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip

Enable to V_IH. Program/erase is aborted if Reset, RP, goes to V_IL.

See Appendix C, Figure 21: Program Suspend & Resume Flowchart and Pseudo Code, and

Figure 23: Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the

Program/Erase Suspend command.

4.11 Program/Erase Resume command

The Program/Erase Resume command is used to restart the program or erase operation

suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue

the command. The command can be issued to any address.

The Program/Erase Resume command does not change the read mode of the banks. If the

suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query

mode the bank remains in that mode and outputs the corresponding data.

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4 Command Interface

M58LT128GST, M58LT128GSB

If a Program command is issued during a Block Erase Suspend, then the erase cannot be

resumed until the program operation has completed.

See Appendix C, Figure 21: Program Suspend & Resume Flowchart and Pseudo Code, and

Figure 23: Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the

Program/Erase Resume command.

4.11.1 Protection Register Program command

The Protection Register Program command is used to program the user One-Time-

Programmable (OTP) segments of the Protection Register and the two Protection Register

Locks.

The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown

in Figure 4: Protection Register Map. The segments are programmed one Word at a time.

When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.

Two Bus Write cycles are required to issue the Protection Register Program command.

1. The first bus cycle sets up the Protection

2. Register Program command.

3. The second latches the address and data to be programmed to the Protection Register

and starts the Program/Erase Controller.

Read operations to the bank being programmed output the Status Register content after the

program operation has started.

Attempting to program a previously protected Protection Register will result in a Status Register

error.

The Protection Register Program cannot be suspended. Dual operations between the

Parameter Bank and the Protection Register memory space are not allowed (see Table 15:

Dual Operation Limitations for details).

The two Protection Register Locks are used to protect the OTP segments from further

modification. The protection of the OTP segments is not reversible. Refer to Figure 4:

Protection Register Map, and Table 8: Protection Register Lock Bits, for details on the Lock bits.

See Appendix C, Figure 24: Protection Register Program Flowchart and Pseudo Code, for a

flowchart for using the Protection Register Program command.

4.12 Set Configuration Register command

The Set Configuration Register command is used to write a new value to the Configuration

Register.

Two Bus Write cycles are required to issue the Set Configuration Register command.

1. The first cycle sets up the Set Configuration Register command and the address

corresponding to the Configuration Register content.

2. The second cycle writes the Configuration Register data and the confirm command.

The Configuration Register data must be written as an address during the bus write cycles, that

is DQ0 = CR0, DQ1 = CR1, …, DQ15 = CR15. Addresses A0-A22 are ignored.

Read operations output the array content after the Set Configuration Register command is

issued.

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M58LT128GST, M58LT128GSB

4 Command Interface

The Read Electronic Signature command is required to read the updated contents of the

Configuration Register.

Table 5.

Standard Commands

Bus Operations⁽¹⁾

Commands

1st Cycle

Add

2nd Cycle

Add

Op.

Data

Op.

Data

RD

Read Array

1+

1

Write

BKA

X

FFh

70h

90h

98h

50h

WA

Read

BKA⁽²⁾

Read Status Register

Read Electronic Signature

Read CFI Query

SRD

ESD

QD

X

BKA

Clear Status Register

BKA or

BA⁽³⁾

Block Erase

Program

2

Write

20h

Write

BA

D0h

PD

BKA or

WA⁽³⁾

40h or 10h

WA

Write

BA

E8h

PD₁

Write

BA

n

PA₁

PA₂

PD₂

Buffer Program

n+4

(4)

Write

X

D0h

PA_n+1

PD_n+1

Program/Erase Suspend

Protection Register Program

Program/Erase Resume

Set Configuration Register

1

2

1

2

Write

X

B0h

C0h

D0h

60h

PRA

X

Write

PRA

CRD

PRD

03h

CRD

1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic

Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA = Protection Register

Address, PRD = Protection Register Data, CRD=Configuration Register Data.

2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7

3. Any address within the bank can be used.

4. n+1 is the number of Words to be programmed.

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4 Command Interface

M58LT128GST, M58LT128GSB

Table 6.

Factory Program Command

Bus Write Operations⁽¹⁾

3rd Final -1

Add Data Add Data

WA₁

Command

Phase

1st

2nd

Final

Add

Data

Add

Data

Add

Data

BKAor

WA⁽²⁾

Setup

2

≥32

1

80h

D0h

Buffer

Enhanced

Factory

Program/

Verify⁽³⁾

WA₁

PD₁

X

WA₁PD₂WA₁PD₃

WA₁

PD₃₁

WA₁

PD₃₂

Program

NOT

Exit

(4)

BA₁

1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address, X = Don’t Care.

2. Any address within the bank can be used.

3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same

block.

4. WA is the Start Address, NOT BA = Not Block Address of WA .

1

Table 7.

Electronic Signature Codes

Code

Address (h)

Data (h)

Manufacturer Code

Top

Bank Address + 00

Bank Address + 01

Block Address + 03

0020

88C6h (M58LT128GST)

88C7h (M58LT128GSB)

Device Code

Bottom

Die Revision Code

DRC⁽¹⁾

CR⁽¹⁾

Configuration Register

ST Factory Default

Bank Address + 05

bit 0 = ‘0’

Protection

Register PR0

Bank Address + 80

OTP Area Permanently

Locked

bit 1 = ‘0’

Bank Address + 81

Bank Address + 84

Unique Device Number

Protection Register PR0

Bank Address + 85

Bank Address + 88

OTP Area

PRLD

Protection Register PR1 through PR16 Lock

Protection Registers PR1-PR16

Bank Address + 89

Bank Address + 8A

Bank Address + 109

OTP Area

1. CR = Configuration Register, DRC = Die Revision Code.

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M58LT128GST, M58LT128GSB

Figure 4. Protection Register Map

4 Command Interface

PROTECTION REGISTERS

109h

PR16

User Programmable OTP

102h

91h

PR1

User Programmable OTP

8Ah

89h

Protection Register Lock

14

15 13 121110 9 8 7 6 5 4 3 2 1 0

88h

PR0

User Programmable OTP

85h

84h

Unique device number

81h

80h

Protection Register Lock

1 0

AI07563

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4 Command Interface

M58LT128GST, M58LT128GSB

Table 8.

Number

Protection Register Lock Bits

Lock

Description

Address

Bits

Read-only bit preprogrammed to ‘0’ protect Unique Device Number (address

81h to 84h in PR0)

Bit 0

Protection

Register

Lock 1

80h

89h

protects 64bits of OTP segment (address 85h to 88h in PR0) when set to ‘0’

Default Value is ‘1’

Bit 1

Bit 0

Bit 1

protects 128bits of OTP segment PR1

protects 128bits of OTP segment PR2

protects 128bits of OTP segment PR3

- - -

Bit 2

Protection

Register

Lock 2

- - -

Bit 13

Bit 14

Bit 15

protects 128bits of OTP segment PR14

protects 128bits of OTP segment PR15

protects 128bits of OTP segment PR16

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M58LT128GST, M58LT128GSB

5 Status Register

5

Status Register

The Status Register provides information on the current or previous program or erase

operations. Issue a Read Status Register command to read the contents of the Status Register,

refer to Read Status Register Command section for more details. To output the contents, the

Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable

signals and can be read until Chip Enable or Output Enable returns to V_IH. The Status Register

can only be read using single Asynchronous or Single Synchronous reads. Bus Read

operations from any address within the bank, always read the Status Register during program

and erase operations.

The various bits convey information about the status and any errors of the operation. Bits SR7,

SR6, SR2 and SR0 give information on the status of the device and are set and reset by the

device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but

must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is

set to ‘1’ the Status Register should be reset before issuing another command.

Refer to Table 9: Status Register Bits in conjunction with the following text descriptions.

5.1

Program/Erase Controller Status Bit (SR7)

The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is

active or inactive in any bank.

When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller

is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the

device is ready to process a new command.

The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend

command is issued until the Program/Erase Controller pauses. After the Program/Erase

Controller pauses the bit is High.

5.2

Erase Suspend Status Bit (SR6)

The Erase Suspend Status bit indicates that an erase operation has been suspended in the

addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase

Suspend command has been issued and the memory is waiting for a Program/Erase Resume

command.

The Erase Suspend Status bit should only be considered valid when the Program/Erase

Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase

Suspend Latency time of the Program/Erase Suspend command being issued therefore the

memory may still complete the operation rather than entering the Suspend mode.

When a Program/Erase Resume command is issued the Erase Suspend Status bit returns

Low.

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5 Status Register

M58LT128GST, M58LT128GSB

5.3

Erase Status Bit (SR5)

The Erase Status bit is used to identify if there was an error during a block or bank erase

operation.

When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the

maximum number of pulses to the block or bank and still failed to verify that it has erased

correctly.

The Erase Status bit should be read once the Program/Erase Controller Status bit is High

(Program/Erase Controller inactive).

Once set High, the Erase Status bit must be set Low by a Clear Status Register command or a

hardware reset before a new erase command is issued, otherwise the new command will

appear to fail.

5.4

Program Status Bit (SR4)

The Program Status bit is used to identify if there was an error during a program operation.

The Program Status bit should be read once the Program/Erase Controller Status bit is High

(Program/Erase Controller inactive).

When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the

maximum number of pulses to the Word and still failed to verify that it has programmed

correctly.

Attempting to program a '1' to an already programmed bit while V_PP= V_PPHwill also set the

Program Status bit High. If V_PPis different from V_PPH, SR4 remains Low (set to '0') and the

attempt is not shown.

Once set High, the Program Status bit must be set Low by a Clear Status Register command or

a hardware reset before a new program command is issued, otherwise the new command will

appear to fail.

5.5

V

Status Bit (SR3)

PP

The V_PPStatus bit is used to identify an invalid voltage on the V_PPpin during program and

erase operations. The V_PPpin is only sampled at the beginning of a program or erase

operation. Program and erase operations are not guaranteed if V_PPbecomes invalid during an

operation.

When the V_PPStatus bit is Low (set to ‘0’), the voltage on the V_PPpin was sampled at a valid

voltage.

when the V_PPStatus bit is High (set to ‘1’), the V_PPpin has a voltage that is below the V_PP

Lockout Voltage, V_PPLK, the memory is protected and program and erase operations cannot be

performed.

Once set High, the V_PPStatus bit must be set Low by a Clear Status Register command or a

hardware reset before a new program or erase command is issued, otherwise the new

command will appear to fail.

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M58LT128GST, M58LT128GSB

5 Status Register

5.6

Program Suspend Status Bit (SR2)

The Program Suspend Status bit indicates that a program operation has been suspended in the

addressed block. The Program Suspend Status bit should only be considered valid when the

Program/Erase Controller Status bit is High (Program/Erase Controller inactive).

When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command

has been issued and the memory is waiting for a Program/Erase Resume command.

SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command

being issued therefore the memory may still complete the operation rather than entering the

Suspend mode.

When a Program/Erase Resume command is issued the Program Suspend Status bit returns

Low.

SR1. Reserved.

5.7

Bank Write/Multiple Word Program Status Bit (SR0)

The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In

Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is

ready to accept a new Word to be programmed to the memory array.

The Bank Write Status bit should only be considered valid when the Program/Erase Controller

Status SR7 is Low (set to ‘0’).

When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set

to ‘0’), the addressed bank is executing a program or erase operation. When the Program/Erase

Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a

program or erase operation is being executed in a bank other than the one being addressed.

In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to

‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to

‘1’) the device is not ready for the next Word.

For further details on how to use the Status Register, see the Flowcharts and Pseudo codes

provided in Appendix C.

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5 Status Register

M58LT128GST, M58LT128GSB

Table 9.

Bit

Status Register Bits

Name

Type LogicLevel

Definition

'1'

Ready

SR7 P/E.C. Status

Status

'0'

Busy

'1'

Erase Suspended

SR6 Erase Suspend Status

SR5 Erase Status

Status

'0'

Erase In progress or Completed

Erase Error

'1'

Error

'0'

Erase Success

'1'

Program Error

SR4 Program Status

Error

'0'

Program Success

V_PPInvalid, Abort

'1'

V_PPStatus

SR3

SR2

Error

'0'

V_PPOK

'1'

Program Suspended

Program Suspend

Status

'0'

Program In Progress or Completed

SR1 Reserved

SR7 = ‘1’ Not Allowed

'1'

Program or erase operation in a bank other than

the addressed bank

SR7 = ‘0’

Bank Write Status

Status

SR7 = ‘1’ No Program or erase operation in the device

SR7 = ‘0’ Program or erase operation in addressed bank

SR7 = ‘1’ Not Allowed

'0'

SR0

'1'

Multiple Word Program

Status (Enhanced

Factory Program mode)

SR7 = ‘0’ the device is NOT ready for the next Word

SR7 = ‘1’ the device is exiting from BEFP

Status

'0'

SR7 = ‘0’ the device is ready for the next Word

1. Logic level '1' is High, '0' is Low.

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M58LT128GST, M58LT128GSB

6 Configuration Register

6

Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will

perform. Refer to Read Modes section for details on read operations.

The Configuration Register is set through the Command Interface using the Set Configuration

Register command. After a reset or power-up the device is configured for asynchronous read

(CR15 = 1). The Configuration Register bits are described in Table 10 They specify the

selection of the burst length, burst type, burst X latency and the read operation. Refer to

Figure 5 and Figure 6 for examples of synchronous burst configurations.

6.1

Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read

operations.

When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read

Select bit is set to ’0’, read operations are synchronous.

Synchronous Burst Read is supported in both parameter and main blocks and can be

performed across banks.

On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

6.2

X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of clock

cycles between the address being latched and the first data becoming available. For correct

operation the X-Latency bits can only assume the values in Table 10: Configuration Register.

The correspondence between X-Latency settings and the maximum sustainable frequency

must be calculated taking into account some system parameters. Two conditions must be

satisfied:

1. Depending on whether t_{AVK_CPU}or t_DELAYis supplied either one of the following two

equations must be satisfied:

(n + 1) t_K≥ t_AVQV- t_{AVK_CPU}+ t_{QVK_CPU}

(n + 2) t_K≥ t_AVQV+ t_DELAY+ t_{QVK_CPU}

2. and also

t_K> t_KQV+ t_{QVK_CPU}

where

■

n is the chosen X-Latency configuration code

t_Kis the clock period

■

t_{AVK_CPU}is clock to address valid, L Low, or E Low, whichever occurs last

t_DELAYis address valid, L Low, or E Low to clock, whichever occurs last

t_{QVK_CPU}is the data setup time required by the system CPU,

t_KQVis the clock to data valid time

t_AVQVis the random access time of the device.

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6 Configuration Register

M58LT128GST, M58LT128GSB

Refer to Figure 5: X-Latency and Data Output Configuration Example.

6.3

6.4

Wait Polarity Bit (CR10)

The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst

Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data

output are valid or a WAIT state must be inserted.

When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is

set to ‘1’ the Wait signal is active High.

Data Output Configuration Bit (CR9)

The Data Output Configuration bit is used to configure the output to remain valid for either one

or two clock cycles during synchronous mode.

When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when

the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles.

The Data Output Configuration must be configured using the following condition:

■

t_K> t_KQV+ t_{QVK_CPU}

where

■

t_Kis the clock period

t_{QVK_CPU}is the data setup time required by the system CPU

t_KQVis the clock to data valid time.

If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock

cycles). Refer to Figure 5: X-Latency and Data Output Configuration Example.

6.5

6.6

36/98

Wait Configuration Bit (CR8)

The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in

Synchronous Burst Read mode.

When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid.

When the Wait Configuration bit is Low (set to ’0’) the Wait output pin is asserted during the

WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is asserted

one data cycle before the WAIT state.

Burst Type Bit (CR7)

The Burst Type bit determines the sequence of addresses read during Synchronous Burst

Reads.

The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses only.

See Table 11: Burst Type Definition, for the sequence of addresses output from a given starting

address in sequential mode.

M58LT128GST, M58LT128GSB

6 Configuration Register

6.7

Valid Clock Edge Bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during

synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge

of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge

of the Clock is the active edge.

6.8

Wrap Burst Bit (CR3)

The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst

reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary

(no wrap).

When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the

burst read does not wrap.

6.9

Burst length Bits (CR2-CR0)

The Burst Length bits are used to set the number of Words to be output during a Synchronous

Burst Read operation as result of a single address latch cycle.

They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are

read sequentially. In continuous burst mode the burst sequence can cross bank boundaries.

In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address, the

device asserts the WAIT signal to indicate that a delay is necessary before the data is output.

If the starting address is aligned to an 8 Word boundary no WAIT states are needed and the

WAIT output is not asserted.

If the starting address is not aligned to the 8 Word boundary, WAIT will be asserted when the

burst sequence crosses the first 16 Word boundary to indicate that the device needs an internal

delay to read the successive Words in the array.

In the worst case, the number of WAIT states is one clock cycle less than the latency setting.

The exact number is reported in Table 12: Wait at the Boundary.

WAIT will be asserted only once during a continuous burst access. See also Table 11: Burst

Type Definition.

CR14, CR5 and CR4 are reserved for future use.

37/98

6 Configuration Register

M58LT128GST, M58LT128GSB

Table 10. Configuration Register

Bit

Description

Value

Description

0

1

Synchronous Read

CR15

CR14

Read Select

Asynchronous Read (Default at power-on)

Reserved

X-Latency

2 clock latency⁽¹⁾

3 clock latency

010

011

100

101

110

111

4 clock latency

CR13-CR11

5 clock latency

6 clock latency

7 clock latency (default)

Other configurations reserved

0

1

0

1

0

1

0

1

0

1

WAIT is active Low (default)

CR10

CR9

CR8

CR7

Wait Polarity

WAIT is active High

Data held for one clock cycle

Data Output

Configuration

Data held for two clock cycles (default)⁽¹⁾

WAIT is active during WAIT state (default)

Wait Configuration

Burst Type

WAIT is active one data cycle before WAIT state⁽¹⁾

Reserved

Sequential (default)

Falling Clock edge

CR6

CR5-CR4

CR3

Valid Clock Edge

Reserved

Rising Clock edge (default)

0

Wrap

Wrap Burst

1

No Wrap (default)

4 Words

001

010

011

111

8 Words

CR2-CR0

Burst Length

16 Words

Continuous (default)

1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not

supported.

38/98

M58LT128GST, M58LT128GSB

Table 11. Burst Type Definition

6 Configuration Register

Sequential

Start

Add.

Continuous Burst

4 Words

8 Words

16 Words

0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-

15

0

1

2

0-1-2-3

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

3-4-5-6-7-8-9...

1-2-3-4-5-6-7-8-9-10-11-12-13-14-

15-0

1-2-3-0

2-3-0-1

3-0-1-2

2-3-4-5-6-7-8-9-10-11-12-13-14-15-

0-1

3-4-5-6-7-8-9-10-11-12-13-14-15-0-

1-2

3

...

7

7-8-9-10-11-12-13-14-15-0-1-2-3-4-

5-6

7-4-5-6

7-0-1-2-3-4-5-6

7-8-9-10-11-12-13...

...

12

12-13-14-15-8-9-10- 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-

11 11

12-13-14-15

13-14-15-12

14-15-12-13

15-12-13-14

0-1-2-3

12-13-14-15-16-17...

13-14-15-16-17-18...

14-15-16-17-18-19...

15-16-17-18-19-20...

13-14-15-8-9-10-11- 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-

12 12

13

14

15

0

14-15-8-9-10-11-12- 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-

13 13

15-8-9-10-11-12-13- 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-

14

0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-

15

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8--9-10-11-12-13-14-

15-16

1

1-2-3-4

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9...

3-4-5-6-7-8-9-10

2-3-4-5--6-7-8-9-10-11-12-13-14-15-

16-17

2

2-3-4-5

3-4-5-6-7-8-9-10-11-12-13-14-15-

16-17-18

3

...

7

3-4-5-6

Same as for Wrap

(Wrap /No Wrap

has no effect on

Continuous Burst)

7-8-9-10-11-12-13-14-15-16-17-18-

19-20-21-22

7-8-9-10

7-8-9-10-11-12-13-14

...

12

12-13-14-15-16-17- 12-13-14-15-16-17-18-19-20-21-22-

18-19 23-24-25-26-27

12-13-14-15

13-14-15-16

14-15-16-17

15-16-17-18

13-14-15-16-17-18- 13-14-15-16-17-18-19-20-21-22-23-

19-20 24-25-26-27-28

13

14

15

14-15-16-17-18-19- 14-15-16-17-18-19-20-21-22-23-24-

20-21 25-26-27-28-29

15-16-17-18-19-20- 15-16-17-18-19-20-21-22-23-24-25-

21-22 26-27-28-29-30

39/98

6 Configuration Register

M58LT128GST, M58LT128GSB

Table 12. Wait at the Boundary

Number of WAIT states

Start

Address

X-Latency = 7 X-Latency = 6 X-Latency = 5 X-Latency = 4 X-Latency = 3 X-Latency = 2

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

0

1

2

3

4

5

0

1

2

3

4

0

1

2

3

0

1

2

0

1

Figure 5. X-Latency and Data Output Configuration Example

X-latency

1st cycle

2nd cycle

3rd cycle

4th cycle

K

E

L

A22-A0

VALID ADDRESS

tAVK_CPU

tDELAY

tQVK_CPU

tK

tACC

tKQV

tQVK_CPU

DQ15-DQ0

VALID ADDRESS

VALID DATA VALID DATA

AI10262

1. The settings shown are X-latency = 4, Data Output held for one clock cycle.

40/98

M58LT128GST, M58LT128GSB

6 Configuration Register

Figure 6. Wait Configuration Example

E

K

L

G

A22-A0

VALID ADDRESS

DQ15-DQ0

VALID DATA VALID DATA NOT VALID VALID DATA

WAIT

CR8 = '0'

CR10 = '0'

WAIT

CR8 = '1'

CR10 = '0'

WAIT

CR8 = '0'

CR10 = '1'

WAIT

CR8 = '1'

CR10 = '1'

AI10263

41/98

7 Read modes

M58LT128GST, M58LT128GSB

7

Read modes

Read operations can be performed in two different ways depending on the settings in the

Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is

asynchronous; if the data output is synchronized with clock, the read operation is synchronous.

The read mode and format of the data output are determined by the Configuration Register.

(See Configuration Register section for details). All banks support both asynchronous and

synchronous read operations.

7.1

Asynchronous Read modes

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data

corresponding to the address latched, that is the memory array, Status Register, Common

Flash Interface or Electronic Signature depending on the command issued. CR15 in the

Configuration Register must be set to ‘1’ for asynchronous operations. In Asynchronous Read

mode, the WAIT signal is always deasserted.

The device features an Automatic Standby mode. During Asynchronous Read operations, after

a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In

this condition the power consumption is reduced to the standby value and the outputs are still

driven.

Asynchronous Read operations can be performed in two different ways, Asynchronous

Random Read and Asynchronous Page Read.

7.1.1 Asynchronous Random Read

Asynchronous Random Read operations are controlled by the Latch Enable, L, signal.

A valid bus operation involves setting the desired address on the Address Inputs, setting Chip

Enable and Latch Enable Low, V_IL, and keeping Write Enable High, V_IH. The address is latched

on the rising edge of Latch Enable, L, before the value is output on the data bus. Once latched,

the Address Inputs can change. Set Output Enable Low, V_IL, to read the data on the Data

Inputs/Outputs.

See Table 22: Asynchronous Read AC Characteristics, and Figure 9: Asynchronous Random

Access Read AC Waveforms for details.

7.1.2 Asynchronous Page Read

Only Asynchronous Page Read takes full advantage of the internal page storage so different

timings are applied. In Asynchronous Page Read mode, a Page of data is internally read and

stored in a Page Buffer. The Page size is 8 Words and is addressed by address inputs A0, A1

and A2.

The first read operation within the Page has the normal access time (t_AVQV), subsequent reads

within the same Page have much shorter access times (t_AVQV1). If the Page changes then the

normal longer timings apply again.

See Table 22: Asynchronous Read AC Characteristics, Figure 10: Asynchronous Page Read

AC Waveforms for details.

42/98

M58LT128GST, M58LT128GSB

7 Read modes

7.2

Synchronous Burst Read modes

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is

possible to perform burst reads across bank boundaries.

Synchronous Burst Read mode can only be used to read the memory array. For other read

operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single

Synchronous Read or Asynchronous Random Access Read must be used.

In Synchronous Burst Read mode the flow of the data output depends on parameters that are

configured in the Configuration Register.

A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge

bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable,

whichever occurs last. Addresses are internally incremented and data is output on each data

cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration

Register.

The number of Words to be output during a Synchronous Burst Read operation can be

configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The

data can be configured to remain valid for one or two clock cycles (Data Output Configuration

bit CR9).

The order of the data output can be modified through the Wrap Burst bit in the Configuration

Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word

boundary (Wrap) or overcome the boundary (No Wrap).

The WAIT signal may be asserted to indicate to the system that an output delay will occur. This

delay will depend on the starting address of the burst sequence and on the burst configuration.

WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word

burst. It is only deasserted when output data are valid or when G is at V_IH. In Continuous Burst

Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the starting

address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no

impact on the output sequence.

The WAIT signal can be configured to be active Low or active High by setting CR10 in the

Configuration Register.

See Table 23: Synchronous Read AC Characteristics, and Figure 11: Synchronous Burst Read

AC Waveforms, for details.

7.2.1 Synchronous Burst Read Suspend

A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher

priority devices. It can be suspended during the initial access latency time (before data is

output) in which case the initial latency time can be reduced to zero, or after the device has

output data. When the Synchronous Burst Read operation is suspended, internal array sensing

continues and any previously latched internal data is retained. A burst sequence can be

suspended and resumed as often as required as long as the operating conditions of the device

are met.

A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the

current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The

Clock signal is then halted at V_IHor at V_IL, and Output Enable, G, goes High.

When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous

Burst Read operation is resumed exactly where it stopped.

43/98

7 Read modes

M58LT128GST, M58LT128GSB

WAIT being gated by E, it will remain active and will not revert to high impedance when G goes

High. So if two or more devices are connected to the system’s READY signal, to prevent bus

contention the WAIT signal of the M58LT128GST and M58LT128GSB should not be directly

connected to the system’s READY signal.

WAIT will revert to high-impedance when Output Enable, G, or Chip Enable, E, goes High.

See Table 23: Synchronous Read AC Characteristics, and Figure 13: Synchronous Burst Read

Suspend AC Waveforms, for details.

7.2.2 Single Synchronous Read mode

Single Synchronous Read operations are similar to Synchronous Burst Read operations except

that the memory outputs the same data to the end of the operation.

Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI,

Configuration Register Status, or Protection Register. When the addressed bank is in Read

CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted

when Output Enable, G, is at V_IHor for the one clock cycle during which output data is valid.

Otherwise, it is asserted.

See Table 23: Synchronous Read AC Characteristics, and Figure 11: Synchronous Burst Read

AC Waveforms, for details.

44/98

M58LT128GST, M58LT128GSB

8 Dual Operations and Multiple Bank architecture

8

Dual Operations and Multiple Bank architecture

The Multiple Bank Architecture of the M58LT128GST and M58LT128GSB gives greater

flexibility for software developers to split the code and data spaces within the memory array.

The Dual Operations feature simplifies the software management of the device by allowing

code to be executed from one bank while another bank is being programmed or erased.

The Dual Operations feature means that while programming or erasing in one bank, read

operations are possible in another bank with zero latency (only one bank at a time is allowed to

be in program or erase mode).

If a read operation is required in a bank, which is programming or erasing, the program or erase

operation can be suspended.

Also if the suspended operation was erase then a program command can be issued to another

block, so the device can have one block in Erase Suspend mode, one programming and other

banks in read mode.

Bus Read operations are allowed in another bank between setup and confirm cycles of

program or erase operations.

By using a combination of these features, read operations are possible at any moment in the

M58LT128GST and M58LT128GSB devices.

Dual operations between the Parameter Bank and either of the CFI, or the Electronic Signature

memory space are not allowed. Table 15 shows which dual operations are allowed or not

between the CFI, the Electronic Signature locations and the memory array.

Table 13 and Table 14 show the dual operations possible in other banks and in the same bank.

Table 13. Dual Operations Allowed In Other Banks

Commands allowed in another bank

Read

Status

Read

CFI

Read

Electronic

Program/ Program/

Status of bank

Read

Array

Program,

Buffer Program Erase

Block

Erase

Register Query Signature

Suspend Resume

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Programming

Erasing

–

Program Suspended

Erase Suspended

–

Yes

–

45/98

8 Dual Operations and Multiple Bank architecture

M58LT128GST, M58LT128GSB

Table 14. Dual Operations Allowed In Same Bank

Commands allowed in same bank

Read

Status

Register

Read

Electronic

Signature

Program,

Buffer

Program

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

Read CFI

Query

Block

Erase

Idle

Yes

–

Yes

–

Yes

–

(1)

Programming

Erasing

–

(1)

–

Program

Suspended

Yes⁽²⁾

Yes

–

Yes

Yes⁽²⁾

Erase Suspended

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.

2. Not allowed in the Word that is being erased or programmed.

Table 15. Dual Operation Limitations

Commands allowed

Read Main Blocks

Current Status

Read CFI / Electronic Read Parameter

Located in

Not Located in

Signature

Blocks

Parameter Bank Parameter Bank

Programming / Erasing

Parameter Blocks

No

Yes

Located in

Parameter

No

Programming

/ Erasing Main

Blocks

Bank

Not Located in

Parameter

Bank

In Different Bank

Only

No

Yes

46/98

M58LT128GST, M58LT128GSB

9 Program and Erase times and Endurance cycles

9

Program and Erase times and Endurance cycles

The Program and Erase times and the number of Program/ Erase cycles per block are shown in

Table 16 Exact erase times may change depending on the memory array condition. The best

case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is when all the

bits in the block are at ‘1’ (not preprogrammed). Usually, the system overhead is negligible with

respect to the erase time. In the M58LT128GST and M58LT128GSB the maximum number of

Program/Erase cycles depends on the V_PPvoltage supply used.

Table 16. Program/Erase Times and Endurance Cycles

Typical

after

100kW/E

Cycles

Condition⁽¹⁾⁽²⁾

Parameter

Min

Typ

Max Unit

Parameter Block (16 KWord)

0.4

1

3

2.5

4

s

Erase

Preprogrammed

Not Preprogrammed

Word Program

Main Block (64

KWord)

1.2

30

4

s

60

µs

SIngle Cell

Buffer Program

Word Program

30

60

µs

90

180

880

µs

Program⁽³⁾

Single Word

Buffer Program

90

µs

Buffer (32 Words) (Buffer Program)

Main Block (64 KWord)

Program

440

880

20

µs

ms

µs

25

Suspend Latency

Erase

20

µs

Main Blocks

100,000

cycles

Program/Erase

Cycles (per Block)

Parameter Blocks

47/98

9 Program and Erase times and Endurance cycles

M58LT128GST, M58LT128GSB

Typical

after

100kW/E

Cycles

Condition⁽¹⁾⁽²⁾

Parameter

Min

Typ

Max Unit

Parameter Block (16 KWord)

Main Block (64 KWord)

0.4

1

2.5

4

s

Erase

Single Cell

Word Program

30

85

60

170

µs

Word Program

Single Word

Buffer Enhanced

Factory Program⁽⁴⁾

10

340

320

640

10

µs

ms

s

Buffer Program

680

Buffer (32 Words)

Buffer Enhanced

Factory Program

Program⁽³⁾

Buffer Program

Main Block (64

KWords)

Buffer Enhanced

Factory Program

Buffer Program

Bank (16 Mbits)

Buffer Enhanced

Factory Program

10

s

Main Blocks

1000 cycles

2500 cycles

Program/Erase

Cycles (per Block)

Parameter Blocks

1.

T

= –25 to 85°C; V = 1.7V to 2V; V

= 2.7 to 3.6V.

DDQ

A

DD

2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling

execution).

3. Excludes the time needed to execute the command sequence.

4. This is an average value on the entire device.

48/98

M58LT128GST, M58LT128GSB

10 Maximum Rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause

permanent damage to the device. These are stress ratings only and operation of the device at

these or any other conditions above those indicated in the Operating sections of this

specification is not implied. Exposure to Absolute Maximum Rating conditions for extended

periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and


型号：	M58LT128GSB
厂家：	ST
描述：	128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories 的128Mbit （8MB X16 ，多银行，多层次，突发） 1.8V供应安全闪存记忆闪存
文件：	总98页 (文件大小：695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58LT128GSB [STMICROELECTRONICS]

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