M58LW032A11ZA6T_技术文档

M58LW032A

32 Mbit (2Mb x16, Uniform Block, Burst)

3V Supply Flash Memory

FEATURES SUMMARY

■ WIDE x16 DATA BUS for HIGH BANDWIDTH

■ SUPPLY VOLTAGE

Figure 1. Packages

– V = 2.7 to 3.6V core supply voltage for Pro-

DD

gram, Erase and Read operations

– V

= 1.8 to V for I/O Buffers

DD

DDQ

■ SYNCHRONOUS/ASYNCHRONOUS READ

– Synchronous Burst read

TSOP56 (N)

14 x 20 mm

– Asynchronous Random Read

– Asynchronous Address Latch Controlled

Read

– Page Read

■ ACCESS TIME

TBGA

– Synchronous Burst Read up to 56MHz

– Asynchronous PageMode Read 90/25nsand

110/25ns

TBGA64 (ZA)

10 x 13 mm

– Random Read 90ns, 110ns.

■ PROGRAMMING TIME

– 16 Word Write Buffer

– 18µs Word effective programming time

■ 64 UNIFORM 32 KWord MEMORY BLOCKS

■ BLOCK PROTECTION/ UNPROTECTION

■ PROGRAM and ERASE SUSPEND

■ 128 bit PROTECTION REGISTER

■ COMMON FLASH INTERFACE

■ 100, 000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code M58LW032A: 8816h

July 2002

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M58LW032A

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. TBGA64 Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Latch Enable (L).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Enable (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PP

V

DD

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Input/Output Supply Voltage (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DDQ

Ground (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SS

Ground (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SSQ

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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M58LW032A

Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Burst Configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 7. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

V

PP

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . 33

Figure 13. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35

Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 35

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable

Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . 37

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable

Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output. . . . . . . . . . . . . . . 40

Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 20. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 42

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 42

Figure 22. TBGA64 10x13mm - 8x8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . . . 43

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data. . . . . . . . . 43

PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 27. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 31. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 32. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 23. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 51

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 52

Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 54

Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 28. Block Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 57

Figure 30. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 58

Figure 31. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 59

Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 60

5/61

M58LW032A

SUMMARY DESCRIPTION

The M58LW032 is a 32 Mbit (2Mb x16) non-vola-

tile memory that can be read, erased and repro-

grammed. These operations can be performed

using a single low voltage (2.7V to 3.6V) core sup-

ply. On power-up the memory defaults to Read

mode with an asynchronous bus where it can be

read in the same way as a non-burst Flash mem-

ory.

The memory is divided into 64 blocks of 512Kbit

that can be erased independently so it is possible

to preserve valid data while old data is erased.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a Programor Erase operation can be detected and

any error conditions identified in the Status Regis-

ter. The command set required to control the

memory is consistent with JEDEC standards.

protected during power-up. The protection of the

blocks is non-volatile; after power-up the protec-

tion status of each block is restored to the state

when power was last removed. Software com-

mands are provided to allow protection of some or

all of the blocks and to cancel all block protection

bits simultaneously. All Program or Erase opera-

tions are blocked whenthe Program Erase Enable

input Vpp is low.

The Reset/Power-Down pin is used to apply a

Hardware Reset to the memory and to set the de-

vice in power-down mode.

In asynchronous mode Chip Enable, Output En-

able and Write Enable signals control the bus op-

eration of the memory. An Address Latch input can

be used to latch addresses. Together they allow

simple, yet powerful, connection to most micropro-

cessors, often without additional logic.

In synchronous mode all Bus Read operations are

synchronous with the Clock. Chip Enable and Out-

put Enable select the Bus Read operation and the

address is Latched using the Latch Enable input.

The signals are compatible with most micropro-

cessor burst interfaces.

The device includes a 128 bit Protection Register.

The Protection Register is divided into two 64 bit

segments, the first one is written by the manufac-

turer (contact STMicroelectronics to define the

code to be written here), while the second one is

programmable by the user. The user programma-

ble segment can be locked.

The Write Buffer allows the microprocessor to pro-

gram from 1 to 16 Words in parallel, both speeding

up the programming and freeing up the micropro-

cessor to perform other work. A Word Program

command is available to program a single word.

Erase can be suspended in order to perform either

Read or Program in any other block and then re-

sumed. Program can be suspended to Read data

in any other block and then resumed. Each block

can be programmed and erased over 100,000 cy-

cles.

The memory is available in TSOP56 (14 x 20 mm)

and TBGA64 (10 x 13mm, 1mm pitch) packages.

Individual block protection against Program or

Erase is provided for data security. All blocks are

6/61

M58LW032A

Figure 2. Logic Diagram

Table 1. Signal Names

V

DD DDQ

A1-A21

Address inputs

DQ0-DQ15

Data Inputs/Outputs

Chip Enable

E

21

G

Output Enable

Clock

A1-A21

K

V

PP

16

L

Latch Enable

W

E

DQ0-DQ15

R

Valid Data Ready

Ready/Busy

RB

RP

M58LW032A

RB

R

Reset/Power-Down

Program/Erase Enable

Write Enable

G

V

PP

RP

L

W

V

Supply Voltage

DD

K

V

Input/Output Supply Voltage

Ground

DDQ

SS

Input/Output Ground

Not Connected Internally

Do Not Use

SSQ

V

SS SSQ

NC

DU

AI04320

7/61

M58LW032A

Figure 3. TSOP56 Connections

NC

R

1

56

NC

W

A21

A20

A19

A18

A17

A16

G

RB

DQ15

DQ7

DQ14

DQ6

V

DD

A15

A14

A13

A12

E

SS

DQ13

DQ5

DQ12

DQ4

14

15

43

42

V

DDQ

SSQ

M58LW032A

V

PP

RP

A11

A10

A9

DQ11

DQ3

DQ10

DQ2

A8

V

DD

V

DQ9

DQ1

DQ8

DQ0

SS

A7

A6

A5

A4

A3

A2

A1

NC

K

NC

L

28

29

AI04321

8/61

M58LW032A

Figure 4. TBGA64 Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A1

A2

A6

A8

A9

V

A13

A14

V

A18

A19

DU

R

PP

E

DD

V

DU

SS

A3

A7

A10

A11

DQ9

DQ10

DQ2

A12

RP

A15

A20

A21

A17

RB

G

A4

A5

DQ1

DQ0

DU

A16

DQ8

K

DQ3

DQ11

DQ4

DQ12

DQ5

DQ13

DU

DQ15

DU

G

H

V

DQ6

DQ14

DQ7

W

DDQ

L

DU

V

DU

DD

SSQ

SS

AI04322

9/61

M58LW032A

Figure 5. Block Addresses

M58LW032A

Word (x16) Bus Width

Address lines A1-A21

1FFFFFh

512 Kbit or

32 KWords

1F8000h

1F7FFFh

512 Kbit or

32 KWords

1F0000h

00FFFFh

512 Kbit or

32 KWords

008000h

007FFFh

512 Kbit or

32 KWords

000000h

AI05500

Note: Also see Appendix A, Table 26 for a full listing of the Block Addresses

10/61

M58LW032A

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

A Hardware Reset is achieved by holding Reset/

Power-Down Low, V , for at least t

. When

IL

PLPH

Reset/Power-Down is Low, V , the Status Regis-

IL

ter information is cleared and the power consump-

tion is reduced to power-down level. The device is

deselected and outputs are high impedance. If Re-

Address Inputs (A1-A21). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the internal state machine.

Chip Enable and Latch Enable must be low when

selecting the addresses.

The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable,

whichever occurs first in a Write operation. The

address latch is transparent when Latch Enable is

set/Power-Down goes low, V ,during a Block

IL

Erase, a Write to Buffer and Program or a Block

Protect/Unprotect the operation is aborted and the

data may be corrupted. In this case the Ready/

Busy pin stays low, V , for a maximum timing of

IL

t

+ t

until the completion of the Reset/

PLPH

PHRH,

Power-Down pulse.

After Reset/Power-Down goes High, V , the

IH

memory will be ready for Bus Read and Bus Write

operations after t

. Note that Ready/Busy

PHQV

low, V . The address is internally latched in an

IL

does not fall during a reset, see Ready/Busy Out-

Erase or Program operation.

put section.

Data Inputs/Outputs (DQ0-DQ15). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

to input the data during a program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

internal state machine. When used to input data or

Write commands they are latched on the rising

edge of Write Enable or Chip Enable, whichever

occurs first.

In an application, it is recommended to associate

Reset/Power-Down pin, RP, with the reset signal

of the microprocessor. Otherwise, if a reset opera-

tion occurs while the memory is performing an

Erase or Program operation, the memory may out-

put the Status Register information instead of be-

ing initialized to the default Asynchronous

Random Read.

Latch Enable (L). The Bus Interface is config-

ured to latch the Address Inputs on the rising edge

of Latch Enable, L. In synchronous bus operations

the address is latched on the active edge of the

When Chip Enable and Output Enable are both

low, V , the data bus outputs data from the mem-

IL

ory array, the Electronic Signature, the Block Pro-

tection status, the CFI Information or the contents

of the Status Register. The data bus is high imped-

ance when the chip is deselected, Output Enable

Clock when Latch Enable is Low, V or on the ris-

IL

ing of Latch Enable, whichever occurs first. Once

latched, the addresses may change without affect-

ing the address used by the memory. When Latch

is high, V or the Reset/Power-Down signal is

IH,

Enable is Low, V , the latch is transparent.

IL

low, V . When the Program/Erase Controller is

IL

active the Ready/Busy status is given on DQ7.

Clock (K). The Clock, K, is used to synchronize

the memory with the external bus during Synchro-

nous Bus Read operations. The Clock can be con-

figured to have an active rising or falling edge. Bus

signals are latched on the active edge of the Clock

during synchronous bus operations. In Synchro-

nous Burst Read mode the address is latched on

the first active clock edge when Latch Enable is

Chip Enable (E). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable, E, at

V

deselects the memory and reduces the power

IH

consumption to the Standby level, I

.

DD1

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

low, V , or on the rising edge of Latch Enable,

IL

a readoperation. WhenOutput Enable, G, is at V

IH

whichever occurs first.

the outputs are high impedance. Output Enable,

G, can be used to inhibit the data output during a

burst read operation.

During asynchronous bus operations the Clock is

not used.

Valid Data Ready (R). The Valid Data Ready

output, R, is an open drain output that can be used

to identify if the memory is ready to output data or

not. The Valid Data Ready output is only active

during Synchronous Burst Read operations when

the Burst Length is set to Continuous. The Valid

Data Ready output can be configured to be active

on the clock edge of the invalid data read cycle or

Write Enable (W). The Write Enable input, W,

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data can be latched on the rising edge of Write En-

able (also see Latch Enable, L).

Reset/Power-Down (RP). The

Reset/Power-

Down pin can be used to apply a Hardware Reset

to the memory.

one cycle before. Valid Data Ready Low, V , in-

OL

11/61

M58LW032A

dicates that the data is not, or will not be valid. Val-

id DataReady in a high-impedance state indicates

that valid data is or will be available.

Unless Synchronous Burst Read has been select-

ed, Valid Data Ready is high-impedance. It may be

tied to other components with the same Valid Data

Ready signal to create a unique System Ready

signal.

Program/Erase Enable must be kept High during

all Program/Erase Controller operations, other-

wise the operations is not guaranteed to succeed

and data may become corrupt.

V

Supply Voltage. The Supply Voltage, V

,

DD

is the core power supply. All internal circuits draw

their current from the V

gram/Erase Controller.

pin, including the Pro-

DD

The Valid Data Ready, R, output has an internal

pull-up resistor of approximately 1 MΩ powered

A 0.1µF capacitor should be connected between

the Supply Voltage, V , and the Ground, V , to

DD

SS

from V

, designers should use an external pull-

decouple the current surges from the power sup-

ply. The PCB track widths must be sufficient to

carry the currents required during all operations of

the parts, see Table 14, DC Characteristics, for

maximum current supply requirements.

DDQ

up resistor of the correct value to meet the external

timing requirements for Valid Data Ready rising.

Refer to Figure 19.

Ready/Busy (RB). The Ready/Busy output, RB,

is an open-drain output that can be used to identify

if the Program/Erase Controller is currently active.

When Ready/Busy is high impedance, the memo-

ry is ready for any Read, Program or Erase opera-

Input/Output Supply Voltage (V

). The In-

DDQ

put/Output Supply Voltage, V

, is the input/out-

DDQ

put buffer power supply. All input and output pins

and voltage references are powered and mea-

sured relative to the Input/Output Supply Voltage

tion. Ready/Busy is Low, V , during Program and

OL

Erase operations. When the device is busy it will

not accept any additional Program or Erase com-

mands exceptProgram/Erase Suspend. When the

Program/Erase Controller is idle, or suspended,

Ready Busy can float High through a pull-up resis-

tor.

pin, V

.

DDQ

The Input/Output Supply Voltage, V

ways be equal or less than the V

age, including during Power-Up.

A 0.1µF capacitor should be connected between

the Input/Output Supply Voltage, V , and the

Ground, V

from the power supply. If V

nected together then only one decoupling capaci-

tor is required.

, must al-

Supply Volt-

DDQ

DD

DDQ

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

, to decouple the current surges

SSQ

and V are con-

DDQ

DD

Ready/Busy is not Low during a reset unless the

reset was applied when the Program/Erase Con-

troller was active; Ready/Busy can rise before Re-

set/Power-Down rises.

Ground (V ). Ground, V

is the reference for

SS,

SS

all core power supply voltages.

Ground (V ). Ground, V

is the reference

SSQ,

SSQ

for input/output voltage measurements. It is es-

sential to connect V and V to the same

Program/Erase Enable (V ). The

Program/

PP

SS

SSQ

Erase Enable input, V

is used to protect all

PP,

ground

.

blocks, preventing Program and Erase operations

from affecting their data.

12/61

M58LW032A

BUS OPERATIONS

There are 12 bus operations that control the mem-

ory. Each of these is described in this section, see

Tables 2 and 3, Bus Operations, for a summary.

The bus operation is selected through the Burst

Configuration Register; the bits in this register are

described at the end of this section.

On Power-up or after a Hardware Reset the mem-

ory defaults to Asynchronous Latch Enable Con-

trolled Read and Asynchronous Bus Write, no

other bus operation can be performed until the

Burst Control Register has been configured.

The Electronic Signature, CFI or Status Register

will be read in asynchronous mode or single syn-

chronous burst mode.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

operations can be performed when the memory is

configured for Asynchronous Latch Enable bus

operations by holding Latch Enable Low, V

throughout the bus operation.

IL

Asynchronous Page Read. Asynchronous Page

Read operations are used to read from several ad-

dresses within the same memory page. Each

memory page is 4 Words and has the same A3-

A21, only A1 and A2 may change.

Valid bus operations are the same as Asynchro-

nous Bus Read operations but with different tim-

ings. The first read operation within the page has

identical timings, subsequent reads within the

same page have much shorter access times. If the

page changes then the normal, longer timings ap-

ply again. See Figure 13, Asynchronous Page

Read AC Waveforms and Table 17, Asynchro-

nous Page Read AC Characteristics for details on

when the outputs become valid.

Asynchronous Bus Write. Asynchronous Bus

Write operations write to the Command Interface

in order to send commands to the memory or to

latch addresses and input data to program. Bus

Write operations are asynchronous, the clock, K,

is don’t care during Bus Write operations.

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 3

together with the text below.

Asynchronous Bus Read. Asynchronous Bus

Read operations read from the memory cells, or

specific registers (Electronic Signature, Status

Register, CFI and Block Protection Status) in the

Command Interface. A valid bus operation in-

volves setting the desired address on the Address

A valid Asynchronous Bus Write operation begins

by setting the desired address on the Address In-

Inputs, applying a Low signal, V , to Chip Enable,

IL

puts and setting Latch Enable Low, V . The Ad-

IL

Output Enable and Latch Enable and keeping

dress Inputs are latched by the Command

Interface on the rising edge of Chip Enable or

Write Enable, whichever occurs first. The Data In-

puts/Outputs are latched by the Command Inter-

face on the rising edge of Chip Enable or Write

Enable, whichever occurs first. Output Enable

Write Enable High, V . The Data Inputs/Outputs

IH

will output the value, see Figure 11, Asynchronous

Bus Read AC Waveforms, and Table 15, Asyn-

chronous Bus Read AC Characteristics, for details

of when the output becomes valid.

Asynchronous Latch Controlled Bus Read.

must remain High, V , during the whole Asyn-

IH

chronous Bus Write operation. See Figures 14,

and 16, Asynchronous Write AC Waveforms, and

Tables 18 and 19, Asynchronous Write and Latch

Controlled Write AC Characteristics, for details of

the timing requirements.

Asynchronous Latch Controlled Bus Read opera-

tions read from the memory cells or specific regis-

ters in the Command Interface. The address is

latched in the memory before the value is output

on the data bus, allowing the address to change

during the cycle without affecting the address that

the memory uses.

Asynchronous Latch Controlled Bus Write.

Asynchronous Latch Controlled Bus Write opera-

tions write to the Command Interface in order to

send commands to the memory or to latch ad-

dresses and input data to program. Bus Write op-

erations are asynchronous, the clock, K, is don’t

care during Bus Write operations.

A valid bus operation involves setting the desired

address on the Address Inputs, setting Chip En-

able and Latch Enable Low, V and keeping Write

IL

Enable High, V ; theaddress is latched on the ris-

IH

ing edge of Address Latch. Once latched, the Ad-

dress Inputs can change. Set Output Enable Low,

A valid Asynchronous Latch Controlled Bus Write

operation begins by setting the desired address on

the Address Inputs and pulsing Latch Enable Low,

V , to read the data on the Data Inputs/Outputs;

IL

see Figure 12, Asynchronous Latch Controlled

Bus Read AC Waveforms and Table 16, Asyn-

chronous Latch Controlled Bus Read AC Charac-

teristics for details on when the output becomes

valid.

V . The Address Inputs are latched by the Com-

IL

mand Interface on the rising edge of Latch Enable,

Chip Enable or Write Enable, whichever occurs

first. The Data Inputs/Outputs are latched by the

Command Interface on the rising edge of Chip En-

able or Write Enable, whichever occurs first. Out-

Note that, since the Latch Enable input is transpar-

ent when set Low, V , Asynchronous Bus Read

IL

13/61

M58LW032A

put Enable must remain High, V , during the

Current, I

, for Program or Erase operations un-

IH

DD3

whole Asynchronous Bus Write operation. See

Figures 15 and 17 Asynchronous Latch Controlled

Write AC Waveforms, and Tables 18 and 19,

Asynchronous Write and Latch Controlled Write

AC Characteristics, for details of the timing re-

quirements.

til the operation completes.

Automatic Low Power. If there is no change in

the state of the bus for a short period of time during

Asynchronous Bus Read operations the memory

enters Auto Low Power mode where the internal

Supply Current is reduced to the Auto-Standby

Supply Current, I

still output data if a Bus Read operation is in

progress.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when the Output Enable

is High.

. The Data Inputs/Outputs will

DD5

Standby. When Chip Enable is High, V , the

Automatic Low Power is only available in Asyn-

chronous Read modes.

IH

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high imped-

ance state regardless of Output Enable or Write

Enable. The Supply Current is reduced to the

Power-Down. The memory is in Power-Down

mode when Reset/Power-Down, RP, is Low. The

power consumption is reduced to the Power-Down

Standby Supply Current, I

.

DD1

level, I

, and the outputs are high impedance,

DD2

During Program or Erase operations the memory

will continue to use the Program/Erase Supply

independent of Chip Enable, Output Enable or

Write Enable.

Table 2. Asynchronous Bus Operations

Bus Operation

Step

E

G

W

RP

L

A1-A21

Address

X

DQ0-DQ15

Data Output

High Z

V

Asynchronous Bus Read

High

IL

IH

IL

V

Address Latch

Read

Asynchronous Latch

Controlled Bus Read

Data Output

Data Input

IH

V

Asynchronous Page Read

Asynchronous Bus Write

Address

IL

V

IH

IL

Asynchronous Latch

Controlled Bus Write

V

Address Latch

High

Address

Data Input

IL

V

Output Disable

Standby

High

X

High Z

IH

X

IH

V

Power-Down

X

IL

Note: 1. X = Don’t Care V or V . High = V or V .

HH

IL

IH

14/61

M58LW032A

Synchronous Bus Operations

For synchronous bus operations refer to Table 3

together with the text below.

Synchronous Burst Read. Synchronous Burst

Read operations are used to read from the memo-

ry at specific times synchronized to an external ref-

erence clock. The burst type, length and latency

can be configured. The different configurations for

Synchronous Burst Read operations are de-

scribed in the Burst Configuration Register sec-

tion.

the X-latency specified in the Burst Control Regis-

ter has expired. The output buffers are activated

by setting Output Enable Low, V . See Figures 6

IL

and 7 for examples of Synchronous Burst Read

operations.

In Continuous Burst mode one Burst Read opera-

tion can access the entire memory sequentially. If

the starting address is not associated with a page

(4 Word) boundary the Valid Data Ready, R, out-

put goes Low, V , to indicate that the data will not

IL

be ready in time and additional wait-states are re-

quired. The Valid Data Ready output timing (bit

M8) can be changed in the Burst Configuration

Register.

A valid Synchronous Burst Read operation begins

when the address is set on the Address Inputs,

Write Enable is High, V , and Chip Enable and

IH

The Synchronous Burst Read timing diagrams

and AC Characteristics are described in the AC

and DC Parameters section. See Figures 18, 19

and Table 20.

Latch Enable are Low, V , during the active edge

IL

of the Clock. The address is latched on the first ac-

tive clock edge when Latch Enable is low, or on

the rising edge of Latch Enable, whichever occurs

first. The data becomes available for output after

Table 3. Synchronous Burst Read Bus Operations

A1-A21

(3)

Bus Operation

Step

E

G

RP

L

K

DQ0-DQ15

Address Input

Data Output

High Z

V

IL

Address Latch

Synchronous Burst Read Read

Read Abort

X

T

IL

IH

V

T

X

IL

IH

V

X

IH

Note: 1. X = Don’t Care, V or V

.

IH

IL

2. M15 = 0, Bit M15 is in the Burst Configuration Register.

3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.

15/61

M58LW032A

Burst Configuration Register

Y-Latency Bit (M9). The Y-Latency bit is used

during Synchronous Bus Read operations to set

the number of clock cycles between consecutive

reads. The Y-Latency value depends on both the

X-Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each

clock cycle; when the Y-Latency is 2 the data

changes every second clock cycle. See Table 4,

Burst Configuration Register for valid combina-

tions of the Y-Latency, the X-Latency and the

Clock frequency.

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform. The Burst Configuration Register bits are

described in Table 4. They specify the selection of

the burst length, burst type, burst X and Y laten-

cies and the Read operation. See figures 6 and 7

for examples of Synchronous Burst Read configu-

rations.

The Burst Configuration Register is set through

the Command Interface and will retain its informa-

tion until it is re-configured, the device is reset, or

the device goes into Reset/Power-Down mode.

The Burst Configuration Register is read using the

Read Electronic Signature Command at address

05h.

Valid Data Ready Bit (M8). The

Valid

Data

Ready bit controls the timing of the Valid Data

Ready output pin, R. When the Valid Data Ready

bit is ’0’ the Valid Data Ready output pin is driven

Low for the active clock edge when invalid data is

output on the bus. When the Valid Data Ready bit

is ’1’ the Valid Data Ready output pin is driven Low

one clock cycle prior to invalid data being output

on the bus.

Burst Type Bit (M7). The Burst Type bit is used

to configure the sequence of addresses read as

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ the memory

outputs from sequential addresses. See Tables 5,

Burst Type Definition, for the sequence of ad-

dresses output from a given starting address in

each mode.

Valid Clock Edge Bit (M6). The Valid Clock Edge

bit, M6, is used to configure the active edge of the

Clock, K, during Synchronous Burst Read opera-

tions. When the Valid Clock Edge bit is ’0’ the fall-

ing edge of the Clock is the active edge; when the

Valid Clock Edge bit is ’1’ the rising edge of the

Clock is active.

Burst Length Bit (M2-M0). The Burst Length bits

set the maximum number of Words that can be

output during a Synchronous Burst Read opera-

tion.

Read Select Bit (M15). The Read Select bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set to

’1’ for asynchronous access.

X-Latency Bits (M13-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 4,

Burst Configuration Register.

Internal Clock Divider Bit (M10). The Internal

Clock DividerBit is used to divide the internal clock

by two. When M10 is set to ‘1’ the internal clock is

divided by two, which effectively means that the X

and Y-Latency values are multiplied by two, that is

the number of clock cycles between the address

being latched and the first data becoming avail-

able will be twice the value set in M13-M11, and

the number of clock cycles between consecutive

reads will be twice the value set in M9. For exam-

ple 8-1-1-1will become 16-2-2-2. When M10 is set

to ‘0’ the internal clock runs normally and the X

and Y-Latency values are those set in M13-M11

and M9.

Table 4, Burst Configuration Register gives the

valid combinations of the Burst Length bits that the

memory accepts; Tables 5, Burst Type Definition,

give the sequence of addresses output from a giv-

en starting address for each length.

M5 M4 and M3 are reserved for future use.

16/61

M58LW032A

Table 4. Burst Configuration Register

Address

Bit

Reset

Value

Mnemonic

Bit Name

Value

Description

Synchronous Burst Read

0

1

16

15

M15

M14

Read Select

1

Asynchronous Bus Read (default at power-up)

Reserved

001

010

011

(1)

X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)

X-Latency = 5, 5-1-1-1, 5-2-2-2

14

to

12

(2)

M13-M11

XXX

X-Latency

100

101

110

X-Latency = 6, 6-1-1-1, 6-2-2-2

X-Latency = 7, 7-1-1-1, 7-2-2-2

X-Latency = 8, 8-1-1-1, 8-2-2-2

0

1

0

1

0

1

0

1

0

1

X and Y-Latencies remains as set in M13-M11 and M9

Internal

Clock Divider

11

10

9

M10

M9

X

Divides internal clock, X and Y-Latencies multiplied by 2

Y-Latency = 1

(3)

Y-Latency

Y-Latency = 2

R valid Low during valid Clock edge

Valid Data

Ready

M8

R valid Low one cycle before valid Clock edge

Interleaved

Sequential

8

M7

Burst Type

Falling Clock edge

Rising Clock edge

Reserved

Valid Clock

Edge

7

M6

6 to 4

M5-M3

001

010

111

4 Words

3

to

1

M2-M0

Burst Length

XXX

8 Words

Continuous

Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed.

2. X latencies can be calculated as: (t

is the clock period).

– t

LLKH

+ t ) + t < (X -1) t (X is an integer number from 4 to 8 and t

QVKH SYSTEM MARGIN K. K

AVQV

3. Y latencies can be calculated as: t

4. t

+ t

< Y t

QVKH K.

KHQV

SYSTEM MARGIN

is the time margin required for the calculation.

SYSTEM MARGIN

17/61

M58LW032A

Table 5. Burst Type Definition

Starting

x4

x8

Addres

s

Continuous

Sequential Interleaved

Sequential

Interleaved

0

1

2

3

4

5

6

7

8

0-1-2-3

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

–

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

–

0-1-2-3-4-5-6-7-8-9-10..

1-2-3-4-5-6-7-8-9-10-11..

2-3-4-5-6-7-8-9-10-11-12..

3-4-5-6-7-8-9-10-11-12-13..

4-5-6-7-8-9-10-11-2-13-14..

5-6-7-8-9-10-11-12-13-14..

6-7-8-9-10-11-12-13-14-15..

7-8-9-10-11-12-13-14-15-16..

8-9-10-11-12-13-14-15-16-17..

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

–

Figure 6. Burst Configuration X-1-1-1

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

DQ

VALID

4-1-1-1

5-1-1-1

DQ

VALID

DQ

VALID

6-1-1-1

7-1-1-1

8-1-1-1

AI05512

18/61

M58LW032A

Figure 7. Burst Configuration X-2-2-2

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

NV

DQ

VALID

NV

VALID

NV

VALID

5-2-2-2

DQ

NV

VALID

NV

VALID

NV

VALID

NV

VALID

NV

6-2-2-2

7-2-2-2

8-2-2-2

VALID

NV=NOT VALID

AI05513

19/61

M58LW032A

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. The Commands are summarized in Table

6, Commands. Refer to Table 6 in conjunction with

the text descriptions below.

Register. One Bus Write cycle is required to issue

the Read Status Register command. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued.

The Status Register information is present on the

output data bus (DQ1-DQ7) when both Chip En-

After power-up or a Reset operation the memory

enters Read mode.

able and Output Enable are low, V .

IL

Synchronous Read operations and Latch Con-

trolled Bus Read operations can only be used to

read the memory array. The Electronic Signature,

CFI or Status Register will be read in asynchro-

nous mode or single synchronous burst mode.

Once the memory returns to Read Memory Array

mode the bus will resume the setting in the Burst

Configuration Register automatically.

See the section on the Status Register and Table

10 for details on the definitions of the Status Reg-

ister bits

Clear Status Register Command. The Clear Sta-

tus Register command can be used to reset bits 1,

3, 4 and 5 in the Status Register to ‘0’. One Bus

Write is required to issue the Clear Status Register

command.

Read Memory Array Command. The Read Mem-

ory Array command returns the memory to Read

mode. One Bus Write cycle is required to issue the

Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read commands will access the memory array.

While the Program/Erase Controller is executing a

Program, Erase, Block Protect, Blocks Unprotect

or Protection Register Program operation the

memory will not accept the Read Memory Array

command until the operation completes.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Write to

Buffer and Program, Erase, Block Protect, Block

Unprotect or Protection Register Program com-

mand is issued. If any error occurs then it is essen-

tial to clear any error bits in the Status Register by

issuing the Clear Status Register command before

attempting a new Program, Erase or Resume

command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all of

the bits in the block to ‘1’. All previous data in the

block is lost. If the block is protected then the

Erase operation will abort, the data in the block will

not be changed and the Status Register will output

the error.

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code, the Device Code, the Block

Protection Status, the Burst Configuration Regis-

ter and the Protection Register. One Bus Write cy-

cle is required to issue the Read Electronic

Signature command. Once the command is is-

sued subsequent Bus Read operations read the

Manufacturer Code, the Device Code, the Block

Protection Status, the Burst Configuration Regis-

ter or the Protection Register until another com-

mand is issued. Refer to Table 7, Read Electronic

Signature, Table 8, Read Protection Register and

Figure 8, Protection Register Memory Map for in-

formation on the addresses.

Read Query Command. The Read Query Com-

mand is used to read data from the Common Flash

Interface (CFI) Memory Area. One Bus Write cycle

is required to issue the Read Query Command.

Once the command is issued subsequent Bus

Read operations read from the Common Flash In-

terface Memory Area. See Appendix B, Tables 27,

28, 29, 30, 31 and 32 for details on the information

contained in the Common Flash Interface (CFI)

memory area.

Two Bus Write operations are required to issue the

command; the second Bus Write cycle latches the

block address in the internal state machine and

starts the Program/Erase Controller. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register. See the section on

the Status Register for details on the definitions of

the Status Register bits.

During the Erase operation the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

commands will be ignored. Typical Erase times

are given in Table 9.

See Appendix C, Figure 25, Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Erase command.

Word Program Command. The Word Program

command is used to program a single word in the

memory array. Two Bus Write operations are re-

quired to issue the command; the first write cycle

sets up the Word Program command, the second

write cycle latches the address and data to be pro-

grammed in the internal state machine and starts

the Program/Erase Controller.

Read Status Register Command. The Read Sta-

tus Register command is used to read the Status

20/61

M58LW032A

If the block being programmed is protected an er-

ror will be set in the Status Register and the oper-

ation will abort without affecting the data in the

memory array. The block must be unprotected us-

ing the Blocks Unprotect command.

Write to Buffer and Program Command. The

Write to Buffer and Program command is used to

program the memory array.

gram or Write to Buffer and Program command if

the Program/Erase Controller is running.

One Bus Write cycle is required to issue the Pro-

gram/Erase Suspend command and pause the

Program/Erase Controller. Once the command is

issued it is necessary to poll the Program/Erase

Controller Status bit (bit 7) to find out when the

Program/Erase Controller has paused; no other

commands will be accepted until the Program/

Erase Controller has paused. After the Program/

Erase Controller has paused, the memory will con-

tinue to output the Status Register until another

command is issued.

Up to 16 Words can be loaded into the Write Buffer

and programmed into the memory. Each Write

Buffer has the same A5-A21 addresses.

Four successive steps are required to issue the

command.

During the polling period between issuing the Pro-

gram/Erase Suspend command and the Program/

Erase Controller pausing it is possible for the op-

eration to complete. Once the Program/Erase

Controller Status bit (bit 7) indicates that the Pro-

gram/Erase Controller is no longer active, the Pro-

gram Suspend Status bit (bit 2) or the Erase

Suspend Status bit (bit 6) can be used to deter-

mine if the operation has completed or is suspend-

ed. For timing on the delay between issuing the

Program/Erase Suspend command and the Pro-

gram/Erase Controller pausing see Table 9.

1. One Bus Write operation is required to set up

the Write to Buffer and Program Command. Is-

sue the set up command with the selected

memory Block Address where the program op-

eration should occur (any address in the block

where the values will be programmed can be

used). AnyBus Read operations will start to out-

put the Status Register after the 1st cycle.

2. Use one Bus Write operation to write the same

block address along with the value N on the

Data Inputs/Output, where N+1 is the number of

Words to be programmed.

During Program/Erase Suspend the Read Memo-

ry Array, Read Status Register, Read Electronic

Signature, Read Query and Program/Erase Re-

sume commands will be accepted by the Com-

mand Interface. Additionally, if the suspended

operation was Erase then the Write to Buffer and

Program, and the Program Suspend commands

will also be accepted. When a program operation

is completed inside a Block Erase Suspend the

Read Memory Array command must be issued to

reset the device in Read mode, then the Erase Re-

sume command can be issued to complete the

whole sequence. Only the blocks not being erased

may be read or programmed correctly.

3. Use N+1 Bus Write operations to load the ad-

dress and data for each Word into the Write

Buffer. See the constraints on the address com-

binations listed below. The addresses must

have the same A5-A21.

4. Finally, useone Bus Write operation to issue the

final cycle to confirm the command and start the

Program operation.

Invalid address combinations or failing to follow

the correct sequence of Bus Write cycles will set

an error in the Status Register and abort the oper-

ation without affecting the data in the memory ar-

ray. The Status Register should be cleared before

re-issuing the command.

If the block being programmed is protected an er-

ror will be set in the Status Register and the oper-

ation will abort without affecting the data in the

memory array. The block must be unprotected us-

ing the Blocks Unprotect command.

See Appendix C, Figure 24, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

26, Erase Suspend & Resume Flowchart and

Pseudo Code, for suggested flowcharts on using

the Program/Erase Suspend command.

Program/Erase Resume Command. The

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after

Pro-

See Appendix C, Figure 23, Write to Buffer and

Program Flowchart and Pseudo Code, for a sug-

gested flowchart on using the Write to Buffer and

Program command.

a

Program/Erase Suspend operation has paused it.

One Bus Write cycle is required to issue the Pro-

gram/Erase Resume command. Once the com-

mand is issued subsequent Bus Read operations

read the Status Register.

Program/Erase Suspend Command. The

Pro-

gram/Erase Suspend command is used to pause a

Word Program, Write to Buffer and Program or

Erase operation. The command will only be ac-

cepted during a Program or an Erase operation. It

can be issued at any time during an Erase opera-

tion but will only be accepted during a Word Pro-

Set Burst Configuration Register Command.

The Set Burst Configuration Register command is

used to write a new value to the Burst Configura-

tion Control Register which defines the burst

length, type, X and Y latencies, Synchronous/

21/61

M58LW032A

Asynchronous Read mode and the valid Clock

edge configuration.

definitions of the Status Register bits. Typical

Block Protection times are given in Table 9.

Two Bus Write cycles are required to issue the Set

Burst Configuration Register command. Once the

command is issued the memory returns to Read

mode as if a Read Memory Array command had

been issued.

The value for the Burst Configuration Register is

presented on A1-A16. M0 is on A1, M1 on A2, etc.;

the other address bits are ignored.

See Appendix C, Figure 28, Block Unprotect Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Unprotect command.

Protection Register Program Command. The

Protection Register Program command is used to

Program the 64 bit user segment of the Protection

Register. The segment is programmed 16 bits at a

time. The memory must be reset by issuing the

Read Memory Array command before the Protec-

tion Register Program command can be issued.

Two write cycles are required to issue the Protec-

tion Register Program command.

Block Protect Command. The Block Protect

command is used to protect a block and prevent

Program or Erase operations from changing the

data in it. Two Bus Write cycles are required to is-

sue the Block Protect command; the second Bus

Write cycle latches the block address in the inter-

nal state machine and starts the Program/Erase

Controller. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister. See the section on the Status Register for

details on the definitions of the Status Register

bits. Typical Block Protection times are given in

Table 9.

The Block Protection bits are non-volatile, once

set they remain set through reset and power-

down/power-up. They are cleared by a Blocks Un-

protect command.

See Appendix C, Figure 27, Block Protect Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Protect command.

■ The first bus cycle sets up the Protection

Register Program command.

■ The secondlatches theAddress and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The user-programmable segment can be locked

by programming bit 1 of the Protection Register

Lock location to ‘0’ (see Table 8). Bit 0 of the Pro-

tection Register Lock location locks the factory

programmed segment and is programmed to ‘0’ in

the factory. The locking of the Protection Register

is not reversible, once the lock bits are pro-

grammed no further changes can be made to the

values stored in the Protection Register, see Fig-

ure 8, Protection Register Memory Map. Attempt-

ing to program a previously protected Protection

Register will result in a Status Register error.

Blocks Unprotect Command. The Blocks Un-

protect command is used to unprotect all of the

blocks. Two Bus Write cycles are required to issue

the Blocks Unprotect command; the second Bus

Write cycle starts the Program/Erase Controller.

Once the command is issued subsequent Bus

Read operations read the Status Register. See the

section on the Status Register for details on the

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 29, Protection

Register Program Flowchart and Pseudo Code,

for the flowchart for using the Protection Register

Program command.

22/61

M58LW032A

Table 6. Commands

Command

Bus Operations

1st Cycle

2nd Cycle

Addr.

Subsequent

Final

Op. Addr. Data Op.

Data Op. Addr. Data Op. Addr. Data

Read Memory Array

≥ 2 Write

X

FFh Read

90h Read

70h Read

98h Read

RA

RD

(3)

Read Electronic Signature ≥ 2 Write

IDA

IDD

Read Status Register

Read Query

2

Write

X

SRD

(4)

≥ 2 Write

QA

QD

Clear Status Register

Block Erase

1

2

Write

X

50h

20h Write

BA

PA

D0

PD

40h

Word Program

2

Write

X

Write

10h

Write to Buffer and

Program

4 + N Write BA

E8h Write

BA

N

Write PA PD Write

X

D0h

Program/Erase Suspend

Program/Erase Resume

1

Write

X

B0h

D0h

Set Burst Configuration

Register

2

Write

X

60h Write

BCR

03h

Block Protect

2

Write BA

60h Write

BA

X

01h

D0h

Blocks Unprotect

Write

X

Protection Register

Program

2

C0h Write

PRA

PRD

Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program

Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register

value.

2. Base Address, refer to Figure 8 and Table 8 for more information.

3. For Identifier addresses and data refer to table 7, Read Electronic Signature.

4. For Query Address and Data refer to Appendix B, CFI.

Table 7. Read Electronic Signature

Code

Manufacturer Code

Address (A21-A1)

000000h

Data (DQ15-DQ0)

0020h

Device Code

000001h

8816h

0000h (Block Unprotected)

0001h (Block Protected)

Block Protection Status

SBA+02h

000005h

Burst Configuration Register

Protection Register

BCR

PRD

(2)

000080h

Note: 1. SBA is the Start Base Address of each block, BCR is Burst Configuration Register data, PRD is Protection Register Data.

2. Base Address, refer to Figure 8 and Table 8 for more information.

23/61

M58LW032A

Table 8. Read Protection Register

Word

Use

Factory, User

Factory (Unique ID)

User

A8

1

A7

0

A6

0

A5

0

A4

0

A3

0

A2

0

A1

0

Lock

0

1

2

3

4

5

6

7

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

User

1

0

1

0

User

1

0

1

User

1

0

1

0

Figure 8. Protection Register Memory Map

WORD

ADDRESS

88h

User Programmable

85h

84h

Unique device number

81h

80h

Protection Register Lock

1

0

AI05501

24/61

M58LW032A

Table 9. Program, Erase Times and Program Erase Endurance Cycles

M58LW032A

Parameters

Unit

Typical after

100k W/E Cycles

Min

Typ

Max

Block (521Kb) Erase

Chip Program

1.1

s

(2)

t.b.a.

Program Write Buffer

290

µs

Program Suspend Latency Time

Erase Suspend Latency Time

Block Protect Time

20

25

µs

18

µs

Blocks Unprotect Time

0.75

s

Program/Erase Cycles (per block)

100,000

Note: 1. (T = 0 to 70°C; V = 2.7V to 3.6V; V =1.8V)

DDQ

cycles

A

DD

2. t.b.a. to be announced

25/61

M58LW032A

STATUS REGISTER

The Status Register provides information on the

current or previous Program, Erase, Block Protect

or Blocks Unprotect operation. The various bits in

the Status Register convey information and errors

on the operation. They are output on DQ7-DQ0.

inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is Low, V

,

OL

the Program/Erase Controller isactive or has com-

To read the Status Register the Read Status Reg-

ister commandcan be issued. The Status Register

is automatically read after Program, Erase, Block

Protect, Blocks Unprotect and Program/Erase Re-

sume commands. The Status Register can be

read from any address.

pleted its operation; when the bit is High, V , a

OH

Program/Erase Suspend command has been is-

sued and the memory is waiting for a Program/

Erase Resume command.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

The Status Register can only be read using Asyn-

chronous Bus Read operations. Once the memory

returns to Read Memory Array mode the bus will

resume the setting in the Burst Configuration Reg-

ister automatically.

Erase Status (Bit 5). The EraseStatus bit can be

used to identify if the memory has failed to verify

that the block has erased correctly or that all

blocks have been unprotected successfully. The

Erase Status bit should be read once the Program/

Erase Controller Status bit is High (Program/Erase

Controller inactive).

The contents of the Status Register can be updat-

ed during an Erase or Program operation by tog-

gling the Output Enable pin or by dis-activating

When the Erase Status bit is Low, V , the mem-

OL

(Chip Enable, V ) and then reactivating (Chip En-

IH

ory has successfully verified that the block has

erased correctly or all blocks have been unprotect-

ed successfully. When the Erase Status bit is

able and Output Enable, V ) the device.

IL

Status Register bits 5, 4, 3 and 1 are associated

with various error conditions and can only be reset

with the Clear Status Register command. The Sta-

tus Register bits are summarized in Table 10, Sta-

tus Register Bits. Refer to Table 10 in conjunction

with the following text descriptions.

High, V , the erase operation has failed. De-

OH

pending on the cause of the failure other Status

Register bits may also be set to High, V

.

OH

■ If only the Erase Status bit (bit 5) is set High,

, then the Program/Erase Controller has

V

OH

Program/Erase Controller Status (Bit 7). ThePro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

applied the maximum number of pulses to the

block and still failed to verify that the block has

erased correctly or that all the blocks have been

unprotected successfully.

Low, V , the Program/Erase Controller is active

OL

■ If the failure is due to an erase or blocks

and all other Status Register bits are High Imped-

unprotect with V low, V , then V Status bit

PP

OL

PP

ance; when the bit is High, V , the Program/

OH

(bit 3) is also set High, V

.

OH

Erase Controller is inactive.

■ If the failure is due to an erase on a protected

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

block then Block Protection Status bit (bit 1) is

also set High, V

.

OH

■ If the failure is due to a program or erase

incorrect command sequence then Program

Status bit (bit 4) is also set High, V

.

OH

During Program, Erase, Block Protect and Blocks

Unprotect operations the Program/Erase Control-

ler Status bit can be polled to find the end of the

operation. The other bits in the Status Register

should not be tested until the Program/Erase Con-

troller completes the operation and the bit is High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status and

Block Protection Status bits should be tested for

errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended and is waiting to be re-

sumed. The Erase Suspend Status should only be

considered valid when the Program/Erase Con-

troller Status bit is High (Program/Erase Controller

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program or Block Protect fail-

ure. The Program Status bit should be read once

the Program/Erase Controller Status bit is High

(Program/Erase Controller inactive).

When the Program Status bit is Low, V , the

OL

memory has successfully verified that the Write

Buffer has programmed correctly or the block is

protected. When the Program Status bit is High,

V

, the program or block protect operation has

OH

26/61

M58LW032A

failed. Depending on the cause of the failure other

Status Register bits may also be set to High, V

Unprotection command is issued, otherwise the

new command will appear to fail.

.

OH

■ If only the Program Status bit (bit 4) is set High,

, then the Program/Erase Controller has

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive); after a Program/Erase Suspend

command is issued the memory may still complete

the operation rather than entering the Suspend

mode.

V

OH

applied the maximum number of pulses to the

byte and still failed to verify that the Write Buffer

has programmed correctly or that the Block is

protected.

■ If the failure is due to a program or block protect

with V low, V , then V Status bit (bit 3) is

PP

OL

PP

also set High, V

.

OH

■ If the failure is due to a program on a protected

When the Program Suspend Status bit is Low,

block then Block Protection Status bit (bit 1) is

V

, the Program/Erase Controller is active or has

OL

also set High, V

.

OH

completed its operation; when the bit is High, V

,

OH

■ If the failure is due to a program or erase

a Program/Erase Suspend command has been is-

sued and the memory is waiting for a Program/

Erase Resume command.

incorrect command sequence then Erase

Status bit (bit 5) is also set High, V

.

OH

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

When a Program/Erase Resume command is is-

sued theProgram Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a protected block.

V

Status (Bit 3). The V

Status bit can be

PP

used to identify if a Word Program, Erase, Block

When the Block Protection Status bit is Low, V

,

OL

Protection or Block Unprotection operation has

no Program or Erase operations have been at-

tempted to protected blocks since the last Clear

Status Register command or hardware reset;

been attempted when V

is Low, V . The V

IL PP

PP

Status bit cannot be used during a Write to Buffer

and Program operation.

when the Block Protection Status bit is High, V

,

OH

When theV Status bit is Low, V , no Word Pro-

PP

OL

a Program (Program Status bit 4 set High) or

Erase (Erase Status bit 5 set High) operation has

been attempted on a protected block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new Program or Erase command is

issued, otherwise the new command will appear to

fail.

gram, Erase, Block Protection or Block Unprotec-

tion operations have been attempted with V

PP

Low, V , since the last Clear Status Register com-

IL

mand, or hardware reset. When the V Status bit

PP

is High, V , a Word Program, Erase, Block Pro-

OH

tection or Block Unprotection operation has been

attempted with V Low, V .

PP

IL

Once setHigh, the V Status bit can only be reset

PP

by a Clear Status Register command or a hard-

ware reset. If set High it should be reset before a

new Program, Erase, Block Protection or Block

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value should be masked.

27/61

M58LW032A

Table 10. Status Register Bits

OPERATION

Result

(Hex)

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3 Bit 2 Bit 1

RB

V

Program/Erase Controller active

Write Buffer not ready

0

1

N/A

80h

C0h

84h

C4h

OL

V

OL

V

OL

V

OL

V

OL

V

OL

Write Buffer ready

0

1

0

1

0

1

0

Hi-Z

Write Buffer ready in Erase Suspend

Program suspended

Program suspended in Erase Suspend

Program/Block Protect completed

successfully

1

0

1

0

1

0

1

0

1

0

1

0

Hi-Z

80h

C0h

B0h

F0h

98h

Program completed successfully in Erase

Suspend

Program/Block protect failure due to

incorrect command sequence

Program failure due to incorrect command

sequence in Erase Suspend

Word Program/Block Protect failure due to

V

error

PP

Word Program failure due to V error in

Erase Suspend

PP

1

0

1

0

1

0

1

Hi-Z

D8h

92h

D2h

Program failure due to Block Protection

Program failure due to Block Protection in

Erase Suspend

Program/Block Protect failure due to cell

failure

1

0

1

0

Hi-Z

90h

Program failure due to cell failure in Erase

Suspend

1

0

1

0

Hi-Z

D0h

C0h

80h

Erase Suspended

Erase/Blocks Unprotect completed

successfully

Erase/Blocks Unprotect failure due to

incorrect command sequence

1

0

1

0

Hi-Z

B0h

Erase/Blocks Unprotect failure due to V

error

PP

1

0

1

0

1

0

1

0

Hi-Z

A8h

A2h

A0h

Erase failure due to Block Protection

Erase/Blocks Unprotect failure due to

failed cells in Block

28/61

M58LW032A

MAXIMUM RATING

Stressing the device above the ratings listed in Ta-

ble 11, Absolute Maximum Ratings, may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

to

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 11. Absolute Maximum Ratings

Value

Symbol

Parameter

Temperature Under Bias

Unit

Min

–40

–55

–0.6

Max

125

150

T

BIAS

°C

V

T

STG

Storage Temperature

Input or Output Voltage

Supply Voltage

V

+0.6

DDQ

IO

V

, V

DD DDQ

5.0

V

29/61

M58LW032A

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 12,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 12. Operating and AC Measurement Conditions

M58LW032A

Units

Parameter

90

110

Min

Max

Min

2.7

1.8

0

Max

Supply Voltage (V

)

2.7

1.8

0

3.6

V

3.6

V

DD

Input/Output Supply Voltage (V

)

V

DDQ

DD

Grade 1

Grade 6

70

85

70

85

°C

pF

ns

V

Ambient Temperature (T )

A

–40

Load Capacitance (C )

30

L

Clock Rise and Fall Times

Input Rise and Fall Times

Input Pulses Voltages

3

4

3

4

0 to V

0.5 V

0 to V

0.5 V

DDQ

Input and Output Timing Ref. Voltages

V

DDQ

Figure 9. AC Measurement Input Output

Waveform

Figure 10. AC Measurement Load Circuit

1.3V

1N914

V

DDQ

V

DD

3.3kΩ

V

DDQ

0.5 V

DDQ

DEVICE

UNDER

TEST

DQ

S

0V

C

L

AI00610

0.1µF

C

includes JIG capacitance

L

AI03459

Table 13. Capacitance

Symbol

Parameter

Test Condition

Typ

6

Max

8

Unit

pF

C

V

= 0V

Input Capacitance

IN

C

V

OUT

Output Capacitance

8

12

OUT

Note: 1. T = 25°C, f = 1 MHz

A

2. Sampled only, not 100% tested.

30/61

M58LW032A

Table 14. DC Characteristics

Symbol

Parameter

Test Condition

Min

Max

±1

±5

20

Unit

µA

I

0V≤ V ≤ V

Input Leakage Current

LI

IN

DDQ

I

Output Leakage Current

0V≤ V

≤V

DDQ

µA

LO

OUT

E = V , G = V , f

= 6MHz

Supply Current (Random Read)

Supply Current (Burst Read)

Supply Current (Standby)

mA

µA

DD

IL

IH add

I

E = V , G = V , f = 50MHz

IH clock

30

DDB

IL

I

E = V , RP = V

40

DD1

DD5

DD2

IH

I

E = V , RP = V

Supply Current (Auto Low-Power)

Supply Current (Reset/Power-Down)

40

µA

IL

RP = V

40

µA

IL

Supply Current (Program or Erase,

Block Protect, Block Unprotect)

Program or Erase operation in

progress

I

30

mA

DD3

DD4

Supply Current

(Erase/Program Suspend)

E = V

40

µA

IH

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

–0.5

2

0.8

V

IL

V

+ 0.5

DDQ

IH

I

= 100µA

OL

0.2

2

OL

V

OH

I

= –100µA

V

–0.2

DDQ

OH

V

Supply Voltage (Erase and

DD

V

LKO

Program lockout)

31/61

M58LW032A

Figure 11. Asynchronous Bus Read AC Waveforms

tAVAV

A1-A21

VALID

tELQV

tELQX

tAXQX

E

L

tGLQV

tGLQX

tEHQZ

tEHQX

G

tAVQV

tGHQZ

tGHQX

DQ0-DQ15

OUTPUT

AI05502

Note: Asynchronous Read M15 = 1

Table 15. Asynchronous Bus Read AC Characteristics.

M58LW032A

90 110

Symbol

Parameter

Test Condition

Unit

t

E = V , G = V

IL

Address Valid to Address Valid

Min

Max

Min

Max

Min

Max

Min

Max

90

0

110

0

ns

AVAV

IL

t

E = V , G = V

Address Valid to Output Valid

AVQV

IL

t

G = V

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Output Transition

Output Enable High to Output Transition

Address Transition to Output Transition

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

ELQX

IL

t

G = V

90

0

110

0

ELQV

IL

t

E = V

GLQX

GLQV

EHQX

IL

25

0

25

0

G = V

E = V

IL

0

GHQX

IL

t

E = V , G = V

0

AXQX

EHQZ

IL

t

G = V

25

20

25

20

IL

E = V

GHQZ

IL

32/61

M58LW032A

Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms

A1-A21

VALID

tAVLH

tLHAX

tAVLL

L

tLHLL

tLLLH

tEHLX

tELLH

tELLL

E

tGLQV

tGLQX

tEHQZ

tEHQX

G

tLLQX

tLLQV

tGHQZ

tGHQX

DQ0-DQ15

OUTPUT

AI05503

Note: Asynchronous Read M15 = 1

Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics

M58LW032A

Symbol

Parameter

Test Condition

E = V

Unit

90

0

110

0

t

Address Valid to Latch Enable Low

Address Valid to Latch Enable High

Latch Enable High to Latch Enable Low

Latch Enable Low to Latch Enable High

Chip Enable Low to Latch Enable Low

Chip Enable Low to Latch Enable High

Latch Enable Low to Output Transition

Latch Enable Low to Output Valid

Min

Max

Min

ns

AVLL

IL

E = V

10

0

10

0

AVLH

IL

t

LHLL

LLLH

t

E = V

IL

t

ELLL

t

10

0

10

0

ELLH

E = V , G = V

LLQX

IL

t

E = V , G = V

90

6

110

6

LLQV

LHAX

IL

t

E = V

Latch Enable High to Address Transition

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Latch Enable Transition

IL

t

E = V

0

GLQX

GLQV

IL

E = V

25

0

25

0

IL

t

EHLX

Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.

33/61

M58LW032A

Figure 13. Asynchronous Page Read AC Waveforms

A1-A2

VALID

A3-A21

VALID

tAVQV

tELQV

tELQX

tAXQX

E

L

tAVQV1

tAXQX1

tEHQZ

tEHQX

tGLQV

tGLQX

G

tGHQZ

tGHQX

DQ0-DQ15

OUTPUT

AI05504

Note: Asynchronous Read M15 = 1

Table 17. Asynchronous Page Read AC Characteristics

M58LW032A

90 110

Symbol

Parameter

Test Condition

Unit

t

E = V , G = V

IL

Address Transition to Output Transition

Address Valid to Output Valid

Min

6

ns

AXQX1

IL

t

E = V , G = V

IL IL

Max

25

AVQV1

Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.

34/61

M58LW032A

Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled

A1-A21

VALID

tAVWH

tWHAX

E

L

tELWL

tGHWL

tWHEH

G

tWHGL

tWLWH

tWHWL

W

tDVWH

INPUT

DQ0-DQ15

tWHDX

RB

tVPHWH

tWHBL

V

PP

AI05505

Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled

A1-A21

VALID

tAVLH

tLHAX

L

tELLL

tLLLH

tWLLH

tLHGL

tLHWH

E

tELWL

tGHWL

tWHEH

G

tWHGL

tWLWH

tDVWH

tWHWL

W

DQ0-DQ15

INPUT

tWHDX

tWHBL

RB

tVPHWH

V

PP

AI05506

35/61

M58LW032A

Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable

Controlled.

M58LW032A

Symbol

Parameter

Test Condition

Unit

90

10

50

0

110

10

50

0

t

Address Valid to Latch Enable High

Min

ns

AVLH

t

E = V

Address Valid to Write Enable High

Min

Max

Min

AVWH

IL

t

Data Input Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Latch Enable Low

Latch Enable High to Address Transition

Latch Enable High to Output Enable Low

Latch Enable High to Write Enable High

Latch Enable low to Latch Enable High

Latch Enable Low to Write Enable High

Program/Erase Enable High to Write Enable High

Write Enable High to Address Transition

Write Enable High to Ready/Busy low

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Enable Low to Latch Enable High

DVWH

t

ELWL

t

0

ELLL

LHAX

LHGL

t

6

95

0

95

0

t

LHWH

t

10

50

0

10

50

0

LLLH

t

LLWH

t

VPHWH

t

E = V

10

500

10

0

10

500

10

0

WHAX

IL

t

WHBL

t

WHDX

t

WHEH

GHWL

WHGL

20

35

30

70

10

20

35

30

70

10

WHWL

t

E = V

WLWH

IL

t

WLLH

36/61

M58LW032A

Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled

A1-A21

VALID

tAVEH

tEHAX

W

G

tWLEL

tEHWH

tGHEL

tELEH

tEHEL

tEHGL

E

L

tDVEH

INPUT

DQ0-DQ15

RB

tEHDX

tEHBL

tVPHEH

V

PP

AI05507

Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled

A1-A21

VALID

tAVLH

tAVEH

tLHAX

tEHAX

L

tLLLH

tELLH

tWLLL

tLHEH

tLHGL

W

G

tWLEL

tGHEL

tEHWH

tELEH

tEHEL

tEHGL

E

tDVEH

INPUT

DQ0-DQ15

tEHDX

RB

tVPHEH

tEHBL

V

PP

AI05508

37/61

M58LW032A

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable

Controlled

M58LW032A

Symbol

Parameter

Test Condition

Min

Unit

90

10

50

0

110

10

50

0

t

Address Valid to Latch Enable High

Address Valid to Chip Enable High

ns

AVLH

t

W = V

Min

Max

Min

AVEH

IL

t

Data Input Valid to Chip Enable High

Write Enable Low to Chip Enable Low

Write Enable Low to Latch Enable Low

Latch Enable High to Address Transition

Latch Enable High to Output Enable Low

Latch Enable High to Chip Enable High

Latch Enable low to Latch Enable High

Latch Enable Low to Chip Enable High

Program/Erase Enable High to Chip Enable High

Chip Enable High to Address Transition

Chip Enable High to Ready/Busy low

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Output Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Chip Enable Low

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

DVEH

t

WLEL

t

0

WLLL

LHAX

LHGL

6

35

0

35

0

LHEH

t

10

50

0

10

50

0

LLLH

t

LLEH

t

VPHEH

t

W = V

10

500

10

0

10

500

10

0

EHAX

IL

t

EHBL

t

EHDX

t

EHWH

t

20

35

30

70

10

20

35

30

70

10

GHEL

t

EHGL

t

EHEL

ELEH

t

W = V

IL

t

ELLH

38/61

M58LW032A

Figure 18. Synchronous Burst Read AC Waveform

Note: Valid Clock Edge = Rising (M6 = 1)

39/61

M58LW032A

Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output

K

(2)

Output

R

V

NV

V

tRLKH

(3)

AI05510

Note: 1. Valid Data Ready = Valid Low during valid clock edge (M8 = 0)

2. V= Valid output, NV= Not Valid output.

3. R is an open drain output with an internal pull up resistor of 1MΩ. Depending on the Valid Data Ready pin capacitance load an

external pull up resistor must be chosen according to the system clock period.

Table 20. Synchronous Burst Read AC Characteristics

M58LW032A

Unit

Symbol

Parameter

Test Condition

90

7

110

7

t

E = V

Address Valid to Active Clock Edge

Address Valid to Latch Enable High

Chip Enable Low to Active Clock Edge

Chip Enable Low to Latch Enable High

Output Enable Low to Valid Clock Edge

Valid Clock Edge to Address Transition

Valid Clock Edge to Latch Enable Low

Valid Clock Edge to Latch Enable High

Valid Clock Edge to Output Transition

Latch Enable Low to Valid Clock Edge

Latch Enable Low to Latch Enable High

Valid Clock Edge to Output Valid

Min

Max

Min

ns

AVKH

IL

t

E = V

10

20

5

10

20

5

AVLH

IL

t

E = V

ELKH

IL

t

E = V

ELLH

IL

t

E = V , L = V

GLKH

IL

IH

t

E = V

KHAX

IL

t

0

KHLL

t

0

KHLH

t

E = V , G = V , L = V

3

KHQX

IL

IH

t

E = V

6

LLKH

t

6

LLLH

t

E = V , G = V , L = V

IL IL

10

5

10

5

KHQV

IH

t

E = V , G = V , L = V

IL IL

Output Valid to Active Clock Edge

QVKH

t

E = V , G = V , L = V

IL IL

Valid Data Ready Low to Valid Clock Edge

5

RLKH

Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.

40/61

M58LW032A

Figure 20. Reset, Power-Down and Power-up AC Waveform

W

E, G

DQ0-DQ15

tPHQV

RB

RP

tPLRH

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

and Reset

Reset during

Program or Erase

AI05521

Table 21. Reset, Power-Down and Power-up AC Characteristics

M58LW032A

110

Symbol

Parameter

Unit

90

150

100

30

t

Reset/Power-Down High to Data Valid

Max

Min

Max

Min

150

100

30

ns

µs

PHQV

t

Reset/Power-Down Low to Reset/Power-Down High

Reset/Power-Down Low to Ready High

PLPH

t

PLRH

t

Supply Voltages High to Reset/Power-Down High

0

VDHPH

41/61

M58LW032A

PACKAGE MECHANICAL

Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Note: Drawing is not to scale.

Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data

mm

inches

Symbol

Typ

Min

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

14.10

–

Typ

Min

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.5551

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

13.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.5472

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0276

5°

α

N

56

CP

0.10

0.0039

42/61

M58LW032A

Figure 22. TBGA64 10x13mm - 8x8 ball array 1mm pitch, Package Outline

D

D1

FD

FE

SD

SE

E

E1

ddd

BALL ”A1”

A

e

b

A2

A1

BGA-Z23

Note: Drawing is not to scale.

Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.350

0.850

0.500

10.100

–

Typ

Max

A

A1

A2

b

0.0472

0.300

0.200

0.0118

0.0079

0.0138

0.0335

0.400

9.900

–

0.0157

0.3898

–

0.0197

D

10.000

7.000

0.3937

0.2756

0.3976

D1

ddd

e

–

0.100

–

0.0039

1.000

13.000

7.000

1.500

3.000

0.500

–

0.0394

0.5118

0.2756

0.0591

0.1181

0.0197

–

E

12.900

13.100

–

0.5079

0.5157

E1

FD

FE

SD

SE

–

43/61

M58LW032A

PART NUMBERING

Table 24. Ordering Information Scheme

Example:

M58LW032A

90

N

1

T

Device Type

M58

Architecture

L = Multi-Bit Cell Compatible Technology, Burst Mode,

Page Mode

Operating Voltage

W = V = 2.7V to 3.6V; V

= 1.8 to V

DD

DDQ

Device Function

032A = 32 Mbit (x16), Uniform Block

Speed

90 = 90ns

11 = 110ns

Package

N = TSOP56: 14 x 20 mm

ZA = TBGA64: 10 x 13 mm, 1mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Note: Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

44/61

M58LW032A

REVISION HISTORY

Table 25. Document Revision History

Date

Version

-01

Revision Details

February 2001

17-Sep-2001

First Issue (Data Brief)

-02

Expanded to full Product Preview.

Changes on Table 18, Asynchronous Write and Latch Controlled Write AC

Characteristics, Write Enable Controlled

Changes on Table 20, Synchronous Burst Read AC Characteristics

27-Sep-2001

1-Feb-2002

-03

-04

Status Register section and Table clarified, Burst Configuration Register Table

clarified, Block Protect, Block Unprotect and Protection Register Program flowcharts

added, Reset, Power-Down and Power-up AC Characteristics Table modified.

Document Status changed to Preliminary Data. Table 18, tWHGL timing modified,

Table 19, tLHGL and tEHGL timings modified. I

modified in DC Characteristics

DD5

12-Mar-2002

-05

table, T

removed from Absolute Maximum Ratings table. TFBGA64 Not

LEAD

Connected pins changed to Do Not Use.

Reference to Temporary Unprotect removed from Word Program Command section,

TFBGA package dimensions added to description. Block Protect and Block

Unprotect Flowcharts clarified, Protection Register Program description and

07-May-2002

04-Jul-2002

-06

-07

Flowchart clarified, Status Register V Status bit description clarified. Document

PP

Status changed to Datasheet.

110ns speed class added.

45/61

M58LW032A

APPENDIX A. BLOCK ADDRESS TABLE

Table 26. Block Addresses

Address Range

(x16 Bus Width)

Block Number

Address Range

Block Number

(x16 Bus Width)

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1F8000h-1FFFFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

8

7

6

5

4

3

2

1

46/61

M58LW032A

APPENDIX B. COMMON FLASH INTERFACE - CFI

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

structure is read from the memory. Tables 27, 28,

29, 30, 31 and 32 show the addresses used to re-

trieve the data.

Table 27. Query Structure Overview

Offset

00h

Sub-section Name

Description

Manufacturer Code

01h

Device Code

10h

CFI Query Identification String

Command set ID and algorithm data offset

Device timing and voltage information

Flash memory layout

1Bh

27h

System Interface Information

Device Geometry Definition

Additional information specific to the Primary

Algorithm (optional)

(1)

Primary Algorithm-specific Extended Query Table

P(h)

Additional information specific to the Alternate

Algorithm (optional)

(2)

Alternate Algorithm-specific Extended Query Table

A(h)

(SBA+02)h Block Status Register

Block-related Information

Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.

2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.

3. SBA is the Start Base Address for each block.

Table 28. CFI - Query Address and Data Output

Data

Instruction

Address A21-A1

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

51h

52h

59h

”Q”

”R”

”Y”

51h; ”Q”

52h; ”R”

59h; ”Y”

Query ASCII String

Primary Vendor:

01h

00h

31h

00h

Command Set and Control Interface ID Code

Primary algorithm extended Query Address Table: P(h)

Alternate Vendor:

Command Set and Control Interface ID Code

Alternate Algorithm Extended Query address Table

(2)

00h

1Ah

Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to ’0’.

2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.

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M58LW032A

Table 29. CFI - Device Voltage and Timing Specification

Data

Description

Address A21-A1

(1)

V

Min, 2.7V

1Bh

DD

PP

27h

36h

00h

(1)

(2)

max, 3.6V

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

min – Not Available

max – Not Available

n

04h

2 µs typical time-out for Word, DWord prog – Not Available

n

08h

0Ah

2 µs, typical time-out for max buffer write

n

2 ms, typical time-out for Erase Block

(3)

n

00h

2 ms, typical time-out for chip erase – Not Available

n

04h

2 x typical for Word Dword time-out max – Not Available

n

2 x typical for buffer write time-out max

n

04h

2 x typical for individual block erase time-out maximum

(3)

n

00h

2 x typical for chip erase max time-out – Not Available

Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.

2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.

3. Not supported.

Table 30. Device Geometry Definition

Data

Description

Address A21-A1

n

27h

16h

n where 2 is number of bytes memory Size

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

01h

00h

05h

00h

01h

3Fh

00h

01h

Device Interface

Organization Sync./Async.

n

Maximum number of bytes in Write Buffer, 2

Bit7-0 = number of Erase Block Regions in device

Number (n-1) of Erase Blocks of identical size; n=64

Erase Block Region Information

x 256 bytes per Erase block (128K bytes)

48/61

M58LW032A

Table 31. Block Status Register

Address A21-A1

Data

Selected Block Information

Block Unlocked

Block Locked

0

1

0

bit0

(2)

(1)

Last erase operation ended successfully

(BA+2)h

bit1

(2)

1

0

Last erase operation not ended successfully

Reserved for future features

bit7-2

Note: 1. BA specifies the block address location, A21-A17.

2. Not Supported.

49/61

M58LW032A

Table 32. Extended Query information

Address

offset

Address

A21-A2

Data (Hex)

x16 Bus Width

Description

(P)h

31h

32h

33h

34h

35h

50h

”P”

”R”

”Y”

(P+1)h

(P+2)h

(P+3)h

(P+4)h

52h

49h

Query ASCII string - Extended Table

31h

Major version number

Minor version number

Optional Feature: (1=yes, 0=no)

bit0, Chip Erase Supported (0=no)

bit1, Suspend Erase Supported (1=yes)

bit2, Suspend Program Supported (1=yes)

bit3, Lock/Unlock Supported (1=yes)

bit4, Queue Erase Supported (0=no)

bit5, Instant Individual Block locking

bit6, Protection bits supported

(P+5)h

36h

CEh

bit7, Page Read supported

bit8, Synchronous Read supported

Bit 31-9 reserved for future use

(P+6)h

(P+7)h

(P+8)h

37h

38h

39h

01h

00h

Synchronous Read supported

Optional Features

Function allowed after Suspend:

(P+9)h

3Ah

01h

Program allowed after Erase Suspend (1=yes)

Bit 7-1 reserved for future use

(2)

(P+A)h

(P+B)h

(P+C)h

(P+D)h

(P+E)h

(P+F)h

(P+10)h

(P+11)h

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

Block Status Register Mask

Lock bit, no lock down

01h

00h

33h

00h

01h

80h

00h

03h

V

OPTIMUM Program/Erase voltage conditions

DD

PP

OTP protection: No. of protection register fields

Lock bit’s physical low address

Lock bit’s physical high address

n

n where 2 is number of factory reprogrammed bytes

n

(P+12)h

43h

03h

n where 2 is number user programmable bytes

n

(P+13)h

(P+14)h

(P+15)h

(P+16)h

(P+17)h

44h

45h

46h

47h

48h

04h

03h

01h

02h

07h

Page Read: 2 Bytes (n = bits 0-7)

Synchronous mode configuration fields

Burst Length = 4

Burst length = 8

Burst Continuous

Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.

2. Not supported.

50/61

M58LW032A

APPENDIX C. FLOW CHARTS

Figure 23. Write to Buffer and Program Flowchart and Pseudo Code

Start

Write to Buffer E8h

Command, Block Address

Read Status

Register

NO

YES

Write to Buffer

Timeout

b7 = 1

YES

(1)

Note 1: N+1 is number of Words

to be programmed

Write N

,

Block Address

Try Again Later

Write Buffer Data,

Start Address

X = 0

YES

X = N

NO

Write Next Buffer Data,

NextProgram Address

Note 2: Next Program Address must

have same A5-A21.

(2)

X = X + 1

Program Buffer to Flash

Confirm D0h

Read Status

Register

NO

b7 = 1

YES

Note 3: A full Status Register Check must be

done to check the program operation’s

success.

Full Status

Register Check

(3)

End

AI05511

51/61

M58LW032A

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend Command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read status register

NO

b7 = 1

YES

while b7 = 1

If b2 = 0, Program completed

b2 = 1

YES

Program Complete

Read Memory Array instruction:

– write FFh

Write FFh

– one or more data reads

from other blocks

Read data from

another block

Program Erase Resume Command:

– write D0h

to resume erasure

– if the program operation completed

then this is not necessary. The device

returns to Read Array as normal

(as if the Program/Erase Suspend

command was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI00612

52/61

M58LW032A

Figure 25. Erase Flowchart and Pseudo Code

Start

Erase command:

– write 20h

Write 20h

– write D0h to Block Address

(A12-A17)

(memory enters read Status

Register after the Erase command)

Write D0h to

Block Address

NO

do:

Read Status

– read status register

– if Program/Erase Suspend command

given execute suspend erase loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

Error (1)

PP

– error handler

b3 = 0

YES

Command

Sequence Error

If b4, b5 = 1, Command Sequence error:

– error handler

b4, b5 = 0

YES

Erase

Error (1)

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase to Protected

Block Error

If b1 = 1, Erase to Protected Block Error:

– error handler

b1 = 0

YES

End

AI00613B

Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper-

ations.

53/61

M58LW032A

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend Command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read status register

NO

b7 = 1

YES

while b7 = 1

If b6 = 0, Erase completed

b6 = 1

YES

Erase Complete

Read Memory Array command:

– write FFh

Write FFh

– one or more data reads

from other blocks

Read data from

another block

or Program

Program/Erase Resume command:

– write D0h to resume the Erase

operation

Write D0h

Write FFh

– if the Program operation completed

then this is not necessary. The device

returns to Read mode as normal

(as if the Program/Erase suspend

was not issued).

Read Data

Erase Continues

AI00615

54/61

M58LW032A

Figure 27. Block Protect Flowchart and Pseudo Code

Start

Write 60h

Block Address

Block Protect Command

– write 60h, Block Adress

– write 01h, Block Adress

Write 01h

Block Address

do:

Read Status Register

(toggle G or E )

– read status register ( toggle G or E,

do not use the Read Status Register command)

NO

b7 = 1

while b7 = 1

YES

Invalid Voltage

b3 = 1

If b3 = 1, Invalid Voltage Error

Error

NO

YES

Invalid Command

b4, b5 = 1,1

If b4 = 1, b5 = 1 Invalid Command Sequence

Error

Sequence Error

NO

YES

Block Protect

If b4 = 1, Block Protect Error

b4 = 1

Error

NO

Block Protect

Sucessful

Read Memory Array Command:

– write FFh

Write FFh

End

AI06157b

55/61

M58LW032A

Figure 28. Block Unprotect Flowchart and Pseudo Code

Start

Write 60h

Block Unprotect Command

– write 60h, Block Adress

– write D0h, Block Adress

Write D0h

do:

Read Status Register

(toggle G or E )

– read status register ( toggle G or E,

do not use the Read Status Register command)

NO

b7 = 1

while b7 = 1

YES

Invalid Voltage

b3 = 1

If b3 = 1, Invalid Voltage Error

Error

NO

YES

Invalid Command

b4, b5 = 1,1

If b4 = 1, b5 = 1 Invalid Command

Sequence Error

NO

YES

Block Unprotect

If b5 = 1, Block Unprotect Error

b5 = 1

Error

NO

Block Unprotect

Sucessful

Read Memory Array Command:

– write FFh

Write FFh

End

AI06158b

56/61

M58LW032A

Figure 29. Protection Register Program Flowchart and Pseudo Code

Start

Read Memory Array Command

– write FFh

Write FFh

Write C0h

Protection Register Program Command

– write C0h

– write Protection Register Address,

Protection Register Data

Write

PR Address, PR Data

do:

Read Status Register

(toggle G or E )

– read status register (toggle G or E,

do not use the Read Status Register command)

NO

b7 = 1

YES

while b7 = 1

YES

If b3 = 1, b4 = 1 Invalid Voltage Error

Invalid Voltage

Error

b3, b4 = 1,1

NO

Protection Register

Program Error

If b1 = 0, b4 = 1 Protection Register

Program Error

b1, b4 = 0,1

NO

YES

Block Unprotect

Error

If b1 = 1, b4 = 1 Program Error due to

Protection Register Protection

b1, b4 = 1,1

NO

PR Program

Sucessful

Read Memory Array Command:

– write FFh

Write FFh

End

AI06159b

Note: PR = Protection Register

57/61

M58LW032A

Figure 30. Command Interface and Program Erase Controller Flowchart (a)

WAIT FOR

COMMAND

WRITE

NO

90h

YES

READ

SIGNATURE

NO

98h

YES

CFI

QUERY

NO

70h

YES

READ

ARRAY

READ

STATUS

NO

50h

YES

CLEAR

STATUS

NO

E8h

YES

PROGRAM

BUFFER

LOAD

NO

(1)

20h

YES

ERASE

NO

FFh

YES

SET-UP

NO

D0h

NO

YES

C

PROGRAM

COMMAND

ERROR

D0h

YES

ERASE

COMMAND

ERROR

A

B

AI03618

Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.

58/61

M58LW032A

Figure 31. Command Interface and Program Erase Controller Flowchart (b)

A

B

ERASE

(READ STATUS)

Program/Erase Controller

Status bit in the Status

Register

YES

READ

STATUS

READY

?

NO

READ

ARRAY

NO

B0h

YES

READ

STATUS

NO

FFh

ERASE

SUSPEND

NO

YES

ERASE

SUSPENDED

READY

?

NO

READ

STATUS

YES

WAIT FOR

COMMAND

WRITE

YES

READ

STATUS

70h

NO

READ

SIGNATURE

90h

NO

CFI

QUERY

98h

NO

PROGRAM

BUFFER

LOAD

E8h

NO

PROGRAM

COMMAND

ERROR

YES

READ

STATUS

D0h

NO

(ERASE RESUME)

YES

READ

ARRAY

c

AI03619

59/61

M58LW032A

Figure 32. Command Interface and Program Erase Controller Flowchart (c).

B

C

PROGRAM

(READ STATUS)

YES

Program/Erase Controller

Status bit in the Status

Register

READ

STATUS

READY

?

NO

READ

ARRAY

NO

B0h

YES

NO

READ

STATUS

FFh

PROGRAM

SUSPEND

NO

YES

PROGRAM

SUSPENDED

READY

?

NO

YES

WAIT FOR

COMMAND

WRITE

READ

STATUS

YES

NO

READ

STATUS

70h

NO

READ

SIGNATURE

90h

NO

CFI

QUERY

98h

NO

YES

READ

ARRAY

READ

STATUS

D0h

(PROGRAM RESUME)

AI00618

60/61

M58LW032A

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics GROUP OF COMPANIES

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61/61


型号：	M58LW032A11ZA6T
厂家：	ST
描述：	2MX16 FLASH 3V PROM, 110ns, PBGA64, 10 X 13 MM, 1 MM PITCH, TBGA-64 可编程只读存储器内存集成电路
文件：	总61页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58LW032A11ZA6T [STMICROELECTRONICS]

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