M58LW032C110N6F [STMICROELECTRONICS]
32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory; 32兆位的2Mb X16 ，统一座，突发3V电源快闪记忆体
| 型号： | M58LW032C110N6F |
| 厂家： | 
ST |
| 描述： | 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory |
| 文件： | 总61页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M58LW032C
32 Mbit (2Mb x16, Uniform Block, Burst)
3V Supply Flash Memory
FEATURES SUMMARY
■ WIDE x16 DATA BUS for HIGH BANDWIDTH
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 2.7 to 3.6V core supply voltage for Pro-
DD
gram, Erase and Read operations
– V
= 1.8 to V for I/O Buffers
DD
DDQ
■ SYNCHRONOUS/ASYNCHRONOUS READ
– Synchronous Burst read
TSOP56 (N)
14 x 20 mm
– Asynchronous Random Read
– Asynchronous Address Latch Controlled
Read
– Page Read
TBGA
■ ACCESS TIME
– Synchronous Burst Read up to 56MHz
– Asynchronous Page Mode Read 90/25ns,
110/25ns
TBGA64 (ZA)
10 x 13 mm
– Random Read 90ns, 110ns
■ PROGRAMMING TIME
– 16 Word Write Buffer
– 12µs Word effective programming time
■ 32 UNIFORM 64 KWord MEMORY BLOCKS
■ ENHANCED SECURITY
– Block Protection/ Unprotection
– Smart Protection: irreversible block locking
system
– V
signal for Program Erase Enable
PEN
– 128 bit Protection Register with 64 bit Unique
Code in OTP area
■ PROGRAM and ERASE SUSPEND
■ COMMON FLASH INTERFACE
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code M58LW032C : 8822h
April 2003
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TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Status/(Ready/Busy) (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
V
V
V
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DD
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DDQ
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SS
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SSQ
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Asynchronous Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Asynchronous Latch Controlled Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Asynchronous Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synchronous Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Single Synchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal Clock Divider Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Y-Latency Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Valid Data Ready Bit (CR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Burst Type Bit (CR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Burst Length Bit (CR2-CR0).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Burst Configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Erase Suspend Status Bit ( SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
V
Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PEN
Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Reserved (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 33
Figure 13. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35
Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 35
Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . 37
Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 40
Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 42
Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 42
Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . . . . 43
Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data. . . . . . . . . 43
PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 30. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 50
Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 51
Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . 57
Figure 31. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . 58
Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 59
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5/61
M58LW032C
SUMMARY DESCRIPTION
M58LW032C is a 32 Mbit (2Mb x16) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage (2.7V to 3.6V) core supply.
On power-up the memory defaults to Read mode
with an asynchronous bus where it can be read in
the same way as a non-burst Flash memory.
■ Block Protection, where each block can be
individually protected against program or erase
operations. All blocks are protected during
power-up. The protection of the blocks is non-
volatile; after power-up the protection status of
each block is restored to the state when power
was last removed.
The memory is divided into 32 blocks of 1Mbit that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
■ Program Erase Enable input V
, program or
PEN
erase operations are not possible when the
Program Erase Enable input V is low.
PEN
■ Smart Protection, which allows protected blocks
to be permanently locked. This feature is not
described in the datasheet for security reasons.
Please contact STMicroelectronics for further
details.
■ 128 bit Protection Register, divided into two 64
bit segments: the first contains a unique device
number written by ST, the second is user
programmable. The user programmable
segment can be protected.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In asynchronous mode an
Address Latch input can be used to latch address-
es in Latch Controlled mode. In synchronous burst
mode, data is output on each clock cycle at fre-
quencies of up to 56MHz.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single Word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in power-down mode.
The device features an Auto Low Power mode. If
the bus becomes inactive during Asynchronous
Read operations, the device automatically enters
Auto Low Power mode. In this mode the power
consumption is reduced to the Auto Low Power
supply current.
The STS signal is an open drain output that can be
used to identify the Program/Erase Controller sta-
tus. It can be configured in two modes: Ready/
Busy mode where a static signal indicates the sta-
tus of the P/E.C, and Status mode where a pulsing
signal indicates the end of a Program or Block
Erase operation. In Status mode it can be used as
a system interrupt signal, useful for saving CPU
time.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10 x 13mm, 1mm pitch) packages.
The M58LW032C has several security features to
increase data protection.
6/61
M58LW032C
Figure 2. Logic Diagram
Table 1. Signal Names
A1-A21
Address inputs
V
V
DD DDQ
DQ0-DQ15
Data Inputs/Outputs
Chip Enable
E
G
Output Enable
Clock
21
K
A1-A21
L
Latch Enable
V
PEN
R
Valid Data Ready
Status/(Ready/Busy)
Reset/Power-Down
Program/Erase Enable
Write Enable
16
STS
RP
W
E
DQ0-DQ15
M58LW032C
STS
V
PEN
G
W
R
RP
L
V
DD
Supply Voltage
V
DDQ
Input/Output Supply Voltage
Ground
K
V
SS
V
Input/Output Ground
Not Connected Internally
SSQ
NC
V
V
SS SSQ
AI06208
7/61
M58LW032C
Figure 3. TSOP56 Connections
NC
R
1
56
NC
W
A21
A20
A19
A18
A17
A16
G
STS
DQ15
DQ7
DQ14
DQ6
V
V
DD
A15
A14
A13
A12
E
SS
DQ13
DQ5
DQ12
DQ4
14
15
43
42
V
V
DDQ
SSQ
M58LW032C
V
PEN
RP
DQ11
DQ3
A11
A10
A9
DQ10
DQ2
A8
V
DD
V
DQ9
DQ1
DQ8
DQ0
NC
SS
A7
A6
A5
A4
A3
A2
A1
K
NC
L
28
29
AI06209
8/61
M58LW032C
Figure 4. TBGA64 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A1
A2
A3
A4
DQ8
K
A6
A8
A9
V
A13
A14
V
A18
A19
NC
R
PEN
E
DD
V
NC
NC
SS
A7
A10
A11
DQ9
DQ10
DQ2
A12
RP
A15
A20
A21
A17
STS
G
A5
DQ1
DQ0
NC
NC
NC
A16
DQ3
DQ11
DQ4
DQ12
DQ5
DQ13
NC
DQ15
NC
NC
G
H
NC
L
V
DQ6
DQ14
DQ7
W
DDQ
NC
V
V
V
SSQ
NC
DD
SS
AI06210b
9/61
M58LW032C
Figure 5. Block Addresses
Word (x16) Bus Width
1FFFFFh
1 Mbit or
64 KWords
1F0000h
1EFFFFh
1 Mbit or
64 KWords
1E0000h
Total of 32
1 Mbit Blocks
01FFFFh
1 Mbit or
64 KWords
010000h
00FFFFh
1 Mbit or
64 KWords
000000h
AI06254
Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses.
10/61
M58LW032C
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 11, Signal
Names, for a brief overview of the signals connect-
ed to this device.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, V , for at least t
. When
PLPH
IL
Reset/Power-Down is Low, V , the Status Regis-
IL
ter information is cleared and the power consump-
tion is reduced to power-down level. The device is
deselected and outputs are high impedance. If Re-
Address Inputs (A1-A21). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable and Latch Enable must be low when
selecting the addresses.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
set/Power-Down goes low, V ,during a Block
IL
Erase, a Write to Buffer and Program or a Block
Protect/Unprotect the operation is aborted and the
data may be corrupted. In this case the Ready/
Busy pin stays low, V , for a maximum timing of
IL
t
+ t
until the completion of the Reset/
PLPH
PHRH,
Power-Down pulse.
After Reset/Power-Down goes High, V , the
IH
memory will be ready for Bus Read and Bus Write
operations after t
. Note that Ready/Busy
PHQV
low, V . The address is internally latched in an
IL
does not fall during a reset, see Ready/Busy Out-
put section.
Erase or Program operation.
Data Inputs/Outputs (DQ0-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
Erase or Program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
Latch Enable (L). The Bus Interface is config-
ured to latch the Address Inputs on the rising edge
of Latch Enable, L. In synchronous bus operations
the address is latched on the active edge of the
When Chip Enable and Output Enable are both
low, V , the data bus outputs data from the mem-
IL
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
Clock when Latch Enable is Low, V or on the ris-
IL
ing of Latch Enable, whichever occurs first. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
is high, V
or the Reset/Power-Down signal is
IH,
Enable is Low, V , the latch is transparent.
IL
low, V . When the Program/Erase Controller is
IL
active the Ready/Busy status is given on DQ7.
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
V
deselects the memory and reduces the power
IH
consumption to the Standby level, I
.
DD1
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at V
the outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
low, V , or on the rising edge of Latch Enable,
IL
IH
whichever occurs first.
During asynchronous bus operations the Clock is
not used.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The
Reset/Power-
Down pin can be used to apply a Hardware Reset
to the memory.
one cycle before. Valid Data Ready Low, V , in-
OL
11/61
M58LW032C
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
Unless Synchronous Burst Read has been select-
ed, Valid Data Ready is high-impedance. It may be
tied to other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active. Ready/Busy can rise before Reset/Power-
Down rises.
Program/Erase Enable (V
). The Program/
is used to protect all
PEN
Erase Enable input, V
PEN,
blocks, preventing Program and Erase operations
from affecting their data.
The Valid Data Ready, R, output has an internal
pull-up resistor of approximately 1 MΩ powered
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
from V
, designers should use an external pull-
DDQ
up resistor of the correct value to meet the external
timing requirements for Valid Data Ready rising.
Refer to Figure 19.
Status/(Ready/Busy) (STS). The STS signal is
an open drain output that can be used to identify
the Program/Erase Controller status. It can be
configured in two modes:
V
Supply Voltage. V
provides the power
DD
DD
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
Supply Voltage. V
provides the power
DDQ
DDQ
supply to the I/O pins and enables all Outputs to
be powered independently from V . V can be
■ Ready/Busy - the pin is Low, V , during
OL
DD DDQ
Program and Erase operations and high
impedance when the memory is ready for any
Read, Program or Erase operation.
tied to V or can use a separate supply.
DD
It is recommended to power-up and power-down
and V together to avoid any condition that
V
DD
DDQ
■ Status - the pin gives a pulsing signal to indicate
would result in data corruption.
the end of a Program or Block Erase operation.
V
Ground. Ground, V is the reference for
SS
SS,
After power-up or reset the STS pin is configured
in Ready/Busy mode. The pin can be configured
for Status mode using the Configure STS com-
mand.
the core power supply. It must be connected to the
system ground.
V
Ground. V
the input/output circuitry driven by V
ground is the reference for
SSQ
SSQ
. V
DDQ
SSQ
When the Program/Erase Controller is idle, or sus-
pended, STS can float High through a pull-up re-
sistor. The use of an open-drain output allows the
STS pins from several memories to be connected
to a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
must be connected to V
.
SS
Note: Each device in a system should have
and V decoupled with a 0.1µF ceramic
V
DD
DDQ
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10, AC Measurement Load Circuit.
12/61
M58LW032C
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Address Latch, Bus Read,
Bus Write, Output Disable, Power-Down and
Standby. See Table 2, Bus Operations, for a sum-
mary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Address Latch. Address latch operations input
valid addresses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
A valid Bus Write operation begins by setting the
desired address on the Address Inputs and setting
Latch Enable Low, V . The Address Inputs are
IL
latched by the Command Interface on the rising
edge of Chip Enable or Write Enable, whichever
occurs first. The Data Inputs/Outputs are latched
by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V , during
IH
the Bus Write operation.
See Figures 14, 15, 16 and 17, Write AC Wave-
forms, and Tables 18 and 19, Write AC Character-
istics, for details of the timing requirements.
Output Disable. The The Data Inputs/Outputs
are high impedance when the Output Enable is at
able and Latch Enable Low, V and keeping Write
IL
Enable High, V ; the address is latched on the ris-
IH
ing edge of Address Latch.
V .
IH
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the Common
Flash Interface and the Block Protection Status.
A valid bus operation involves setting the desired
address on the Address Inputs, applying a Low
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
, and the outputs are high impedance,
DD2
independent of Chip Enable, Output Enable or
Write Enable.
Standby. Standby disables most of the internal
circuitry, allowing a substantial reduction of the
current consumption. The memory is in standby
signal, V , to Chip Enable, Output Enable and
IL
Latch Enable and keeping Write Enable High, V .
IH
The data read depends on the previous command
written to the memory (see Command Interface
section). See Figures 11, 12, 13, 18 and 19 Read
AC Waveforms, and Tables 15, 16, 17 and 20
Read AC Characteristics, for details of when the
output becomes valid.
when Chip Enable is at V . The power consump-
IH
tion is reduced to the standby level I
and the
DD1
outputs are set to high impedance, independently
from the Output Enable or Write Enable inputs.
If Chip Enable switches to V during a program or
erase operation, the device enters Standby mode
when finished.
IH
Bus Write. Bus Write operations write Com-
mands to the memory or latch addresses and input
data to be programmed.
Table 2. Bus Operations
Operation
Address Latch
Bus Read
E
G
W
RP
L
A1-A21
Address
Address
Address
X
DQ0-DQ15
(2)
V
V
IH
V
IH
V
X
IL
IL
IL
IL
IL
IL
IL
Data Output or Hi-Z
Data Output
Data Input
High Z
V
V
V
V
V
IH
V
IH
V
V
IL
IH
IH
V
V
V
V
V
IH
Bus Write
IL
V
IH
Output Disable
Power-Down
Standby
X
IH
V
X
X
X
X
X
X
High Z
IL
V
IH
V
IH
X
X
X
High Z
Note: 1. X = Don’t Care V or V
.
IL
IH
2. Depends on G
13/61
M58LW032C
READ MODES
Read operations can be performed in two different
ways depending on the settings in the Configura-
tion Register. If the clock signal is ‘don’t care’ for
the data output, the read operation is asynchro-
nous; if the data output is synchronized with clock,
the read operation is synchronous.
The read mode and format of the data output are
determined by the Configuration Register. (See
Configuration Register section for details).
Asynchronous Random Read. As the Latch En-
able input is transparent when set Low, V , Asyn-
IL
chronous Random Read operations can be
performed by holding Latch Enable Low, V
IL
throughout the bus operation.
See Figures 11, Asynchronous Random Read AC
Waveforms, and Table 15, Asynchronous Ran-
dom Read AC Characteristics, for details.
Asynchronous Page Read. In
Asynchronous
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Read mode.
Asynchronous Read Modes
In Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corre-
sponding to the address latched, that is the mem-
ory array, Status Register, Common Flash
Interface, Electronic Signature or Block Protection
Status depending on the command issued. CR15
in the Configuration Register must be set to ‘1’ for
asynchronous operations.
Page Read mode a Page of data is internally read
and stored in a Page Buffer. Each memory page is
4 Words and has the same A3-A22, only A1 and
A2 may change.
The first read operation within the Page has the
normal access time (t
), subsequent reads
AVQV
within the same Page have much shorter access
times (t ). If the Page changes then the nor-
AVQV1
mal, longer timings apply again.
See Figures 13, Asynchronous Page Read AC
Waveforms, and Table 17, Asynchronous Page
Read AC Characteristics, for details.
During Asynchronous Read operations, if the bus
is inactive for a time equivalent to t
, the de-
Synchronous Read Modes
AVQV
vice automatically enters Auto Low Power mode.
In this mode the internal supply current is reduced
In Synchronous Read mode the data output is syn-
chronized with the clock. CR15 in the Configura-
tion Register must be set to ‘0’ for synchronous
operations.
to the Auto Low Power supply current, I
. The
DD5
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Asynchronous Read operations can be performed
in three different ways, Asynchronous Latch Con-
trolled Read, Asynchronous Random Read and
Asynchronous Page Read.
Synchronous Burst Read. In
Synchronous
Burst Read mode the data is output in bursts syn-
chronized with the clock. It is possible to perform
burst reads across bank boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read opera-
tions, such as Read Status Register, Read CFI,
Read Electronic Signature and Block Protection
Status, Single Synchronous Read or Asynchro-
nous Read must be used.
Asynchronous Latch Controlled Read.
In Asynchronous Latch Controlled Read opera-
tions read the address is latched in the memory
before the value is output on the data bus, allowing
the address to change during the cycle without af-
fecting the address that the memory uses.
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are con-
figured in the Configuration Register.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
able and Latch Enable Low, V and keeping Write
Write Enable is High, V , and Chip Enable and
IL
IH
Enable High, V ; the address is latched on the ris-
ing edge of Address Latch. Once latched, the Ad-
dress Inputs can change. Set Output Enable Low,
Latch Enable are Low, V , during the active edge
IH
IL
of the Clock. The address is latched on the first ac-
tive clock edge when Latch Enable is low, or on
the rising edge of Latch Enable, whichever occurs
first. The data becomes available for output after
the X-latency specified in the Burst Control Regis-
ter has expired. The output buffers are activated
V , to read the data on the Data Inputs/Outputs;
IL
see Figure 12, Asynchronous Latch Controlled
Read AC Waveforms and Table 16, Asynchro-
nous Latch Controlled Read AC Characteristics for
details on when the output becomes valid.
by setting Output Enable Low, V . See Figures 6
IL
and 7 for examples of Synchronous Burst Read
operations.
The number of Words to be output during a Syn-
chronous Burst Read operation can be configured
as 4 Words, 8 Words or Continuous (Burst Length
See Figures 12, Asynchronous Latch Controlled
Read AC Waveforms, and Table 16, Asynchro-
nous Latch Controlled Read AC Characteristics,
for details.
14/61
M58LW032C
bits CR2-CR0). In Synchronous Continuous Burst
Read mode one Burst Read operation can access
the entire memory sequentially. If the starting ad-
dress is not associated with a page (4 Word)
boundary the Valid Data Ready, R, output goes
Register. The burst sequence can be sequential or
interleaved.
See Table 20, Synchronous Read AC Character-
istics and Figure 18 and 19, Synchronous Burst
Read AC Waveform for details.
Low, V , to indicate that the data will not be ready
IL
Single Synchronous Read. Single
Synchro-
in time and additional wait-states are required. The
Valid Data Ready output timing (bit CR8) can be
changed in the Configuration Register.
The order of the data output can be modified
through the Burst Type bit in the Configuration
nous Read operations are similar to Synchronous
Burst Read operations except that only the first
data output after the X latency is valid. Single Syn-
chronous Reads are used to read the Status Reg-
ister, CFI, Electronic Signature and Block
Protection Status.
15/61
M58LW032C
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will per-
form. The Configuration Register bits are de-
scribed in Table 3. They specify the selection of
the burst length, burst type, burst X and Y laten-
cies and the Read operation. See figures 6 and 7
for examples of Synchronous Burst Read configu-
rations.
The Configuration Register is set through the
Command Interface and will retain its information
until it is re-configured, the device is reset, or the
device goes into Reset/Power-Down mode. The
Configuration Register is read using the Read
Electronic Signature Command at address 05h.
Read Select Bit (CR15). The Read Select bit,
CR15, is used to switch between asynchronous
and synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in CR9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table 3,
Configuration Register for valid combinations of
the Y-Latency, the X-Latency and the Clock fre-
quency.
Valid Data Ready Bit (CR8). The Valid Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. When the Valid Data Ready
bit is ’0’ the Valid Data Ready output pin is driven
Low for the active clock edge when invalid data is
output on the bus. When the Valid Data Ready bit
is ’1’ the Valid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Burst Type Bit (CR7). The Burst Type bit is used
to configure the sequence of addresses read as
sequential or interleaved. When the Burst Type bit
is ’0’ the memory outputs from interleaved ad-
dresses; when the Burst Type bit is ’1’ the memory
outputs from sequential addresses. See Tables 4,
Burst Type Definition, for the sequence of ad-
dresses output from a given starting address in
each mode.
Valid Clock Edge Bit (CR6). The Valid Clock
Edge bit, CR6, is used to configure the active edge
of the Clock, K, during Synchronous Burst Read
operations. When the Valid Clock Edge bit is ’0’
the falling edge of the Clock is the active edge;
when the Valid Clock Edge bit is ’1’ the rising edge
of the Clock is active.
Burst Length Bit (CR2-CR0). The Burst Length
bits set the maximum number of Words that can
be output during a Synchronous Burst Read oper-
ation.
Table 3, Configuration Register gives the valid
combinations of the Burst Length bits that the
memory accepts; Tables 4, Burst Type Definition,
give the sequence of addresses output from a giv-
en starting address for each length.
On reset or power-up the Read Select bit is set to
’1’ for asynchronous access.
X-Latency Bits (CR13-CR11). The
X-Latency
bits are used during Synchronous Bus Read oper-
ations to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assume the values in Table 3,
Configuration Register.
Internal Clock Divider Bit (CR10). The Internal
Clock Divider Bit is used to divide the internal clock
by two. When CR10 is set to ‘1’ the internal clock
is divided by two, which effectively means that the
X and Y-Latency values are multiplied by two, that
is the number of clock cycles between the address
being latched and the first data becoming avail-
able will be twice the value set in CR13-CR11, and
the number of clock cycles between consecutive
reads will be twice the value set in CR9. For exam-
ple 8-1-1-1 will become 16-2-2-2. When CR10 is
set to ‘0’ the internal clock runs normally and the X
and Y-Latency values are those set in CR13-CR11
and CR9.
Y-Latency Bit (CR9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
CR5 CR4 and CR3 are reserved for future use.
16/61
M58LW032C
Table 3. Configuration Register
Address
Reset
Value
Mnemonic
Bit Name
Value
Description
Synchronous Burst Read
Bit
16
15
0
1
CR15
CR14
Read Select
1
Asynchronous Bus Read (default at power-up)
Reserved
Reserved
001
010
011
100
101
110
(1)
X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)
14
to
12
X-Latency = 5, 5-1-1-1, 5-2-2-2
(2)
CR13-CR11
XXX
X-Latency
X-Latency = 6, 6-1-1-1, 6-2-2-2
X-Latency = 7, 7-1-1-1, 7-2-2-2
X-Latency = 8, 8-1-1-1, 8-2-2-2
X and Y-Latencies remains as set in CR13-CR11 and
CR9
0
Internal
Clock Divider
11
CR10
X
1
0
1
0
1
0
1
0
1
Divides internal clock, X and Y-Latencies multiplied by 2
Y-Latency = 1
(3)
10
9
CR9
CR8
CR7
X
X
X
X
Y-Latency
Y-Latency = 2
R valid Low during valid Clock edge
Valid Data
Ready
R valid Low one cycle before valid Clock edge
Interleaved
Sequential
8
Burst Type
Falling Clock edge
Rising Clock edge
Reserved
Valid Clock
Edge
7
CR6
6 to 4
CR5-CR3
001
010
111
4 Words
3
to
1
CR2-CR0 Burst Length
XXX
8 Words
Continuous
Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed.
2. X latencies can be calculated as: (t
– t
LLKH
+ t
) + t < (X -1) t (X is an integer number from 4 to 8 and t
QVKH SYSTEM MARGIN K. K
AVQV
is the clock period).
3. Y latencies can be calculated as: t
+ t
+ t < Y t
QVKH K.
KHQV
SYSTEM MARGIN
4. t
is the time margin required for the calculation.
SYSTEM MARGIN
17/61
M58LW032C
Table 4. Burst Type Definition
Starting
x4
x4
x8
x8
Continuous
Address Sequential Interleaved
Sequential
Interleaved
0
1
2
3
4
5
6
7
8
0-1-2-3
0-1-2-3
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
–
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
–
0-1-2-3-4-5-6-7-8-9-10..
1-2-3-4-5-6-7-8-9-10-11..
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
2-3-4-5-6-7-8-9-10-11-12..
3-4-5-6-7-8-9-10-11-12-13..
4-5-6-7-8-9-10-11-2-13-14..
5-6-7-8-9-10-11-12-13-14..
6-7-8-9-10-11-12-13-14-15..
7-8-9-10-11-12-13-14-15-16..
8-9-10-11-12-13-14-15-16-17..
3-0-1-2
3-2-1-0
–
–
–
–
–
–
–
–
–
–
Figure 6. Burst Configuration X-1-1-1
0
1
2
3
4
5
6
7
8
9
K
ADD
VALID
L
DQ
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
4-1-1-1
5-1-1-1
DQ
VALID
VALID
VALID
VALID
DQ
DQ
DQ
VALID
VALID
VALID
VALID
VALID
6-1-1-1
7-1-1-1
8-1-1-1
VALID
VALID
AI05512
18/61
M58LW032C
Figure 7. Burst Configuration X-2-2-2
0
1
2
3
4
5
6
7
8
9
K
ADD
VALID
L
DQ
NV
VALID
NV
NV
VALID
NV
VALID
5-2-2-2
DQ
DQ
DQ
NV
VALID
NV
VALID
NV
NV
VALID
NV
VALID
NV
6-2-2-2
7-2-2-2
8-2-2-2
VALID
NV=NOT VALID
AI05513
19/61
M58LW032C
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
5, Commands. Refer to Table 5 in conjunction with
the text descriptions below.
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued.
The Status Register information is present on the
output data bus (DQ1-DQ7) when both Chip En-
After power-up or a Reset operation the memory
enters Read mode.
able and Output Enable are low, V .
IL
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in asynchro-
nous mode or single synchronous burst mode.
Once the memory returns to Read Memory Array
mode the bus will resume the setting in the Config-
uration Register automatically.
See the section on the Status Register and Table
10 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits
SR1, SR3, SR4 and SR5 in the Status Register to
‘0’. One Bus Write is required to issue the Clear
Status Register command.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to Read
mode. One Bus Write cycle is required to issue the
Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read commands will access the memory array.
While the Program/Erase Controller is executing a
Program, Erase, Block Protect, Blocks Unprotect
or Protection Register Program operation the
memory will not accept the Read Memory Array
command until the operation completes.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status, the Configuration Register and
the Protection Register. One Bus Write cycle is re-
quired to issue the Read Electronic Signature
command. Once the command is issued subse-
quent Bus Read operations read the Manufacturer
Code, the Device Code, the Block Protection Sta-
tus, the Configuration Register or the Protection
Register until another command is issued. Refer to
Table 7, Read Electronic Signature, Table 8, Read
Protection Register and Figure 8, Protection Reg-
ister Memory Map for information on the address-
es.
Read Query Command. The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 26,
27, 28, 29, 30 and 31 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect, Block
Unprotect or Protection Register Program com-
mand is issued. If any error occurs then it is essen-
tial to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 9.
See Appendix C, Figure 25, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Word Program Command. The Word Program
command is used to program a single word in the
memory array. Two Bus Write operations are re-
quired to issue the command; the first write cycle
sets up the Word Program command, the second
write cycle latches the address and data to be pro-
grammed in the internal state machine and starts
the Program/Erase Controller.
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
20/61
M58LW032C
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
Write to Buffer and Program Command. The
Write to Buffer and Program command is used to
program the memory array.
gram or Write to Buffer and Program command if
the Program/Erase Controller is running.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (SR7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
Up to 16 Words can be loaded into the Write Buffer
and programmed into the memory. Each Write
Buffer has the same A5-A21 addresses.
Four successive steps are required to issue the
command.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (SR7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (SR2) or the Erase
Suspend Status bit (SR6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 9.
1. One Bus Write operation is required to set up
the Write to Buffer and Program Command. Is-
sue the set up command with the selected
memory Block Address where the program op-
eration should occur (any address in the block
where the values will be programmed can be
used). Any Bus Read operations will start to out-
put the Status Register after the 1st cycle.
2. Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words to be programmed.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Write to Buffer and
Program, and the Program Suspend commands
will also be accepted. When a program operation
is completed inside a Block Erase Suspend the
Read Memory Array command must be issued to
reset the device in Read mode, then the Erase Re-
sume command can be issued to complete the
whole sequence. Only the blocks not being erased
may be read or programmed correctly.
3. Use N+1 Bus Write operations to load the ad-
dress and data for each Word into the Write
Buffer. See the constraints on the address com-
binations listed below. The addresses must
have the same A5-A21.
4. Finally, use one Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray. The Status Register should be cleared before
re-issuing the command.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command.
See Appendix C, Figure 23, Write to Buffer and
Program Flowchart and Pseudo Code, for a sug-
gested flowchart on using the Write to Buffer and
Program command.
See Appendix C, Figure 24, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
26, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after
Pro-
a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Program/Erase Suspend Command. The
Pro-
gram/Erase Suspend command is used to pause a
Word Program, Write to Buffer and Program or
Erase operation. The command will only be ac-
cepted during a Program or an Erase operation. It
can be issued at any time during an Erase opera-
tion but will only be accepted during a Word Pro-
Set Configuration Register Command. The
Set Configuration Register command is used to
write a new value to the Burst Configuration Con-
trol Register which defines the burst length, type,
X and Y latencies, Synchronous/Asynchronous
21/61
M58LW032C
Read mode and the valid Clock edge configura-
tion.
time. Two write cycles are required to issue the
Protection Register Program command.
Two Bus Write cycles are required to issue the Set
Configuration Register command. Once the com-
mand is issued the memory returns to Read mode
as if a Read Memory Array command had been is-
sued.
■ The first bus cycle sets up the Protection
Register Program command.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
The value for the Configuration Register is pre-
sented on A1-A16. CR0 is on A1, CR1 on A2, etc.;
the other address bits are ignored.
Read operations output the Status Register con-
tent after the programming has started.
The user-programmable segment can be locked
by programming bit 1 of the Protection Register
Lock location to ‘0’ (see Table 8). Bit 0 of the Pro-
tection Register Lock location locks the factory
programmed segment and is programmed to ‘0’ in
the factory. The locking of the Protection Register
is not reversible, once the lock bits are pro-
grammed no further changes can be made to the
values stored in the Protection Register, see Fig-
ure 8, Protection Register Memory Map. Attempt-
ing to program a previously protected Protection
Register will result in a Status Register error.
The Protection Register Program cannot be sus-
pended. See Appendix C, Figure 29, Protection
Register Program Flowchart and Pseudo Code,
for the flowchart for using the Protection Register
Program command.
Block Protect Command. The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to is-
sue the Block Protect command; the second Bus
Write cycle latches the block address in the inter-
nal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
During the Block Protect operation the memory will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 9.
The Block Protection bits are non-volatile, once
set they remain set through reset and power-
down/power-up. They are cleared by a Blocks Un-
protect command.
See Appendix C, Figure 27, Block Protect Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Protect command.
Configure STS Command.
The Configure STS command is used to configure
the Status/(Ready/Busy) pin. After power-up or re-
set the STS pin is configured in Ready/Busy
mode. The pin can be configured in Status mode
using the Configure STS command (refer to Sta-
tus/(Ready/Busy) section for more details.
Blocks Unprotect Command. The Blocks Un-
protect command is used to unprotect all of the
blocks. Two Bus Write cycles are required to issue
the Blocks Unprotect command; the second Bus
Write cycle starts the Program/Erase Controller.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits.
Two write cycles are required to issue the Config-
ure STS command.
■ The first bus cycle sets up the Configure STS
command.
■ The second specifies one of the four possible
configurations (refer to Table 6, Configuration
Codes):
– Ready/Busy mode
During the Block Unprotect operation the memory
will only accept the Read Status Register com-
mand. All other commands will be ignored. Typical
Block Protection times are given in Table 9.
– Pulse on Erase complete mode
– Pulse on Program complete mode
– Pulse on Erase or Program complete mode
See Appendix C, Figure 28, Block Unprotect Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Unprotect command.
Protection Register Program Command. The
Protection Register Program command is used to
Program the 64 bit user segment of the Protection
Register. The segment is programmed 16 bits at a
The device will not accept the Configure STS com-
mand while the Program/Erase controller is busy
or during Program/Erase Suspend. When STS pin
is pulsing it remains Low for a typical time of
250ns. Any invalid Configuration Code will set an
error in the Status Register.
22/61
M58LW032C
Table 5. Commands
Command
Bus Operations
1st Cycle
2nd Cycle
Addr.
Subsequent
Final
Op. Addr. Data Op.
Data Op. Addr. Data Op. Addr. Data
Read Memory Array
≥ 2 Write
X
X
X
X
FFh Read
90h Read
70h Read
98h Read
RA
RD
(3)
(3)
Read Electronic Signature ≥ 2 Write
IDA
IDD
Read Status Register
Read Query
2
Write
X
SRD
(4)
(4)
≥ 2 Write
QA
QD
Clear Status Register
Block Erase
1
2
Write
Write
X
X
50h
20h Write
BA
PA
D0
PD
40h
Word Program
2
Write
X
Write
10h
Write to Buffer and
Program
4 + N Write BA E8h Write
BA
N
Write PA
PD Write
X
D0h
Program/Erase Suspend
Program/Erase Resume
Set Configuration Register
Block Protect
1
1
2
2
2
Write
Write
Write
Write
Write
X
X
X
X
X
B0h
D0h
60h Write
60h Write
60h Write
BCR
BA
X
03h
01h
D0h
Blocks Unprotect
Protection Register
Program
2
2
Write
Write
X
X
C0h Write
B8h Write
PRA
X
PRD
CC
Configure STS command
Note: 1. X Don’t Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program
Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Configuration Register value,
CC Configuration Code.
2. Base Address, refer to Figure 8 and Table 8 for more information.
3. For Identifier addresses and data refer to table 7, Read Electronic Signature.
4. For Query Address and Data refer to Appendix B, CFI.
23/61
M58LW032C
Table 6. Configuration Codes
Configuration
DQ1 DQ2
Code
Mode
STS Pin
Description
V
during P/E
The STS pin is Low during Program and
Erase operations and high impedance when
the memory is ready for any Read, Program
or Erase operation.
OL
operations
Hi-Z when the
memory is ready
00h
0
0
Ready/Busy
Pulse on Erase
complete
Supplies a system interrupt pulse at the end
of a Block Erase operation.
01h
02h
0
1
1
0
Pulse Low then
High when
Pulse on
Program
complete
Supplies a system interrupt pulse at the end
of a Program operation.
operation
(2)
completed
Pulse on Erase
or Program
complete
Supplies a system interrupt pulse at the end
of a Block Erase or Program operation.
03h
1
1
Note: 1. DQ2-DQ7 are reserved
2. When STS pin is pulsing it remains Low for a typical time of 250ns.
Table 7. Read Electronic Signature
Code
Manufacturer Code
Address (A21-A1)
000000h
Data (DQ15-DQ0)
0020h
Device Code
000001h
8822h
0000h (Block Unprotected)
0001h (Block Protected)
Block Protection Status
SBA+02h
000005h
Configuration Register
Protection Register
BCR
PRD
(2)
000080h
Note: 1. SBA is the Start Base Address of each block, BCR is Configuration Register data, PRD is Protection Register Data.
2. Base Address, refer to Figure 8 and Table 8 for more information.
Table 8. Read Protection Register
Word
Use
Factory, User
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
Factory (Unique ID)
User
A8
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
Lock
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
24/61
M58LW032C
Figure 8. Protection Register Memory Map
WORD
ADDRESS
88h
User Programmable
85h
84h
Unique device number
81h
80h
Protection Register Lock
1
0
AI05501
Table 9. Program, Erase Times and Program Erase Endurance Cycles
M58LW032C
Parameters
Unit
(1,2)
(2)
Min
Typ
Max
(4)
Block (1Mb) Erase
1.2
s
s
4.8
(4)
Chip Program (Write to Buffer)
Chip Erase Time
24
37
72
110
576
(4)
(4)
s
(3)
Program Write Buffer
µs
192
Word/Byte Program Time
(Word/Byte Program command)
(4)
16
µs
48
(5)
(5)
(5)
(5)
Program Suspend Latency Time
Erase Suspend Latency Time
Block Protect Time
1
1
µs
µs
µs
20
25
30
1.2
18
0.75
Blocks Unprotect Time
Program/Erase Cycles (per block)
Data Retention
s
100,000
20
cycles
years
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Effective byte programming time 6µs, effective word programming time 12µs.
4. Maximum value measured at worst case conditions for both temperature and V after 100,000 program/erase cycles.
DD
5. Maximum value measured at worst case conditions for both temperature and V
.
DD
25/61
M58LW032C
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, V
,
OL
the Program/Erase Controller is active or has com-
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. The Status Register can be
read from any address.
pleted its operation; when the bit is High, V , a
OH
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
The Status Register can only be read using Asyn-
chronous Bus Read or Single Synchronous Read
operations. Once the memory returns to Read
Memory Array mode the bus will resume the set-
ting in the Configuration Register automatically.
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
Erase Status Bit (SR5). The Erase Status bit
can be used to identify if the memory has failed to
verify that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
When the Erase Status bit is Low, V , the mem-
OL
(Chip Enable, V ) and then reactivating (Chip En-
IH
ory has successfully verified that the block has
erased correctly or all blocks have been unprotect-
ed successfully. When the Erase Status bit is
able and Output Enable, V ) the device.
IL
Status Register bits SR5, SR4, SR3 and SR1 are
associated with various error conditions and can
only be reset with the Clear Status Register com-
mand. The Status Register bits are summarized in
Table 10, Status Register Bits. Refer to Table 10
in conjunction with the following text descriptions.
High, V , the erase operation has failed. De-
OH
pending on the cause of the failure other Status
Register bits may also be set to High, V
.
OH
■ If only the Erase Status bit (SR5) is set High,
, then the Program/Erase Controller has
V
OH
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Sta-
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully.
tus bit is Low, V , the Program/Erase Controller
is active and all other Status Register bits are High
OL
■ If the failure is due to an erase or blocks
unprotect with V
bit (SR3) is also set High, V
low, V , then V
Status
PEN
OL
PEN
Impedance; when the bit is High, V , the Pro-
OH
.
OH
gram/Erase Controller is inactive.
■ If the failure is due to an erase on a protected
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
block then Block Protection Status bit (SR1) is
also set High, V
.
OH
■ If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (SR4) is also set High, V
.
OH
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status Bit (SR4). The Program Status
bit is used to identify a Program or Block Protect
failure. The Program Status bit should be read
once the Program/Erase Controller Status bit is
High (Program/Erase Controller inactive).
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status Bit ( SR6). The
Erase
When the Program Status bit is Low, V , the
OL
Suspend Status bit indicates that an Erase opera-
tion has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
V
, the program or block protect operation has
OH
26/61
M58LW032C
failed. Depending on the cause of the failure other
Status Register bits may also be set to High, V
Program Suspend Status Bit (SR2). The Pro-
gram Suspend Status bit indicates that a Program
operation has been suspended and is waiting to
be resumed. The Program Suspend Status should
only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.
.
OH
■ If only the Program Status bit (SR4) is set High,
, then the Program/Erase Controller has
V
OH
applied the maximum number of pulses to the
byte and still failed to verify that the Write Buffer
has programmed correctly or that the Block is
protected.
■ If the failure is due to a program or block protect
with V
is also set High, V
low, V , then V
Status bit (SR3)
PEN
OL
PEN
When the Program Suspend Status bit is Low,
.
OH
V
, the Program/Erase Controller is active or has
OL
■ If the failure is due to a program on a protected
completed its operation; when the bit is High, V
,
OH
block then Block Protection Status bit (SR1) is
a Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
also set High, V
.
OH
■ If the failure is due to a program or erase
incorrect command sequence then Erase
Status bit (SR5) is also set High, V
.
OH
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Block Protection Status Bit (SR1). The Block
Protection Status bit can be used to identify if a
Program or Erase operation has tried to modify the
contents of a protected block.
When the Block Protection Status bit is Low, V
,
OL
V
Status Bit (SR3). The V
Status bit can
PEN
PEN
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
be used to identify if a Program, Erase, Block Pro-
tection or Block Unprotection operation has been
attempted when V
is Low, V .
PEN
IL
when the Block Protection Status bit is High, V
,
OH
When the V
Status bit is Low, V , no Pro-
OL
PEN
a Program (Program Status bit SR4 set High) or
Erase (Erase Status bit SR5 set High) operation
has been attempted on a protected block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
gram, Erase, Block Protection or Block Unprotec-
tion operations have been attempted with V
PEN
Low, V , since the last Clear Status Register com-
IL
mand, or hardware reset. When the V
Status
PEN
bit is High, V , a Program, Erase, Block Protec-
OH
tion or Block Unprotection operation has been at-
tempted with V
Low, V .
PEN
IL
Once set High, the V
Status bit can only be re-
PEN
set by a Clear Status Register command or a hard-
ware reset. If set High it should be reset before a
new Program, Erase, Block Protection or Block
Unprotection command is issued, otherwise the
new command will appear to fail.
Reserved (SR0). SR0 of the Status Register is
reserved. Its value should be masked.
27/61
M58LW032C
Table 10. Status Register Bits
OPERATION
Result
(Hex)
SR7
SR6
SR5
SR4
SR3
SR2
SR1
RB
V
Program/Erase Controller active
Write Buffer not ready
0
0
1
1
1
1
Hi-Z
Hi-Z
N/A
N/A
80h
C0h
84h
C4h
OL
V
OL
Write Buffer ready
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write Buffer ready in Erase Suspend
Program suspended
Program suspended in Erase Suspend
Program/Block Protect completed
successfully
1
1
1
1
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
80h
C0h
B0h
F0h
98h
Program completed successfully in Erase
Suspend
Program/Block protect failure due to
incorrect command sequence
Program failure due to incorrect command
sequence in Erase Suspend
Program/Block Protect failure due to
V
error
PEN
Program failure due to V
Suspend
error in Erase
PEN
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
Hi-Z
Hi-Z
Hi-Z
D8h
92h
D2h
Program failure due to Block Protection
Program failure due to Block Protection in
Erase Suspend
Program/Block Protect failure due to cell
failure
1
0
0
1
0
0
0
Hi-Z
90h
Program failure due to cell failure in Erase
Suspend
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
D0h
C0h
80h
Erase Suspended
Erase/Blocks Unprotect completed
successfully
Erase/Blocks Unprotect failure due to
incorrect command sequence
1
0
1
1
0
0
0
Hi-Z
B0h
Erase/Blocks Unprotect failure due to
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
Hi-Z
Hi-Z
Hi-Z
A8h
A2h
A0h
V
PEN
error
Erase failure due to Block Protection
Erase/Blocks Unprotect failure due to
failed cells in Block
28/61
M58LW032C
MAXIMUM RATING
Stressing the device above the ratings listed in Ta-
ble 11, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 11. Absolute Maximum Ratings
Value
Symbol
Parameter
Temperature Under Bias
Unit
Min
–40
–55
–0.6
–0.6
Max
125
150
T
BIAS
°C
°C
V
T
Storage Temperature
Input or Output Voltage
Supply Voltage
STG
V
V
+0.6
DDQ
IO
V
, V
DD DDQ
5.0
V
29/61
M58LW032C
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Parameter
M58LW032C
90, 110
Units
Min
Max
Supply Voltage (V
)
2.7
1.8
0
3.6
V
V
DD
Input/Output Supply Voltage (V
)
V
DDQ
DD
Grade 1
70
°C
°C
pF
ns
ns
V
Ambient Temperature (T )
A
Grade 6
–40
85
Load Capacitance (C )
30
L
Clock Rise and Fall Times
Input Rise and Fall Times
Input Pulses Voltages
3
4
0 to V
DDQ
0.5 V
Input and Output Timing Ref. Voltages
V
DDQ
Figure 9. AC Measurement Input Output
Waveform
Figure 10. AC Measurement Load Circuit
1.3V
1N914
V
DDQ
V
DD
3.3kΩ
V
DDQ
0.5 V
DDQ
DEVICE
UNDER
TEST
DQ
S
0V
C
L
AI00610
0.1µF
0.1µF
C
includes JIG capacitance
L
AI03459
Table 13. Capacitance
Symbol
Parameter
Test Condition
Typ
6
Max
8
Unit
pF
pF
C
V
IN
= 0V
= 0V
Input Capacitance
Output Capacitance
IN
C
OUT
V
OUT
8
12
Note: 1. T = 25°C, f = 1 MHz
A
2. Sampled only, not 100% tested.
30/61
M58LW032C
Table 14. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
±1
±5
20
Unit
µA
I
0V≤ V ≤ V
Input Leakage Current
LI
IN
DDQ
I
0V≤ V
≤V
Output Leakage Current
µA
LO
OUT DDQ
I
E = V , G = V , f
= 6MHz
Supply Current (Random Read)
Supply Current (Burst Read)
Supply Current (Standby)
mA
mA
µA
DD
IL
IH add
I
E = V , G = V , f = 50MHz
IH clock
30
DDB
IL
I
E = V , RP = V
40
DD1
IH
IH
I
E = V , RP = V
Supply Current (Auto Low-Power)
Supply Current (Reset/Power-Down)
40
µA
DD5
IL
IH
I
RP = V
40
µA
DD2
IL
Supply Current (Program or Erase,
Block Protect, Block Unprotect)
Program or Erase operation in
progress
I
30
40
mA
µA
DD3
Supply Current
(Erase/Program Suspend)
I
E = V
DD4
IH
V
V
x 0.3
DDQ
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.5
V
V
V
V
IL
V
IH
V
x 0.7
V + 0.5
DDQ
DDQ
V
OL
I
= 100µA
OL
0.2
V
OH
I
= –100µA
V
–0.2
OH
DDQ
V
Supply Voltage (Erase and
DD
V
2
V
LKO
Program lockout)
31/61
M58LW032C
Figure 11. Asynchronous Bus Read AC Waveforms
tAVAV
A1-A21
VALID
tELQV
tELQX
tAXQX
E
L
tGLQV
tGLQX
tEHQZ
tEHQX
G
tAVQV
tGHQZ
tGHQX
DQ0-DQ15
OUTPUT
AI06255
Note: Asynchronous Read CR15 = 1
Table 15. Asynchronous Bus Read AC Characteristics.
M58LW032C
Symbol
Parameter
Unit
90
110
110
110
0
t
Address Valid to Address Valid
Min
Max
Min
Max
Min
Max
Min
Min
Min
Max
Max
90
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
AVQV
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Transition
Output Enable High to Output Transition
Address Transition to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
ELQX
t
90
0
110
0
ELQV
t
GLQX
t
25
0
25
0
GLQV
t
EHQX
t
0
0
GHQX
t
0
0
AXQX
t
25
20
25
20
EHQZ
t
GHQZ
32/61
M58LW032C
Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms
A1-A21
VALID
tAVLH
tLHAX
tAVLL
L
tLHLL
tLLLH
tELLH
tEHLX
tELLL
E
tGLQV
tEHQZ
tEHQX
tGLQX
G
tLLQX
tLLQV
tGHQZ
tGHQX
DQ0-DQ15
OUTPUT
AI06256b
Note: Asynchronous Read CR15 = 1
Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics
M58LW032C
Symbol
Parameter
Unit
90
110
0
t
Address Valid to Latch Enable Low
Address Valid to Latch Enable High
Latch Enable High to Latch Enable Low
Latch Enable Low to Latch Enable High
Chip Enable Low to Latch Enable Low
Chip Enable Low to Latch Enable High
Latch Enable Low to Output Transition
Latch Enable Low to Output Valid
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
0
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
t
10
10
10
0
AVLH
t
LHLL
t
LLLH
t
ELLL
t
10
0
10
0
ELLH
t
LLQX
t
90
6
110
6
LLQV
t
Latch Enable High to Address Transition
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Latch Enable Transition
LHAX
t
0
0
GLQX
t
25
0
25
0
GLQV
t
EHLX
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
33/61
M58LW032C
Figure 13. Asynchronous Page Read AC Waveforms
A1-A2
VALID
VALID
A3-A21
VALID
tAVQV
tELQV
tELQX
tAXQX
E
L
tAVQV1
tEHQZ
tEHQX
tGLQV
tGLQX
tAXQX1
G
tGHQZ
tGHQX
DQ0-DQ15
OUTPUT
OUTPUT
AI06257
Note: Asynchronous Read CR15 = 1
Table 17. Asynchronous Page Read AC Characteristics
M58LW032C
Symbol
Parameter
Unit
90, 110
t
Address Transition to Output Transition
Address Valid to Output Valid
Min
6
ns
ns
AXQX1
t
Max
25
AVQV1
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
34/61
M58LW032C
Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled
A1-A21
VALID
tAVWH
tWHAX
E
L
tELWL
tGHWL
tWHEH
G
tWHGL
tWLWH
tWHWL
W
tDVWH
INPUT
DQ0-DQ15
tWHDX
RB
tVPHWH
tWHBL
V
PEN
AI06258
Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled
A1-A21
VALID
tAVLH
tLHAX
L
tELLL
tLLLH
tWLLH
tLHGL
tLHWH
E
tELWL
tGHWL
tWHEH
G
tWLWH
tDVWH
tWHWL
tWHGL
W
DQ0-DQ15
INPUT
tWHDX
tWHBL
RB
tVPHWH
V
PEN
AI06259
35/61
M58LW032C
Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled.
M58LW032C
Symbol
Parameter
Address Valid to Latch Enable High
Unit
90, 110
10
50
50
0
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLH
t
Address Valid to Write Enable High
AVWH
t
Data Input Valid to Write Enable High
Chip Enable Low to Write Enable Low
Chip Enable Low to Latch Enable Low
Latch Enable High to Address Transition
Latch Enable High to Output Enable Low
Latch Enable High to Write Enable High
Latch Enable low to Latch Enable High
Latch Enable Low to Write Enable High
Program/Erase Enable High to Write Enable High
Write Enable High to Address Transition
Write Enable High to Ready/Busy low
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Enable Low to Latch Enable High
DVWH
t
ELWL
t
0
ELLL
t
6
LHAX
t
95
0
LHGL
t
LHWH
t
10
50
0
LLLH
t
LLWH
t
VPHWH
t
0
WHAX
t
500
0
WHBL
t
WHDX
t
0
WHEH
t
20
35
30
70
10
GHWL
t
WHGL
t
WHWL
t
WLWH
t
WLLH
36/61
M58LW032C
Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled
A1-A21
VALID
tAVEH
tEHAX
W
G
tWLEL
tEHWH
tGHEL
tELEH
tEHEL
tEHGL
E
L
tDVEH
INPUT
DQ0-DQ15
RB
tEHDX
tEHBL
tVPHEH
V
PEN
AI06260
Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled
A1-A21
VALID
tAVLH
tAVEH
tLHAX
tEHAX
L
tLLLH
tELLH
tWLLL
tLHEH
tLHGL
W
G
tWLEL
tGHEL
tEHWH
tELEH
tEHEL
tEHGL
E
tDVEH
INPUT
DQ0-DQ15
tEHDX
RB
tVPHEH
tEHBL
V
PEN
AI06261
37/61
M58LW032C
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled
M58LW032C
Symbol
Parameter
Address Valid to Latch Enable High
Unit
90, 110
10
50
50
0
t
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLH
t
Address Valid to Chip Enable High
AVEH
t
Data Input Valid to Chip Enable High
Chip Enable High to Address Transition
Chip Enable High to Ready/Busy low
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Output Enable Low
Chip Enable High to Chip Enable Low
Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
Output Enable High to Chip Enable Low
Latch Enable High to Address Transition
Latch Enable High to Output Enable Low
Latch Enable High to Chip Enable High
Latch Enable low to Latch Enable High
Latch Enable Low to Chip Enable High
Program/Erase Enable High to Chip Enable High
Write Enable Low to Chip Enable Low
Write Enable Low to Latch Enable Low
DVEH
t
EHAX
t
500
0
EHBL
t
EHDX
t
0
EHWH
t
35
30
70
10
20
6
EHGL
t
EHEL
t
ELEH
t
ELLH
t
GHEL
t
LHAX
t
35
0
LHGL
t
LHEH
t
10
50
0
LLLH
t
LLEH
t
VPHEH
t
0
WLEL
t
0
WLLL
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M58LW032C
Figure 18. Synchronous Burst Read AC Waveform
Note: Valid Clock Edge = Rising (CR6 = 1)
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M58LW032C
Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
(2)
Output
R
V
V
V
NV
NV
V
V
tRLKH
(3)
AI05510
Note: 1. Valid Data Ready = Valid Low during valid clock edge (CR8 = 0)
2. V= Valid output, NV= Not Valid output.
3. R is an open drain output with an internal pull up resistor of 1MΩ. Depending on the Valid Data Ready pin capacitance load an
external pull up resistor must be chosen according to the system clock period.
Table 20. Synchronous Burst Read AC Characteristics
M58LW032C
Unit
Symbol
Parameter
90, 110
t
Address Valid to Active Clock Edge
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
7
10
10
10
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVKH
t
Address Valid to Latch Enable High
Chip Enable Low to Active Clock Edge
Chip Enable Low to Latch Enable High
Output Enable Low to Valid Clock Edge
Valid Clock Edge to Address Transition
Valid Clock Edge to Latch Enable Low
Valid Clock Edge to Latch Enable High
Valid Clock Edge to Output Transition
Latch Enable Low to Valid Clock Edge
Latch Enable Low to Latch Enable High
Valid Clock Edge to Output Valid
AVLH
t
ELKH
t
ELLH
t
GLKH
t
KHAX
t
0
KHLL
t
0
KHLH
t
3
KHQX
t
6
LLKH
t
7
LLLH
t
15
5
KHQV
t
Output Valid to Active Clock Edge
QVKH
t
Valid Data Ready Low to Valid Clock Edge
5
RLKH
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
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M58LW032C
Figure 20. Reset, Power-Down and Power-up AC Waveform
W
E, G
DQ0-DQ15
tPHQV
RB
RP
tPLRH
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
and Reset
Reset during
Program or Erase
AI05521
Table 21. Reset, Power-Down and Power-up AC Characteristics
M58LW032C
Symbol
Parameter
Reset/Power-Down High to Data Valid
Unit
90
110
150
100
30
t
Max
Min
Max
Min
130
100
30
ns
ns
µs
µs
PHQV
t
Reset/Power-Down Low to Reset/Power-Down High
Reset/Power-Down Low to Ready High
PLPH
t
PLRH
t
Supply Voltages High to Reset/Power-Down High
0
0
VDHPH
41/61
M58LW032C
PACKAGE MECHANICAL
Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
14.10
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.5551
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
13.90
–
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.5472
–
C
D
D1
E
e
0.50
0.0197
L
0.50
0°
0.70
5°
0.0197
0°
0.0276
5°
α
N
56
56
CP
0.10
0.0039
42/61
M58LW032C
Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline
D
D1
FD
FE
SD
SE
E
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
Note: Drawing is not to scale.
Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.350
0.850
0.500
10.100
–
Typ
Max
A
A1
A2
b
0.0472
0.300
0.200
0.0118
0.0079
0.0138
0.0335
0.400
9.900
–
0.0157
0.3898
–
0.0197
D
10.000
7.000
0.3937
0.3976
D1
ddd
e
0.2756
–
0.100
–
0.0039
1.000
13.000
7.000
1.500
3.000
0.500
0.500
–
0.0394
0.5118
0.2756
0.0591
0.1181
0.0197
0.0197
–
–
E
12.900
13.100
–
0.5079
0.5157
E1
FD
FE
SD
SE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
43/61
M58LW032C
PART NUMBERING
Table 24. Ordering Information Scheme
Example:
M58LW032C
110 N
1
T
Device Type
M58
Architecture
L = Page Mode, Burst
Operating Voltage
W = V = 2.7V to 3.6V; V
= 1.8 to V
DD
DD
DDQ
Device Function
032C = 32 Mbit (x16), Uniform Block
Speed
90 = 90ns
110 = 110ns
Package
N = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x 13mm, 1mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
44/61
M58LW032C
APPENDIX A. BLOCK ADDRESS TABLE
Table 25. Block Addresses
Block
Number
Address Range
(x16 Bus Width)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
8
7
6
5
4
3
2
1
45/61
M58LW032C
APPENDIX B. COMMON FLASH INTERFACE - CFI
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 26, 27,
28, 29, 30 and 31 show the addresses used to re-
trieve the data.
Table 26. Query Structure Overview
Offset
00h
Sub-section Name
Description
Manufacturer Code
01h
Device Code
10h
CFI Query Identification String
Command set ID and algorithm data offset
Device timing and voltage information
Flash memory layout
1Bh
27h
System Interface Information
Device Geometry Definition
Additional information specific to the Primary
Algorithm (optional)
(1)
Primary Algorithm-specific Extended Query Table
P(h)
Additional information specific to the Alternate
Algorithm (optional)
(2)
Alternate Algorithm-specific Extended Query Table
A(h)
(SBA+02)h Block Status Register
Block-related Information
Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.
2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
3. SBA is the Start Base Address for each block.
Table 27. CFI - Query Address and Data Output
Data
Instruction
Address A21-A1
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
51h
52h
59h
"Q"
"R"
"Y"
51h; "Q"
52h; "R"
59h; "Y"
Query ASCII String
Primary Vendor:
01h
00h
31h
00h
00h
00h
00h
00h
Command Set and Control Interface ID Code
Primary algorithm extended Query Address Table: P(h)
Alternate Vendor:
Command Set and Control Interface ID Code
Alternate Algorithm Extended Query address Table
(2)
1Ah
Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to ’0’.
2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
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M58LW032C
Table 28. CFI - Device Voltage and Timing Specification
Data
Description
Address A21-A1
(1)
V
V
V
V
Min, 2.7V
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
DD
DD
PP
PP
27h
36h
00h
00h
(1)
(2)
(2)
max, 3.6V
min – Not Available
max – Not Available
n
04h
2 µs typical time-out for Word, DWord prog – Not Available
n
08h
0Ah
2 µs, typical time-out for max buffer write
n
2 ms, typical time-out for Erase Block
(3)
n
00h
2 ms, typical time-out for chip erase – Not Available
n
04h
04h
04h
2 x typical for Word Dword time-out max – Not Available
n
2 x typical for buffer write time-out max
n
2 x typical for individual block erase time-out maximum
(3)
n
00h
2 x typical for chip erase max time-out – Not Available
Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
3. Not supported.
Table 29. Device Geometry Definition
Data
Description
Address A21-A1
n
27h
16h
n where 2 is number of bytes memory Size
Device Interface
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
01h
00h
05h
00h
01h
1Fh
00h
00h
02h
Organization Sync./Async.
n
Maximum number of bytes in Write Buffer, 2
Bit7-0 = number of Erase Block Regions in device
Number (n-1) of Erase Blocks of identical size; n=64
Erase Block Region Information
x 256 bytes per Erase block (128K bytes)
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M58LW032C
Table 30. Block Status Register
Address A21-A1
Data
Selected Block Information
Block UnProtected
0
1
0
bit0
Block Protected
(2)
(1)
Last erase operation ended successfully
(BA+2)h
bit1
(2)
1
0
Last erase operation not ended successfully
Reserved for future features
bit7-2
Note: 1. BA specifies the block address location, A21-A17.
2. Not Supported.
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M58LW032C
Table 31. Extended Query information
Address
offset
Address
A21-A2
Data (Hex)
x16 Bus Width
Description
(P)h
31h
32h
33h
34h
35h
36h
37h
38h
50h
"P"
"R"
"I"
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
52h
49h
Query ASCII string - Extended Table
31h
31h
CEh
01h
00h
Major version number
Minor version number
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Protect/UnProtect Supported (1=yes)
bit4, Queue Erase Supported (0=no)
bit5, Instant Individual Block locking (0=no)
bit6, Protection bits supported (1=yes)
bit7, Page Read supported (1=yes)
bit8, Synchronous Read supported (1=yes)
bits 9 to 31 reserved for future use
(P+8)h
39h
00h
Function allowed after Suspend:
(P+9)h
3Ah
01h
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
Block Status Register
(P+A)h
(P+B)h
3Bh
3Ch
01h
00h
bit0, Block Protect Bit status active (1=yes)
bit1, Block Lock-Down Bit status active (not available)
bits 2 to 15 reserved for future use
V
V
OPTIMUM Program/Erase voltage conditions
OPTIMUM Program/Erase voltage conditions
(P+C)h
(P+D)h
(P+E)h
(P+F)h
(P+10)h
(P+11)h
3Dh
3Eh
3Fh
40h
41h
42h
33h
00h
01h
80h
00h
03h
DD
PP
OTP protection: No. of protection register fields
Protection Register’s start address, least significant bits
Protection Register’s start address, most significant bits
n
n where 2 is number of factory reprogrammed bytes
n
(P+12)h
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
43h
44h
45h
46h
47h
48h
03h
03h
03h
01h
02h
07h
n where 2 is number user programmable bytes
n
Page Read: 2 Bytes (n = bits 0-7)
Synchronous mode configuration fields
n+1
n where 2
is the number of Words for the burst Length = 4
is the number of Words for the burst Length = 8
n+1
n where 2
Burst Continuous
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
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M58LW032C
APPENDIX C. FLOW CHARTS
Figure 23. Write to Buffer and Program Flowchart and Pseudo Code
Start
Write to Buffer E8h
Command, Block Address
Read Status
Register
NO
NO
YES
Write to Buffer
Timeout
SR7 = 1
YES
(1)
Note 1: N+1 is number of Words
to be programmed
Write N
,
Block Address
Try Again Later
Write Buffer Data,
Start Address
X = 0
YES
X = N
NO
Write Next Buffer Data,
Next Program Address
Note 2: Next Program Address must
have same A5-A21.
(2)
X = X + 1
Program Buffer to Flash
Confirm D0h
Read Status
Register
NO
SR7 = 1
YES
Note 3: A full Status Register Check must be
done to check the program operation's
success.
Full Status
Register Check
(3)
End
AI06263b
50/61
M58LW032C
Figure 24. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read status register
NO
NO
SR7 = 1
YES
while SR7 = 1
If SR2 = 0, Program completed
SR2 = 1
YES
Program Complete
Read Memory Array command:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
Program Erase Resume Command:
– write D0h
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
Write D0h
Write FFh
Read Data
Program Continues
AI00612b
51/61
M58LW032C
Figure 25. Erase Flowchart and Pseudo Code
Start
Erase command:
– write 20h
Write 20h
– write D0h to Block Address
(A12-A17)
(memory enters read Status
Register after the Erase command)
Write D0h to
Block Address
NO
do:
Read Status
– read status register
– if Program/Erase Suspend command
given execute suspend erase loop
Register
Suspend
YES
NO
Suspend
Loop
SR7 = 1
while SR7 = 1
YES
NO
NO
NO
NO
V
Invalid
Error (1)
If SR3 = 1, V
invalid error:
PEN
PEN
– error handler
SR3 = 0
YES
Command
Sequence Error
If SR4, SR5 = 1, Command Sequence error:
– error handler
SR4, SR5 = 0
YES
Erase
Error (1)
If SR5 = 1, Erase error:
– error handler
SR5 = 0
YES
Erase to Protected
Block Error
If SR1 = 1, Erase to Protected Block Error:
– error handler
SR1 = 0
YES
End
AI00613C
Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper-
ations.
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M58LW032C
Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read status register
NO
NO
SR7 = 1
YES
while SR7 = 1
If SR6 = 0, Erase completed
SR6 = 1
YES
Erase Complete
Read Memory Array command:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
or Program
Program/Erase Resume command:
– write D0h to resume the Erase
operation
– if the Program operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
Write D0h
Write FFh
Read Data
Erase Continues
AI00615b
53/61
M58LW032C
Figure 27. Block Protect Flowchart and Pseudo Code
Start
Write 60h
Block Address
Block Protect Command
– write 60h, Block Adress
– write 01h, Block Adress
Write 01h
Block Address
do:
Read Status Register
– read status register
NO
SR7 = 1
while SR7 = 1
YES
YES
SR3 = 1
NO
V
Invalid Error
If SR3 = 1, V
Invalid Error
PEN
PEN
YES
YES
Invalid Command
Sequence Error
If SR4 = 1, SR5 = 1 Invalid Command Sequence
Error
SR4, SR5 = 1,1
NO
Block Protect
Error
If SR4 = 1, Block Protect Error
SR4 = 1
NO
Write FFh
Read Memory Array Command:
– write FFh
Block Protect
Sucessful
AI06157b
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M58LW032C
Figure 28. Blocks Unprotect Flowchart and Pseudo Code
Start
Write 60h
Blocks Unprotect Command
– write 60h, Block Adress
– write D0h, Block Adress
Write D0h
do:
Read Status Register
– read status register
NO
SR7 = 1
while SR7 = 1
YES
YES
SR3 = 1
NO
V
Invalid Error
PEN
If SR3 = 1, V
Invalid Error
PEN
YES
YES
Invalid Command
Sequence Error
If SR4 = 1, SR5 = 1 Invalid Command
Sequence Error
SR4, SR5 = 1,1
NO
Blocks Unprotect
Error
If SR5 = 1, Blocks Unprotect Error
SR5 = 1
NO
Write FFh
Read Memory Array Command:
– write FFh
Blocks Unprotect
Sucessful
AI06158b
55/61
M58LW032C
Figure 29. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
Protection Register Program Command
– write C0h
– write Protection Register Address,
Protection Register Data
Write
PR Address, PR Data
do:
Read Status Register
– read status register
NO
SR7 = 1
YES
while SR7 = 1
YES
YES
If SR3 = 1, SR4 = 1 V
Invalid Error
PEN
V
Invalid Error
SR3, SR4 = 1,1
NO
PEN
Protection Register
Program Error
If SR1 = 0, SR4 = 1 Protection Register
Program Error
SR1, SR4 = 0,1
NO
YES
Protection Register
Program Error
If SR1 = 1, SR4 = 1 Program Error due to
Protection Register Protection
SR1, SR4 = 1,1
NO
Write FFh
Read Memory Array Command:
– write FFh
PR Program
Sucessful
AI06159b
Note: PR = Protection Register
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M58LW032C
Figure 30. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE
NO
90h
YES
READ
SIGNATURE
NO
98h
YES
CFI
QUERY
NO
70h
YES
READ
ARRAY
READ
STATUS
NO
50h
YES
CLEAR
STATUS
NO
E8h
YES
PROGRAM
BUFFER
LOAD
NO
(1)
20h
YES
ERASE
NO
FFh
YES
SET-UP
NO
D0h
NO
YES
C
PROGRAM
COMMAND
ERROR
D0h
YES
ERASE
COMMAND
ERROR
A
B
AI03618
Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
57/61
M58LW032C
Figure 31. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
(READ STATUS)
Program/Erase Controller
Status bit in the Status
Register
YES
READ
STATUS
READY
?
NO
READ
NO
ARRAY
B0h
YES
YES
READ
STATUS
NO
FFh
ERASE
SUSPEND
NO
YES
ERASE
SUSPENDED
READY
?
NO
READ
STATUS
YES
WAIT FOR
COMMAND
WRITE
YES
YES
YES
YES
READ
STATUS
70h
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
PROGRAM
BUFFER
LOAD
E8h
NO
NO
PROGRAM
COMMAND
ERROR
YES
READ
STATUS
D0h
D0h
NO
(ERASE RESUME)
YES
READ
ARRAY
c
AI03619
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M58LW032C
Figure 32. Command Interface and Program Erase Controller Flowchart (c).
B
C
PROGRAM
(READ STATUS)
YES
Program/Erase Controller
Status bit in the Status
Register
READ
STATUS
READY
?
NO
READ
ARRAY
NO
B0h
YES
YES
NO
READ
STATUS
FFh
PROGRAM
SUSPEND
NO
YES
PROGRAM
SUSPENDED
READY
?
NO
YES
WAIT FOR
COMMAND
WRITE
READ
STATUS
YES
YES
YES
NO
READ
STATUS
70h
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
YES
READ
ARRAY
READ
STATUS
D0h
(PROGRAM RESUME)
AI00618
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M58LW032C
REVISION HISTORY
Table 32. Document Revision History
Date
Version
-01
Revision Details
11-Mar-2002
10-Jul-2002
First Issue (Data Brief)
-02
Document expanded to full Product Preview
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 02 equals 2.0).
06-Aug-2002
02-Sep-2002
16-Dec-2002
2.1
2.2
2.3
Word Effective Programming Time modified. Program Write Buffer and Block Erase
Time parameters modified in Table 9. Speed Class 90ns added. V , V
, V and
DD DDQ
SS
V
SSQ
signal descriptions modified.
Figure 12, Asynchronous Latch Controlled Bus Read AC Waveforms, modified.
REVISION HISTORY moved to after the appendices. Table 9, Program, Erase Times
and Program Erase Endurance Cycles table modified. All DU connections changed to
NC in Table 4, TBGA64 Connections (Top view through package). V max and V
IL
IH
min modified in Table 14, DC Characteristics. Block Protect setup command address
modified in Table 5, Commands. Data and Descriptions clarified in CFI Table 31,
Extended Query information.
Document promoted to full datasheet. Summary Description clarified, Bus Operations
clarified, Smart Protection added, Read Modes section added, Status Register and
29-Apr-2003
3.0
Configuration Register bit nomenclature modified, V
Invalid Error clarified in
PEN
Flowcharts. Lead-free packing options added to Ordering Information Scheme.
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